diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/vect/vect-cond-12.c | 14 | ||||
| -rw-r--r-- | gcc/tree-vect-stmts.c | 10 |
4 files changed, 34 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 922e404..fc7af98 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2019-12-29 Richard Sandiford <richard.sandiford@arm.com> + + * tree-vect-stmts.c (vectorizable_condition): For extract-last + reductions, check that the target supports the required comparison + operation. + 2019-12-27 Richard Sandiford <richard.sandiford@arm.com> * config/aarch64/iterators.md (V_INT_CONTAINER): Fix VNx2SF entry. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index eec8b0b..2e0f364 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2019-12-29 Richard Sandiford <richard.sandiford@arm.com> + + * gcc.dg/vect/vect-cond-12.c: New test. + 2019-12-27 Richard Sandiford <richard.sandiford@arm.com> * gcc.target/aarch64/sve/mixed_size_11.c: New test. diff --git a/gcc/testsuite/gcc.dg/vect/vect-cond-12.c b/gcc/testsuite/gcc.dg/vect/vect-cond-12.c new file mode 100644 index 0000000..1add96a --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-cond-12.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ + +int +f (int *x, short *y) +{ + int res = 100; + for (int i = 0; i < 40; ++i) + { + if (y[i] > 1) + res = x[i]; + x[i] += y[i]; + } + return res; +} diff --git a/gcc/tree-vect-stmts.c b/gcc/tree-vect-stmts.c index 706da5b..feb0b7e 100644 --- a/gcc/tree-vect-stmts.c +++ b/gcc/tree-vect-stmts.c @@ -10081,6 +10081,16 @@ vectorizable_condition (stmt_vec_info stmt_info, gimple_stmt_iterator *gsi, cond_code = SSA_NAME; } + if (TREE_CODE_CLASS (cond_code) == tcc_comparison + && reduction_type == EXTRACT_LAST_REDUCTION + && !expand_vec_cmp_expr_p (comp_vectype, vec_cmp_type, cond_code)) + { + if (dump_enabled_p ()) + dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, + "reduction comparison operation not supported.\n"); + return false; + } + if (!vec_stmt) { if (bitop1 != NOP_EXPR) |