diff options
Diffstat (limited to 'gcc')
949 files changed, 16491 insertions, 2961 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3968cf2..37be830 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,497 @@ +2023-09-28 Richard Biener <rguenther@suse.de> + + PR tree-optimization/111614 + * tree-ssa-reassoc.cc (undistribute_bitref_for_vector): Properly + convert the first vector when required. + +2023-09-28 xuli <xuli1@eswincomputing.com> + + PR target/111533 + * config/riscv/riscv-v.cc (expand_const_vector): Fix bug. + * config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): Fix bug. + +2023-09-27 Sandra Loosemore <sandra@codesourcery.com> + + * gimple.cc (gimple_copy): Add case GIMPLE_OMP_STRUCTURED_BLOCK. + +2023-09-27 Iain Sandoe <iain@sandoe.co.uk> + + PR target/111610 + * configure: Regenerate. + * configure.ac: Rename the missing dsymutil case to "DET_UNKNOWN". + +2023-09-27 Manos Anagnostakis <manos.anagnostakis@vrull.eu> + Philipp Tomsich <philipp.tomsich@vrull.eu> + Manolis Tsamis <manolis.tsamis@vrull.eu> + + * config/aarch64/aarch64-opts.h (enum aarch64_ldp_policy): New + enum type. + (enum aarch64_stp_policy): New enum type. + * config/aarch64/aarch64-protos.h (struct tune_params): Add + appropriate enums for the policies. + (aarch64_mem_ok_with_ldpstp_policy_model): New declaration. + * config/aarch64/aarch64-tuning-flags.def + (AARCH64_EXTRA_TUNING_OPTION): Remove superseded tuning + options. + * config/aarch64/aarch64.cc (aarch64_parse_ldp_policy): New + function to parse ldp-policy parameter. + (aarch64_parse_stp_policy): New function to parse stp-policy parameter. + (aarch64_override_options_internal): Call parsing functions. + (aarch64_mem_ok_with_ldpstp_policy_model): New function. + (aarch64_operands_ok_for_ldpstp): Add call to + aarch64_mem_ok_with_ldpstp_policy_model for parameter-value + check and alignment check and remove superseded ones. + (aarch64_operands_adjust_ok_for_ldpstp): Add call to + aarch64_mem_ok_with_ldpstp_policy_model for parameter-value + check and alignment check and remove superseded ones. + * config/aarch64/aarch64.opt (aarch64-ldp-policy): New param. + (aarch64-stp-policy): New param. + * doc/invoke.texi: Document the parameters accordingly. + +2023-09-27 Andre Vieira <andre.simoesdiasvieira@arm.com> + + * tree-data-ref.cc (include calls.h): Add new include. + (get_references_in_stmt): Correctly handle IFN_MASK_CALL. + +2023-09-27 Richard Biener <rguenther@suse.de> + + * match.pd (abs (copysign (x, y)) -> abs (x)): New pattern. + +2023-09-27 Jakub Jelinek <jakub@redhat.com> + + PR c++/105606 + * system.h (BROKEN_VALUE_INITIALIZATION): Don't define. + * vec.h (vec_default_construct): Remove BROKEN_VALUE_INITIALIZATION + workaround. + * function.cc (assign_parm_find_data_types): Likewise. + +2023-09-27 Pan Li <pan2.li@intel.com> + + * config/riscv/autovec.md (roundeven<mode>2): New pattern. + * config/riscv/riscv-protos.h (enum insn_flags): New enum type. + (enum insn_type): Ditto. + (expand_vec_roundeven): New func decl. + * config/riscv/riscv-v.cc (expand_vec_roundeven): New func impl. + +2023-09-27 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + PR target/111590 + * dse.cc (find_shift_sequence): Check the mode with access_size exist on the target. + +2023-09-27 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * tree-if-conv.cc (is_cond_scalar_reduction): Fix comments. + +2023-09-27 Pan Li <pan2.li@intel.com> + + * config/riscv/autovec.md (btrunc<mode>2): New pattern. + * config/riscv/riscv-protos.h (expand_vec_trunc): New func decl. + * config/riscv/riscv-v.cc (emit_vec_cvt_x_f_rtz): New func impl. + (expand_vec_trunc): Ditto. + +2023-09-26 Hans-Peter Nilsson <hp@axis.com> + + PR target/107567 + PR target/109166 + * builtins.cc (expand_builtin) <case BUILT_IN_ATOMIC_TEST_AND_SET>: + Handle failure from expand_builtin_atomic_test_and_set. + * optabs.cc (expand_atomic_test_and_set): When all attempts fail to + generate atomic code through target support, return NULL + instead of emitting non-atomic code. Also, for code handling + targetm.atomic_test_and_set_trueval != 1, gcc_assert result + from calling emit_store_flag_force instead of returning NULL. + +2023-09-26 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/111599 + * value-relation.cc (relation_oracle::valid_equivs): Ensure + ssa_name is valid. + +2023-09-26 Andrew Pinski <apinski@marvell.com> + + PR tree-optimization/106164 + PR tree-optimization/111456 + * match.pd (`(A ==/!= B) & (A CMP C)`): + Support an optional cast on the second A. + (`(A ==/!= B) | (A CMP C)`): Likewise. + +2023-09-26 Andrew Pinski <apinski@marvell.com> + + PR tree-optimization/111469 + * tree-ssa-phiopt.cc (minmax_replacement): Fix + the assumption for the `non-diamond` handling cases + of diamond code. + +2023-09-26 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * match.pd: Optimize COND_ADD reduction pattern. + +2023-09-26 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + PR tree-optimization/111594 + PR tree-optimization/110660 + * match.pd: Optimize COND_LEN_ADD reduction. + +2023-09-26 Pan Li <pan2.li@intel.com> + + * config/riscv/autovec.md (round<mode>2): New pattern. + * config/riscv/riscv-protos.h (enum insn_flags): New enum type. + (enum insn_type): Ditto. + (expand_vec_round): New function decl. + * config/riscv/riscv-v.cc (expand_vec_round): New function impl. + +2023-09-26 Iain Sandoe <iain@sandoe.co.uk> + + * config/darwin.h (DARWIN_CC1_SPEC): Remove -dynamiclib. + +2023-09-26 Tobias Burnus <tobias@codesourcery.com> + + PR middle-end/111547 + * doc/invoke.texi (-fopenmp): Mention C++11 [[omp::decl(...)]] syntax. + (-fopenmp-simd): Likewise. Clarify 'loop' directive semantic. + +2023-09-26 Pan Li <pan2.li@intel.com> + + * config/riscv/autovec.md (rint<mode>2): New pattern. + * config/riscv/riscv-protos.h (expand_vec_rint): New function decl. + * config/riscv/riscv-v.cc (expand_vec_rint): New function impl. + +2023-09-26 Pan Li <pan2.li@intel.com> + + * config/riscv/autovec.md (nearbyint<mode>2): New pattern. + * config/riscv/riscv-protos.h (enum insn_type): New enum. + (expand_vec_nearbyint): New function decl. + * config/riscv/riscv-v.cc (expand_vec_nearbyint): New func impl. + +2023-09-26 Pan Li <pan2.li@intel.com> + + * config/riscv/riscv-v.cc (gen_ceil_const_fp): Remove. + (get_fp_rounding_coefficient): Rename. + (gen_floor_const_fp): Remove. + (expand_vec_ceil): Take renamed func. + (expand_vec_floor): Ditto. + +2023-09-25 Vladimir N. Makarov <vmakarov@redhat.com> + + PR middle-end/111497 + * lra-constraints.cc (lra_constraints): Copy substituted + equivalence. + * lra.cc (lra): Change comment for calling unshare_all_rtl_again. + +2023-09-25 Eric Botcazou <ebotcazou@adacore.com> + + * gimple-range-gori.cc (gori_compute::logical_combine): Add missing + return statement in the varying case. + +2023-09-25 Xi Ruoyao <xry111@xry111.site> + + * doc/invoke.texi: Update -m[no-]explicit-relocs for r14-4160. + +2023-09-25 Andrew Pinski <apinski@marvell.com> + + PR tree-optimization/110386 + * gimple-ssa-backprop.cc (strip_sign_op_1): Remove ABSU_EXPR. + +2023-09-25 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + PR target/111548 + * config/riscv/riscv-vsetvl.cc (earliest_pred_can_be_fused_p): Bugfix + +2023-09-25 Kewen Lin <linkw@linux.ibm.com> + + PR target/111366 + * config/rs6000/rs6000.cc (rs6000_update_ipa_fn_target_info): Skip + empty inline asm. + +2023-09-25 Kewen Lin <linkw@linux.ibm.com> + + PR target/111380 + * config/rs6000/rs6000.cc (rs6000_can_inline_p): Adopt + target_option_default_node when the callee has no option + attributes, also simplify the existing code accordingly. + +2023-09-25 Guo Jie <guojie@loongson.cn> + + * config/loongarch/lasx.md (lasx_vecinit_merge_<LASX:mode>): New + pattern for vector construction. + (vec_set<mode>_internal): Ditto. + (lasx_xvinsgr2vr_<mode256_i_half>_internal): Ditto. + (lasx_xvilvl_<lasxfmt_f>_internal): Ditto. + * config/loongarch/loongarch.cc (loongarch_expand_vector_init): + Optimized the implementation of vector construction. + (loongarch_expand_vector_init_same): New function. + * config/loongarch/lsx.md (lsx_vilvl_<lsxfmt_f>_internal): New + pattern for vector construction. + (lsx_vreplvei_mirror_<lsxfmt_f>): New pattern for vector + construction. + (vec_concatv2df): Ditto. + (vec_concatv4sf): Ditto. + +2023-09-24 Pan Li <pan2.li@intel.com> + + PR target/111546 + * config/riscv/riscv-v.cc + (expand_vector_init_merge_repeating_sequence): Bugfix + +2023-09-24 Andrew Pinski <apinski@marvell.com> + + PR tree-optimization/111543 + * match.pd (`(X & ~Y) & Y`, `(X | ~Y) | Y`): New patterns. + +2023-09-24 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/autovec-opt.md: Extend VLS modes + * config/riscv/vector-iterators.md: Ditto. + +2023-09-23 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/autovec-opt.md: Add VLS modes for conditional ABS/SQRT. + +2023-09-23 Pan Li <pan2.li@intel.com> + + * config/riscv/autovec.md (floor<mode>2): New pattern. + * config/riscv/riscv-protos.h (enum insn_flags): New enum type. + (enum insn_type): Ditto. + (expand_vec_floor): New function decl. + * config/riscv/riscv-v.cc (gen_floor_const_fp): New function impl. + (expand_vec_floor): Ditto. + +2023-09-22 Pan Li <pan2.li@intel.com> + + * config/riscv/riscv-v.cc (expand_vec_float_cmp_mask): Refactor. + (emit_vec_float_cmp_mask): Rename. + (expand_vec_copysign): Ditto. + (emit_vec_copysign): Ditto. + (emit_vec_abs): New function impl. + (emit_vec_cvt_x_f): Ditto. + (emit_vec_cvt_f_x): Ditto. + (expand_vec_ceil): Ditto. + +2023-09-22 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/vector-iterators.md: Extend VLS modes. + +2023-09-22 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-v.cc (gen_const_vector_dup): Use global expand function. + * config/riscv/vector.md (@vec_duplicate<mode>): Remove @. + (vec_duplicate<mode>): Ditto. + +2023-09-22 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/autovec.md: Add VLS conditional patterns. + * config/riscv/riscv-protos.h (expand_cond_unop): Ditto. + (expand_cond_binop): Ditto. + (expand_cond_ternop): Ditto. + * config/riscv/riscv-v.cc (expand_cond_unop): Ditto. + (expand_cond_binop): Ditto. + (expand_cond_ternop): Ditto. + +2023-09-22 xuli <xuli1@eswincomputing.com> + + PR target/111451 + * config/riscv/riscv-v.cc (emit_vlmax_gather_insn): Optimization of vrgather.vv + into vrgatherei16.vv. + +2023-09-22 Lehua Ding <lehua.ding@rivai.ai> + + * config/riscv/autovec-opt.md (*cond_widen_reduc_plus_scal_<mode>): + New combine patterns. + * config/riscv/riscv-protos.h (enum insn_type): New insn_type. + +2023-09-22 Lehua Ding <lehua.ding@rivai.ai> + + * config/riscv/riscv-protos.h (enum avl_type): New VLS avl_type. + * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Move comments. + +2023-09-22 Pan Li <pan2.li@intel.com> + + * config/riscv/autovec.md (ceil<mode>2): New pattern. + * config/riscv/riscv-protos.h (enum insn_flags): New enum type. + (enum insn_type): Ditto. + (expand_vec_ceil): New function decl. + * config/riscv/riscv-v.cc (gen_ceil_const_fp): New function impl. + (expand_vec_float_cmp_mask): Ditto. + (expand_vec_copysign): Ditto. + (expand_vec_ceil): Ditto. + * config/riscv/vector.md: Add VLS mode support. + +2023-09-21 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/autovec.md: Extend VLS modes. + +2023-09-21 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/vector-iterators.md: Extend VLS modes. + +2023-09-21 Lehua Ding <lehua.ding@rivai.ai> + Robin Dapp <rdapp.gcc@gmail.com> + + * config/riscv/riscv-v.cc (emit_vlmax_insn): Adjust comments. + (emit_nonvlmax_insn): Adjust comments. + (emit_vlmax_insn_lra): Adjust comments. + +2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org> + + * config.gcc (*linux*): Set rust target_objs, and + target_has_targetrustm, + * config/t-linux (linux-rust.o): New rule. + * config/linux-rust.cc: New file. + +2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org> + + * config.gcc (i[34567]86-*-mingw* | x86_64-*-mingw*): Set + rust_target_objs and target_has_targetrustm. + * config/t-winnt (winnt-rust.o): New rule. + * config/winnt-rust.cc: New file. + +2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org> + + * config.gcc (*-*-fuchsia): Set tmake_rule, rust_target_objs, + and target_has_targetrustm. + * config/fuchsia-rust.cc: New file. + * config/t-fuchsia: New file. + +2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org> + + * config.gcc (*-*-vxworks*): Set rust_target_objs and + target_has_targetrustm. + * config/t-vxworks (vxworks-rust.o): New rule. + * config/vxworks-rust.cc: New file. + +2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org> + + * config.gcc (*-*-dragonfly*): Set rust_target_objs and + target_has_targetrustm. + * config/t-dragonfly (dragonfly-rust.o): New rule. + * config/dragonfly-rust.cc: New file. + +2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org> + + * config.gcc (*-*-solaris2*): Set rust_target_objs and + target_has_targetrustm. + * config/t-sol2 (sol2-rust.o): New rule. + * config/sol2-rust.cc: New file. + +2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org> + + * config.gcc (*-*-openbsd*): Set rust_target_objs and + target_has_targetrustm. + * config/t-openbsd (openbsd-rust.o): New rule. + * config/openbsd-rust.cc: New file. + +2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org> + + * config.gcc (*-*-netbsd*): Set rust_target_objs and + target_has_targetrustm. + * config/t-netbsd (netbsd-rust.o): New rule. + * config/netbsd-rust.cc: New file. + +2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org> + + * config.gcc (*-*-freebsd*): Set rust_target_objs and + target_has_targetrustm. + * config/t-freebsd (freebsd-rust.o): New rule. + * config/freebsd-rust.cc: New file. + +2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org> + + * config.gcc (*-*-darwin*): Set rust_target_objs and + target_has_targetrustm. + * config/t-darwin (darwin-rust.o): New rule. + * config/darwin-rust.cc: New file. + +2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org> + + * config/i386/t-i386 (i386-rust.o): New rule. + * config/i386/i386-rust.cc: New file. + * config/i386/i386-rust.h: New file. + +2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org> + + * doc/tm.texi: Regenerate. + * doc/tm.texi.in: Document TARGET_RUST_OS_INFO. + +2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org> + + * doc/tm.texi: Regenerate. + * doc/tm.texi.in: Add @node for Rust language and ABI, and document + TARGET_RUST_CPU_INFO. + +2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org> + + * Makefile.in (tm_rust_file_list, tm_rust_include_list, TM_RUST_H, + RUST_TARGET_DEF, RUST_TARGET_H, RUST_TARGET_OBJS): New variables. + (tm_rust.h, cs-tm_rust.h, default-rust.o, + rust/rust-target-hooks-def.h, s-rust-target-hooks-def-h): New rules. + (s-tm-texi): Also check timestamp on rust-target.def. + (generated_files): Add TM_RUST_H and rust-target-hooks-def.h. + (build/genhooks.o): Also depend on RUST_TARGET_DEF. + * config.gcc (tm_rust_file, rust_target_objs, target_has_targetrustm): + New variables. + * configure: Regenerate. + * configure.ac (tm_rust_file_list, tm_rust_include_list, + rust_target_objs): Add substitutes. + * doc/tm.texi: Regenerate. + * doc/tm.texi.in (targetrustm): Document. + (target_has_targetrustm): Document. + * genhooks.cc: Include rust/rust-target.def. + * config/default-rust.cc: New file. + +2023-09-21 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + PR target/110751 + * config/riscv/autovec.md: Enable scratch rtx in ELSE operand. + * config/riscv/predicates.md (autovec_else_operand): New predicate. + * config/riscv/riscv-v.cc (get_else_operand): New function. + (expand_cond_len_unop): Adapt ELSE value. + (expand_cond_len_binop): Ditto. + (expand_cond_len_ternop): Ditto. + * config/riscv/riscv.cc (riscv_preferred_else_value): New function. + (TARGET_PREFERRED_ELSE_VALUE): New targethook. + +2023-09-21 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + PR target/111486 + * config/riscv/riscv.cc (riscv_legitimize_move): Fix bug. + +2023-09-21 Jiufu Guo <guojiufu@linux.ibm.com> + + PR tree-optimization/111355 + * match.pd ((X + C) / N): Update pattern. + +2023-09-21 Jiufu Guo <guojiufu@linux.ibm.com> + + * match.pd ((t * 2) / 2): Update to use overflow_free_p. + +2023-09-21 xuli <xuli1@eswincomputing.com> + + PR target/111450 + * config/riscv/constraints.md (c01): const_int 1. + (c02): const_int 2. + (c04): const_int 4. + (c08): const_int 8. + * config/riscv/predicates.md (vector_eew8_stride_operand): New predicate for stride operand. + (vector_eew16_stride_operand): Ditto. + (vector_eew32_stride_operand): Ditto. + (vector_eew64_stride_operand): Ditto. + * config/riscv/vector-iterators.md: New iterator for stride operand. + * config/riscv/vector.md: Add stride = element width constraint. + +2023-09-21 Lehua Ding <lehua.ding@rivai.ai> + + * config/riscv/predicates.md (const_1_or_2_operand): Rename. + (const_1_or_4_operand): Ditto. + (vector_gs_scale_operand_16): Ditto. + (vector_gs_scale_operand_32): Ditto. + * config/riscv/vector-iterators.md: Adjust. + +2023-09-21 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/autovec.md: Extend VLS modes. + * config/riscv/vector-iterators.md: Ditto. + * config/riscv/vector.md: Ditto. + 2023-09-20 Andrew MacLeod <amacleod@redhat.com> * gimple-range-cache.cc (ssa_cache::merge_range): Change meaning diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 707983c..7cf5e25 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20230921 +20230928 diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index 056adce..f549aa2 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,83 @@ +2023-09-26 Eric Botcazou <ebotcazou@adacore.com> + + * exp_ch7.adb (Build_Finalizer.Process_Declarations): Remove call + to Is_Simple_Protected_Type as redundant. + (Build_Finalizer.Process_Object_Declaration): Do not retrieve the + corresponding record type for simple protected objects. Make the + flow of control more explicit in their specific processing. + * exp_util.adb (Requires_Cleanup_Actions): Return false for simple + protected objects present in library-level package bodies for the + sake of consistency with Build_Finalizer and remove call to + Is_Simple_Protected_Type as redundant. + +2023-09-26 Eric Botcazou <ebotcazou@adacore.com> + + PR ada/110488 + * sem_ch3.adb (Analyze_Object_Declaration): Do not build a default + subtype for a deferred constant in the definite case too. + +2023-09-26 Marc Poulhiès <poulhies@adacore.com> + + * exp_ch7.adb (Contains_Subprogram): Recursively search for subp + in loop's statements. + (Unnest_Loop)<Fixup_Inner_Scopes>: New. + (Unnest_Loop): Rename local variable for more clarity. + * exp_unst.ads: Refresh comment. + +2023-09-26 Javier Miranda <miranda@adacore.com> + + * exp_ch6.adb (Expand_Call_Helper): When computing the + accessibility level of an actual parameter based on the + expresssion of a constant declaration, add missing support for + deferred constants + +2023-09-26 Eric Botcazou <ebotcazou@adacore.com> + + * einfo.ads (Status_Flag_Or_Transient_Decl): Remove ??? comment. + * exp_ch6.adb (Expand_N_Extended_Return_Statement): Extend the + handling of finalizable return objects to the non-BIP case. + * exp_ch7.adb (Build_Finalizer.Process_Declarations): Adjust the + comment accordingly. + * exp_util.adb (Requires_Cleanup_Actions): Likewise. + +2023-09-26 Daniel King <dmking@adacore.com> + + * raise-gcc.c (get_ip_from_context): Adapt for CHERI purecap + (get_call_site_action_for): Adapt for CHERI purecap + +2023-09-26 Daniel King <dmking@adacore.com> + + * libgnat/a-tags.adb (To_Tag): Use System.Storage_Elements for + integer to address conversion. + * libgnat/s-putima.adb (Put_Image_Pointer): Likewise. + +2023-09-26 Daniel King <dmking@adacore.com> + + * libgnat/s-stratt__cheri.adb: New file + +2023-09-26 Daniel King <dmking@adacore.com> + + * libgnat/i-cheri.ads (Capability_Bound_Error) + (Capability_Permission_Error, Capability_Sealed_Error) + (Capability_Tag_Error): New, define CHERI exception types. + +2023-09-26 Ronan Desplanques <desplanques@adacore.com> + + * exp_prag.adb: Make minor corrections in comments. + * rtsfind.ads: Remove unused element from RTU_Id definition. + +2023-09-26 Derek Schacht <schacht@adacore.com> + + * doc/gnat_ugn/gnat_and_program_execution.rst: Add more details on + using Generic Elementary Functions with dimensional analysis. + * gnat_ugn.texi: Regenerate. + +2023-09-26 Yannick Moy <moy@adacore.com> + + * exp_ch5.adb (Expand_N_Case_Statement): Reference both sections + of the Ada RM that deal with case statements and case expressions + to justify the insertion of a runtime check. + 2023-09-19 Richard Wai <richard@annexi-strayline.com> * exp_ch3.adb (Expand_Freeze_Class_Wide_Type): Expanded comments diff --git a/gcc/ada/doc/gnat_ugn/gnat_and_program_execution.rst b/gcc/ada/doc/gnat_ugn/gnat_and_program_execution.rst index 62abca2..35e3477 100644 --- a/gcc/ada/doc/gnat_ugn/gnat_and_program_execution.rst +++ b/gcc/ada/doc/gnat_ugn/gnat_and_program_execution.rst @@ -3294,6 +3294,18 @@ requires ``DV(Source)`` = ``DV(Target)``, and analogously for parameter passing (the dimension vector for the actual parameter must be equal to the dimension vector for the formal parameter). +When using dimensioned types with elementary functions it is necessary to +instantiate the ``Ada.Numerics.Generic_Elementary_Functions`` package using +the ``Mks_Type`` and not any of the derived subtypes such as ``Distance``. +For functions such as ``Sqrt`` the dimensional analysis will fail when using +the subtypes because both the parameter and return are of the same type. + +An example instantiation + + .. code-block:: ada + + package Mks_Numerics is new + Ada.Numerics.Generic_Elementary_Functions (System.Dim.Mks.Mks_Type); .. _Stack_Related_Facilities: diff --git a/gcc/ada/einfo.ads b/gcc/ada/einfo.ads index 9773928..9165fb7 100644 --- a/gcc/ada/einfo.ads +++ b/gcc/ada/einfo.ads @@ -4518,11 +4518,11 @@ package Einfo is -- Status_Flag_Or_Transient_Decl -- Defined in constant, loop, and variable entities. Applies to objects -- that require special treatment by the finalization machinery, such as --- extended return results, IF and CASE expression results, and objects +-- extended return objects, conditional expression results, and objects -- inside N_Expression_With_Actions nodes. The attribute contains the --- entity of a flag which specifies particular behavior over a region of --- code or the declaration of a "hook" object. --- In which case is it a flag, or a hook object??? +-- entity of a flag which specifies a particular behavior over a region +-- of the extended return for the return objects, or the declaration of a +-- hook object for conditional expressions and N_Expression_With_Actions. -- Storage_Size_Variable [implementation base type only] -- Defined in access types and task type entities. This flag is set diff --git a/gcc/ada/exp_ch5.adb b/gcc/ada/exp_ch5.adb index d55fdb3..cd3b02b 100644 --- a/gcc/ada/exp_ch5.adb +++ b/gcc/ada/exp_ch5.adb @@ -4092,8 +4092,9 @@ package body Exp_Ch5 is end if; -- First step is to worry about possible invalid argument. The RM - -- requires (RM 5.4(13)) that if the result is invalid (e.g. it is - -- outside the base range), then Constraint_Error must be raised. + -- requires (RM 4.5.7 (21/3) and 5.4 (13)) that if the result is + -- invalid (e.g. it is outside the base range), then Constraint_Error + -- must be raised. -- Case of validity check required (validity checks are on, the -- expression is not known to be valid, and the case statement @@ -4274,7 +4275,7 @@ package body Exp_Ch5 is -- If Predicates_Ignored is true the value does not satisfy the -- predicate, and there is no Others choice, Constraint_Error - -- must be raised (4.5.7 (21/3)). + -- must be raised (RM 4.5.7 (21/3) and 5.4 (13)). if Predicates_Ignored (Etype (Expr)) then declare diff --git a/gcc/ada/exp_ch6.adb b/gcc/ada/exp_ch6.adb index a16dfe2..c1d5fa3 100644 --- a/gcc/ada/exp_ch6.adb +++ b/gcc/ada/exp_ch6.adb @@ -4352,13 +4352,23 @@ package body Exp_Ch6 is -- Generate the accessibility level based on the expression in -- the constant's declaration. - Add_Extra_Actual - (Expr => Accessibility_Level - (Expr => Expression - (Parent (Entity (Prev))), - Level => Dynamic_Level, - Allow_Alt_Model => False), - EF => Extra_Accessibility (Formal)); + declare + Ent : Entity_Id := Entity (Prev); + + begin + -- Handle deferred constants + + if Present (Full_View (Ent)) then + Ent := Full_View (Ent); + end if; + + Add_Extra_Actual + (Expr => Accessibility_Level + (Expr => Expression (Parent (Ent)), + Level => Dynamic_Level, + Allow_Alt_Model => False), + EF => Extra_Accessibility (Formal)); + end; -- Normal case @@ -5607,7 +5617,7 @@ package body Exp_Ch6 is -- with the scope finalizer. There is one flag per each return object -- in case of multiple returns. - if Is_BIP_Func and then Needs_Finalization (Etype (Ret_Obj_Id)) then + if Needs_Finalization (Etype (Ret_Obj_Id)) then declare Flag_Decl : Node_Id; Flag_Id : Entity_Id; @@ -5706,7 +5716,7 @@ package body Exp_Ch6 is -- Update the state of the function right before the object is -- returned. - if Is_BIP_Func and then Needs_Finalization (Etype (Ret_Obj_Id)) then + if Needs_Finalization (Etype (Ret_Obj_Id)) then declare Flag_Id : constant Entity_Id := Status_Flag_Or_Transient_Decl (Ret_Obj_Id); diff --git a/gcc/ada/exp_ch7.adb b/gcc/ada/exp_ch7.adb index 4ea5e6e..5049de54 100644 --- a/gcc/ada/exp_ch7.adb +++ b/gcc/ada/exp_ch7.adb @@ -2356,8 +2356,7 @@ package body Exp_Ch7 is elsif Ekind (Obj_Id) = E_Variable and then not In_Library_Level_Package_Body (Obj_Id) - and then (Is_Simple_Protected_Type (Obj_Typ) - or else Has_Simple_Protected_Object (Obj_Typ)) + and then Has_Simple_Protected_Object (Obj_Typ) then Processing_Actions (Is_Protected => True); end if; @@ -2381,9 +2380,9 @@ package body Exp_Ch7 is elsif Is_Ignored_Ghost_Entity (Obj_Id) then null; - -- Return object of a build-in-place function. This case is - -- recognized and marked by the expansion of an extended return - -- statement (see Expand_N_Extended_Return_Statement). + -- Return object of extended return statements. This case is + -- recognized and marked by the expansion of extended return + -- statements (see Expand_N_Extended_Return_Statement). elsif Needs_Finalization (Obj_Typ) and then Is_Return_Object (Obj_Id) @@ -3006,7 +3005,9 @@ package body Exp_Ch7 is -- Start of processing for Process_Object_Declaration begin - -- Handle the object type and the reference to the object + -- Handle the object type and the reference to the object. Note + -- that objects having simple protected components must retain + -- their original form for the processing below to work. Obj_Ref := New_Occurrence_Of (Obj_Id, Loc); Obj_Typ := Base_Type (Etype (Obj_Id)); @@ -3018,6 +3019,7 @@ package body Exp_Ch7 is elsif Is_Concurrent_Type (Obj_Typ) and then Present (Corresponding_Record_Type (Obj_Typ)) + and then not Is_Protected then Obj_Typ := Corresponding_Record_Type (Obj_Typ); Obj_Ref := Unchecked_Convert_To (Obj_Typ, Obj_Ref); @@ -3180,12 +3182,11 @@ package body Exp_Ch7 is Fin_Stmts := New_List (Fin_Call); end if; - elsif Has_Simple_Protected_Object (Obj_Typ) then - if Is_Record_Type (Obj_Typ) then - Fin_Stmts := Cleanup_Record (Decl, Obj_Ref, Obj_Typ); - elsif Is_Array_Type (Obj_Typ) then - Fin_Stmts := Cleanup_Array (Decl, Obj_Ref, Obj_Typ); - end if; + elsif Is_Array_Type (Obj_Typ) then + Fin_Stmts := Cleanup_Array (Decl, Obj_Ref, Obj_Typ); + + else + Fin_Stmts := Cleanup_Record (Decl, Obj_Ref, Obj_Typ); end if; -- Generate: @@ -4378,6 +4379,32 @@ package body Exp_Ch7 is begin E := First_Entity (Blk); + -- The compiler may generate loops with a declare block containing + -- nested procedures used for finalization. Recursively search for + -- subprograms in such constructs. + + if Ekind (Blk) = E_Loop + and then Parent_Kind (Blk) = N_Loop_Statement + then + declare + Stmt : Node_Id := First (Statements (Parent (Blk))); + begin + while Present (Stmt) loop + if Nkind (Stmt) = N_Block_Statement then + declare + Id : constant Entity_Id := + Entity (Identifier (Stmt)); + begin + if Contains_Subprogram (Id) then + return True; + end if; + end; + end if; + Next (Stmt); + end loop; + end; + end if; + while Present (E) loop if Is_Subprogram (E) then return True; @@ -9350,17 +9377,67 @@ package body Exp_Ch7 is ----------------- procedure Unnest_Loop (Loop_Stmt : Node_Id) is + + procedure Fixup_Inner_Scopes (Loop_Stmt : Node_Id); + -- The loops created by the compiler for array aggregates can have + -- nested finalization procedure when the type of the array components + -- needs finalization. It has the following form: + + -- for J4b in 10 .. 12 loop + -- declare + -- procedure __finalizer; + -- begin + -- procedure __finalizer is + -- ... + -- end; + -- ... + -- obj (J4b) := ...; + + -- When the compiler creates the N_Block_Statement, it sets its scope to + -- the upper scope (the one containing the loop). + + -- The Unnest_Loop procedure moves the N_Loop_Statement inside a new + -- procedure and correctly sets the scopes for both the new procedure + -- and the loop entity. The inner block scope is not modified and this + -- leaves the Tree in an incoherent state (i.e. the inner procedure must + -- have its enclosing procedure in its scope ancestries). + + -- This procedure fixes the scope links. + + -- Another (better) fix would be to have the block scope set to be the + -- loop entity earlier (when the block is created or when the loop gets + -- an actual entity set). But unfortunately this proved harder to + -- implement ??? + + procedure Fixup_Inner_Scopes (Loop_Stmt : Node_Id) is + Stmt : Node_Id := First (Statements (Loop_Stmt)); + Loop_Stmt_Ent : constant Entity_Id := Entity (Identifier (Loop_Stmt)); + Ent_To_Fix : Entity_Id; + begin + while Present (Stmt) loop + if Nkind (Stmt) = N_Block_Statement + and then Is_Abort_Block (Stmt) + then + Ent_To_Fix := Entity (Identifier (Stmt)); + Set_Scope (Ent_To_Fix, Loop_Stmt_Ent); + elsif Nkind (Stmt) = N_Loop_Statement then + Fixup_Inner_Scopes (Stmt); + end if; + Next (Stmt); + end loop; + end Fixup_Inner_Scopes; + Loc : constant Source_Ptr := Sloc (Loop_Stmt); Ent : Entity_Id; Local_Body : Node_Id; Local_Call : Node_Id; + Loop_Ent : Entity_Id; Local_Proc : Entity_Id; - Local_Scop : Entity_Id; Loop_Copy : constant Node_Id := Relocate_Node (Loop_Stmt); begin - Local_Scop := Entity (Identifier (Loop_Stmt)); - Ent := First_Entity (Local_Scop); + Loop_Ent := Entity (Identifier (Loop_Stmt)); + Ent := First_Entity (Loop_Ent); Local_Proc := Make_Temporary (Loc, 'P'); @@ -9389,8 +9466,10 @@ package body Exp_Ch7 is -- New procedure has the same scope as the original loop, and the scope -- of the loop is the new procedure. - Set_Scope (Local_Proc, Scope (Local_Scop)); - Set_Scope (Local_Scop, Local_Proc); + Set_Scope (Local_Proc, Scope (Loop_Ent)); + Set_Scope (Loop_Ent, Local_Proc); + + Fixup_Inner_Scopes (Loop_Copy); -- The entity list of the new procedure is that of the loop diff --git a/gcc/ada/exp_prag.adb b/gcc/ada/exp_prag.adb index 1cc4653..d2807cd 100644 --- a/gcc/ada/exp_prag.adb +++ b/gcc/ada/exp_prag.adb @@ -685,7 +685,7 @@ package body Exp_Prag is -- Blocks_Id'address, -- Mem_Id'address, -- Stream_Id'address), - -- CUDA.Runtime_Api.Launch_Kernel ( + -- CUDA.Internal.Launch_Kernel ( -- My_Proc'Address, -- Blocks_Id, -- Grids_Id, @@ -703,7 +703,7 @@ package body Exp_Prag is Decls : List_Id; Copies : Elist_Id); -- For each parameter in list Params, create an object declaration of - -- the followinng form: + -- the following form: -- -- Copy_Id : Param_Typ := Param_Val; -- @@ -755,8 +755,8 @@ package body Exp_Prag is Kernel_Arg : Entity_Id; Memory : Entity_Id; Stream : Entity_Id) return Node_Id; - -- Builds and returns a call to CUDA.Launch_Kernel using the given - -- arguments. Proc is the entity of the procedure passed to the + -- Builds and returns a call to CUDA.Internal.Launch_Kernel using the + -- given arguments. Proc is the entity of the procedure passed to the -- CUDA_Execute pragma. Grid_Dims and Block_Dims are entities of the -- generated declarations that hold the kernel's dimensions. Args is the -- entity of the temporary array that holds the arguments of the kernel. diff --git a/gcc/ada/exp_unst.ads b/gcc/ada/exp_unst.ads index 40d2257..0538535 100644 --- a/gcc/ada/exp_unst.ads +++ b/gcc/ada/exp_unst.ads @@ -42,11 +42,8 @@ package Exp_Unst is -- references, and implements an appropriate static chain approach to -- dealing with such uplevel references. - -- However, we also want to be able to interface with back ends that do - -- not easily handle such uplevel references. One example is the back end - -- that translates the tree into standard C source code. In the future, - -- other back ends might need the same capability (e.g. a back end that - -- generated LLVM intermediate code). + -- However, we also want to be able to interface with back ends that do not + -- easily handle such uplevel references. One example is the LLVM back end. -- We could imagine simply handling such references in the appropriate -- back end. For example the back end that generates C could recognize diff --git a/gcc/ada/exp_util.adb b/gcc/ada/exp_util.adb index 2e6a1cf..1aff5a0 100644 --- a/gcc/ada/exp_util.adb +++ b/gcc/ada/exp_util.adb @@ -13100,10 +13100,38 @@ package body Exp_Util is -- Simple protected objects which use type System.Tasking. -- Protected_Objects.Protection to manage their locks should be -- treated as controlled since they require manual cleanup. + -- The only exception is illustrated in the following example: + + -- package Pkg is + -- type Ctrl is new Controlled ... + -- procedure Finalize (Obj : in out Ctrl); + -- Lib_Obj : Ctrl; + -- end Pkg; + + -- package body Pkg is + -- protected Prot is + -- procedure Do_Something (Obj : in out Ctrl); + -- end Prot; + + -- protected body Prot is + -- procedure Do_Something (Obj : in out Ctrl) is ... + -- end Prot; + + -- procedure Finalize (Obj : in out Ctrl) is + -- begin + -- Prot.Do_Something (Obj); + -- end Finalize; + -- end Pkg; + + -- Since for the most part entities in package bodies depend on + -- those in package specs, Prot's lock should be cleaned up + -- first. The subsequent cleanup of the spec finalizes Lib_Obj. + -- This act however attempts to invoke Do_Something and fails + -- because the lock has disappeared. elsif Ekind (Obj_Id) = E_Variable - and then (Is_Simple_Protected_Type (Obj_Typ) - or else Has_Simple_Protected_Object (Obj_Typ)) + and then not In_Library_Level_Package_Body (Obj_Id) + and then Has_Simple_Protected_Object (Obj_Typ) then return True; end if; @@ -13127,9 +13155,9 @@ package body Exp_Util is elsif Is_Ignored_Ghost_Entity (Obj_Id) then null; - -- Return object of a build-in-place function. This case is - -- recognized and marked by the expansion of an extended return - -- statement (see Expand_N_Extended_Return_Statement). + -- Return object of extended return statements. This case is + -- recognized and marked by the expansion of extended return + -- statements (see Expand_N_Extended_Return_Statement). elsif Needs_Finalization (Obj_Typ) and then Is_Return_Object (Obj_Id) diff --git a/gcc/ada/gnat_ugn.texi b/gcc/ada/gnat_ugn.texi index 7c5926e..1562bee 100644 --- a/gcc/ada/gnat_ugn.texi +++ b/gcc/ada/gnat_ugn.texi @@ -19,7 +19,7 @@ @copying @quotation -GNAT User's Guide for Native Platforms , Aug 31, 2023 +GNAT User's Guide for Native Platforms , Sep 26, 2023 AdaCore @@ -15510,7 +15510,6 @@ Linker to be used. The default is @code{bfd} for @code{ld.bfd}; @code{gold} (for @code{ld.gold}) and @code{mold} (for @code{ld.mold}) are more recent and faster alternatives, but only available on GNU/Linux platforms. - @end table @node Binding with gnatbind,Linking with gnatlink,Linker Switches,Building Executable Programs with GNAT @@ -22093,6 +22092,22 @@ requires @code{DV(Source)} = @code{DV(Target)}, and analogously for parameter passing (the dimension vector for the actual parameter must be equal to the dimension vector for the formal parameter). +When using dimensioned types with elementary functions it is necessary to +instantiate the @code{Ada.Numerics.Generic_Elementary_Functions} package using +the @code{Mks_Type} and not any of the derived subtypes such as @code{Distance}. +For functions such as @code{Sqrt} the dimensional analysis will fail when using +the subtypes because both the parameter and return are of the same type. + +An example instantiation + +@quotation + +@example +package Mks_Numerics is new + Ada.Numerics.Generic_Elementary_Functions (System.Dim.Mks.Mks_Type); +@end example +@end quotation + @node Stack Related Facilities,Memory Management Issues,Performing Dimensionality Analysis in GNAT,GNAT and Program Execution @anchor{gnat_ugn/gnat_and_program_execution id52}@anchor{14d}@anchor{gnat_ugn/gnat_and_program_execution stack-related-facilities}@anchor{1aa} @section Stack Related Facilities diff --git a/gcc/ada/libgnat/a-tags.adb b/gcc/ada/libgnat/a-tags.adb index 3590785..1ffc78e 100644 --- a/gcc/ada/libgnat/a-tags.adb +++ b/gcc/ada/libgnat/a-tags.adb @@ -93,7 +93,10 @@ package body Ada.Tags is -- Disable warnings on possible aliasing problem function To_Tag is - new Unchecked_Conversion (Integer_Address, Tag); + new Unchecked_Conversion (System.Address, Tag); + + function To_Tag (S : Integer_Address) return Tag is + (To_Tag (To_Address (S))); function To_Dispatch_Table_Ptr is new Ada.Unchecked_Conversion (Tag, Dispatch_Table_Ptr); diff --git a/gcc/ada/libgnat/i-cheri.ads b/gcc/ada/libgnat/i-cheri.ads index 547b033..8098521 100644 --- a/gcc/ada/libgnat/i-cheri.ads +++ b/gcc/ada/libgnat/i-cheri.ads @@ -467,4 +467,20 @@ is External_Name => "__builtin_cheri_stack_get"; -- Get the Capability Stack Pointer (CSP) + --------------------------- + -- Capability Exceptions -- + --------------------------- + + Capability_Bound_Error : exception; + -- An out-of-bounds access was attempted + + Capability_Permission_Error : exception; + -- An attempted access exceeded the permissions granted by a capability + + Capability_Sealed_Error : exception; + -- A sealed capability was dereferenced + + Capability_Tag_Error : exception; + -- An invalid capability was dereferenced + end Interfaces.CHERI; diff --git a/gcc/ada/libgnat/s-putima.adb b/gcc/ada/libgnat/s-putima.adb index 1d6e608..bcc7af2 100644 --- a/gcc/ada/libgnat/s-putima.adb +++ b/gcc/ada/libgnat/s-putima.adb @@ -32,7 +32,7 @@ with Ada.Strings.Text_Buffers.Utils; use Ada.Strings.Text_Buffers; use Ada.Strings.Text_Buffers.Utils; -with Ada.Unchecked_Conversion; +with System.Storage_Elements; use System.Storage_Elements; package body System.Put_Images is @@ -132,15 +132,13 @@ package body System.Put_Images is procedure Put_Image_Pointer (S : in out Sink'Class; X : Pointer; Type_Kind : String) is - function Cast is new Ada.Unchecked_Conversion - (System.Address, Unsigned_Address); begin if X = null then Put_UTF_8 (S, "null"); else Put_UTF_8 (S, "("); Put_UTF_8 (S, Type_Kind); - Hex.Put_Image (S, Cast (X.all'Address)); + Hex.Put_Image (S, Unsigned_Address (To_Integer (X.all'Address))); Put_UTF_8 (S, ")"); end if; end Put_Image_Pointer; diff --git a/gcc/ada/libgnat/s-stratt__cheri.adb b/gcc/ada/libgnat/s-stratt__cheri.adb new file mode 100644 index 0000000..f753cf3 --- /dev/null +++ b/gcc/ada/libgnat/s-stratt__cheri.adb @@ -0,0 +1,1019 @@ +------------------------------------------------------------------------------ +-- -- +-- GNAT RUN-TIME COMPONENTS -- +-- -- +-- S Y S T E M . S T R E A M _ A T T R I B U T E S -- +-- -- +-- B o d y -- +-- -- +-- Copyright (C) 1992-2023, Free Software Foundation, Inc. -- +-- -- +-- GNAT is free software; you can redistribute it and/or modify it under -- +-- terms of the GNU General Public License as published by the Free Soft- -- +-- ware Foundation; either version 3, or (at your option) any later ver- -- +-- sion. GNAT is distributed in the hope that it will be useful, but WITH- -- +-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- +-- or FITNESS FOR A PARTICULAR PURPOSE. -- +-- -- +-- As a special exception under Section 7 of GPL version 3, you are granted -- +-- additional permissions described in the GCC Runtime Library Exception, -- +-- version 3.1, as published by the Free Software Foundation. -- +-- -- +-- You should have received a copy of the GNU General Public License and -- +-- a copy of the GCC Runtime Library Exception along with this program; -- +-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -- +-- <http://www.gnu.org/licenses/>. -- +-- -- +-- GNAT was originally developed by the GNAT team at New York University. -- +-- Extensive contributions were provided by Ada Core Technologies Inc. -- +-- -- +------------------------------------------------------------------------------ + +-- This is the CHERI variant of this package + +with Ada.IO_Exceptions; +with Ada.Streams; use Ada.Streams; +with Ada.Unchecked_Conversion; +with System.Stream_Attributes.XDR; + +package body System.Stream_Attributes is + + XDR_Stream : constant Integer; + pragma Import (C, XDR_Stream, "__gl_xdr_stream"); + -- This imported value is used to determine whether the build had the + -- binder switch "-xdr" present which enables XDR streaming and sets this + -- flag to 1. + + function XDR_Support return Boolean is (XDR_Stream = 1); + pragma Inline (XDR_Support); + -- Return True if XDR streaming should be used. Note that 128-bit integers + -- are not supported by the XDR protocol and will raise Device_Error. + + Err : exception renames Ada.IO_Exceptions.End_Error; + -- Exception raised if insufficient data read (note that the RM implies + -- that Data_Error might be the appropriate choice, but AI95-00132 + -- decides with a binding interpretation that End_Error is preferred). + + SU : constant := System.Storage_Unit; + + subtype SEA is Ada.Streams.Stream_Element_Array; + subtype SEO is Ada.Streams.Stream_Element_Offset; + + generic function UC renames Ada.Unchecked_Conversion; + + -- Subtypes used to define Stream_Element_Array values that map + -- into the elementary types, using unchecked conversion. + + Thin_Pointer_Size : constant := System.Address'Size; + Fat_Pointer_Size : constant := System.Address'Size * 2; + + subtype S_AD is SEA (1 .. (Fat_Pointer_Size + SU - 1) / SU); + subtype S_AS is SEA (1 .. (Thin_Pointer_Size + SU - 1) / SU); + subtype S_B is SEA (1 .. (Boolean'Size + SU - 1) / SU); + subtype S_C is SEA (1 .. (Character'Size + SU - 1) / SU); + subtype S_F is SEA (1 .. (Float'Size + SU - 1) / SU); + subtype S_I is SEA (1 .. (Integer'Size + SU - 1) / SU); + subtype S_I24 is SEA (1 .. (Integer_24'Size + SU - 1) / SU); + subtype S_LF is SEA (1 .. (Long_Float'Size + SU - 1) / SU); + subtype S_LI is SEA (1 .. (Long_Integer'Size + SU - 1) / SU); + subtype S_LLF is SEA (1 .. (Long_Long_Float'Size + SU - 1) / SU); + subtype S_LLI is SEA (1 .. (Long_Long_Integer'Size + SU - 1) / SU); + subtype S_LLLI is SEA (1 .. (Long_Long_Long_Integer'Size + SU - 1) / SU); + subtype S_LLLU is + SEA (1 .. (UST.Long_Long_Long_Unsigned'Size + SU - 1) / SU); + subtype S_LLU is SEA (1 .. (UST.Long_Long_Unsigned'Size + SU - 1) / SU); + subtype S_LU is SEA (1 .. (UST.Long_Unsigned'Size + SU - 1) / SU); + subtype S_SF is SEA (1 .. (Short_Float'Size + SU - 1) / SU); + subtype S_SI is SEA (1 .. (Short_Integer'Size + SU - 1) / SU); + subtype S_SSI is SEA (1 .. (Short_Short_Integer'Size + SU - 1) / SU); + subtype S_SSU is SEA (1 .. (UST.Short_Short_Unsigned'Size + SU - 1) / SU); + subtype S_SU is SEA (1 .. (UST.Short_Unsigned'Size + SU - 1) / SU); + subtype S_U is SEA (1 .. (UST.Unsigned'Size + SU - 1) / SU); + subtype S_U24 is SEA (1 .. (Unsigned_24'Size + SU - 1) / SU); + subtype S_WC is SEA (1 .. (Wide_Character'Size + SU - 1) / SU); + subtype S_WWC is SEA (1 .. (Wide_Wide_Character'Size + SU - 1) / SU); + + -- Unchecked conversions from the elementary type to the stream type + + function From_AD is new UC (Fat_Pointer, S_AD); + function From_AS is new UC (Thin_Pointer, S_AS); + function From_F is new UC (Float, S_F); + function From_I is new UC (Integer, S_I); + function From_I24 is new UC (Integer_24, S_I24); + function From_LF is new UC (Long_Float, S_LF); + function From_LI is new UC (Long_Integer, S_LI); + function From_LLF is new UC (Long_Long_Float, S_LLF); + function From_LLI is new UC (Long_Long_Integer, S_LLI); + function From_LLLI is new UC (Long_Long_Long_Integer, S_LLLI); + function From_LLLU is new UC (UST.Long_Long_Long_Unsigned, S_LLLU); + function From_LLU is new UC (UST.Long_Long_Unsigned, S_LLU); + function From_LU is new UC (UST.Long_Unsigned, S_LU); + function From_SF is new UC (Short_Float, S_SF); + function From_SI is new UC (Short_Integer, S_SI); + function From_SSI is new UC (Short_Short_Integer, S_SSI); + function From_SSU is new UC (UST.Short_Short_Unsigned, S_SSU); + function From_SU is new UC (UST.Short_Unsigned, S_SU); + function From_U is new UC (UST.Unsigned, S_U); + function From_U24 is new UC (Unsigned_24, S_U24); + function From_WC is new UC (Wide_Character, S_WC); + function From_WWC is new UC (Wide_Wide_Character, S_WWC); + + -- Unchecked conversions from the stream type to elementary type + + function To_F is new UC (S_F, Float); + function To_I is new UC (S_I, Integer); + function To_I24 is new UC (S_I24, Integer_24); + function To_LF is new UC (S_LF, Long_Float); + function To_LI is new UC (S_LI, Long_Integer); + function To_LLF is new UC (S_LLF, Long_Long_Float); + function To_LLI is new UC (S_LLI, Long_Long_Integer); + function To_LLLI is new UC (S_LLLI, Long_Long_Long_Integer); + function To_LLLU is new UC (S_LLLU, UST.Long_Long_Long_Unsigned); + function To_LLU is new UC (S_LLU, UST.Long_Long_Unsigned); + function To_LU is new UC (S_LU, UST.Long_Unsigned); + function To_SF is new UC (S_SF, Short_Float); + function To_SI is new UC (S_SI, Short_Integer); + function To_SSI is new UC (S_SSI, Short_Short_Integer); + function To_SSU is new UC (S_SSU, UST.Short_Short_Unsigned); + function To_SU is new UC (S_SU, UST.Short_Unsigned); + function To_U is new UC (S_U, UST.Unsigned); + function To_U24 is new UC (S_U24, Unsigned_24); + function To_WC is new UC (S_WC, Wide_Character); + function To_WWC is new UC (S_WWC, Wide_Wide_Character); + + ----------------- + -- Block_IO_OK -- + ----------------- + + function Block_IO_OK return Boolean is + begin + return not XDR_Support; + end Block_IO_OK; + + ---------- + -- I_AD -- + ---------- + + function I_AD (Stream : not null access RST) return Fat_Pointer is + pragma Unreferenced (Stream); + begin + raise Program_Error with "Operation not supported on CHERI targets"; + + return Fat_Pointer'(Null_Address, Null_Address); + end I_AD; + + ---------- + -- I_AS -- + ---------- + + function I_AS (Stream : not null access RST) return Thin_Pointer is + pragma Unreferenced (Stream); + begin + raise Program_Error with "Operation not supported on CHERI targets"; + + return Null_Address; + end I_AS; + + --------- + -- I_B -- + --------- + + function I_B (Stream : not null access RST) return Boolean is + T : S_B; + L : SEO; + + begin + if XDR_Support then + return XDR.I_B (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return Boolean'Val (T (1)); + end if; + end I_B; + + --------- + -- I_C -- + --------- + + function I_C (Stream : not null access RST) return Character is + T : S_C; + L : SEO; + + begin + if XDR_Support then + return XDR.I_C (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return Character'Val (T (1)); + end if; + end I_C; + + --------- + -- I_F -- + --------- + + function I_F (Stream : not null access RST) return Float is + T : S_F; + L : SEO; + + begin + if XDR_Support then + return XDR.I_F (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_F (T); + end if; + end I_F; + + --------- + -- I_I -- + --------- + + function I_I (Stream : not null access RST) return Integer is + T : S_I; + L : SEO; + + begin + if XDR_Support then + return XDR.I_I (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_I (T); + end if; + end I_I; + + ----------- + -- I_I24 -- + ----------- + + function I_I24 (Stream : not null access RST) return Integer_24 is + T : S_I24; + L : SEO; + + begin + if XDR_Support then + return XDR.I_I24 (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_I24 (T); + end if; + end I_I24; + + ---------- + -- I_LF -- + ---------- + + function I_LF (Stream : not null access RST) return Long_Float is + T : S_LF; + L : SEO; + + begin + if XDR_Support then + return XDR.I_LF (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_LF (T); + end if; + end I_LF; + + ---------- + -- I_LI -- + ---------- + + function I_LI (Stream : not null access RST) return Long_Integer is + T : S_LI; + L : SEO; + + begin + if XDR_Support then + return XDR.I_LI (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_LI (T); + end if; + end I_LI; + + ----------- + -- I_LLF -- + ----------- + + function I_LLF (Stream : not null access RST) return Long_Long_Float is + T : S_LLF; + L : SEO; + + begin + if XDR_Support then + return XDR.I_LLF (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_LLF (T); + end if; + end I_LLF; + + ----------- + -- I_LLI -- + ----------- + + function I_LLI (Stream : not null access RST) return Long_Long_Integer is + T : S_LLI; + L : SEO; + + begin + if XDR_Support then + return XDR.I_LLI (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_LLI (T); + end if; + end I_LLI; + + ------------ + -- I_LLLI -- + ------------ + + function I_LLLI (Stream : not null access RST) return Long_Long_Long_Integer + is + T : S_LLLI; + L : SEO; + + begin + if XDR_Support then + raise Ada.IO_Exceptions.Device_Error; + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_LLLI (T); + end if; + end I_LLLI; + + ------------ + -- I_LLLU -- + ------------ + + function I_LLLU + (Stream : not null access RST) return UST.Long_Long_Long_Unsigned + is + T : S_LLLU; + L : SEO; + + begin + if XDR_Support then + raise Ada.IO_Exceptions.Device_Error; + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_LLLU (T); + end if; + end I_LLLU; + + ----------- + -- I_LLU -- + ----------- + + function I_LLU + (Stream : not null access RST) return UST.Long_Long_Unsigned + is + T : S_LLU; + L : SEO; + + begin + if XDR_Support then + return XDR.I_LLU (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_LLU (T); + end if; + end I_LLU; + + ---------- + -- I_LU -- + ---------- + + function I_LU (Stream : not null access RST) return UST.Long_Unsigned is + T : S_LU; + L : SEO; + + begin + if XDR_Support then + return XDR.I_LU (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_LU (T); + end if; + end I_LU; + + ---------- + -- I_SF -- + ---------- + + function I_SF (Stream : not null access RST) return Short_Float is + T : S_SF; + L : SEO; + + begin + if XDR_Support then + return XDR.I_SF (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_SF (T); + end if; + end I_SF; + + ---------- + -- I_SI -- + ---------- + + function I_SI (Stream : not null access RST) return Short_Integer is + T : S_SI; + L : SEO; + + begin + if XDR_Support then + return XDR.I_SI (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_SI (T); + end if; + end I_SI; + + ----------- + -- I_SSI -- + ----------- + + function I_SSI (Stream : not null access RST) return Short_Short_Integer is + T : S_SSI; + L : SEO; + + begin + if XDR_Support then + return XDR.I_SSI (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_SSI (T); + end if; + end I_SSI; + + ----------- + -- I_SSU -- + ----------- + + function I_SSU + (Stream : not null access RST) return UST.Short_Short_Unsigned + is + T : S_SSU; + L : SEO; + + begin + if XDR_Support then + return XDR.I_SSU (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_SSU (T); + end if; + end I_SSU; + + ---------- + -- I_SU -- + ---------- + + function I_SU (Stream : not null access RST) return UST.Short_Unsigned is + T : S_SU; + L : SEO; + + begin + if XDR_Support then + return XDR.I_SU (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_SU (T); + end if; + end I_SU; + + --------- + -- I_U -- + --------- + + function I_U (Stream : not null access RST) return UST.Unsigned is + T : S_U; + L : SEO; + + begin + if XDR_Support then + return XDR.I_U (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_U (T); + end if; + end I_U; + + ----------- + -- I_U24 -- + ----------- + + function I_U24 (Stream : not null access RST) return Unsigned_24 is + T : S_U24; + L : SEO; + + begin + if XDR_Support then + return XDR.I_U24 (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_U24 (T); + end if; + end I_U24; + + ---------- + -- I_WC -- + ---------- + + function I_WC (Stream : not null access RST) return Wide_Character is + T : S_WC; + L : SEO; + + begin + if XDR_Support then + return XDR.I_WC (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_WC (T); + end if; + end I_WC; + + ----------- + -- I_WWC -- + ----------- + + function I_WWC (Stream : not null access RST) return Wide_Wide_Character is + T : S_WWC; + L : SEO; + + begin + if XDR_Support then + return XDR.I_WWC (Stream); + end if; + + Ada.Streams.Read (Stream.all, T, L); + + if L < T'Last then + raise Err; + else + return To_WWC (T); + end if; + end I_WWC; + + ---------- + -- W_AD -- + ---------- + + procedure W_AD (Stream : not null access RST; Item : Fat_Pointer) is + T : constant S_AD := From_AD (Item); + begin + if XDR_Support then + XDR.W_AD (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, T); + end W_AD; + + ---------- + -- W_AS -- + ---------- + + procedure W_AS (Stream : not null access RST; Item : Thin_Pointer) is + T : constant S_AS := From_AS (Item); + begin + if XDR_Support then + XDR.W_AS (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, T); + end W_AS; + + --------- + -- W_B -- + --------- + + procedure W_B (Stream : not null access RST; Item : Boolean) is + T : S_B; + begin + if XDR_Support then + XDR.W_B (Stream, Item); + return; + end if; + + T (1) := Boolean'Pos (Item); + Ada.Streams.Write (Stream.all, T); + end W_B; + + --------- + -- W_C -- + --------- + + procedure W_C (Stream : not null access RST; Item : Character) is + T : S_C; + begin + if XDR_Support then + XDR.W_C (Stream, Item); + return; + end if; + + T (1) := Character'Pos (Item); + Ada.Streams.Write (Stream.all, T); + end W_C; + + --------- + -- W_F -- + --------- + + procedure W_F (Stream : not null access RST; Item : Float) is + begin + if XDR_Support then + XDR.W_F (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, From_F (Item)); + end W_F; + + --------- + -- W_I -- + --------- + + procedure W_I (Stream : not null access RST; Item : Integer) is + begin + if XDR_Support then + XDR.W_I (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, From_I (Item)); + end W_I; + + ----------- + -- W_I24 -- + ----------- + + procedure W_I24 (Stream : not null access RST; Item : Integer_24) is + begin + if XDR_Support then + XDR.W_I24 (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, From_I24 (Item)); + end W_I24; + + ---------- + -- W_LF -- + ---------- + + procedure W_LF (Stream : not null access RST; Item : Long_Float) is + begin + if XDR_Support then + XDR.W_LF (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, From_LF (Item)); + end W_LF; + + ---------- + -- W_LI -- + ---------- + + procedure W_LI (Stream : not null access RST; Item : Long_Integer) is + begin + if XDR_Support then + XDR.W_LI (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, From_LI (Item)); + end W_LI; + + ----------- + -- W_LLF -- + ----------- + + procedure W_LLF (Stream : not null access RST; Item : Long_Long_Float) is + begin + if XDR_Support then + XDR.W_LLF (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, From_LLF (Item)); + end W_LLF; + + ----------- + -- W_LLI -- + ----------- + + procedure W_LLI (Stream : not null access RST; Item : Long_Long_Integer) is + begin + if XDR_Support then + XDR.W_LLI (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, From_LLI (Item)); + end W_LLI; + + ------------ + -- W_LLLI -- + ------------ + + procedure W_LLLI + (Stream : not null access RST; Item : Long_Long_Long_Integer) is + begin + if XDR_Support then + raise Ada.IO_Exceptions.Device_Error; + end if; + + Ada.Streams.Write (Stream.all, From_LLLI (Item)); + end W_LLLI; + + ------------ + -- W_LLLU -- + ------------ + + procedure W_LLLU + (Stream : not null access RST; Item : UST.Long_Long_Long_Unsigned) + is + begin + if XDR_Support then + raise Ada.IO_Exceptions.Device_Error; + end if; + + Ada.Streams.Write (Stream.all, From_LLLU (Item)); + end W_LLLU; + + ----------- + -- W_LLU -- + ----------- + + procedure W_LLU + (Stream : not null access RST; Item : UST.Long_Long_Unsigned) + is + begin + if XDR_Support then + XDR.W_LLU (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, From_LLU (Item)); + end W_LLU; + + ---------- + -- W_LU -- + ---------- + + procedure W_LU (Stream : not null access RST; Item : UST.Long_Unsigned) is + begin + if XDR_Support then + XDR.W_LU (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, From_LU (Item)); + end W_LU; + + ---------- + -- W_SF -- + ---------- + + procedure W_SF (Stream : not null access RST; Item : Short_Float) is + begin + if XDR_Support then + XDR.W_SF (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, From_SF (Item)); + end W_SF; + + ---------- + -- W_SI -- + ---------- + + procedure W_SI (Stream : not null access RST; Item : Short_Integer) is + begin + if XDR_Support then + XDR.W_SI (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, From_SI (Item)); + end W_SI; + + ----------- + -- W_SSI -- + ----------- + + procedure W_SSI + (Stream : not null access RST; Item : Short_Short_Integer) + is + begin + if XDR_Support then + XDR.W_SSI (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, From_SSI (Item)); + end W_SSI; + + ----------- + -- W_SSU -- + ----------- + + procedure W_SSU + (Stream : not null access RST; Item : UST.Short_Short_Unsigned) + is + begin + if XDR_Support then + XDR.W_SSU (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, From_SSU (Item)); + end W_SSU; + + ---------- + -- W_SU -- + ---------- + + procedure W_SU (Stream : not null access RST; Item : UST.Short_Unsigned) is + begin + if XDR_Support then + XDR.W_SU (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, From_SU (Item)); + end W_SU; + + --------- + -- W_U -- + --------- + + procedure W_U (Stream : not null access RST; Item : UST.Unsigned) is + begin + if XDR_Support then + XDR.W_U (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, From_U (Item)); + end W_U; + + ----------- + -- W_U24 -- + ----------- + + procedure W_U24 (Stream : not null access RST; Item : Unsigned_24) is + begin + if XDR_Support then + XDR.W_U24 (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, From_U24 (Item)); + end W_U24; + + ---------- + -- W_WC -- + ---------- + + procedure W_WC (Stream : not null access RST; Item : Wide_Character) is + begin + if XDR_Support then + XDR.W_WC (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, From_WC (Item)); + end W_WC; + + ----------- + -- W_WWC -- + ----------- + + procedure W_WWC + (Stream : not null access RST; Item : Wide_Wide_Character) + is + begin + if XDR_Support then + XDR.W_WWC (Stream, Item); + return; + end if; + + Ada.Streams.Write (Stream.all, From_WWC (Item)); + end W_WWC; + +end System.Stream_Attributes; diff --git a/gcc/ada/raise-gcc.c b/gcc/ada/raise-gcc.c index 56ddfc5..bdf1c26 100644 --- a/gcc/ada/raise-gcc.c +++ b/gcc/ada/raise-gcc.c @@ -50,10 +50,12 @@ #ifdef __cplusplus # include <cstdarg> +# include <cstddef> # include <cstdlib> #else # include <stdarg.h> # include <stdbool.h> +# include <stddef.h> # include <stdlib.h> #endif @@ -592,6 +594,11 @@ get_ip_from_context (_Unwind_Context *uw_context) #else _Unwind_Ptr ip = _Unwind_GetIP (uw_context); #endif + +#if !defined(__USING_SJLJ_EXCEPTIONS__) && defined(__CHERI__) + ip = __builtin_code_address_from_pointer ((void *)ip); +#endif + /* Subtract 1 if necessary because GetIPInfo yields a call return address in this case, while we are interested in information for the call point. This does not always yield the exact call instruction address but always @@ -850,7 +857,27 @@ get_call_site_action_for (_Unwind_Ptr ip, /* Note that all call-site encodings are "absolute" displacements. */ p = read_encoded_value (0, region->call_site_encoding, p, &cs_start); p = read_encoded_value (0, region->call_site_encoding, p, &cs_len); +#ifdef __CHERI_PURE_CAPABILITY__ + // Single uleb128 value as the capability marker. + _Unwind_Ptr marker = 0; + p = read_encoded_value (0, DW_EH_PE_uleb128, p, &marker); + if (marker == 0xd) + { + /* 8-byte offset to the (indirected) capability. */ + p = read_encoded_value (0, DW_EH_PE_pcrel | DW_EH_PE_udata8, p, + &cs_lp); + } + else if (marker) + { + /* Unsupported landing pad marker value. */ + abort (); + } + else + cs_lp = 0; // No landing pad. +#else p = read_encoded_value (0, region->call_site_encoding, p, &cs_lp); +#endif + p = read_uleb128 (p, &cs_action); db (DB_CSITE, @@ -859,18 +886,24 @@ get_call_site_action_for (_Unwind_Ptr ip, (char *)region->lp_base + cs_lp, (void *)cs_lp); /* The table is sorted, so if we've passed the IP, stop. */ - if (ip < region->base + cs_start) + if (ip < region->base + (size_t)cs_start) break; /* If we have a match, fill the ACTION fields accordingly. */ - else if (ip < region->base + cs_start + cs_len) + else if (ip < region->base + (size_t)cs_start + (size_t)cs_len) { /* Let the caller know there may be an action to take, but let it determine the kind. */ action->kind = unknown; if (cs_lp) - action->landing_pad = region->lp_base + cs_lp; + { +#ifdef __CHERI_PURE_CAPABILITY__ + action->landing_pad = *(_Unwind_Ptr *)cs_lp; +#else + action->landing_pad = region->lp_base + cs_lp; +#endif + } else action->landing_pad = 0; diff --git a/gcc/ada/rtsfind.ads b/gcc/ada/rtsfind.ads index 881f723..669f6df 100644 --- a/gcc/ada/rtsfind.ads +++ b/gcc/ada/rtsfind.ads @@ -179,7 +179,6 @@ package Rtsfind is CUDA_Driver_Types, CUDA_Internal, - CUDA_Runtime_Api, CUDA_Vector_Types, -- Interfaces diff --git a/gcc/ada/sem_ch3.adb b/gcc/ada/sem_ch3.adb index 92902a7..c79d323 100644 --- a/gcc/ada/sem_ch3.adb +++ b/gcc/ada/sem_ch3.adb @@ -5048,9 +5048,11 @@ package body Sem_Ch3 is Apply_Length_Check (E, T); end if; - -- When possible, build the default subtype + -- When possible, and not a deferred constant, build the default subtype - elsif Build_Default_Subtype_OK (T) then + elsif Build_Default_Subtype_OK (T) + and then (not Constant_Present (N) or else Present (E)) + then if No (E) then Act_T := Build_Default_Subtype (T, N); else diff --git a/gcc/builtins.cc b/gcc/builtins.cc index 6e4274b..40dfd36 100644 --- a/gcc/builtins.cc +++ b/gcc/builtins.cc @@ -8387,7 +8387,10 @@ expand_builtin (tree exp, rtx target, rtx subtarget, machine_mode mode, break; case BUILT_IN_ATOMIC_TEST_AND_SET: - return expand_builtin_atomic_test_and_set (exp, target); + target = expand_builtin_atomic_test_and_set (exp, target); + if (target) + return target; + break; case BUILT_IN_ATOMIC_CLEAR: return expand_builtin_atomic_clear (exp); diff --git a/gcc/config/aarch64/aarch64-opts.h b/gcc/config/aarch64/aarch64-opts.h index 7e8f1ba..db83485 100644 --- a/gcc/config/aarch64/aarch64-opts.h +++ b/gcc/config/aarch64/aarch64-opts.h @@ -108,4 +108,20 @@ enum aarch64_key_type { AARCH64_KEY_B }; +/* Load pair policy type. */ +enum aarch64_ldp_policy { + LDP_POLICY_DEFAULT, + LDP_POLICY_ALWAYS, + LDP_POLICY_NEVER, + LDP_POLICY_ALIGNED +}; + +/* Store pair policy type. */ +enum aarch64_stp_policy { + STP_POLICY_DEFAULT, + STP_POLICY_ALWAYS, + STP_POLICY_NEVER, + STP_POLICY_ALIGNED +}; + #endif diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 70303d6..3c8f418 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -568,6 +568,30 @@ struct tune_params /* Place prefetch struct pointer at the end to enable type checking errors when tune_params misses elements (e.g., from erroneous merges). */ const struct cpu_prefetch_tune *prefetch; +/* An enum specifying how to handle load pairs using a fine-grained policy: + - LDP_POLICY_ALIGNED: Emit ldp if the source pointer is aligned + to at least double the alignment of the type. + - LDP_POLICY_ALWAYS: Emit ldp regardless of alignment. + - LDP_POLICY_NEVER: Do not emit ldp. */ + + enum aarch64_ldp_policy_model + { + LDP_POLICY_ALIGNED, + LDP_POLICY_ALWAYS, + LDP_POLICY_NEVER + } ldp_policy_model; +/* An enum specifying how to handle store pairs using a fine-grained policy: + - STP_POLICY_ALIGNED: Emit stp if the source pointer is aligned + to at least double the alignment of the type. + - STP_POLICY_ALWAYS: Emit stp regardless of alignment. + - STP_POLICY_NEVER: Do not emit stp. */ + + enum aarch64_stp_policy_model + { + STP_POLICY_ALIGNED, + STP_POLICY_ALWAYS, + STP_POLICY_NEVER + } stp_policy_model; }; /* Classifies an address. @@ -1015,6 +1039,7 @@ bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset); bool aarch64_mergeable_load_pair_p (machine_mode, rtx, rtx); bool aarch64_operands_ok_for_ldpstp (rtx *, bool, machine_mode); bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, machine_mode); +bool aarch64_mem_ok_with_ldpstp_policy_model (rtx, bool, machine_mode); void aarch64_swap_ldrstr_operands (rtx *, bool); extern void aarch64_asm_output_pool_epilogue (FILE *, const char *, diff --git a/gcc/config/aarch64/aarch64-tuning-flags.def b/gcc/config/aarch64/aarch64-tuning-flags.def index 52112ba..774568e 100644 --- a/gcc/config/aarch64/aarch64-tuning-flags.def +++ b/gcc/config/aarch64/aarch64-tuning-flags.def @@ -30,11 +30,6 @@ AARCH64_EXTRA_TUNING_OPTION ("rename_fma_regs", RENAME_FMA_REGS) -/* Don't create non-8 byte aligned load/store pair. That is if the -two load/stores are not at least 8 byte aligned don't create load/store -pairs. */ -AARCH64_EXTRA_TUNING_OPTION ("slow_unaligned_ldpw", SLOW_UNALIGNED_LDPW) - /* Some of the optional shift to some arthematic instructions are considered cheap. Logical shift left <=4 with or without a zero extend are considered cheap. Sign extend; non logical shift left @@ -44,9 +39,6 @@ AARCH64_EXTRA_TUNING_OPTION ("cheap_shift_extend", CHEAP_SHIFT_EXTEND) /* Disallow load/store pair instructions on Q-registers. */ AARCH64_EXTRA_TUNING_OPTION ("no_ldp_stp_qregs", NO_LDP_STP_QREGS) -/* Disallow load-pair instructions to be formed in combine/peephole. */ -AARCH64_EXTRA_TUNING_OPTION ("no_ldp_combine", NO_LDP_COMBINE) - AARCH64_EXTRA_TUNING_OPTION ("rename_load_regs", RENAME_LOAD_REGS) AARCH64_EXTRA_TUNING_OPTION ("cse_sve_vl_constants", CSE_SVE_VL_CONSTANTS) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 219c4ee..f1e98ea 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -1357,7 +1357,9 @@ static const struct tune_params generic_tunings = Neoverse V1. It does not have a noticeable effect on A64FX and should have at most a very minor effect on SVE2 cores. */ (AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS), /* tune_flags. */ - &generic_prefetch_tune + &generic_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; static const struct tune_params cortexa35_tunings = @@ -1391,7 +1393,9 @@ static const struct tune_params cortexa35_tunings = 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ - &generic_prefetch_tune + &generic_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; static const struct tune_params cortexa53_tunings = @@ -1425,7 +1429,9 @@ static const struct tune_params cortexa53_tunings = 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ - &generic_prefetch_tune + &generic_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; static const struct tune_params cortexa57_tunings = @@ -1459,7 +1465,9 @@ static const struct tune_params cortexa57_tunings = 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_RENAME_FMA_REGS), /* tune_flags. */ - &generic_prefetch_tune + &generic_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; static const struct tune_params cortexa72_tunings = @@ -1493,7 +1501,9 @@ static const struct tune_params cortexa72_tunings = 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ - &generic_prefetch_tune + &generic_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; static const struct tune_params cortexa73_tunings = @@ -1527,7 +1537,9 @@ static const struct tune_params cortexa73_tunings = 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ - &generic_prefetch_tune + &generic_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; @@ -1562,7 +1574,9 @@ static const struct tune_params exynosm1_tunings = 48, /* max_case_values. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ - &exynosm1_prefetch_tune + &exynosm1_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; static const struct tune_params thunderxt88_tunings = @@ -1594,8 +1608,10 @@ static const struct tune_params thunderxt88_tunings = 2, /* min_div_recip_mul_df. */ 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW), /* tune_flags. */ - &thunderxt88_prefetch_tune + (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ + &thunderxt88_prefetch_tune, + tune_params::LDP_POLICY_ALIGNED, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALIGNED /* stp_policy_model. */ }; static const struct tune_params thunderx_tunings = @@ -1627,9 +1643,10 @@ static const struct tune_params thunderx_tunings = 2, /* min_div_recip_mul_df. */ 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW - | AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND), /* tune_flags. */ - &thunderx_prefetch_tune + (AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND), /* tune_flags. */ + &thunderx_prefetch_tune, + tune_params::LDP_POLICY_ALIGNED, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALIGNED /* stp_policy_model. */ }; static const struct tune_params tsv110_tunings = @@ -1663,7 +1680,9 @@ static const struct tune_params tsv110_tunings = 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ - &tsv110_prefetch_tune + &tsv110_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; static const struct tune_params xgene1_tunings = @@ -1696,7 +1715,9 @@ static const struct tune_params xgene1_tunings = 17, /* max_case_values. */ tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS), /* tune_flags. */ - &xgene1_prefetch_tune + &xgene1_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; static const struct tune_params emag_tunings = @@ -1729,7 +1750,9 @@ static const struct tune_params emag_tunings = 17, /* max_case_values. */ tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS), /* tune_flags. */ - &xgene1_prefetch_tune + &xgene1_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; static const struct tune_params qdf24xx_tunings = @@ -1763,7 +1786,9 @@ static const struct tune_params qdf24xx_tunings = 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ AARCH64_EXTRA_TUNE_RENAME_LOAD_REGS, /* tune_flags. */ - &qdf24xx_prefetch_tune + &qdf24xx_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; /* Tuning structure for the Qualcomm Saphira core. Default to falkor values @@ -1799,7 +1824,9 @@ static const struct tune_params saphira_tunings = 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ - &generic_prefetch_tune + &generic_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; static const struct tune_params thunderx2t99_tunings = @@ -1833,7 +1860,9 @@ static const struct tune_params thunderx2t99_tunings = 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ - &thunderx2t99_prefetch_tune + &thunderx2t99_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; static const struct tune_params thunderx3t110_tunings = @@ -1867,7 +1896,9 @@ static const struct tune_params thunderx3t110_tunings = 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ - &thunderx3t110_prefetch_tune + &thunderx3t110_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; static const struct tune_params neoversen1_tunings = @@ -1900,7 +1931,9 @@ static const struct tune_params neoversen1_tunings = 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND), /* tune_flags. */ - &generic_prefetch_tune + &generic_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; static const struct tune_params ampere1_tunings = @@ -1936,8 +1969,10 @@ static const struct tune_params ampere1_tunings = 2, /* min_div_recip_mul_df. */ 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_NO_LDP_COMBINE), /* tune_flags. */ - &ere1_prefetch_tune + (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ + &ere1_prefetch_tune, + tune_params::LDP_POLICY_ALIGNED, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALIGNED /* stp_policy_model. */ }; static const struct tune_params ampere1a_tunings = @@ -1974,8 +2009,10 @@ static const struct tune_params ampere1a_tunings = 2, /* min_div_recip_mul_df. */ 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_NO_LDP_COMBINE), /* tune_flags. */ - &ere1_prefetch_tune + (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ + &ere1_prefetch_tune, + tune_params::LDP_POLICY_ALIGNED, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALIGNED /* stp_policy_model. */ }; static const advsimd_vec_cost neoversev1_advsimd_vector_cost = @@ -2156,7 +2193,9 @@ static const struct tune_params neoversev1_tunings = | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT | AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND), /* tune_flags. */ - &generic_prefetch_tune + &generic_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; static const sve_vec_cost neoverse512tvb_sve_vector_cost = @@ -2293,7 +2332,9 @@ static const struct tune_params neoverse512tvb_tunings = (AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT), /* tune_flags. */ - &generic_prefetch_tune + &generic_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; static const advsimd_vec_cost neoversen2_advsimd_vector_cost = @@ -2483,7 +2524,9 @@ static const struct tune_params neoversen2_tunings = | AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT), /* tune_flags. */ - &generic_prefetch_tune + &generic_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; static const advsimd_vec_cost neoversev2_advsimd_vector_cost = @@ -2673,7 +2716,9 @@ static const struct tune_params neoversev2_tunings = | AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT), /* tune_flags. */ - &generic_prefetch_tune + &generic_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; static const struct tune_params a64fx_tunings = @@ -2706,7 +2751,9 @@ static const struct tune_params a64fx_tunings = 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ - &a64fx_prefetch_tune + &a64fx_prefetch_tune, + tune_params::LDP_POLICY_ALWAYS, /* ldp_policy_model. */ + tune_params::STP_POLICY_ALWAYS /* stp_policy_model. */ }; /* Support for fine-grained override of the tuning structures. */ @@ -17819,6 +17866,36 @@ aarch64_parse_tune (const char *to_parse, const struct processor **res) return AARCH_PARSE_INVALID_ARG; } +/* Parse a command-line -param=aarch64-ldp-policy= parameter. VALUE is + the value of the parameter. */ + +static void +aarch64_parse_ldp_policy (enum aarch64_ldp_policy value, + struct tune_params* tune) +{ + if (value == LDP_POLICY_ALWAYS) + tune->ldp_policy_model = tune_params::LDP_POLICY_ALWAYS; + else if (value == LDP_POLICY_NEVER) + tune->ldp_policy_model = tune_params::LDP_POLICY_NEVER; + else if (value == LDP_POLICY_ALIGNED) + tune->ldp_policy_model = tune_params::LDP_POLICY_ALIGNED; +} + +/* Parse a command-line -param=aarch64-stp-policy= parameter. VALUE is + the value of the parameter. */ + +static void +aarch64_parse_stp_policy (enum aarch64_stp_policy value, + struct tune_params* tune) +{ + if (value == STP_POLICY_ALWAYS) + tune->stp_policy_model = tune_params::STP_POLICY_ALWAYS; + else if (value == STP_POLICY_NEVER) + tune->stp_policy_model = tune_params::STP_POLICY_NEVER; + else if (value == STP_POLICY_ALIGNED) + tune->stp_policy_model = tune_params::STP_POLICY_ALIGNED; +} + /* Parse TOKEN, which has length LENGTH to see if it is an option described in FLAG. If it is, return the index bit for that fusion type. If not, error (printing OPTION_NAME) and return zero. */ @@ -18167,6 +18244,14 @@ aarch64_override_options_internal (struct gcc_options *opts) aarch64_parse_override_string (opts->x_aarch64_override_tune_string, &aarch64_tune_params); + if (opts->x_aarch64_ldp_policy_param) + aarch64_parse_ldp_policy (opts->x_aarch64_ldp_policy_param, + &aarch64_tune_params); + + if (opts->x_aarch64_stp_policy_param) + aarch64_parse_stp_policy (opts->x_aarch64_stp_policy_param, + &aarch64_tune_params); + /* This target defaults to strict volatile bitfields. */ if (opts->x_flag_strict_volatile_bitfields < 0 && abi_version_at_least (2)) opts->x_flag_strict_volatile_bitfields = 1; @@ -26457,6 +26542,43 @@ aarch64_mergeable_load_pair_p (machine_mode mode, rtx mem1, rtx mem2) return aarch64_check_consecutive_mems (&mem1, &mem2, nullptr); } +/* Return true if MEM agrees with the ldp-stp policy model. + Otherwise, false. */ + +bool +aarch64_mem_ok_with_ldpstp_policy_model (rtx mem, bool load, machine_mode mode) +{ + /* If we have LDP_POLICY_NEVER, reject the load pair. */ + if (load + && aarch64_tune_params.ldp_policy_model == tune_params::LDP_POLICY_NEVER) + return false; + + /* If we have STP_POLICY_NEVER, reject the store pair. */ + if (!load + && aarch64_tune_params.stp_policy_model == tune_params::STP_POLICY_NEVER) + return false; + + /* If we have LDP_POLICY_ALIGNED, + do not emit the load pair unless the alignment is checked to be + at least double the alignment of the type. */ + if (load + && aarch64_tune_params.ldp_policy_model == tune_params::LDP_POLICY_ALIGNED + && !optimize_function_for_size_p (cfun) + && MEM_ALIGN (mem) < 2 * GET_MODE_ALIGNMENT (mode)) + return false; + + /* If we have STP_POLICY_ALIGNED, + do not emit the store pair unless the alignment is checked to be + at least double the alignment of the type. */ + if (!load + && aarch64_tune_params.stp_policy_model == tune_params::STP_POLICY_ALIGNED + && !optimize_function_for_size_p (cfun) + && MEM_ALIGN (mem) < 2 * GET_MODE_ALIGNMENT (mode)) + return false; + + return true; +} + /* Given OPERANDS of consecutive load/store, check if we can merge them into ldp/stp. LOAD is true if they are load instructions. MODE is the mode of memory operands. */ @@ -26468,20 +26590,6 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load, enum reg_class rclass_1, rclass_2; rtx mem_1, mem_2, reg_1, reg_2; - /* Allow the tuning structure to disable LDP instruction formation - from combining instructions (e.g., in peephole2). - TODO: Implement fine-grained tuning control for LDP and STP: - 1. control policies for load and store separately; - 2. support the following policies: - - default (use what is in the tuning structure) - - always - - never - - aligned (only if the compiler can prove that the - load will be aligned to 2 * element_size) */ - if (load && (aarch64_tune_params.extra_tuning_flags - & AARCH64_EXTRA_TUNE_NO_LDP_COMBINE)) - return false; - if (load) { mem_1 = operands[1]; @@ -26506,13 +26614,8 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load, if (MEM_VOLATILE_P (mem_1) || MEM_VOLATILE_P (mem_2)) return false; - /* If we have SImode and slow unaligned ldp, - check the alignment to be at least 8 byte. */ - if (mode == SImode - && (aarch64_tune_params.extra_tuning_flags - & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW) - && !optimize_size - && MEM_ALIGN (mem_1) < 8 * BITS_PER_UNIT) + /* Check if mem_1 is ok with the ldp-stp policy model. */ + if (!aarch64_mem_ok_with_ldpstp_policy_model (mem_1, load, mode)) return false; /* Check if the addresses are in the form of [base+offset]. */ @@ -26729,13 +26832,8 @@ aarch64_operands_adjust_ok_for_ldpstp (rtx *operands, bool load, if (offvals[0] % msize != offvals[2] % msize) return false; - /* If we have SImode and slow unaligned ldp, - check the alignment to be at least 8 byte. */ - if (mode == SImode - && (aarch64_tune_params.extra_tuning_flags - & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW) - && !optimize_size - && MEM_ALIGN (mem[0]) < 8 * BITS_PER_UNIT) + /* Check if mem[0] is ok with the ldp-stp policy model. */ + if (!aarch64_mem_ok_with_ldpstp_policy_model (mem[0], load, mode)) return false; return true; diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt index 4a05804..2101c5a 100644 --- a/gcc/config/aarch64/aarch64.opt +++ b/gcc/config/aarch64/aarch64.opt @@ -337,3 +337,41 @@ Constant memset size in bytes from which to start using MOPS sequence. -param=aarch64-vect-unroll-limit= Target Joined UInteger Var(aarch64_vect_unroll_limit) Init(4) Param Limit how much the autovectorizer may unroll a loop. + +-param=aarch64-ldp-policy= +Target Joined Var(aarch64_ldp_policy_param) Enum(aarch64_ldp_policy) Init(LDP_POLICY_DEFAULT) Param +--param=aarch64-ldp-policy=[default|always|never|aligned] Fine-grained policy for load pairs. + +Enum +Name(aarch64_ldp_policy) Type(enum aarch64_ldp_policy) UnknownError(unknown aarch64_ldp_policy mode %qs) + +EnumValue +Enum(aarch64_ldp_policy) String(default) Value(LDP_POLICY_DEFAULT) + +EnumValue +Enum(aarch64_ldp_policy) String(always) Value(LDP_POLICY_ALWAYS) + +EnumValue +Enum(aarch64_ldp_policy) String(never) Value(LDP_POLICY_NEVER) + +EnumValue +Enum(aarch64_ldp_policy) String(aligned) Value(LDP_POLICY_ALIGNED) + +-param=aarch64-stp-policy= +Target Joined Var(aarch64_stp_policy_param) Enum(aarch64_stp_policy) Init(STP_POLICY_DEFAULT) Param +--param=aarch64-stp-policy=[default|always|never|aligned] Fine-grained policy for store pairs. + +Enum +Name(aarch64_stp_policy) Type(enum aarch64_stp_policy) UnknownError(unknown aarch64_stp_policy mode %qs) + +EnumValue +Enum(aarch64_stp_policy) String(default) Value(STP_POLICY_DEFAULT) + +EnumValue +Enum(aarch64_stp_policy) String(always) Value(STP_POLICY_ALWAYS) + +EnumValue +Enum(aarch64_stp_policy) String(never) Value(STP_POLICY_NEVER) + +EnumValue +Enum(aarch64_stp_policy) String(aligned) Value(STP_POLICY_ALIGNED) diff --git a/gcc/config/darwin.h b/gcc/config/darwin.h index 61e46f7..2ee66c1 100644 --- a/gcc/config/darwin.h +++ b/gcc/config/darwin.h @@ -307,7 +307,7 @@ extern GTY(()) int darwin_ms_struct; %:version-compare(>= 10.7 mmacosx-version-min= -no_pie) }" #define DARWIN_CC1_SPEC \ - "%<dynamic %<force_cpusubtype_ALL %<multiply_defined* " + "%<dynamic %<force_cpusubtype_ALL %<multiply_defined* %<dynamiclib" #define SUBSUBTARGET_OVERRIDE_OPTIONS \ do { \ diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index 8111c8b..2bc5d47 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -186,6 +186,9 @@ UNSPEC_LASX_XVLDI UNSPEC_LASX_XVLDX UNSPEC_LASX_XVSTX + UNSPEC_LASX_VECINIT_MERGE + UNSPEC_LASX_VEC_SET_INTERNAL + UNSPEC_LASX_XVILVL_INTERNAL ]) ;; All vector modes with 256 bits. @@ -255,6 +258,15 @@ [(V8SF "V4SF") (V4DF "V2DF")]) +;; The attribute gives half int/float modes for vector modes. +(define_mode_attr VHMODE256_ALL + [(V32QI "V16QI") + (V16HI "V8HI") + (V8SI "V4SI") + (V4DI "V2DI") + (V8SF "V4SF") + (V4DF "V2DF")]) + ;; The attribute gives double modes for vector modes in LASX. (define_mode_attr VDMODE256 [(V8SI "V4DI") @@ -312,6 +324,11 @@ (V4DI "v4df") (V8SI "v8sf")]) +;; This attribute gives V32QI mode and V16HI mode with half size. +(define_mode_attr mode256_i_half + [(V32QI "v16qi") + (V16HI "v8hi")]) + ;; This attribute gives suffix for LASX instructions. HOW? (define_mode_attr lasxfmt [(V4DF "d") @@ -756,6 +773,20 @@ [(set_attr "type" "simd_splat") (set_attr "mode" "<MODE>")]) +;; Only for loongarch_expand_vector_init in loongarch.cc. +;; Support a LSX-mode input op2. +(define_insn "lasx_vecinit_merge_<LASX:mode>" + [(set (match_operand:LASX 0 "register_operand" "=f") + (unspec:LASX + [(match_operand:LASX 1 "register_operand" "0") + (match_operand:<VHMODE256_ALL> 2 "register_operand" "f") + (match_operand 3 "const_uimm8_operand")] + UNSPEC_LASX_VECINIT_MERGE))] + "ISA_HAS_LASX" + "xvpermi.q\t%u0,%u2,%3" + [(set_attr "type" "simd_splat") + (set_attr "mode" "<MODE>")]) + (define_insn "lasx_xvpickve2gr_d<u>" [(set (match_operand:DI 0 "register_operand" "=r") (any_extend:DI @@ -779,6 +810,33 @@ DONE; }) +;; Only for loongarch_expand_vector_init in loongarch.cc. +;; Simulate missing instructions xvinsgr2vr.b and xvinsgr2vr.h. +(define_expand "vec_set<mode>_internal" + [(match_operand:ILASX_HB 0 "register_operand") + (match_operand:<UNITMODE> 1 "reg_or_0_operand") + (match_operand 2 "const_<indeximm256>_operand")] + "ISA_HAS_LASX" +{ + rtx index = GEN_INT (1 << INTVAL (operands[2])); + emit_insn (gen_lasx_xvinsgr2vr_<mode256_i_half>_internal + (operands[0], operands[1], operands[0], index)); + DONE; +}) + +(define_insn "lasx_xvinsgr2vr_<mode256_i_half>_internal" + [(set (match_operand:ILASX_HB 0 "register_operand" "=f") + (unspec:ILASX_HB [(match_operand:<UNITMODE> 1 "reg_or_0_operand" "rJ") + (match_operand:ILASX_HB 2 "register_operand" "0") + (match_operand 3 "const_<bitmask256>_operand" "")] + UNSPEC_LASX_VEC_SET_INTERNAL))] + "ISA_HAS_LASX" +{ + return "vinsgr2vr.<lasxfmt>\t%w0,%z1,%y3"; +} + [(set_attr "type" "simd_insert") + (set_attr "mode" "<MODE>")]) + (define_expand "vec_set<mode>" [(match_operand:FLASX 0 "register_operand") (match_operand:<UNITMODE> 1 "reg_or_0_operand") @@ -1567,6 +1625,17 @@ [(set_attr "type" "simd_flog2") (set_attr "mode" "<MODE>")]) +;; Only for loongarch_expand_vector_init in loongarch.cc. +;; Merge two scalar floating-point op1 and op2 into a LASX op0. +(define_insn "lasx_xvilvl_<lasxfmt_f>_internal" + [(set (match_operand:FLASX 0 "register_operand" "=f") + (unspec:FLASX [(match_operand:<UNITMODE> 1 "register_operand" "f") + (match_operand:<UNITMODE> 2 "register_operand" "f")] + UNSPEC_LASX_XVILVL_INTERNAL))] + "ISA_HAS_LASX" + "xvilvl.<lasxfmt>\t%u0,%u2,%u1" + [(set_attr "type" "simd_permute") + (set_attr "mode" "<MODE>")]) (define_insn "smax<mode>3" [(set (match_operand:FLASX 0 "register_operand" "=f") diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 845fad5..9e1b0d0 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -10199,300 +10199,344 @@ loongarch_expand_vector_group_init (rtx target, rtx vals) ops[1]))); } +/* Expand initialization of a vector which has all same elements. */ + void -loongarch_expand_vector_init (rtx target, rtx vals) +loongarch_expand_vector_init_same (rtx target, rtx vals, unsigned nvar) { machine_mode vmode = GET_MODE (target); machine_mode imode = GET_MODE_INNER (vmode); - unsigned i, nelt = GET_MODE_NUNITS (vmode); - unsigned nvar = 0; - bool all_same = true; - rtx x; + rtx same = XVECEXP (vals, 0, 0); + rtx temp, temp2; - for (i = 0; i < nelt; ++i) + if (CONST_INT_P (same) && nvar == 0 + && loongarch_signed_immediate_p (INTVAL (same), 10, 0)) + { + switch (vmode) + { + case E_V32QImode: + case E_V16HImode: + case E_V8SImode: + case E_V4DImode: + case E_V16QImode: + case E_V8HImode: + case E_V4SImode: + case E_V2DImode: + temp = gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)); + emit_move_insn (target, temp); + return; + default: + gcc_unreachable (); + } + } + temp = gen_reg_rtx (imode); + if (imode == GET_MODE (same)) + temp2 = same; + else if (GET_MODE_SIZE (imode) >= UNITS_PER_WORD) { - x = XVECEXP (vals, 0, i); - if (!loongarch_constant_elt_p (x)) - nvar++; - if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0))) - all_same = false; + if (GET_CODE (same) == MEM) + { + rtx reg_tmp = gen_reg_rtx (GET_MODE (same)); + loongarch_emit_move (reg_tmp, same); + temp2 = simplify_gen_subreg (imode, reg_tmp, GET_MODE (reg_tmp), 0); + } + else + temp2 = simplify_gen_subreg (imode, same, GET_MODE (same), 0); } - - if (ISA_HAS_LASX && GET_MODE_SIZE (vmode) == 32) + else { - if (all_same) + if (GET_CODE (same) == MEM) { - rtx same = XVECEXP (vals, 0, 0); - rtx temp, temp2; + rtx reg_tmp = gen_reg_rtx (GET_MODE (same)); + loongarch_emit_move (reg_tmp, same); + temp2 = lowpart_subreg (imode, reg_tmp, GET_MODE (reg_tmp)); + } + else + temp2 = lowpart_subreg (imode, same, GET_MODE (same)); + } + emit_move_insn (temp, temp2); - if (CONST_INT_P (same) && nvar == 0 - && loongarch_signed_immediate_p (INTVAL (same), 10, 0)) - { - switch (vmode) - { - case E_V32QImode: - case E_V16HImode: - case E_V8SImode: - case E_V4DImode: - temp = gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)); - emit_move_insn (target, temp); - return; + switch (vmode) + { + case E_V32QImode: + case E_V16HImode: + case E_V8SImode: + case E_V4DImode: + case E_V16QImode: + case E_V8HImode: + case E_V4SImode: + case E_V2DImode: + loongarch_emit_move (target, gen_rtx_VEC_DUPLICATE (vmode, temp)); + break; - default: - gcc_unreachable (); - } - } + case E_V8SFmode: + emit_insn (gen_lasx_xvreplve0_w_f_scalar (target, temp)); + break; - temp = gen_reg_rtx (imode); - if (imode == GET_MODE (same)) - temp2 = same; - else if (GET_MODE_SIZE (imode) >= UNITS_PER_WORD) - { - if (GET_CODE (same) == MEM) - { - rtx reg_tmp = gen_reg_rtx (GET_MODE (same)); - loongarch_emit_move (reg_tmp, same); - temp2 = simplify_gen_subreg (imode, reg_tmp, - GET_MODE (reg_tmp), 0); - } - else - temp2 = simplify_gen_subreg (imode, same, - GET_MODE (same), 0); - } - else - { - if (GET_CODE (same) == MEM) - { - rtx reg_tmp = gen_reg_rtx (GET_MODE (same)); - loongarch_emit_move (reg_tmp, same); - temp2 = lowpart_subreg (imode, reg_tmp, - GET_MODE (reg_tmp)); - } - else - temp2 = lowpart_subreg (imode, same, GET_MODE (same)); - } - emit_move_insn (temp, temp2); + case E_V4DFmode: + emit_insn (gen_lasx_xvreplve0_d_f_scalar (target, temp)); + break; - switch (vmode) - { - case E_V32QImode: - case E_V16HImode: - case E_V8SImode: - case E_V4DImode: - loongarch_emit_move (target, - gen_rtx_VEC_DUPLICATE (vmode, temp)); - break; + case E_V4SFmode: + emit_insn (gen_lsx_vreplvei_w_f_scalar (target, temp)); + break; - case E_V8SFmode: - emit_insn (gen_lasx_xvreplve0_w_f_scalar (target, temp)); - break; + case E_V2DFmode: + emit_insn (gen_lsx_vreplvei_d_f_scalar (target, temp)); + break; - case E_V4DFmode: - emit_insn (gen_lasx_xvreplve0_d_f_scalar (target, temp)); - break; + default: + gcc_unreachable (); + } +} - default: - gcc_unreachable (); - } - } - else - { - rtvec vec = shallow_copy_rtvec (XVEC (vals, 0)); +/* Expand a vector initialization. */ - for (i = 0; i < nelt; ++i) - RTVEC_ELT (vec, i) = CONST0_RTX (imode); +void +loongarch_expand_vector_init (rtx target, rtx vals) +{ + machine_mode vmode = GET_MODE (target); + machine_mode imode = GET_MODE_INNER (vmode); + unsigned i, nelt = GET_MODE_NUNITS (vmode); + /* VALS is divided into high and low half-part. */ + /* Number of non constant elements in corresponding parts of VALS. */ + unsigned nvar = 0, hi_nvar = 0, lo_nvar = 0; + /* all_same : true if all elements of VALS are the same. + hi_same : true if all elements of the high half-part are the same. + lo_same : true if all elements of the low half-part are the same. + half_same : true if the high half-part is the same as the low one. */ + bool all_same = false, hi_same = true, lo_same = true, half_same = true; + rtx val[32], val_hi[32], val_lo[16]; + rtx x, op0, op1; + /* Copy one element of vals to per element of target vector. */ + typedef rtx (*loongarch_vec_repl1_fn) (rtx, rtx); + /* Copy two elements of vals to target vector. */ + typedef rtx (*loongarch_vec_repl2_fn) (rtx, rtx, rtx); + /* Insert scalar operands into the specified position of the vector. */ + typedef rtx (*loongarch_vec_set_fn) (rtx, rtx, rtx); + /* Copy 64bit lowpart to highpart. */ + typedef rtx (*loongarch_vec_mirror_fn) (rtx, rtx, rtx); + /* Merge lowpart and highpart into target. */ + typedef rtx (*loongarch_vec_merge_fn) (rtx, rtx, rtx, rtx); + + loongarch_vec_repl1_fn loongarch_vec_repl1_128 = NULL, + loongarch_vec_repl1_256 = NULL; + loongarch_vec_repl2_fn loongarch_vec_repl2_128 = NULL, + loongarch_vec_repl2_256 = NULL; + loongarch_vec_set_fn loongarch_vec_set128 = NULL, loongarch_vec_set256 = NULL; + loongarch_vec_mirror_fn loongarch_vec_mirror = NULL; + loongarch_vec_merge_fn loongarch_lasx_vecinit_merge = NULL; + machine_mode half_mode = VOIDmode; + + /* Check whether elements of each part are the same. */ + for (i = 0; i < nelt / 2; ++i) + { + val_hi[i] = val_hi[i + nelt / 2] = val[i + nelt / 2] + = XVECEXP (vals, 0, i + nelt / 2); + val_lo[i] = val[i] = XVECEXP (vals, 0, i); + if (!loongarch_constant_elt_p (val_hi[i])) + hi_nvar++; + if (!loongarch_constant_elt_p (val_lo[i])) + lo_nvar++; + if (i > 0 && !rtx_equal_p (val_hi[i], val_hi[0])) + hi_same = false; + if (i > 0 && !rtx_equal_p (val_lo[i], val_lo[0])) + lo_same = false; + if (!rtx_equal_p (val_hi[i], val_lo[i])) + half_same = false; + } + + /* If all elements are the same, set all_same true. */ + if (hi_same && lo_same && half_same) + all_same = true; + + nvar = hi_nvar + lo_nvar; - emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec)); + switch (vmode) + { + case E_V32QImode: + half_mode = E_V16QImode; + loongarch_vec_set256 = gen_vec_setv32qi_internal; + loongarch_vec_repl1_256 = gen_lasx_xvreplgr2vr_b; + loongarch_lasx_vecinit_merge + = half_same ? gen_lasx_xvpermi_q_v32qi : gen_lasx_vecinit_merge_v32qi; + /* FALLTHRU. */ + case E_V16QImode: + loongarch_vec_set128 = gen_vec_setv16qi; + loongarch_vec_repl1_128 = gen_lsx_vreplgr2vr_b; + loongarch_vec_mirror = gen_lsx_vreplvei_mirror_b; + break; - machine_mode half_mode = VOIDmode; - rtx target_hi, target_lo; + case E_V16HImode: + half_mode = E_V8HImode; + loongarch_vec_set256 = gen_vec_setv16hi_internal; + loongarch_vec_repl1_256 = gen_lasx_xvreplgr2vr_h; + loongarch_lasx_vecinit_merge + = half_same ? gen_lasx_xvpermi_q_v16hi : gen_lasx_vecinit_merge_v16hi; + /* FALLTHRU. */ + case E_V8HImode: + loongarch_vec_set128 = gen_vec_setv8hi; + loongarch_vec_repl1_128 = gen_lsx_vreplgr2vr_h; + loongarch_vec_mirror = gen_lsx_vreplvei_mirror_h; + break; - switch (vmode) - { - case E_V32QImode: - half_mode=E_V16QImode; - target_hi = gen_reg_rtx (half_mode); - target_lo = gen_reg_rtx (half_mode); - for (i = 0; i < nelt/2; ++i) - { - rtx temp_hi = gen_reg_rtx (imode); - rtx temp_lo = gen_reg_rtx (imode); - emit_move_insn (temp_hi, XVECEXP (vals, 0, i+nelt/2)); - emit_move_insn (temp_lo, XVECEXP (vals, 0, i)); - if (i == 0) - { - emit_insn (gen_lsx_vreplvei_b_scalar (target_hi, - temp_hi)); - emit_insn (gen_lsx_vreplvei_b_scalar (target_lo, - temp_lo)); - } - else - { - emit_insn (gen_vec_setv16qi (target_hi, temp_hi, - GEN_INT (i))); - emit_insn (gen_vec_setv16qi (target_lo, temp_lo, - GEN_INT (i))); - } - } - emit_insn (gen_rtx_SET (target, - gen_rtx_VEC_CONCAT (vmode, target_hi, - target_lo))); - break; + case E_V8SImode: + half_mode = V4SImode; + loongarch_vec_set256 = gen_vec_setv8si; + loongarch_vec_repl1_256 = gen_lasx_xvreplgr2vr_w; + loongarch_lasx_vecinit_merge + = half_same ? gen_lasx_xvpermi_q_v8si : gen_lasx_vecinit_merge_v8si; + /* FALLTHRU. */ + case E_V4SImode: + loongarch_vec_set128 = gen_vec_setv4si; + loongarch_vec_repl1_128 = gen_lsx_vreplgr2vr_w; + loongarch_vec_mirror = gen_lsx_vreplvei_mirror_w; + break; - case E_V16HImode: - half_mode=E_V8HImode; - target_hi = gen_reg_rtx (half_mode); - target_lo = gen_reg_rtx (half_mode); - for (i = 0; i < nelt/2; ++i) - { - rtx temp_hi = gen_reg_rtx (imode); - rtx temp_lo = gen_reg_rtx (imode); - emit_move_insn (temp_hi, XVECEXP (vals, 0, i+nelt/2)); - emit_move_insn (temp_lo, XVECEXP (vals, 0, i)); - if (i == 0) - { - emit_insn (gen_lsx_vreplvei_h_scalar (target_hi, - temp_hi)); - emit_insn (gen_lsx_vreplvei_h_scalar (target_lo, - temp_lo)); - } - else - { - emit_insn (gen_vec_setv8hi (target_hi, temp_hi, - GEN_INT (i))); - emit_insn (gen_vec_setv8hi (target_lo, temp_lo, - GEN_INT (i))); - } - } - emit_insn (gen_rtx_SET (target, - gen_rtx_VEC_CONCAT (vmode, target_hi, - target_lo))); - break; + case E_V4DImode: + half_mode = E_V2DImode; + loongarch_vec_set256 = gen_vec_setv4di; + loongarch_vec_repl1_256 = gen_lasx_xvreplgr2vr_d; + loongarch_lasx_vecinit_merge + = half_same ? gen_lasx_xvpermi_q_v4di : gen_lasx_vecinit_merge_v4di; + /* FALLTHRU. */ + case E_V2DImode: + loongarch_vec_set128 = gen_vec_setv2di; + loongarch_vec_repl1_128 = gen_lsx_vreplgr2vr_d; + loongarch_vec_mirror = gen_lsx_vreplvei_mirror_d; + break; - case E_V8SImode: - half_mode=V4SImode; - target_hi = gen_reg_rtx (half_mode); - target_lo = gen_reg_rtx (half_mode); - for (i = 0; i < nelt/2; ++i) - { - rtx temp_hi = gen_reg_rtx (imode); - rtx temp_lo = gen_reg_rtx (imode); - emit_move_insn (temp_hi, XVECEXP (vals, 0, i+nelt/2)); - emit_move_insn (temp_lo, XVECEXP (vals, 0, i)); - if (i == 0) - { - emit_insn (gen_lsx_vreplvei_w_scalar (target_hi, - temp_hi)); - emit_insn (gen_lsx_vreplvei_w_scalar (target_lo, - temp_lo)); - } - else - { - emit_insn (gen_vec_setv4si (target_hi, temp_hi, - GEN_INT (i))); - emit_insn (gen_vec_setv4si (target_lo, temp_lo, - GEN_INT (i))); - } - } - emit_insn (gen_rtx_SET (target, - gen_rtx_VEC_CONCAT (vmode, target_hi, - target_lo))); - break; + case E_V8SFmode: + half_mode = E_V4SFmode; + loongarch_vec_set256 = gen_vec_setv8sf; + loongarch_vec_repl1_128 = gen_lsx_vreplvei_w_f_scalar; + loongarch_vec_repl2_256 = gen_lasx_xvilvl_w_f_internal; + loongarch_lasx_vecinit_merge + = half_same ? gen_lasx_xvpermi_q_v8sf : gen_lasx_vecinit_merge_v8sf; + /* FALLTHRU. */ + case E_V4SFmode: + loongarch_vec_set128 = gen_vec_setv4sf; + loongarch_vec_repl2_128 = gen_lsx_vilvl_w_f_internal; + loongarch_vec_mirror = gen_lsx_vreplvei_mirror_w_f; + break; - case E_V4DImode: - half_mode=E_V2DImode; - target_hi = gen_reg_rtx (half_mode); - target_lo = gen_reg_rtx (half_mode); - for (i = 0; i < nelt/2; ++i) - { - rtx temp_hi = gen_reg_rtx (imode); - rtx temp_lo = gen_reg_rtx (imode); - emit_move_insn (temp_hi, XVECEXP (vals, 0, i+nelt/2)); - emit_move_insn (temp_lo, XVECEXP (vals, 0, i)); - if (i == 0) - { - emit_insn (gen_lsx_vreplvei_d_scalar (target_hi, - temp_hi)); - emit_insn (gen_lsx_vreplvei_d_scalar (target_lo, - temp_lo)); - } - else - { - emit_insn (gen_vec_setv2di (target_hi, temp_hi, - GEN_INT (i))); - emit_insn (gen_vec_setv2di (target_lo, temp_lo, - GEN_INT (i))); - } - } - emit_insn (gen_rtx_SET (target, - gen_rtx_VEC_CONCAT (vmode, target_hi, - target_lo))); - break; + case E_V4DFmode: + half_mode = E_V2DFmode; + loongarch_vec_set256 = gen_vec_setv4df; + loongarch_vec_repl1_128 = gen_lsx_vreplvei_d_f_scalar; + loongarch_vec_repl2_256 = gen_lasx_xvilvl_d_f_internal; + loongarch_lasx_vecinit_merge + = half_same ? gen_lasx_xvpermi_q_v4df : gen_lasx_vecinit_merge_v4df; + /* FALLTHRU. */ + case E_V2DFmode: + loongarch_vec_set128 = gen_vec_setv2df; + loongarch_vec_repl2_128 = gen_lsx_vilvl_d_f_internal; + loongarch_vec_mirror = gen_lsx_vreplvei_mirror_d_f; + break; - case E_V8SFmode: - half_mode=E_V4SFmode; - target_hi = gen_reg_rtx (half_mode); - target_lo = gen_reg_rtx (half_mode); - for (i = 0; i < nelt/2; ++i) + default: + gcc_unreachable (); + } + + if (ISA_HAS_LASX && GET_MODE_SIZE (vmode) == 32) + { + /* If all elements are the same, just do a broadcost. */ + if (all_same) + loongarch_expand_vector_init_same (target, vals, nvar); + else + { + gcc_assert (nelt >= 4); + + rtx target_hi, target_lo; + /* Write elements of high half-part in target directly. */ + target_hi = target; + target_lo = gen_reg_rtx (half_mode); + + /* If all elements of high half-part are the same, + just do a broadcost. Also applicable to low half-part. */ + if (hi_same) + { + rtx vtmp = gen_rtx_PARALLEL (vmode, gen_rtvec_v (nelt, val_hi)); + loongarch_expand_vector_init_same (target_hi, vtmp, hi_nvar); + } + if (lo_same) + { + rtx vtmp + = gen_rtx_PARALLEL (half_mode, gen_rtvec_v (nelt / 2, val_lo)); + loongarch_expand_vector_init_same (target_lo, vtmp, lo_nvar); + } + + for (i = 0; i < nelt / 2; ++i) + { + if (!hi_same) { - rtx temp_hi = gen_reg_rtx (imode); - rtx temp_lo = gen_reg_rtx (imode); - emit_move_insn (temp_hi, XVECEXP (vals, 0, i+nelt/2)); - emit_move_insn (temp_lo, XVECEXP (vals, 0, i)); - if (i == 0) + if (vmode == E_V8SFmode || vmode == E_V4DFmode) { - emit_insn (gen_lsx_vreplvei_w_f_scalar (target_hi, - temp_hi)); - emit_insn (gen_lsx_vreplvei_w_f_scalar (target_lo, - temp_lo)); + /* Using xvilvl to load lowest 2 elements simultaneously + to reduce the number of instructions. */ + if (i == 1) + { + op0 = gen_reg_rtx (imode); + emit_move_insn (op0, val_hi[0]); + op1 = gen_reg_rtx (imode); + emit_move_insn (op1, val_hi[1]); + emit_insn ( + loongarch_vec_repl2_256 (target_hi, op0, op1)); + } + else if (i > 1) + { + op0 = gen_reg_rtx (imode); + emit_move_insn (op0, val_hi[i]); + emit_insn ( + loongarch_vec_set256 (target_hi, op0, GEN_INT (i))); + } } else { - emit_insn (gen_vec_setv4sf (target_hi, temp_hi, - GEN_INT (i))); - emit_insn (gen_vec_setv4sf (target_lo, temp_lo, - GEN_INT (i))); + /* Assign the lowest element of val_hi to all elements + of target_hi. */ + if (i == 0) + { + op0 = gen_reg_rtx (imode); + emit_move_insn (op0, val_hi[0]); + emit_insn (loongarch_vec_repl1_256 (target_hi, op0)); + } + else if (!rtx_equal_p (val_hi[i], val_hi[0])) + { + op0 = gen_reg_rtx (imode); + emit_move_insn (op0, val_hi[i]); + emit_insn ( + loongarch_vec_set256 (target_hi, op0, GEN_INT (i))); + } } } - emit_insn (gen_rtx_SET (target, - gen_rtx_VEC_CONCAT (vmode, target_hi, - target_lo))); - break; - - case E_V4DFmode: - half_mode=E_V2DFmode; - target_hi = gen_reg_rtx (half_mode); - target_lo = gen_reg_rtx (half_mode); - for (i = 0; i < nelt/2; ++i) + if (!lo_same && !half_same) { - rtx temp_hi = gen_reg_rtx (imode); - rtx temp_lo = gen_reg_rtx (imode); - emit_move_insn (temp_hi, XVECEXP (vals, 0, i+nelt/2)); - emit_move_insn (temp_lo, XVECEXP (vals, 0, i)); + /* Assign the lowest element of val_lo to all elements + of target_lo. */ if (i == 0) { - emit_insn (gen_lsx_vreplvei_d_f_scalar (target_hi, - temp_hi)); - emit_insn (gen_lsx_vreplvei_d_f_scalar (target_lo, - temp_lo)); + op0 = gen_reg_rtx (imode); + emit_move_insn (op0, val_lo[0]); + emit_insn (loongarch_vec_repl1_128 (target_lo, op0)); } - else + else if (!rtx_equal_p (val_lo[i], val_lo[0])) { - emit_insn (gen_vec_setv2df (target_hi, temp_hi, - GEN_INT (i))); - emit_insn (gen_vec_setv2df (target_lo, temp_lo, - GEN_INT (i))); + op0 = gen_reg_rtx (imode); + emit_move_insn (op0, val_lo[i]); + emit_insn ( + loongarch_vec_set128 (target_lo, op0, GEN_INT (i))); } } - emit_insn (gen_rtx_SET (target, - gen_rtx_VEC_CONCAT (vmode, target_hi, - target_lo))); - break; - - default: - gcc_unreachable (); } - + if (half_same) + { + emit_insn (loongarch_lasx_vecinit_merge (target, target_hi, + target_hi, const0_rtx)); + return; + } + emit_insn (loongarch_lasx_vecinit_merge (target, target_hi, target_lo, + GEN_INT (0x20))); } return; } @@ -10500,130 +10544,54 @@ loongarch_expand_vector_init (rtx target, rtx vals) if (ISA_HAS_LSX) { if (all_same) + loongarch_expand_vector_init_same (target, vals, nvar); + else { - rtx same = XVECEXP (vals, 0, 0); - rtx temp, temp2; - - if (CONST_INT_P (same) && nvar == 0 - && loongarch_signed_immediate_p (INTVAL (same), 10, 0)) - { - switch (vmode) - { - case E_V16QImode: - case E_V8HImode: - case E_V4SImode: - case E_V2DImode: - temp = gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)); - emit_move_insn (target, temp); - return; - - default: - gcc_unreachable (); - } - } - temp = gen_reg_rtx (imode); - if (imode == GET_MODE (same)) - temp2 = same; - else if (GET_MODE_SIZE (imode) >= UNITS_PER_WORD) - { - if (GET_CODE (same) == MEM) - { - rtx reg_tmp = gen_reg_rtx (GET_MODE (same)); - loongarch_emit_move (reg_tmp, same); - temp2 = simplify_gen_subreg (imode, reg_tmp, - GET_MODE (reg_tmp), 0); - } - else - temp2 = simplify_gen_subreg (imode, same, GET_MODE (same), 0); - } - else + for (i = 0; i < nelt; ++i) { - if (GET_CODE (same) == MEM) + if (vmode == E_V4SFmode || vmode == E_V2DFmode) { - rtx reg_tmp = gen_reg_rtx (GET_MODE (same)); - loongarch_emit_move (reg_tmp, same); - temp2 = lowpart_subreg (imode, reg_tmp, GET_MODE (reg_tmp)); + /* Using vilvl to load lowest 2 elements simultaneously to + reduce the number of instructions. */ + if (i == 1) + { + op0 = gen_reg_rtx (imode); + emit_move_insn (op0, val[0]); + op1 = gen_reg_rtx (imode); + emit_move_insn (op1, val[1]); + emit_insn (loongarch_vec_repl2_128 (target, op0, op1)); + } + else if (i > 1) + { + op0 = gen_reg_rtx (imode); + emit_move_insn (op0, val[i]); + emit_insn ( + loongarch_vec_set128 (target, op0, GEN_INT (i))); + } } else - temp2 = lowpart_subreg (imode, same, GET_MODE (same)); - } - emit_move_insn (temp, temp2); - - switch (vmode) - { - case E_V16QImode: - case E_V8HImode: - case E_V4SImode: - case E_V2DImode: - loongarch_emit_move (target, gen_rtx_VEC_DUPLICATE (vmode, temp)); - break; - - case E_V4SFmode: - emit_insn (gen_lsx_vreplvei_w_f_scalar (target, temp)); - break; - - case E_V2DFmode: - emit_insn (gen_lsx_vreplvei_d_f_scalar (target, temp)); - break; - - default: - gcc_unreachable (); - } - } - else - { - emit_move_insn (target, CONST0_RTX (vmode)); - - for (i = 0; i < nelt; ++i) - { - rtx temp = gen_reg_rtx (imode); - emit_move_insn (temp, XVECEXP (vals, 0, i)); - switch (vmode) { - case E_V16QImode: - if (i == 0) - emit_insn (gen_lsx_vreplvei_b_scalar (target, temp)); - else - emit_insn (gen_vec_setv16qi (target, temp, GEN_INT (i))); - break; - - case E_V8HImode: - if (i == 0) - emit_insn (gen_lsx_vreplvei_h_scalar (target, temp)); - else - emit_insn (gen_vec_setv8hi (target, temp, GEN_INT (i))); - break; - - case E_V4SImode: - if (i == 0) - emit_insn (gen_lsx_vreplvei_w_scalar (target, temp)); - else - emit_insn (gen_vec_setv4si (target, temp, GEN_INT (i))); - break; - - case E_V2DImode: - if (i == 0) - emit_insn (gen_lsx_vreplvei_d_scalar (target, temp)); - else - emit_insn (gen_vec_setv2di (target, temp, GEN_INT (i))); - break; - - case E_V4SFmode: - if (i == 0) - emit_insn (gen_lsx_vreplvei_w_f_scalar (target, temp)); - else - emit_insn (gen_vec_setv4sf (target, temp, GEN_INT (i))); - break; - - case E_V2DFmode: + if (half_same && i == nelt / 2) + { + emit_insn ( + loongarch_vec_mirror (target, target, const0_rtx)); + return; + } + /* Assign the lowest element of val to all elements of + target. */ if (i == 0) - emit_insn (gen_lsx_vreplvei_d_f_scalar (target, temp)); - else - emit_insn (gen_vec_setv2df (target, temp, GEN_INT (i))); - break; - - default: - gcc_unreachable (); + { + op0 = gen_reg_rtx (imode); + emit_move_insn (op0, val[0]); + emit_insn (loongarch_vec_repl1_128 (target, op0)); + } + else if (!rtx_equal_p (val[i], val[0])) + { + op0 = gen_reg_rtx (imode); + emit_move_insn (op0, val[i]); + emit_insn ( + loongarch_vec_set128 (target, op0, GEN_INT (i))); + } } } } @@ -10640,8 +10608,8 @@ loongarch_expand_vector_init (rtx target, rtx vals) /* For two-part initialization, always use CONCAT. */ if (nelt == 2) { - rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0)); - rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1)); + rtx op0 = force_reg (imode, val[0]); + rtx op1 = force_reg (imode, val[1]); x = gen_rtx_VEC_CONCAT (vmode, op0, op1); emit_insn (gen_rtx_SET (target, x)); return; diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index fb4d228..075f6ba 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -176,6 +176,8 @@ UNSPEC_LSX_VSSRARNI UNSPEC_LSX_VSSRARNI2 UNSPEC_LSX_VPERMI + UNSPEC_LSX_VILVL_INTERNAL + UNSPEC_LSX_VREPLVEI_MIRROR ]) ;; This attribute gives suffix for integers in VHMODE. @@ -1551,6 +1553,18 @@ [(set_attr "type" "simd_flog2") (set_attr "mode" "<MODE>")]) +;; Only for loongarch_expand_vector_init in loongarch.cc. +;; Merge two scalar floating-point op1 and op2 into a LSX op0. +(define_insn "lsx_vilvl_<lsxfmt_f>_internal" + [(set (match_operand:FLSX 0 "register_operand" "=f") + (unspec:FLSX [(match_operand:<UNITMODE> 1 "register_operand" "f") + (match_operand:<UNITMODE> 2 "register_operand" "f")] + UNSPEC_LSX_VILVL_INTERNAL))] + "ISA_HAS_LSX" + "vilvl.<lsxfmt>\t%w0,%w2,%w1" + [(set_attr "type" "simd_permute") + (set_attr "mode" "<MODE>")]) + (define_insn "smax<mode>3" [(set (match_operand:FLSX 0 "register_operand" "=f") (smax:FLSX (match_operand:FLSX 1 "register_operand" "f") @@ -2289,6 +2303,16 @@ [(set_attr "type" "simd_splat") (set_attr "mode" "<MODE>")]) +(define_insn "lsx_vreplvei_mirror_<lsxfmt_f>" + [(set (match_operand:LSX 0 "register_operand" "=f") + (unspec: LSX [(match_operand:LSX 1 "register_operand" "f") + (match_operand 2 "const_<indeximm>_operand" "")] + UNSPEC_LSX_VREPLVEI_MIRROR))] + "ISA_HAS_LSX" + "vreplvei.d\t%w0,%w1,%2" + [(set_attr "type" "simd_splat") + (set_attr "mode" "<MODE>")]) + (define_insn "lsx_vreplvei_<lsxfmt_f>" [(set (match_operand:LSX 0 "register_operand" "=f") (vec_duplicate:LSX @@ -2450,6 +2474,99 @@ DONE; }) +;; Implement vec_concatv2df by vilvl.d. +(define_insn_and_split "vec_concatv2df" + [(set (match_operand:V2DF 0 "register_operand" "=f") + (vec_concat:V2DF + (match_operand:DF 1 "register_operand" "f") + (match_operand:DF 2 "register_operand" "f")))] + "ISA_HAS_LSX" + "" + "&& reload_completed" + [(const_int 0)] +{ + emit_insn (gen_lsx_vilvl_d_f (operands[0], + gen_rtx_REG (V2DFmode, REGNO (operands[1])), + gen_rtx_REG (V2DFmode, REGNO (operands[2])))); + DONE; +} + [(set_attr "mode" "V2DF")]) + +;; Implement vec_concatv4sf. +;; Optimize based on hardware register allocation of operands. +(define_insn_and_split "vec_concatv4sf" + [(set (match_operand:V4SF 0 "register_operand" "=f") + (vec_concat:V4SF + (vec_concat:V2SF + (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")) + (vec_concat:V2SF + (match_operand:SF 3 "register_operand" "f") + (match_operand:SF 4 "register_operand" "f"))))] + "ISA_HAS_LSX" + "" + "&& reload_completed" + [(const_int 0)] +{ + operands[5] = GEN_INT (1); + operands[6] = GEN_INT (2); + operands[7] = GEN_INT (4); + operands[8] = GEN_INT (8); + + /* If all input are same, use vreplvei.w to broadcast. */ + if (REGNO (operands[1]) == REGNO (operands[2]) + && REGNO (operands[1]) == REGNO (operands[3]) + && REGNO (operands[1]) == REGNO (operands[4])) + { + emit_insn (gen_lsx_vreplvei_w_f_scalar (operands[0], operands[1])); + } + /* If op0 is equal to op3, use vreplvei.w to set each element of op0 as op3. + If other input is different from op3, use vextrins.w to insert. */ + else if (REGNO (operands[0]) == REGNO (operands[3])) + { + emit_insn (gen_lsx_vreplvei_w_f_scalar (operands[0], operands[3])); + if (REGNO (operands[1]) != REGNO (operands[3])) + emit_insn (gen_lsx_vextrins_w_f_scalar (operands[0], operands[1], + operands[0], operands[5])); + if (REGNO (operands[2]) != REGNO (operands[3])) + emit_insn (gen_lsx_vextrins_w_f_scalar (operands[0], operands[2], + operands[0], operands[6])); + if (REGNO (operands[4]) != REGNO (operands[3])) + emit_insn (gen_lsx_vextrins_w_f_scalar (operands[0], operands[4], + operands[0], operands[8])); + } + /* If op0 is equal to op4, use vreplvei.w to set each element of op0 as op4. + If other input is different from op4, use vextrins.w to insert. */ + else if (REGNO (operands[0]) == REGNO (operands[4])) + { + emit_insn (gen_lsx_vreplvei_w_f_scalar (operands[0], operands[4])); + if (REGNO (operands[1]) != REGNO (operands[4])) + emit_insn (gen_lsx_vextrins_w_f_scalar (operands[0], operands[1], + operands[0], operands[5])); + if (REGNO (operands[2]) != REGNO (operands[4])) + emit_insn (gen_lsx_vextrins_w_f_scalar (operands[0], operands[2], + operands[0], operands[6])); + if (REGNO (operands[3]) != REGNO (operands[4])) + emit_insn (gen_lsx_vextrins_w_f_scalar (operands[0], operands[3], + operands[0], operands[7])); + } + /* Otherwise, use vilvl.w to merge op1 and op2 first. + If op3 is different from op1, use vextrins.w to insert. + If op4 is different from op2, use vextrins.w to insert. */ + else + { + emit_insn ( + gen_lsx_vilvl_w_f (operands[0], + gen_rtx_REG (V4SFmode, REGNO (operands[1])), + gen_rtx_REG (V4SFmode, REGNO (operands[2])))); + emit_insn (gen_lsx_vextrins_w_f_scalar (operands[0], operands[3], + operands[0], operands[7])); + emit_insn (gen_lsx_vextrins_w_f_scalar (operands[0], operands[4], + operands[0], operands[8])); + } + DONE; +} + [(set_attr "mode" "V4SF")]) (define_insn "vandn<mode>3" [(set (match_operand:LSX 0 "register_operand" "=f") @@ -4465,3 +4582,20 @@ "vpermi.w\t%w0,%w2,%3" [(set_attr "type" "simd_bit") (set_attr "mode" "V4SI")]) + +;; Delete one of two instructions that exactly play the same role. +(define_peephole2 + [(set (match_operand:V2DI 0 "register_operand") + (vec_duplicate:V2DI (match_operand:DI 1 "register_operand"))) + (set (match_operand:V2DI 2 "register_operand") + (vec_merge:V2DI + (vec_duplicate:V2DI (match_operand:DI 3 "register_operand")) + (match_operand:V2DI 4 "register_operand") + (match_operand 5 "const_int_operand")))] + "operands[0] == operands[2] && + operands[1] == operands[3] && + operands[2] == operands[4] && + INTVAL (operands[5]) == 2" + [(set (match_dup 0) + (vec_duplicate:V2DI (match_dup 1)))] + "") diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index a97a095..d0f8b3c 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -99,41 +99,37 @@ ;; Currently supported operations: ;; abs(FP) (define_insn_and_split "*cond_abs<mode>" - [(set (match_operand:VF 0 "register_operand") - (if_then_else:VF - (match_operand:<VM> 3 "register_operand") - (abs:VF (match_operand:VF 1 "nonmemory_operand")) - (match_operand:VF 2 "register_operand")))] + [(set (match_operand:V_VLSF 0 "register_operand") + (if_then_else:V_VLSF + (match_operand:<VM> 1 "register_operand") + (abs:V_VLSF (match_operand:V_VLSF 2 "nonmemory_operand")) + (match_operand:V_VLSF 3 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" [(const_int 0)] { - emit_insn (gen_cond_len_abs<mode> (operands[0], operands[3], operands[1], - operands[2], - gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred (ABS, <MODE>mode); + riscv_vector::expand_cond_unop (icode, operands); DONE; } [(set_attr "type" "vector")]) ;; Combine vfsqrt.v and cond_mask (define_insn_and_split "*cond_<optab><mode>" - [(set (match_operand:VF 0 "register_operand") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand") + (if_then_else:V_VLSF (match_operand:<VM> 1 "register_operand") - (any_float_unop:VF - (match_operand:VF 2 "register_operand")) - (match_operand:VF 3 "register_operand")))] + (any_float_unop:V_VLSF + (match_operand:V_VLSF 2 "register_operand")) + (match_operand:V_VLSF 3 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" [(const_int 0)] { insn_code icode = code_for_pred (<CODE>, <MODE>mode); - rtx ops[] = {operands[0], operands[1], operands[2], operands[3], - gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)}; - riscv_vector::expand_cond_len_unop (icode, ops); + riscv_vector::expand_cond_unop (icode, operands); DONE; } [(set_attr "type" "vector")]) @@ -266,7 +262,7 @@ (if_then_else:<VCONVERT> (match_operand:<VM> 1 "register_operand") (any_fix:<VCONVERT> - (match_operand:VF 2 "register_operand")) + (match_operand:V_VLSF 2 "register_operand")) (match_operand:<VCONVERT> 3 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" @@ -283,12 +279,12 @@ ;; Combine convert(INT->FP) + vcond_mask (define_insn_and_split "*cond_<float_cvt><vconvert><mode>" - [(set (match_operand:VF 0 "register_operand") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand") + (if_then_else:V_VLSF (match_operand:<VM> 1 "register_operand") - (any_float:VF + (any_float:V_VLSF (match_operand:<VCONVERT> 2 "register_operand")) - (match_operand:VF 3 "register_operand")))] + (match_operand:V_VLSF 3 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -325,12 +321,12 @@ ;; Combine convert(INT->2xFP) + vcond_mask (define_insn_and_split "*cond_<float_cvt><vnconvert><mode>" - [(set (match_operand:VF 0 "register_operand") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand") + (if_then_else:V_VLSF (match_operand:<VM> 1 "register_operand") - (any_float:VF + (any_float:V_VLSF (match_operand:<VNCONVERT> 2 "register_operand")) - (match_operand:VF 3 "register_operand")))] + (match_operand:V_VLSF 3 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -350,7 +346,7 @@ (if_then_else:<VNCONVERT> (match_operand:<VM> 1 "register_operand") (any_fix:<VNCONVERT> - (match_operand:VF 2 "register_operand")) + (match_operand:V_VLSF 2 "register_operand")) (match_operand:<VNCONVERT> 3 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" @@ -388,13 +384,13 @@ ;; Combine vfsgnj.vv + vcond_mask (define_insn_and_split "*cond_copysign<mode>" - [(set (match_operand:VF 0 "register_operand") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand") + (if_then_else:V_VLSF (match_operand:<VM> 1 "register_operand") - (unspec:VF - [(match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand")] UNSPEC_VCOPYSIGN) - (match_operand:VF 4 "register_operand")))] + (unspec:V_VLSF + [(match_operand:V_VLSF 2 "register_operand") + (match_operand:V_VLSF 3 "register_operand")] UNSPEC_VCOPYSIGN) + (match_operand:V_VLSF 4 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -764,8 +760,8 @@ [(set (match_operand:<V_DOUBLE_EXTEND_VEL> 0 "register_operand") (unspec:<V_DOUBLE_EXTEND_VEL> [ (float_extend:<V_DOUBLE_EXTEND> - (match_operand:VF_HS_NO_M8 2 "register_operand")) - (match_operand:<V_DOUBLE_EXTEND_VEL> 1 "register_operand") + (match_operand:VF_HS_NO_M8 1 "register_operand")) + (match_operand:<V_DOUBLE_EXTEND_VEL> 2 "register_operand") ] UNSPEC_REDUC_SUM_ORDERED))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" @@ -774,7 +770,7 @@ { riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED, riscv_vector::REDUCE_OP_FRM_DYN, - operands, operands[1]); + operands, operands[2]); DONE; } [(set_attr "type" "vector")]) @@ -1119,6 +1115,78 @@ } [(set_attr "type" "vfwmuladd")]) +;; Combine mask_extend + vredsum to mask_vwredsum[u] +;; where the mrege of mask_extend is vector const 0 +(define_insn_and_split "*cond_widen_reduc_plus_scal_<mode>" + [(set (match_operand:<V_DOUBLE_EXTEND_VEL> 0 "register_operand") + (unspec:<V_DOUBLE_EXTEND_VEL> [ + (if_then_else:<V_DOUBLE_EXTEND> + (match_operand:<VM> 1 "register_operand") + (any_extend:<V_DOUBLE_EXTEND> + (match_operand:VI_QHS_NO_M8 2 "register_operand")) + (if_then_else:<V_DOUBLE_EXTEND> + (unspec:<VM> [ + (match_operand:<VM> 3 "vector_all_trues_mask_operand") + (match_operand 6 "vector_length_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_int_operand") + (match_operand 9 "const_1_or_2_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + ] UNSPEC_VPREDICATE) + (match_operand:<V_DOUBLE_EXTEND> 5 "vector_const_0_operand") + (match_operand:<V_DOUBLE_EXTEND> 4 "vector_merge_operand"))) + ] UNSPEC_REDUC_SUM))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + rtx ops[] = {operands[0], operands[2], operands[1], + gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)}; + riscv_vector::expand_reduction (<WREDUC_UNSPEC>, + riscv_vector::REDUCE_OP_M, + ops, CONST0_RTX (<V_DOUBLE_EXTEND_VEL>mode)); + DONE; +} +[(set_attr "type" "vector")]) + +;; Combine mask_extend + vfredsum to mask_vfwredusum +;; where the mrege of mask_extend is vector const 0 +(define_insn_and_split "*cond_widen_reduc_plus_scal_<mode>" + [(set (match_operand:<V_DOUBLE_EXTEND_VEL> 0 "register_operand") + (unspec:<V_DOUBLE_EXTEND_VEL> [ + (if_then_else:<V_DOUBLE_EXTEND> + (match_operand:<VM> 1 "register_operand") + (float_extend:<V_DOUBLE_EXTEND> + (match_operand:VF_HS_NO_M8 2 "register_operand")) + (if_then_else:<V_DOUBLE_EXTEND> + (unspec:<VM> [ + (match_operand:<VM> 3 "vector_all_trues_mask_operand") + (match_operand 6 "vector_length_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_int_operand") + (match_operand 9 "const_1_or_2_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + ] UNSPEC_VPREDICATE) + (match_operand:<V_DOUBLE_EXTEND> 5 "vector_const_0_operand") + (match_operand:<V_DOUBLE_EXTEND> 4 "vector_merge_operand"))) + ] UNSPEC_REDUC_SUM_UNORDERED))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + rtx ops[] = {operands[0], operands[2], operands[1], + gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)}; + riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED, + riscv_vector::REDUCE_OP_M_FRM_DYN, + ops, CONST0_RTX (<V_DOUBLE_EXTEND_VEL>mode)); + DONE; +} +[(set_attr "type" "vector")]) + ;; ============================================================================= ;; Misc combine patterns ;; ============================================================================= diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index f0f1abc..cd0cbdd 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1004,9 +1004,9 @@ ;; ------------------------------------------------------------------------------- (define_insn_and_split "abs<mode>2" - [(set (match_operand:VI 0 "register_operand") - (abs:VI - (match_operand:VI 1 "register_operand")))] + [(set (match_operand:V_VLSI 0 "register_operand") + (abs:V_VLSI + (match_operand:V_VLSI 1 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -1492,18 +1492,15 @@ ;; ------------------------------------------------------------------------- (define_expand "cond_<optab><mode>" - [(match_operand:VI 0 "register_operand") + [(match_operand:V_VLSI 0 "register_operand") (match_operand:<VM> 1 "vector_mask_operand") - (any_int_unop:VI - (match_operand:VI 2 "register_operand")) - (match_operand:VI 3 "autovec_else_operand")] + (any_int_unop:V_VLSI + (match_operand:V_VLSI 2 "register_operand")) + (match_operand:V_VLSI 3 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_<optab><mode> (operands[0], operands[1], operands[2], - operands[3], - gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred (<CODE>, <MODE>mode); + riscv_vector::expand_cond_unop (icode, operands); DONE; }) @@ -1530,18 +1527,15 @@ ;; ------------------------------------------------------------------------- (define_expand "cond_<optab><mode>" - [(match_operand:VF 0 "register_operand") + [(match_operand:V_VLSF 0 "register_operand") (match_operand:<VM> 1 "vector_mask_operand") - (any_float_unop_nofrm:VF - (match_operand:VF 2 "register_operand")) - (match_operand:VF 3 "autovec_else_operand")] + (any_float_unop_nofrm:V_VLSF + (match_operand:V_VLSF 2 "register_operand")) + (match_operand:V_VLSF 3 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_<optab><mode> (operands[0], operands[1], operands[2], - operands[3], - gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred (<CODE>, <MODE>mode); + riscv_vector::expand_cond_unop (icode, operands); DONE; }) @@ -1568,19 +1562,16 @@ ;; ------------------------------------------------------------------------- (define_expand "cond_<optab><mode>" - [(match_operand:VI 0 "register_operand") + [(match_operand:V_VLSI 0 "register_operand") (match_operand:<VM> 1 "vector_mask_operand") - (any_shift:VI - (match_operand:VI 2 "register_operand") - (match_operand:VI 3 "vector_shift_operand")) - (match_operand:VI 4 "autovec_else_operand")] + (any_shift:V_VLSI + (match_operand:V_VLSI 2 "register_operand") + (match_operand:V_VLSI 3 "vector_shift_operand")) + (match_operand:V_VLSI 4 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_<optab><mode> (operands[0], operands[1], operands[2], - operands[3], operands[4], - gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred (<CODE>, <MODE>mode); + riscv_vector::expand_cond_binop (icode, operands); DONE; }) @@ -1609,19 +1600,16 @@ ;; ------------------------------------------------------------------------- (define_expand "cond_<optab><mode>" - [(match_operand:VI 0 "register_operand") + [(match_operand:V_VLSI 0 "register_operand") (match_operand:<VM> 1 "vector_mask_operand") - (any_int_binop_no_shift:VI - (match_operand:VI 2 "<binop_rhs1_predicate>") - (match_operand:VI 3 "<binop_rhs2_predicate>")) - (match_operand:VI 4 "autovec_else_operand")] + (any_int_binop_no_shift:V_VLSI + (match_operand:V_VLSI 2 "<binop_rhs1_predicate>") + (match_operand:V_VLSI 3 "<binop_rhs2_predicate>")) + (match_operand:V_VLSI 4 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_<optab><mode> (operands[0], operands[1], operands[2], - operands[3], operands[4], - gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred (<CODE>, <MODE>mode); + riscv_vector::expand_cond_binop (icode, operands); DONE; }) @@ -1650,19 +1638,16 @@ ;; ------------------------------------------------------------------------- (define_expand "cond_<optab><mode>" - [(match_operand:VF 0 "register_operand") + [(match_operand:V_VLSF 0 "register_operand") (match_operand:<VM> 1 "vector_mask_operand") - (any_float_binop:VF - (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand")) - (match_operand:VF 4 "autovec_else_operand")] + (any_float_binop:V_VLSF + (match_operand:V_VLSF 2 "register_operand") + (match_operand:V_VLSF 3 "register_operand")) + (match_operand:V_VLSF 4 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_<optab><mode> (operands[0], operands[1], operands[2], - operands[3], operands[4], - gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred (<CODE>, <MODE>mode); + riscv_vector::expand_cond_binop (icode, operands); DONE; }) @@ -1689,19 +1674,16 @@ ;; ------------------------------------------------------------------------- (define_expand "cond_<optab><mode>" - [(match_operand:VF 0 "register_operand") + [(match_operand:V_VLSF 0 "register_operand") (match_operand:<VM> 1 "vector_mask_operand") - (any_float_binop_nofrm:VF - (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand")) - (match_operand:VF 4 "autovec_else_operand")] + (any_float_binop_nofrm:V_VLSF + (match_operand:V_VLSF 2 "register_operand") + (match_operand:V_VLSF 3 "register_operand")) + (match_operand:V_VLSF 4 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_<optab><mode> (operands[0], operands[1], operands[2], - operands[3], operands[4], - gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred (<CODE>, <MODE>mode); + riscv_vector::expand_cond_binop (icode, operands); DONE; }) @@ -1729,19 +1711,16 @@ ;; ------------------------------------------------------------------------- (define_expand "cond_fma<mode>" - [(match_operand:VI 0 "register_operand") + [(match_operand:V_VLSI 0 "register_operand") (match_operand:<VM> 1 "vector_mask_operand") - (match_operand:VI 2 "register_operand") - (match_operand:VI 3 "register_operand") - (match_operand:VI 4 "register_operand") - (match_operand:VI 5 "autovec_else_operand")] + (match_operand:V_VLSI 2 "register_operand") + (match_operand:V_VLSI 3 "register_operand") + (match_operand:V_VLSI 4 "register_operand") + (match_operand:V_VLSI 5 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_fma<mode> (operands[0], operands[1], operands[2], - operands[3], operands[4], operands[5], - gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred_mul_plus (<MODE>mode); + riscv_vector::expand_cond_ternop (icode, operands); DONE; }) @@ -1762,19 +1741,16 @@ }) (define_expand "cond_fnma<mode>" - [(match_operand:VI 0 "register_operand") + [(match_operand:V_VLSI 0 "register_operand") (match_operand:<VM> 1 "vector_mask_operand") - (match_operand:VI 2 "register_operand") - (match_operand:VI 3 "register_operand") - (match_operand:VI 4 "register_operand") - (match_operand:VI 5 "autovec_else_operand")] + (match_operand:V_VLSI 2 "register_operand") + (match_operand:V_VLSI 3 "register_operand") + (match_operand:V_VLSI 4 "register_operand") + (match_operand:V_VLSI 5 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_fnma<mode> (operands[0], operands[1], operands[2], - operands[3], operands[4], operands[5], - gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred_minus_mul (<MODE>mode); + riscv_vector::expand_cond_ternop (icode, operands); DONE; }) @@ -1802,19 +1778,16 @@ ;; ------------------------------------------------------------------------- (define_expand "cond_fma<mode>" - [(match_operand:VF 0 "register_operand") + [(match_operand:V_VLSF 0 "register_operand") (match_operand:<VM> 1 "vector_mask_operand") - (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand") - (match_operand:VF 4 "register_operand") - (match_operand:VF 5 "autovec_else_operand")] + (match_operand:V_VLSF 2 "register_operand") + (match_operand:V_VLSF 3 "register_operand") + (match_operand:V_VLSF 4 "register_operand") + (match_operand:V_VLSF 5 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_fma<mode> (operands[0], operands[1], operands[2], - operands[3], operands[4], operands[5], - gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred_mul (PLUS, <MODE>mode); + riscv_vector::expand_cond_ternop (icode, operands); DONE; }) @@ -1835,19 +1808,16 @@ }) (define_expand "cond_fnma<mode>" - [(match_operand:VF 0 "register_operand") + [(match_operand:V_VLSF 0 "register_operand") (match_operand:<VM> 1 "vector_mask_operand") - (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand") - (match_operand:VF 4 "register_operand") - (match_operand:VF 5 "autovec_else_operand")] + (match_operand:V_VLSF 2 "register_operand") + (match_operand:V_VLSF 3 "register_operand") + (match_operand:V_VLSF 4 "register_operand") + (match_operand:V_VLSF 5 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_fnma<mode> (operands[0], operands[1], operands[2], - operands[3], operands[4], operands[5], - gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred_mul_neg (PLUS, <MODE>mode); + riscv_vector::expand_cond_ternop (icode, operands); DONE; }) @@ -1868,19 +1838,16 @@ }) (define_expand "cond_fms<mode>" - [(match_operand:VF 0 "register_operand") + [(match_operand:V_VLSF 0 "register_operand") (match_operand:<VM> 1 "vector_mask_operand") - (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand") - (match_operand:VF 4 "register_operand") - (match_operand:VF 5 "autovec_else_operand")] + (match_operand:V_VLSF 2 "register_operand") + (match_operand:V_VLSF 3 "register_operand") + (match_operand:V_VLSF 4 "register_operand") + (match_operand:V_VLSF 5 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_fms<mode> (operands[0], operands[1], operands[2], - operands[3], operands[4], operands[5], - gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred_mul (MINUS, <MODE>mode); + riscv_vector::expand_cond_ternop (icode, operands); DONE; }) @@ -1901,19 +1868,16 @@ }) (define_expand "cond_fnms<mode>" - [(match_operand:VF 0 "register_operand") + [(match_operand:V_VLSF 0 "register_operand") (match_operand:<VM> 1 "vector_mask_operand") - (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand") - (match_operand:VF 4 "register_operand") - (match_operand:VF 5 "autovec_else_operand")] + (match_operand:V_VLSF 2 "register_operand") + (match_operand:V_VLSF 3 "register_operand") + (match_operand:V_VLSF 4 "register_operand") + (match_operand:V_VLSF 5 "autovec_else_operand")] "TARGET_VECTOR" { - /* Normalize into cond_len_* operations. */ - emit_insn (gen_cond_len_fnms<mode> (operands[0], operands[1], operands[2], - operands[3], operands[4], operands[5], - gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode), - const0_rtx)); + insn_code icode = code_for_pred_mul_neg (MINUS, <MODE>mode); + riscv_vector::expand_cond_ternop (icode, operands); DONE; }) @@ -2239,3 +2203,81 @@ riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, ops3); DONE; }) + +;; ------------------------------------------------------------------------- +;; ---- [FP] Math.h. +;; ------------------------------------------------------------------------- +;; Includes: +;; - ceil/ceilf +;; - floor/floorf +;; - nearbyint/nearbyintf +;; ------------------------------------------------------------------------- +(define_expand "ceil<mode>2" + [(match_operand:V_VLSF 0 "register_operand") + (match_operand:V_VLSF 1 "register_operand")] + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" + { + riscv_vector::expand_vec_ceil (operands[0], operands[1], <MODE>mode, <VCONVERT>mode); + DONE; + } +) + +(define_expand "floor<mode>2" + [(match_operand:V_VLSF 0 "register_operand") + (match_operand:V_VLSF 1 "register_operand")] + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" + { + riscv_vector::expand_vec_floor (operands[0], operands[1], <MODE>mode, <VCONVERT>mode); + DONE; + } +) + +(define_expand "nearbyint<mode>2" + [(match_operand:V_VLSF 0 "register_operand") + (match_operand:V_VLSF 1 "register_operand")] + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" + { + riscv_vector::expand_vec_nearbyint (operands[0], operands[1], <MODE>mode, <VCONVERT>mode); + DONE; + } +) + +(define_expand "rint<mode>2" + [(match_operand:V_VLSF 0 "register_operand") + (match_operand:V_VLSF 1 "register_operand")] + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" + { + riscv_vector::expand_vec_rint (operands[0], operands[1], <MODE>mode, <VCONVERT>mode); + DONE; + } +) + +(define_expand "round<mode>2" + [(match_operand:V_VLSF 0 "register_operand") + (match_operand:V_VLSF 1 "register_operand")] + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" + { + riscv_vector::expand_vec_round (operands[0], operands[1], <MODE>mode, <VCONVERT>mode); + DONE; + } +) + +(define_expand "btrunc<mode>2" + [(match_operand:V_VLSF 0 "register_operand") + (match_operand:V_VLSF 1 "register_operand")] + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" + { + riscv_vector::expand_vec_trunc (operands[0], operands[1], <MODE>mode, <VCONVERT>mode); + DONE; + } +) + +(define_expand "roundeven<mode>2" + [(match_operand:V_VLSF 0 "register_operand") + (match_operand:V_VLSF 1 "register_operand")] + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" + { + riscv_vector::expand_vec_roundeven (operands[0], operands[1], <MODE>mode, <VCONVERT>mode); + DONE; + } +) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 9ea0bcf..368982a 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -250,6 +250,18 @@ enum insn_flags : unsigned int /* flags for the floating-point rounding mode. */ /* Means INSN has FRM operand and the value is FRM_DYN. */ FRM_DYN_P = 1 << 15, + + /* Means INSN has FRM operand and the value is FRM_RUP. */ + FRM_RUP_P = 1 << 16, + + /* Means INSN has FRM operand and the value is FRM_RDN. */ + FRM_RDN_P = 1 << 17, + + /* Means INSN has FRM operand and the value is FRM_RMM. */ + FRM_RMM_P = 1 << 18, + + /* Means INSN has FRM operand and the value is FRM_RNE. */ + FRM_RNE_P = 1 << 19, }; enum insn_type : unsigned int @@ -290,6 +302,11 @@ enum insn_type : unsigned int UNARY_OP_TAMA = __MASK_OP_TAMA | UNARY_OP_P, UNARY_OP_TAMU = __MASK_OP_TAMU | UNARY_OP_P, UNARY_OP_FRM_DYN = UNARY_OP | FRM_DYN_P, + UNARY_OP_TAMU_FRM_DYN = UNARY_OP_TAMU | FRM_DYN_P, + UNARY_OP_TAMU_FRM_RUP = UNARY_OP_TAMU | FRM_RUP_P, + UNARY_OP_TAMU_FRM_RDN = UNARY_OP_TAMU | FRM_RDN_P, + UNARY_OP_TAMU_FRM_RMM = UNARY_OP_TAMU | FRM_RMM_P, + UNARY_OP_TAMU_FRM_RNE = UNARY_OP_TAMU | FRM_RNE_P, /* Binary operator. */ BINARY_OP = __NORMAL_OP | BINARY_OP_P, @@ -337,6 +354,7 @@ enum insn_type : unsigned int /* For vreduce, no mask policy operand. */ REDUCE_OP = __NORMAL_OP_TA | BINARY_OP_P | VTYPE_MODE_FROM_OP1_P, + REDUCE_OP_M = __MASK_OP_TA | BINARY_OP_P | VTYPE_MODE_FROM_OP1_P, REDUCE_OP_FRM_DYN = REDUCE_OP | FRM_DYN_P | VTYPE_MODE_FROM_OP1_P, REDUCE_OP_M_FRM_DYN = __MASK_OP_TA | BINARY_OP_P | FRM_DYN_P | VTYPE_MODE_FROM_OP1_P, @@ -364,10 +382,27 @@ enum vlmul_type NUM_LMUL = 8 }; +/* The RISC-V vsetvli pass uses "known vlmax" operations for optimization. + Whether or not an instruction actually is a vlmax operation is not + recognizable from the length operand alone but the avl_type operand + is used instead. In general, there are two cases: + + - Emit a vlmax operation by calling emit_vlmax_insn[_lra]. Here we emit + a vsetvli with vlmax configuration and set the avl_type to VLMAX for + VLA modes or VLS for VLS modes. + - Emit an operation that uses the existing (last-set) length and + set the avl_type to NONVLMAX. + + Sometimes we also need to set the VLMAX or VLS avl_type to an operation that + already uses a given length register. This can happen during or after + register allocation when we are not allowed to create a new register. + For that case we also allow to set the avl_type to VLMAX or VLS. +*/ enum avl_type { - NONVLMAX, - VLMAX, + NONVLMAX = 0, + VLMAX = 1, + VLS = 2, }; /* Routines implemented in riscv-vector-builtins.cc. */ void init_builtins (void); @@ -432,6 +467,13 @@ bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool); void expand_cond_len_unop (unsigned, rtx *); void expand_cond_len_binop (unsigned, rtx *); void expand_reduction (unsigned, unsigned, rtx *, rtx); +void expand_vec_ceil (rtx, rtx, machine_mode, machine_mode); +void expand_vec_floor (rtx, rtx, machine_mode, machine_mode); +void expand_vec_nearbyint (rtx, rtx, machine_mode, machine_mode); +void expand_vec_rint (rtx, rtx, machine_mode, machine_mode); +void expand_vec_round (rtx, rtx, machine_mode, machine_mode); +void expand_vec_trunc (rtx, rtx, machine_mode, machine_mode); +void expand_vec_roundeven (rtx, rtx, machine_mode, machine_mode); #endif bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode, bool, void (*)(rtx *, rtx)); @@ -462,6 +504,9 @@ void expand_cond_len_ternop (unsigned, rtx *); void prepare_ternary_operands (rtx *); void expand_lanes_load_store (rtx *, bool); void expand_fold_extract_last (rtx *); +void expand_cond_unop (unsigned, rtx *); +void expand_cond_binop (unsigned, rtx *); +void expand_cond_ternop (unsigned, rtx *); /* Rounding mode bitfield for fixed point VXRM. */ enum fixed_point_rounding_mode diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 366f065..26700cf 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -284,6 +284,7 @@ public: /* Add vl operand. */ rtx len = m_vl_op; + bool vls_p = false; if (m_vlmax_p) { if (riscv_v_ext_vls_mode_p (vtype_mode)) @@ -294,7 +295,7 @@ public: len = gen_int_mode (nunits, Pmode); if (!satisfies_constraint_K (len)) len = force_reg (Pmode, len); - m_vlmax_p = false; + vls_p = true; } else if (const_vlmax_p (vtype_mode)) { @@ -302,7 +303,7 @@ public: the vsetvli to obtain the value of vlmax. */ poly_uint64 nunits = GET_MODE_NUNITS (vtype_mode); len = gen_int_mode (nunits, Pmode); - m_vlmax_p = false; + vls_p = true; } else if (can_create_pseudo_p ()) { @@ -318,11 +319,21 @@ public: add_policy_operand (); /* Add avl_type operand. */ - add_avl_type_operand (m_vlmax_p ? avl_type::VLMAX : avl_type::NONVLMAX); + add_avl_type_operand ( + vls_p ? avl_type::VLS + : (m_vlmax_p ? avl_type::VLMAX : avl_type::NONVLMAX)); /* Add rounding mode operand. */ if (m_insn_flags & FRM_DYN_P) add_rounding_mode_operand (FRM_DYN); + else if (m_insn_flags & FRM_RUP_P) + add_rounding_mode_operand (FRM_RUP); + else if (m_insn_flags & FRM_RDN_P) + add_rounding_mode_operand (FRM_RDN); + else if (m_insn_flags & FRM_RMM_P) + add_rounding_mode_operand (FRM_RMM); + else if (m_insn_flags & FRM_RNE_P) + add_rounding_mode_operand (FRM_RNE); gcc_assert (insn_data[(int) icode].n_operands == m_opno); expand (icode, any_mem_p); @@ -347,33 +358,42 @@ private: expand_operand m_ops[MAX_OPERANDS]; }; -/* Emit RVV insn which vl is VLMAX. - This function can only be used before LRA pass or - for VLS_AVL_IMM modes. */ +/* Emit an RVV insn with a vector length that equals the number of units of the + vector mode. For VLA modes this corresponds to VLMAX. + + Unless the vector length can be encoded in the vsetivl[i] instruction this + function must only be used as long as we can create pseudo registers. This is + because it will set a pseudo register to VLMAX using vsetvl and use this as + definition for the vector length. */ void emit_vlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops) { insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, true); + gcc_assert (can_create_pseudo_p () || const_vlmax_p (e.get_vtype_mode (ops))); + e.emit_insn ((enum insn_code) icode, ops); } -/* Emit RVV insn which vl is VL. */ +/* Like emit_vlmax_insn but must only be used when we cannot create pseudo + registers anymore. This function, however, takes a predefined vector length + from the value in VL. */ void -emit_nonvlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) +emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) { - insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, false); + gcc_assert (!can_create_pseudo_p ()); + + insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, true); e.set_vl (vl); e.emit_insn ((enum insn_code) icode, ops); } -/* Emit RVV insn which vl is VL but the AVL_TYPE insn attr is VLMAX. - This function used after LRA pass that cann't create pseudo register. */ +/* Emit an RVV insn with a predefined vector length. Contrary to + emit_vlmax_insn the instruction's vector length is not deduced from its mode + but taken from the value in VL. */ void -emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) +emit_nonvlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) { - gcc_assert (!can_create_pseudo_p ()); - - insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, true); + insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, false); e.set_vl (vl); e.emit_insn ((enum insn_code) icode, ops); } @@ -682,9 +702,7 @@ gen_const_vector_dup (machine_mode mode, poly_int64 val) { /* When VAL is const_poly_int value, we need to explicitly broadcast it into a vector using RVV broadcast instruction. */ - rtx dup = gen_reg_rtx (mode); - emit_insn (gen_vec_duplicate (mode, dup, c)); - return dup; + return expand_vector_broadcast (mode, c); } return gen_const_vec_duplicate (mode, c); } @@ -758,22 +776,6 @@ autovec_use_vlmax_p (void) || riscv_autovec_preference == RVV_FIXED_VLMAX); } -/* The RISC-V vsetvli pass uses "known vlmax" operations for optimization. - Whether or not an instruction actually is a vlmax operation is not - recognizable from the length operand alone but the avl_type operand - is used instead. In general, there are two cases: - - - Emit a vlmax operation by passing a NULL length. Here we emit - a vsetvli with vlmax configuration and set the avl_type to VLMAX. - - Emit an operation that uses the existing (last-set) length and - set the avl_type to NONVLMAX. - - Sometimes we also need to set the VLMAX avl_type to an operation that - already uses a given length register. This can happen during or after - register allocation when we are not allowed to create a new register. - For that case we also allow to set the avl_type to VLMAX. -*/ - /* This function emits VLMAX vrgather instruction. Emit vrgather.vx/vi when sel is a const duplicate vector. Otherwise, emit vrgather.vv. */ static void @@ -790,6 +792,24 @@ emit_vlmax_gather_insn (rtx target, rtx op, rtx sel) icode = code_for_pred_gather_scalar (data_mode); sel = elt; } + else if (CONST_VECTOR_P (sel) + && GET_MODE_BITSIZE (GET_MODE_INNER (sel_mode)) > 16 + && riscv_get_v_regno_alignment (data_mode) > 1) + { + /* If the inner mode of data is not QI or HI and data_lmul > 1, + emitting vrgatherei16.vv instruction will lower register + pressure. + data_mode sel_mode ei16 + RVVM1QI RVVM1QI RVVM2HI not needed + RVVM2QI RVVM2QI RVVM4HI not needed + RVVM2HI RVVM2HI RVVM2HI not needed + RVVM2SI RVVM2SI RVVM1HI need + RVVM4SI RVVM4SI RVVM2HI need + RVVM8DI RVVM8DI RVVM2HI need */ + PUT_MODE (sel, get_vector_mode (HImode, + GET_MODE_NUNITS (data_mode)).require ()); + icode = code_for_pred_gatherei16 (data_mode); + } else icode = code_for_pred_gather (data_mode); rtx ops[] = {target, op, sel}; @@ -1129,8 +1149,9 @@ expand_const_vector (rtx target, rtx src) for (unsigned int i = 0; i < v.npatterns (); ++i) { /* Calculate the diff between the target sequence and - vid sequence. */ - HOST_WIDE_INT diff = INTVAL (builder.elt (i)) - i; + vid sequence. The elt (i) can be either const_int or + const_poly_int. */ + poly_int64 diff = rtx_to_poly_int64 (builder.elt (i)) - i; v.quick_push (gen_int_mode (diff, v.inner_mode ())); } /* Step 2: Generate result = VID + diff. */ @@ -2038,12 +2059,17 @@ static void expand_vector_init_merge_repeating_sequence (rtx target, const rvv_builder &builder) { - machine_mode dup_mode = get_repeating_sequence_dup_machine_mode (builder); - machine_mode mask_mode = get_mask_mode (builder.mode ()); + /* We can't use BIT mode (BI) directly to generate mask = 0b01010... + since we don't have such instruction in RVV. + Instead, we should use INT mode (QI/HI/SI/DI) with integer move + instruction to generate the mask data we want. */ + machine_mode mask_int_mode + = get_repeating_sequence_dup_machine_mode (builder); + machine_mode mask_bit_mode = get_mask_mode (builder.mode ()); uint64_t full_nelts = builder.full_nelts ().to_constant (); /* Step 1: Broadcast the first pattern. */ - rtx ops[] = {target, force_reg (GET_MODE_INNER (dup_mode), builder.elt (0))}; + rtx ops[] = {target, force_reg (builder.inner_mode (), builder.elt (0))}; emit_vlmax_insn (code_for_pred_broadcast (builder.mode ()), UNARY_OP, ops); /* Step 2: Merge the rest iteration of pattern. */ @@ -2051,8 +2077,8 @@ expand_vector_init_merge_repeating_sequence (rtx target, { /* Step 2-1: Generate mask register v0 for each merge. */ rtx merge_mask = builder.get_merge_scalar_mask (i); - rtx mask = gen_reg_rtx (mask_mode); - rtx dup = gen_reg_rtx (dup_mode); + rtx mask = gen_reg_rtx (mask_bit_mode); + rtx dup = gen_reg_rtx (mask_int_mode); if (full_nelts <= builder.inner_bits_size ()) /* vmv.s.x. */ { @@ -2062,14 +2088,15 @@ expand_vector_init_merge_repeating_sequence (rtx target, } else /* vmv.v.x. */ { - rtx ops[] = {dup, force_reg (GET_MODE_INNER (dup_mode), merge_mask)}; + rtx ops[] = {dup, + force_reg (GET_MODE_INNER (mask_int_mode), merge_mask)}; rtx vl = gen_int_mode (CEIL (full_nelts, builder.inner_bits_size ()), Pmode); - emit_nonvlmax_insn (code_for_pred_broadcast (dup_mode), UNARY_OP, + emit_nonvlmax_insn (code_for_pred_broadcast (mask_int_mode), UNARY_OP, ops, vl); } - emit_move_insn (mask, gen_lowpart (mask_mode, dup)); + emit_move_insn (mask, gen_lowpart (mask_bit_mode, dup)); /* Step 2-2: Merge pattern according to the mask. */ rtx ops[] = {target, target, builder.elt (i), mask}; @@ -3045,6 +3072,20 @@ expand_cond_len_unop (unsigned icode, rtx *ops) expand_cond_len_op (icode, UNARY_OP_P, cond_ops, len); } +/* Expand unary ops COND_*. */ +void +expand_cond_unop (unsigned icode, rtx *ops) +{ + rtx dest = ops[0]; + rtx mask = ops[1]; + rtx src = ops[2]; + rtx merge = get_else_operand (ops[3]); + rtx len = gen_int_mode (GET_MODE_NUNITS (GET_MODE (dest)), Pmode); + + rtx cond_ops[] = {dest, mask, merge, src}; + expand_cond_len_op (icode, UNARY_OP_P, cond_ops, len); +} + /* Expand binary ops COND_LEN_*. */ void expand_cond_len_binop (unsigned icode, rtx *ops) @@ -3060,6 +3101,21 @@ expand_cond_len_binop (unsigned icode, rtx *ops) expand_cond_len_op (icode, BINARY_OP_P, cond_ops, len); } +/* Expand binary ops COND_*. */ +void +expand_cond_binop (unsigned icode, rtx *ops) +{ + rtx dest = ops[0]; + rtx mask = ops[1]; + rtx src1 = ops[2]; + rtx src2 = ops[3]; + rtx merge = get_else_operand (ops[4]); + rtx len = gen_int_mode (GET_MODE_NUNITS (GET_MODE (dest)), Pmode); + + rtx cond_ops[] = {dest, mask, merge, src1, src2}; + expand_cond_len_op (icode, BINARY_OP_P, cond_ops, len); +} + /* Prepare insn_code for gather_load/scatter_store according to the vector mode and index mode. */ static insn_code @@ -3232,6 +3288,22 @@ expand_cond_len_ternop (unsigned icode, rtx *ops) expand_cond_len_op (icode, TERNARY_OP_P, cond_ops, len); } +/* Expand COND_*. */ +void +expand_cond_ternop (unsigned icode, rtx *ops) +{ + rtx dest = ops[0]; + rtx mask = ops[1]; + rtx src1 = ops[2]; + rtx src2 = ops[3]; + rtx src3 = ops[4]; + rtx merge = get_else_operand (ops[5]); + rtx len = gen_int_mode (GET_MODE_NUNITS (GET_MODE (dest)), Pmode); + + rtx cond_ops[] = {dest, mask, src1, src2, src3, merge}; + expand_cond_len_op (icode, TERNARY_OP_P, cond_ops, len); +} + /* Expand reduction operations. Case 1: ops = {scalar_dest, vector_src} Case 2: ops = {scalar_dest, vector_src, mask, vl} @@ -3430,4 +3502,303 @@ cmp_lmul_gt_one (machine_mode mode) return false; } +/* We don't have to convert the floating point to integer when the + mantissa is zero. Thus, ther will be a limitation for both the + single and double precision floating point. There will be no + mantissa if the floating point is greater than the limit. + + 1. Half floating point. + +-----------+---------------+ + | float | binary layout | + +-----------+---------------+ + | 1023.5 | 0x63ff | + +-----------+---------------+ + | 1024.0 | 0x6400 | + +-----------+---------------+ + | 1025.0 | 0x6401 | + +-----------+---------------+ + | ... | ... | + + All half floating point will be unchanged for ceil if it is + greater than and equal to 1024. + + 2. Single floating point. + +-----------+---------------+ + | float | binary layout | + +-----------+---------------+ + | 8388607.5 | 0x4affffff | + +-----------+---------------+ + | 8388608.0 | 0x4b000000 | + +-----------+---------------+ + | 8388609.0 | 0x4b000001 | + +-----------+---------------+ + | ... | ... | + + All single floating point will be unchanged for ceil if it is + greater than and equal to 8388608. + + 3. Double floating point. + +--------------------+--------------------+ + | float | binary layout | + +--------------------+--------------------+ + | 4503599627370495.5 | 0X432fffffffffffff | + +--------------------+--------------------+ + | 4503599627370496.0 | 0X4330000000000000 | + +--------------------+--------------------+ + | 4503599627370497.0 | 0X4340000000000000 | + +--------------------+--------------------+ + | ... | ... | + + All double floating point will be unchanged for ceil if it is + greater than and equal to 4503599627370496. + */ +static rtx +get_fp_rounding_coefficient (machine_mode inner_mode) +{ + REAL_VALUE_TYPE real; + + if (inner_mode == E_HFmode) + real_from_integer (&real, inner_mode, 1024, SIGNED); + else if (inner_mode == E_SFmode) + real_from_integer (&real, inner_mode, 8388608, SIGNED); + else if (inner_mode == E_DFmode) + real_from_integer (&real, inner_mode, 4503599627370496, SIGNED); + else + gcc_unreachable (); + + return const_double_from_real_value (real, inner_mode); +} + +static rtx +emit_vec_float_cmp_mask (rtx fp_vector, rtx_code code, rtx fp_scalar, + machine_mode vec_fp_mode) +{ + /* Step-1: Prepare the scalar float compare register. */ + rtx fp_reg = gen_reg_rtx (GET_MODE_INNER (vec_fp_mode)); + emit_insn (gen_move_insn (fp_reg, fp_scalar)); + + /* Step-2: Generate the mask. */ + machine_mode mask_mode = get_mask_mode (vec_fp_mode); + rtx mask = gen_reg_rtx (mask_mode); + rtx cmp = gen_rtx_fmt_ee (code, mask_mode, fp_vector, fp_reg); + rtx cmp_ops[] = {mask, cmp, fp_vector, fp_reg}; + insn_code icode = code_for_pred_cmp_scalar (vec_fp_mode); + emit_vlmax_insn (icode, COMPARE_OP, cmp_ops); + + return mask; +} + +static void +emit_vec_copysign (rtx op_dest, rtx op_src_0, rtx op_src_1, + machine_mode vec_mode) +{ + rtx sgnj_ops[] = {op_dest, op_src_0, op_src_1}; + insn_code icode = code_for_pred (UNSPEC_VCOPYSIGN, vec_mode); + + emit_vlmax_insn (icode, BINARY_OP, sgnj_ops); +} + +static void +emit_vec_abs (rtx op_dest, rtx op_src, machine_mode vec_mode) +{ + rtx abs_ops[] = {op_dest, op_src}; + insn_code icode = code_for_pred (ABS, vec_mode); + + emit_vlmax_insn (icode, UNARY_OP, abs_ops); +} + +static void +emit_vec_cvt_x_f (rtx op_dest, rtx op_src, rtx mask, + insn_type type, machine_mode vec_mode) +{ + rtx cvt_x_ops[] = {op_dest, mask, op_dest, op_src}; + insn_code icode = code_for_pred_fcvt_x_f (UNSPEC_VFCVT, vec_mode); + + emit_vlmax_insn (icode, type, cvt_x_ops); +} + +static void +emit_vec_cvt_f_x (rtx op_dest, rtx op_src, rtx mask, + insn_type type, machine_mode vec_mode) +{ + rtx cvt_fp_ops[] = {op_dest, mask, op_dest, op_src}; + insn_code icode = code_for_pred (FLOAT, vec_mode); + + emit_vlmax_insn (icode, type, cvt_fp_ops); +} + +static void +emit_vec_cvt_x_f_rtz (rtx op_dest, rtx op_src, rtx mask, + machine_mode vec_mode) +{ + rtx cvt_x_ops[] = {op_dest, mask, op_dest, op_src}; + insn_code icode = code_for_pred (FIX, vec_mode); + + emit_vlmax_insn (icode, UNARY_OP_TAMU, cvt_x_ops); +} + +void +expand_vec_ceil (rtx op_0, rtx op_1, machine_mode vec_fp_mode, + machine_mode vec_int_mode) +{ + /* Step-1: Get the abs float value for mask generation. */ + emit_vec_abs (op_0, op_1, vec_fp_mode); + + /* Step-2: Generate the mask on const fp. */ + rtx const_fp = get_fp_rounding_coefficient (GET_MODE_INNER (vec_fp_mode)); + rtx mask = emit_vec_float_cmp_mask (op_0, LT, const_fp, vec_fp_mode); + + /* Step-3: Convert to integer on mask, with rounding up (aka ceil). */ + rtx tmp = gen_reg_rtx (vec_int_mode); + emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMU_FRM_RUP, vec_fp_mode); + + /* Step-4: Convert to floating-point on mask for the final result. + To avoid unnecessary frm register access, we use RUP here and it will + never do the rounding up because the tmp rtx comes from the float + to int conversion. */ + emit_vec_cvt_f_x (op_0, tmp, mask, UNARY_OP_TAMU_FRM_RUP, vec_fp_mode); + + /* Step-5: Retrieve the sign bit for -0.0. */ + emit_vec_copysign (op_0, op_0, op_1, vec_fp_mode); +} + +void +expand_vec_floor (rtx op_0, rtx op_1, machine_mode vec_fp_mode, + machine_mode vec_int_mode) +{ + /* Step-1: Get the abs float value for mask generation. */ + emit_vec_abs (op_0, op_1, vec_fp_mode); + + /* Step-2: Generate the mask on const fp. */ + rtx const_fp = get_fp_rounding_coefficient (GET_MODE_INNER (vec_fp_mode)); + rtx mask = emit_vec_float_cmp_mask (op_0, LT, const_fp, vec_fp_mode); + + /* Step-3: Convert to integer on mask, with rounding down (aka floor). */ + rtx tmp = gen_reg_rtx (vec_int_mode); + emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMU_FRM_RDN, vec_fp_mode); + + /* Step-4: Convert to floating-point on mask for the floor result. */ + emit_vec_cvt_f_x (op_0, tmp, mask, UNARY_OP_TAMU_FRM_RDN, vec_fp_mode); + + /* Step-5: Retrieve the sign bit for -0.0. */ + emit_vec_copysign (op_0, op_0, op_1, vec_fp_mode); +} + +void +expand_vec_nearbyint (rtx op_0, rtx op_1, machine_mode vec_fp_mode, + machine_mode vec_int_mode) +{ + /* Step-1: Get the abs float value for mask generation. */ + emit_vec_abs (op_0, op_1, vec_fp_mode); + + /* Step-2: Generate the mask on const fp. */ + rtx const_fp = get_fp_rounding_coefficient (GET_MODE_INNER (vec_fp_mode)); + rtx mask = emit_vec_float_cmp_mask (op_0, LT, const_fp, vec_fp_mode); + + /* Step-3: Backup FP exception flags, nearbyint never raise exceptions. */ + rtx fflags = gen_reg_rtx (SImode); + emit_insn (gen_riscv_frflags (fflags)); + + /* Step-4: Convert to integer on mask, with rounding down (aka nearbyint). */ + rtx tmp = gen_reg_rtx (vec_int_mode); + emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode); + + /* Step-5: Convert to floating-point on mask for the nearbyint result. */ + emit_vec_cvt_f_x (op_0, tmp, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode); + + /* Step-6: Restore FP exception flags. */ + emit_insn (gen_riscv_fsflags (fflags)); + + /* Step-7: Retrieve the sign bit for -0.0. */ + emit_vec_copysign (op_0, op_0, op_1, vec_fp_mode); +} + +void +expand_vec_rint (rtx op_0, rtx op_1, machine_mode vec_fp_mode, + machine_mode vec_int_mode) +{ + /* Step-1: Get the abs float value for mask generation. */ + emit_vec_abs (op_0, op_1, vec_fp_mode); + + /* Step-2: Generate the mask on const fp. */ + rtx const_fp = get_fp_rounding_coefficient (GET_MODE_INNER (vec_fp_mode)); + rtx mask = emit_vec_float_cmp_mask (op_0, LT, const_fp, vec_fp_mode); + + /* Step-3: Convert to integer on mask, with dyn rounding (aka rint). */ + rtx tmp = gen_reg_rtx (vec_int_mode); + emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode); + + /* Step-4: Convert to floating-point on mask for the rint result. */ + emit_vec_cvt_f_x (op_0, tmp, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode); + + /* Step-5: Retrieve the sign bit for -0.0. */ + emit_vec_copysign (op_0, op_0, op_1, vec_fp_mode); +} + +void +expand_vec_round (rtx op_0, rtx op_1, machine_mode vec_fp_mode, + machine_mode vec_int_mode) +{ + /* Step-1: Get the abs float value for mask generation. */ + emit_vec_abs (op_0, op_1, vec_fp_mode); + + /* Step-2: Generate the mask on const fp. */ + rtx const_fp = get_fp_rounding_coefficient (GET_MODE_INNER (vec_fp_mode)); + rtx mask = emit_vec_float_cmp_mask (op_0, LT, const_fp, vec_fp_mode); + + /* Step-3: Convert to integer on mask, rounding to nearest (aka round). */ + rtx tmp = gen_reg_rtx (vec_int_mode); + emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMU_FRM_RMM, vec_fp_mode); + + /* Step-4: Convert to floating-point on mask for the round result. */ + emit_vec_cvt_f_x (op_0, tmp, mask, UNARY_OP_TAMU_FRM_RMM, vec_fp_mode); + + /* Step-5: Retrieve the sign bit for -0.0. */ + emit_vec_copysign (op_0, op_0, op_1, vec_fp_mode); +} + +void +expand_vec_trunc (rtx op_0, rtx op_1, machine_mode vec_fp_mode, + machine_mode vec_int_mode) +{ + /* Step-1: Get the abs float value for mask generation. */ + emit_vec_abs (op_0, op_1, vec_fp_mode); + + /* Step-2: Generate the mask on const fp. */ + rtx const_fp = get_fp_rounding_coefficient (GET_MODE_INNER (vec_fp_mode)); + rtx mask = emit_vec_float_cmp_mask (op_0, LT, const_fp, vec_fp_mode); + + /* Step-3: Convert to integer on mask, rounding to zero (aka truncate). */ + rtx tmp = gen_reg_rtx (vec_int_mode); + emit_vec_cvt_x_f_rtz (tmp, op_1, mask, vec_fp_mode); + + /* Step-4: Convert to floating-point on mask for the rint result. */ + emit_vec_cvt_f_x (op_0, tmp, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode); + + /* Step-5: Retrieve the sign bit for -0.0. */ + emit_vec_copysign (op_0, op_0, op_1, vec_fp_mode); +} + +void +expand_vec_roundeven (rtx op_0, rtx op_1, machine_mode vec_fp_mode, + machine_mode vec_int_mode) +{ + /* Step-1: Get the abs float value for mask generation. */ + emit_vec_abs (op_0, op_1, vec_fp_mode); + + /* Step-2: Generate the mask on const fp. */ + rtx const_fp = get_fp_rounding_coefficient (GET_MODE_INNER (vec_fp_mode)); + rtx mask = emit_vec_float_cmp_mask (op_0, LT, const_fp, vec_fp_mode); + + /* Step-3: Convert to integer on mask, rounding to nearest, ties to even. */ + rtx tmp = gen_reg_rtx (vec_int_mode); + emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMU_FRM_RNE, vec_fp_mode); + + /* Step-4: Convert to floating-point on mask for the rint result. */ + emit_vec_cvt_f_x (op_0, tmp, mask, UNARY_OP_TAMU_FRM_RNE, vec_fp_mode); + + /* Step-5: Retrieve the sign bit for -0.0. */ + emit_vec_copysign (op_0, op_0, op_1, vec_fp_mode); +} + } // namespace riscv_vector diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index e0f6114..af8c31d 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -307,8 +307,7 @@ anticipatable_occurrence_p (const bb_info *bb, const vector_insn_info dem) if (dem.has_avl_reg ()) { /* rs1 (avl) are not modified in the basic block prior to the VSETVL. */ - rtx avl - = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ()) : dem.get_avl (); + rtx avl = dem.get_avl_or_vl_reg (); if (dem.dirty_p ()) { gcc_assert (!vsetvl_insn_p (insn->rtl ())); @@ -1514,7 +1513,6 @@ earliest_pred_can_be_fused_p (const bb_info *earliest_pred, const vector_insn_info &earliest_info, const vector_insn_info &expr, rtx *vlmax_vl) { - rtx vl = NULL_RTX; /* Backward VLMAX VL: bb 3: vsetivli zero, 1 ... -> vsetvli t1, zero @@ -1526,10 +1524,9 @@ earliest_pred_can_be_fused_p (const bb_info *earliest_pred, We should forward "t1". */ if (!earliest_info.has_avl_reg () && expr.has_avl_reg ()) { - rtx avl = expr.get_avl (); + rtx avl_or_vl_reg = expr.get_avl_or_vl_reg (); + gcc_assert (avl_or_vl_reg); const insn_info *last_insn = earliest_info.get_insn (); - if (vlmax_avl_p (avl)) - vl = get_vl (expr.get_insn ()->rtl ()); /* To fuse demand on earlest edge, we make sure AVL/VL didn't change from the consume insn to the predecessor of the edge. */ @@ -1538,17 +1535,15 @@ earliest_pred_can_be_fused_p (const bb_info *earliest_pred, && after_or_same_p (i, last_insn); i = i->prev_nondebug_insn ()) { - if (!vl && find_access (i->defs (), REGNO (avl))) + if (find_access (i->defs (), REGNO (avl_or_vl_reg))) return false; - if (vl && find_access (i->defs (), REGNO (vl))) - return false; - if (vl && find_access (i->uses (), REGNO (vl))) + if (find_access (i->uses (), REGNO (avl_or_vl_reg))) return false; } + if (vlmax_vl && vlmax_avl_p (expr.get_avl ())) + *vlmax_vl = avl_or_vl_reg; } - if (vlmax_vl) - *vlmax_vl = vl; return true; } diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 5c4b433..b6cd872 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -670,6 +670,53 @@ RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") (RVVM8DI "TARGET_FULL_V") (RVVM4DI "TARGET_FULL_V") (RVVM2DI "TARGET_FULL_V") (RVVM1DI "TARGET_FULL_V") + + (V1QI "TARGET_VECTOR_VLS") + (V2QI "TARGET_VECTOR_VLS") + (V4QI "TARGET_VECTOR_VLS") + (V8QI "TARGET_VECTOR_VLS") + (V16QI "TARGET_VECTOR_VLS") + (V32QI "TARGET_VECTOR_VLS") + (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64") + (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128") + (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256") + (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512") + (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024") + (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048") + (V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096") + (V1HI "TARGET_VECTOR_VLS") + (V2HI "TARGET_VECTOR_VLS") + (V4HI "TARGET_VECTOR_VLS") + (V8HI "TARGET_VECTOR_VLS") + (V16HI "TARGET_VECTOR_VLS") + (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64") + (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128") + (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256") + (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512") + (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024") + (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048") + (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096") + (V1SI "TARGET_VECTOR_VLS") + (V2SI "TARGET_VECTOR_VLS") + (V4SI "TARGET_VECTOR_VLS") + (V8SI "TARGET_VECTOR_VLS") + (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64") + (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128") + (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256") + (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512") + (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024") + (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048") + (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096") + (V1DI "TARGET_VECTOR_VLS && TARGET_FULL_V") + (V2DI "TARGET_VECTOR_VLS && TARGET_FULL_V") + (V4DI "TARGET_VECTOR_VLS && TARGET_FULL_V") + (V8DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 64") + (V16DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 128") + (V32DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 256") + (V64DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 512") + (V128DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 1024") + (V256DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 2048") + (V512DI "TARGET_VECTOR_VLS && TARGET_FULL_V && TARGET_MIN_VLEN >= 4096") ]) (define_mode_iterator VI_QH [ @@ -684,6 +731,43 @@ RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") + + (V1QI "TARGET_VECTOR_VLS") + (V2QI "TARGET_VECTOR_VLS") + (V4QI "TARGET_VECTOR_VLS") + (V8QI "TARGET_VECTOR_VLS") + (V16QI "TARGET_VECTOR_VLS") + (V32QI "TARGET_VECTOR_VLS") + (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64") + (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128") + (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256") + (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512") + (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024") + (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048") + (V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096") + (V1HI "TARGET_VECTOR_VLS") + (V2HI "TARGET_VECTOR_VLS") + (V4HI "TARGET_VECTOR_VLS") + (V8HI "TARGET_VECTOR_VLS") + (V16HI "TARGET_VECTOR_VLS") + (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64") + (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128") + (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256") + (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512") + (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024") + (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048") + (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096") + (V1SI "TARGET_VECTOR_VLS") + (V2SI "TARGET_VECTOR_VLS") + (V4SI "TARGET_VECTOR_VLS") + (V8SI "TARGET_VECTOR_VLS") + (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64") + (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128") + (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256") + (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512") + (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024") + (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048") + (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096") ]) (define_mode_iterator VI_QHS_NO_M8 [ @@ -692,6 +776,40 @@ RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") + + (V1QI "TARGET_VECTOR_VLS") + (V2QI "TARGET_VECTOR_VLS") + (V4QI "TARGET_VECTOR_VLS") + (V8QI "TARGET_VECTOR_VLS") + (V16QI "TARGET_VECTOR_VLS") + (V32QI "TARGET_VECTOR_VLS") + (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64") + (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128") + (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256") + (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512") + (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024") + (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048") + (V1HI "TARGET_VECTOR_VLS") + (V2HI "TARGET_VECTOR_VLS") + (V4HI "TARGET_VECTOR_VLS") + (V8HI "TARGET_VECTOR_VLS") + (V16HI "TARGET_VECTOR_VLS") + (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64") + (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128") + (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256") + (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512") + (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024") + (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048") + (V1SI "TARGET_VECTOR_VLS") + (V2SI "TARGET_VECTOR_VLS") + (V4SI "TARGET_VECTOR_VLS") + (V8SI "TARGET_VECTOR_VLS") + (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64") + (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128") + (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256") + (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512") + (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024") + (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048") ]) (define_mode_iterator VF_HS [ @@ -701,6 +819,30 @@ (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") + + (V1HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V2HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V4HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V8HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V16HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V32HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 64") + (V64HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 128") + (V128HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 256") + (V256HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 512") + (V512HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024") + (V1024HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048") + (V2048HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 4096") + (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64") + (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") + (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256") + (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512") + (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024") + (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048") + (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096") ]) (define_mode_iterator VF_HS_NO_M8 [ @@ -713,6 +855,28 @@ (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") + + (V1HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V2HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V4HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V8HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V16HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V32HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 64") + (V64HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 128") + (V128HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 256") + (V256HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 512") + (V512HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024") + (V1024HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048") + (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64") + (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") + (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256") + (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512") + (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024") + (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048") ]) (define_mode_iterator VF_HS_M8 [ @@ -1027,6 +1191,28 @@ (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") + + (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") + (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") + (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") + (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") + (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64") + (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") + (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256") + (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512") + (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024") + (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048") + (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096") + (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") + (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") + (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") + (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64") + (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128") + (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256") + (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512") + (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024") + (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048") + (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096") ]) (define_mode_iterator VWCONVERTI [ @@ -1514,6 +1700,66 @@ (RVVM8HF "RVVM1SF") (RVVM4HF "RVVM1SF") (RVVM2HF "RVVM1SF") (RVVM1HF "RVVM1SF") (RVVMF2HF "RVVM1SF") (RVVMF4HF "RVVM1SF") (RVVM8SF "RVVM1DF") (RVVM4SF "RVVM1DF") (RVVM2SF "RVVM1DF") (RVVM1SF "RVVM1DF") (RVVMF2SF "RVVM1DF") + + (V1QI "RVVM1HI") + (V2QI "RVVM1HI") + (V4QI "RVVM1HI") + (V8QI "RVVM1HI") + (V16QI "RVVM1HI") + (V32QI "RVVM1HI") + (V64QI "RVVM1HI") + (V128QI "RVVM1HI") + (V256QI "RVVM1HI") + (V512QI "RVVM1HI") + (V1024QI "RVVM1HI") + (V2048QI "RVVM1HI") + (V4096QI "RVVM1HI") + (V1HI "RVVM1SI") + (V2HI "RVVM1SI") + (V4HI "RVVM1SI") + (V8HI "RVVM1SI") + (V16HI "RVVM1SI") + (V32HI "RVVM1SI") + (V64HI "RVVM1SI") + (V128HI "RVVM1SI") + (V256HI "RVVM1SI") + (V512HI "RVVM1SI") + (V1024HI "RVVM1SI") + (V2048HI "RVVM1SI") + (V1SI "RVVM1DI") + (V2SI "RVVM1DI") + (V4SI "RVVM1DI") + (V8SI "RVVM1DI") + (V16SI "RVVM1DI") + (V32SI "RVVM1DI") + (V64SI "RVVM1DI") + (V128SI "RVVM1DI") + (V256SI "RVVM1DI") + (V512SI "RVVM1DI") + (V1024SI "RVVM1DI") + (V1HF "RVVM1SF") + (V2HF "RVVM1SF") + (V4HF "RVVM1SF") + (V8HF "RVVM1SF") + (V16HF "RVVM1SF") + (V32HF "RVVM1SF") + (V64HF "RVVM1SF") + (V128HF "RVVM1SF") + (V256HF "RVVM1SF") + (V512HF "RVVM1SF") + (V1024HF "RVVM1SF") + (V2048HF "RVVM1SF") + (V1SF "RVVM1DF") + (V2SF "RVVM1DF") + (V4SF "RVVM1DF") + (V8SF "RVVM1DF") + (V16SF "RVVM1DF") + (V32SF "RVVM1DF") + (V64SF "RVVM1DF") + (V128SF "RVVM1DF") + (V256SF "RVVM1DF") + (V512SF "RVVM1DF") + (V1024SF "RVVM1DF") ]) (define_int_iterator ANY_REDUC [ @@ -1982,6 +2228,61 @@ (RVVM4HF "SF") (RVVM2HF "SF") (RVVM1HF "SF") (RVVMF2HF "SF") (RVVMF4HF "SF") (RVVM4SF "DF") (RVVM2SF "DF") (RVVM1SF "DF") (RVVMF2SF "DF") + + (V1QI "HI") + (V2QI "HI") + (V4QI "HI") + (V8QI "HI") + (V16QI "HI") + (V32QI "HI") + (V64QI "HI") + (V128QI "HI") + (V256QI "HI") + (V512QI "HI") + (V1024QI "HI") + (V2048QI "HI") + (V1HI "SI") + (V2HI "SI") + (V4HI "SI") + (V8HI "SI") + (V16HI "SI") + (V32HI "SI") + (V64HI "SI") + (V128HI "SI") + (V256HI "SI") + (V512HI "SI") + (V1024HI "SI") + (V1SI "SI") + (V2SI "SI") + (V4SI "SI") + (V8SI "SI") + (V16SI "SI") + (V32SI "SI") + (V64SI "SI") + (V128SI "SI") + (V256SI "SI") + (V512SI "SI") + (V1HF "SF") + (V2HF "SF") + (V4HF "SF") + (V8HF "SF") + (V16HF "SF") + (V32HF "SF") + (V64HF "SF") + (V128HF "SF") + (V256HF "SF") + (V512HF "SF") + (V1024HF "SF") + (V1SF "DF") + (V2SF "DF") + (V4SF "DF") + (V8SF "DF") + (V16SF "DF") + (V32SF "DF") + (V64SF "DF") + (V128SF "DF") + (V256SF "DF") + (V512SF "DF") ]) (define_mode_attr vel [ @@ -2126,6 +2427,28 @@ (V1SI "HI") (V2SI "HI") (V4SI "HI") (V8SI "HI") (V16SI "HI") (V32SI "HI") (V64SI "HI") (V128SI "HI") (V256SI "HI") (V512SI "HI") (V1024SI "HI") (V1DI "SI") (V2DI "SI") (V4DI "SI") (V8DI "SI") (V16DI "SI") (V32DI "SI") (V64DI "SI") (V128DI "SI") (V256DI "SI") (V512DI "SI") + + (V1SF "HF") + (V2SF "HF") + (V4SF "HF") + (V8SF "HF") + (V16SF "HF") + (V32SF "HF") + (V64SF "HF") + (V128SF "HF") + (V256SF "HF") + (V512SF "HF") + (V1024SF "HF") + (V1DF "SF") + (V2DF "SF") + (V4DF "SF") + (V8DF "SF") + (V16DF "SF") + (V32DF "SF") + (V64DF "SF") + (V128DF "SF") + (V256DF "SF") + (V512DF "SF") ]) (define_mode_attr nf [ @@ -2352,6 +2675,61 @@ (RVVM4HF "RVVM8SF") (RVVM2HF "RVVM4SF") (RVVM1HF "RVVM2SF") (RVVMF2HF "RVVM1SF") (RVVMF4HF "RVVMF2SF") (RVVM4SF "RVVM8DF") (RVVM2SF "RVVM4DF") (RVVM1SF "RVVM2DF") (RVVMF2SF "RVVM1DF") + + (V1QI "V1HI") + (V2QI "V2HI") + (V4QI "V4HI") + (V8QI "V8HI") + (V16QI "V16HI") + (V32QI "V32HI") + (V64QI "V64HI") + (V128QI "V128HI") + (V256QI "V256HI") + (V512QI "V512HI") + (V1024QI "V1024HI") + (V2048QI "V2048HI") + (V1HI "V1SI") + (V2HI "V2SI") + (V4HI "V4SI") + (V8HI "V8SI") + (V16HI "V16SI") + (V32HI "V32SI") + (V64HI "V64SI") + (V128HI "V128SI") + (V256HI "V256SI") + (V512HI "V512SI") + (V1024HI "V1024SI") + (V1SI "V1SI") + (V2SI "V2SI") + (V4SI "V4SI") + (V8SI "V8SI") + (V16SI "V16SI") + (V32SI "V32SI") + (V64SI "V64SI") + (V128SI "V128SI") + (V256SI "V256SI") + (V512SI "V512SI") + (V1HF "V1SF") + (V2HF "V2SF") + (V4HF "V4SF") + (V8HF "V8SF") + (V16HF "V16SF") + (V32HF "V32SF") + (V64HF "V64SF") + (V128HF "V128SF") + (V256HF "V256SF") + (V512HF "V512SF") + (V1024HF "V1024SF") + (V1SF "V1DF") + (V2SF "V2DF") + (V4SF "V4DF") + (V8SF "V8DF") + (V16SF "V16DF") + (V32SF "V32DF") + (V64SF "V64DF") + (V128SF "V128DF") + (V256SF "V256DF") + (V512SF "V512DF") ]) (define_mode_attr V_DOUBLE_TRUNC [ diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 36f0256..d5300a3 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1371,7 +1371,7 @@ ;; This pattern only handles duplicates of non-constant inputs. ;; Constant vectors go through the movm pattern instead. ;; So "direct_broadcast_operand" can only be mem or reg, no CONSTANT. -(define_insn_and_split "@vec_duplicate<mode>" +(define_insn_and_split "vec_duplicate<mode>" [(set (match_operand:V_VLS 0 "register_operand") (vec_duplicate:V_VLS (match_operand:<VEL> 1 "direct_broadcast_operand")))] @@ -7438,7 +7438,7 @@ (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (unspec:<VCONVERT> - [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS) + [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS) (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vfcvt.x<v_su>.f.v\t%0,%3%p1" diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index caf9eee..cc9253b 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -25477,9 +25477,12 @@ rs6000_update_ipa_fn_target_info (unsigned int &info, const gimple *stmt) /* Assume inline asm can use any instruction features. */ if (gimple_code (stmt) == GIMPLE_ASM) { - /* Should set any bits we concerned, for now OPTION_MASK_HTM is - the only bit we care about. */ - info |= RS6000_FN_TARGET_INFO_HTM; + const char *asm_str = gimple_asm_string (as_a<const gasm *> (stmt)); + /* Ignore empty inline asm string. */ + if (strlen (asm_str) > 0) + /* Should set any bits we concerned, for now OPTION_MASK_HTM is + the only bit we care about. */ + info |= RS6000_FN_TARGET_INFO_HTM; return false; } else if (gimple_code (stmt) == GIMPLE_CALL) @@ -25510,49 +25513,44 @@ rs6000_can_inline_p (tree caller, tree callee) tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller); tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee); - /* If the callee has no option attributes, then it is ok to inline. */ + /* If the caller/callee has option attributes, then use them. + Otherwise, use the command line options. */ if (!callee_tree) - ret = true; + callee_tree = target_option_default_node; + if (!caller_tree) + caller_tree = target_option_default_node; - else - { - HOST_WIDE_INT caller_isa; - struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree); - HOST_WIDE_INT callee_isa = callee_opts->x_rs6000_isa_flags; - HOST_WIDE_INT explicit_isa = callee_opts->x_rs6000_isa_flags_explicit; + struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree); + struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree); - /* If the caller has option attributes, then use them. - Otherwise, use the command line options. */ - if (caller_tree) - caller_isa = TREE_TARGET_OPTION (caller_tree)->x_rs6000_isa_flags; - else - caller_isa = rs6000_isa_flags; + HOST_WIDE_INT callee_isa = callee_opts->x_rs6000_isa_flags; + HOST_WIDE_INT caller_isa = caller_opts->x_rs6000_isa_flags; + HOST_WIDE_INT explicit_isa = callee_opts->x_rs6000_isa_flags_explicit; - cgraph_node *callee_node = cgraph_node::get (callee); - if (ipa_fn_summaries && ipa_fn_summaries->get (callee_node) != NULL) + cgraph_node *callee_node = cgraph_node::get (callee); + if (ipa_fn_summaries && ipa_fn_summaries->get (callee_node) != NULL) + { + unsigned int info = ipa_fn_summaries->get (callee_node)->target_info; + if ((info & RS6000_FN_TARGET_INFO_HTM) == 0) { - unsigned int info = ipa_fn_summaries->get (callee_node)->target_info; - if ((info & RS6000_FN_TARGET_INFO_HTM) == 0) - { - callee_isa &= ~OPTION_MASK_HTM; - explicit_isa &= ~OPTION_MASK_HTM; - } + callee_isa &= ~OPTION_MASK_HTM; + explicit_isa &= ~OPTION_MASK_HTM; } + } - /* Ignore -mpower8-fusion and -mpower10-fusion options for inlining - purposes. */ - callee_isa &= ~(OPTION_MASK_P8_FUSION | OPTION_MASK_P10_FUSION); - explicit_isa &= ~(OPTION_MASK_P8_FUSION | OPTION_MASK_P10_FUSION); + /* Ignore -mpower8-fusion and -mpower10-fusion options for inlining + purposes. */ + callee_isa &= ~(OPTION_MASK_P8_FUSION | OPTION_MASK_P10_FUSION); + explicit_isa &= ~(OPTION_MASK_P8_FUSION | OPTION_MASK_P10_FUSION); - /* The callee's options must be a subset of the caller's options, i.e. - a vsx function may inline an altivec function, but a no-vsx function - must not inline a vsx function. However, for those options that the - callee has explicitly enabled or disabled, then we must enforce that - the callee's and caller's options match exactly; see PR70010. */ - if (((caller_isa & callee_isa) == callee_isa) - && (caller_isa & explicit_isa) == (callee_isa & explicit_isa)) - ret = true; - } + /* The callee's options must be a subset of the caller's options, i.e. + a vsx function may inline an altivec function, but a no-vsx function + must not inline a vsx function. However, for those options that the + callee has explicitly enabled or disabled, then we must enforce that + the callee's and caller's options match exactly; see PR70010. */ + if (((caller_isa & callee_isa) == callee_isa) + && (caller_isa & explicit_isa) == (callee_isa & explicit_isa)) + ret = true; if (TARGET_DEBUG_TARGET) fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n", diff --git a/gcc/configure b/gcc/configure index 307a3e0..c43bde8 100755 --- a/gcc/configure +++ b/gcc/configure @@ -30746,7 +30746,7 @@ $as_echo_n "checking dsymutil version \"$dsymutil_temp\"... " >&6; } dsymutil_kind=LLVM dsymutil_vers=`echo $dsymutil_temp | sed 's/.*LLVM\ version\ \([0-9\.]*\).*/\1/'` else - dsymutil_kind=UNKNOWN + dsymutil_kind=DET_UNKNOWN dsymutil_vers="0.0" fi dsymutil_major=`expr "$dsymutil_vers" : '\([0-9]*\)'` diff --git a/gcc/configure.ac b/gcc/configure.ac index 9b35c0f..fb8e32f 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -6363,7 +6363,7 @@ if test x"$dsymutil_flag" = x"yes"; then dsymutil_kind=LLVM dsymutil_vers=`echo $dsymutil_temp | sed 's/.*LLVM\ version\ \([[0-9\.]]*\).*/\1/'` else - dsymutil_kind=UNKNOWN + dsymutil_kind=DET_UNKNOWN dsymutil_vers="0.0" fi dsymutil_major=`expr "$dsymutil_vers" : '\([[0-9]]*\)'` diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 66adfcd..34f20b2 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,34 @@ +2023-09-22 Jason Merrill <jason@redhat.com> + + PR c++/111357 + * pt.cc (expand_integer_pack): Use IMPLICIT_CONV_EXPR. + +2023-09-22 Jason Merrill <jason@redhat.com> + + * constexpr.cc (free_constructor): Handle null ce->value. + +2023-09-22 Jason Merrill <jason@redhat.com> + + PR c++/111529 + * parser.cc (cp_parser_lambda_declarator_opt): Don't suggest + -std=c++14 for lambda templates. + * pt.cc (tsubst_expr): Move ANNOTATE_EXPR handling... + (tsubst_copy_and_build): ...here. + +2023-09-22 Patrick Palka <ppalka@redhat.com> + + PR c++/111493 + * decl2.cc (grok_array_decl): Guard diagnostic and backward + compatibility fallback code paths with tf_error. + +2023-09-22 Patrick Palka <ppalka@redhat.com> + + PR c++/111485 + * pt.cc (is_compatible_template_arg): New parameter 'args'. + Add the outer template arguments 'args' to 'new_args'. + (convert_template_argument): Pass 'args' to + is_compatible_template_arg. + 2023-09-20 Jakub Jelinek <jakub@redhat.com> * parser.cc (cp_parser_postfix_expression): Parse diff --git a/gcc/cp/constexpr.cc b/gcc/cp/constexpr.cc index a673a60..2a6601c 100644 --- a/gcc/cp/constexpr.cc +++ b/gcc/cp/constexpr.cc @@ -1753,7 +1753,7 @@ free_constructor (tree t) { constructor_elt *ce; for (HOST_WIDE_INT i = 0; vec_safe_iterate (elts, i, &ce); ++i) - if (TREE_CODE (ce->value) == CONSTRUCTOR) + if (ce->value && TREE_CODE (ce->value) == CONSTRUCTOR) vec_safe_push (ctors, ce->value); ggc_free (elts); } diff --git a/gcc/cp/decl2.cc b/gcc/cp/decl2.cc index 113b031..344e19e 100644 --- a/gcc/cp/decl2.cc +++ b/gcc/cp/decl2.cc @@ -459,7 +459,10 @@ grok_array_decl (location_t loc, tree array_expr, tree index_exp, { expr = build_op_subscript (loc, array_expr, index_exp_list, &overload, complain & tf_decltype); - if (expr == error_mark_node) + if (expr == error_mark_node + /* Don't do the backward compatibility fallback in a SFINAE + context. */ + && (complain & tf_error)) { tree idx = build_x_compound_expr_from_vec (*index_exp_list, NULL, tf_none); @@ -510,6 +513,11 @@ grok_array_decl (location_t loc, tree array_expr, tree index_exp, if (index_exp == NULL_TREE) { + if (!(complain & tf_error)) + /* Don't do the backward compatibility fallback in a SFINAE + context. */ + return error_mark_node; + if ((*index_exp_list)->is_empty ()) { error_at (loc, "built-in subscript operator without expression " @@ -561,8 +569,9 @@ grok_array_decl (location_t loc, tree array_expr, tree index_exp, swapped = true, array_expr = p2, index_exp = i1; else { - error_at (loc, "invalid types %<%T[%T]%> for array subscript", - type, TREE_TYPE (index_exp)); + if (complain & tf_error) + error_at (loc, "invalid types %<%T[%T]%> for array subscript", + type, TREE_TYPE (index_exp)); return error_mark_node; } diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc index 0e1cbbf..f3abae7 100644 --- a/gcc/cp/parser.cc +++ b/gcc/cp/parser.cc @@ -11695,11 +11695,8 @@ cp_parser_lambda_declarator_opt (cp_parser* parser, tree lambda_expr) an opening angle if present. */ if (cp_lexer_next_token_is (parser->lexer, CPP_LESS)) { - if (cxx_dialect < cxx14) - pedwarn (parser->lexer->next_token->location, OPT_Wc__14_extensions, - "lambda templates are only available with " - "%<-std=c++14%> or %<-std=gnu++14%>"); - else if (pedantic && cxx_dialect < cxx20) + if (cxx_dialect < cxx20 + && (pedantic || cxx_dialect < cxx14)) pedwarn (parser->lexer->next_token->location, OPT_Wc__20_extensions, "lambda templates are only available with " "%<-std=c++20%> or %<-std=gnu++20%>"); diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc index 5c300f4..73ac1cb 100644 --- a/gcc/cp/pt.cc +++ b/gcc/cp/pt.cc @@ -3769,6 +3769,13 @@ expand_integer_pack (tree call, tree args, tsubst_flags_t complain, { if (hi != ohi) { + /* Work around maybe_convert_nontype_argument not doing this for + dependent arguments. Don't use IMPLICIT_CONV_EXPR_NONTYPE_ARG + because that will make tsubst_copy_and_build ignore it. */ + tree type = tsubst (TREE_TYPE (ohi), args, complain, in_decl); + if (!TREE_TYPE (hi) || !same_type_p (type, TREE_TYPE (hi))) + hi = build1 (IMPLICIT_CONV_EXPR, type, hi); + call = copy_node (call); CALL_EXPR_ARG (call, 0) = hi; } @@ -3779,8 +3786,6 @@ expand_integer_pack (tree call, tree args, tsubst_flags_t complain, } else { - hi = perform_implicit_conversion_flags (integer_type_node, hi, complain, - LOOKUP_IMPLICIT); hi = instantiate_non_dependent_expr (hi, complain); hi = cxx_constant_value (hi, complain); int len = valid_constant_size_p (hi) ? tree_to_shwi (hi) : -1; @@ -8361,7 +8366,7 @@ canonicalize_expr_argument (tree arg, tsubst_flags_t complain) constrained than the parameter. */ static bool -is_compatible_template_arg (tree parm, tree arg) +is_compatible_template_arg (tree parm, tree arg, tree args) { tree parm_cons = get_constraints (parm); @@ -8382,6 +8387,7 @@ is_compatible_template_arg (tree parm, tree arg) { tree aparms = DECL_INNERMOST_TEMPLATE_PARMS (arg); new_args = template_parms_level_to_args (aparms); + new_args = add_to_template_args (args, new_args); ++processing_template_decl; parm_cons = tsubst_constraint_info (parm_cons, new_args, tf_none, NULL_TREE); @@ -8636,7 +8642,7 @@ convert_template_argument (tree parm, // Check that the constraints are compatible before allowing the // substitution. if (val != error_mark_node) - if (!is_compatible_template_arg (parm, arg)) + if (!is_compatible_template_arg (parm, arg, args)) { if (in_decl && (complain & tf_error)) { @@ -19912,13 +19918,6 @@ tsubst_expr (tree t, tree args, tsubst_flags_t complain, tree in_decl) templated_operator_saved_lookups (t), complain)); - case ANNOTATE_EXPR: - tmp = RECUR (TREE_OPERAND (t, 0)); - RETURN (build3_loc (EXPR_LOCATION (t), ANNOTATE_EXPR, - TREE_TYPE (tmp), tmp, - RECUR (TREE_OPERAND (t, 1)), - RECUR (TREE_OPERAND (t, 2)))); - case PREDICT_EXPR: RETURN (add_stmt (copy_node (t))); @@ -21867,6 +21866,13 @@ tsubst_copy_and_build (tree t, RETURN (op); } + case ANNOTATE_EXPR: + op1 = RECUR (TREE_OPERAND (t, 0)); + RETURN (build3_loc (EXPR_LOCATION (t), ANNOTATE_EXPR, + TREE_TYPE (op1), op1, + RECUR (TREE_OPERAND (t, 1)), + RECUR (TREE_OPERAND (t, 2)))); + default: /* Handle Objective-C++ constructs, if appropriate. */ { diff --git a/gcc/d/ChangeLog b/gcc/d/ChangeLog index 23b391c..403e27e 100644 --- a/gcc/d/ChangeLog +++ b/gcc/d/ChangeLog @@ -1,3 +1,22 @@ +2023-09-23 Iain Buclaw <ibuclaw@gdcproject.org> + + * dmd/MERGE: Merge upstream dmd 4574d1728d. + * dmd/VERSION: Bump version to v2.105.0. + * d-diagnostic.cc (verror): Remove. + (verrorSupplemental): Remove. + (vwarning): Remove. + (vwarningSupplemental): Remove. + (vdeprecation): Remove. + (vdeprecationSupplemental): Remove. + (vmessage): Remove. + (vtip): Remove. + (verrorReport): New function. + (verrorReportSupplemental): New function. + * d-lang.cc (d_parse_file): Update for new front-end interface. + * decl.cc (d_mangle_decl): Update for new front-end interface. + * intrinsics.cc (maybe_set_intrinsic): Update for new front-end + interface. + 2023-08-20 Iain Buclaw <ibuclaw@gdcproject.org> * dmd/MERGE: Merge upstream dmd 26f049fb26. diff --git a/gcc/d/d-diagnostic.cc b/gcc/d/d-diagnostic.cc index 7e5b17c..57f36f2 100644 --- a/gcc/d/d-diagnostic.cc +++ b/gcc/d/d-diagnostic.cc @@ -218,139 +218,116 @@ d_diagnostic_report_diagnostic (const Loc &loc, int opt, const char *format, va_end (argp); } -/* Print a hard error message with explicit location LOC with an optional - message prefix PREFIX1 and PREFIX2, increasing the global or gagged - error count. */ +/* Print a diagnostic message of type KIND with explicit location LOC with an + optional message prefix PREFIX1 and PREFIX2, increasing the global or gagged + error count depending on how KIND is treated. */ -void ATTRIBUTE_GCC_DIAG(2,0) -verror (const Loc &loc, const char *format, va_list ap, - const char *prefix1, const char *prefix2, const char *) +void D_ATTRIBUTE_FORMAT(2,0) ATTRIBUTE_GCC_DIAG(2,0) +verrorReport (const Loc& loc, const char *format, va_list ap, ErrorKind kind, + const char *prefix1 = NULL, const char *prefix2 = NULL) { - if (!global.gag || global.params.showGaggedErrors) - { - char *xformat; - - /* Build string and emit. */ - if (prefix2 != NULL) - xformat = xasprintf ("%s %s %s", escape_d_format (prefix1), - escape_d_format (prefix2), format); - else if (prefix1 != NULL) - xformat = xasprintf ("%s %s", escape_d_format (prefix1), format); - else - xformat = xasprintf ("%s", format); - - d_diagnostic_report_diagnostic (loc, 0, xformat, ap, - global.gag ? DK_ANACHRONISM : DK_ERROR, - false); - free (xformat); - } - - if (global.gag) - global.gaggedErrors++; + diagnostic_t diag_kind = DK_UNSPECIFIED; + int opt = 0; + bool verbatim = false; + char *xformat; - global.errors++; -} - -/* Print supplementary message about the last error with explicit location LOC. - This doesn't increase the global error count. */ + if (kind == ErrorKind::error) + { + global.errors++; + if (global.gag) + global.gaggedErrors++; -void ATTRIBUTE_GCC_DIAG(2,0) -verrorSupplemental (const Loc &loc, const char *format, va_list ap) -{ - if (global.gag && !global.params.showGaggedErrors) - return; + if (global.gag && !global.params.showGaggedErrors) + return; - d_diagnostic_report_diagnostic (loc, 0, format, ap, DK_NOTE, false); -} + diag_kind = global.gag ? DK_ANACHRONISM : DK_ERROR; + } + else if (kind == ErrorKind::warning) + { + if (global.gag || global.params.warnings == DIAGNOSTICoff) + { + if (global.gag) + global.gaggedWarnings++; -/* Print a warning message with explicit location LOC, increasing the - global warning count. */ + return; + } -void ATTRIBUTE_GCC_DIAG(2,0) -vwarning (const Loc &loc, const char *format, va_list ap) -{ - if (!global.gag && global.params.warnings != DIAGNOSTICoff) - { /* Warnings don't count if not treated as errors. */ if (global.params.warnings == DIAGNOSTICerror) global.warnings++; - d_diagnostic_report_diagnostic (loc, 0, format, ap, DK_WARNING, false); + diag_kind = DK_WARNING; } - else if (global.gag) - global.gaggedWarnings++; -} - -/* Print supplementary message about the last warning with explicit location - LOC. This doesn't increase the global warning count. */ - -void ATTRIBUTE_GCC_DIAG(2,0) -vwarningSupplemental (const Loc &loc, const char *format, va_list ap) -{ - if (global.params.warnings == DIAGNOSTICoff || global.gag) - return; - - d_diagnostic_report_diagnostic (loc, 0, format, ap, DK_NOTE, false); -} + else if (kind == ErrorKind::deprecation) + { + if (global.params.useDeprecated == DIAGNOSTICerror) + return verrorReport (loc, format, ap, ErrorKind::error, prefix1, + prefix2); + else if (global.gag || global.params.useDeprecated != DIAGNOSTICinform) + { + if (global.gag) + global.gaggedWarnings++; -/* Print a deprecation message with explicit location LOC with an optional - message prefix PREFIX1 and PREFIX2, increasing the global warning or - error count depending on how deprecations are treated. */ + return; + } -void ATTRIBUTE_GCC_DIAG(2,0) -vdeprecation (const Loc &loc, const char *format, va_list ap, - const char *prefix1, const char *prefix2) -{ - if (global.params.useDeprecated == DIAGNOSTICerror) - verror (loc, format, ap, prefix1, prefix2); - else if (global.params.useDeprecated == DIAGNOSTICinform && !global.gag) + opt = OPT_Wdeprecated; + diag_kind = DK_WARNING; + } + else if (kind == ErrorKind::message) { - char *xformat; - - /* Build string and emit. */ - if (prefix2 != NULL) - xformat = xasprintf ("%s %s %s", escape_d_format (prefix1), - escape_d_format (prefix2), format); - else if (prefix1 != NULL) - xformat = xasprintf ("%s %s", escape_d_format (prefix1), format); - else - xformat = xasprintf ("%s", format); - - d_diagnostic_report_diagnostic (loc, OPT_Wdeprecated, xformat, ap, - DK_WARNING, false); - free (xformat); + diag_kind = DK_NOTE; + verbatim = true; } - else if (global.gag) - global.gaggedWarnings++; -} - -/* Print supplementary message about the last deprecation with explicit - location LOC. This does not increase the global error count. */ + else if (kind == ErrorKind::tip) + { + diag_kind = DK_DEBUG; + verbatim = true; + } + else + gcc_unreachable (); + + /* Build string and emit. */ + if (prefix2 != NULL) + xformat = xasprintf ("%s %s %s", escape_d_format (prefix1), + escape_d_format (prefix2), format); + else if (prefix1 != NULL) + xformat = xasprintf ("%s %s", escape_d_format (prefix1), format); + else + xformat = xasprintf ("%s", format); -void ATTRIBUTE_GCC_DIAG(2,0) -vdeprecationSupplemental (const Loc &loc, const char *format, va_list ap) -{ - if (global.params.useDeprecated == DIAGNOSTICerror) - verrorSupplemental (loc, format, ap); - else if (global.params.useDeprecated == DIAGNOSTICinform && !global.gag) - d_diagnostic_report_diagnostic (loc, 0, format, ap, DK_NOTE, false); + d_diagnostic_report_diagnostic (loc, opt, xformat, ap, diag_kind, verbatim); + free (xformat); } -/* Print a verbose message with explicit location LOC. */ +/* Print supplementary message about the last diagnostic of type KIND, with + explicit location LOC. This doesn't increase the global error count. */ -void ATTRIBUTE_GCC_DIAG(2,0) -vmessage (const Loc &loc, const char *format, va_list ap) +void D_ATTRIBUTE_FORMAT(2,0) ATTRIBUTE_GCC_DIAG(2,0) +verrorReportSupplemental (const Loc& loc, const char* format, va_list ap, + ErrorKind kind) { - d_diagnostic_report_diagnostic (loc, 0, format, ap, DK_NOTE, true); -} - -/* Print a tip message with prefix and highlighing. */ + if (kind == ErrorKind::error) + { + if (global.gag && !global.params.showGaggedErrors) + return; + } + else if (kind == ErrorKind::warning) + { + if (global.params.warnings == DIAGNOSTICoff || global.gag) + return; + } + else if (kind == ErrorKind::deprecation) + { + if (global.params.useDeprecated == DIAGNOSTICerror) + return verrorReportSupplemental (loc, format, ap, ErrorKind::error); + else if (global.params.useDeprecated != DIAGNOSTICinform || global.gag) + return; + } + else + gcc_unreachable (); -void ATTRIBUTE_GCC_DIAG(1,0) -vtip (const char *format, va_list ap) -{ - if (!global.gag) - d_diagnostic_report_diagnostic (Loc (), 0, format, ap, DK_DEBUG, true); + d_diagnostic_report_diagnostic (loc, 0, format, ap, DK_NOTE, false); } /* Call this after printing out fatal error messages to clean up and diff --git a/gcc/d/d-lang.cc b/gcc/d/d-lang.cc index 10b9000..7dddcf5 100644 --- a/gcc/d/d-lang.cc +++ b/gcc/d/d-lang.cc @@ -1101,7 +1101,7 @@ d_parse_file (void) if (m->filetype == FileType::ddoc) { - gendocfile (m); + gendocfile (m, global.errorSink); /* Remove M from list of modules. */ modules.remove (i); i--; @@ -1256,7 +1256,7 @@ d_parse_file (void) /* Declare the name of the root module as the first global name in order to make the middle-end fully deterministic. */ OutBuffer buf; - mangleToBuffer (Module::rootModule, &buf); + mangleToBuffer (Module::rootModule, buf); first_global_object_name = buf.extractChars (); } @@ -1337,7 +1337,7 @@ d_parse_file (void) for (size_t i = 0; i < modules.length; i++) { Module *m = modules[i]; - gendocfile (m); + gendocfile (m, global.errorSink); } } diff --git a/gcc/d/decl.cc b/gcc/d/decl.cc index b866593..7e612e1 100644 --- a/gcc/d/decl.cc +++ b/gcc/d/decl.cc @@ -73,7 +73,7 @@ d_mangle_decl (Dsymbol *decl) else { OutBuffer buf; - mangleToBuffer (decl, &buf); + mangleToBuffer (decl, buf); return buf.extractChars (); } } diff --git a/gcc/d/dmd/MERGE b/gcc/d/dmd/MERGE index a02a8cb..dc26778 100644 --- a/gcc/d/dmd/MERGE +++ b/gcc/d/dmd/MERGE @@ -1,4 +1,4 @@ -26f049fb26e755096dea3f1474decea7c0fef187 +4574d1728d1f7e52ff40e6733b8c39889d128349 The first line of this file holds the git revision number of the last merge done from the dlang/dmd repository. diff --git a/gcc/d/dmd/README.md b/gcc/d/dmd/README.md index 4fd7831..d0c75a5b 100644 --- a/gcc/d/dmd/README.md +++ b/gcc/d/dmd/README.md @@ -31,7 +31,8 @@ Note that these groups have no strict meaning, the category assignments are a bi | File | Purpose | |-----------------------------------------------------------------------------|-----------------------------------------------------------------------| -| [mars.d](https://github.com/dlang/dmd/blob/master/compiler/src/dmd/mars.d) | The entry point. Contains `main`. | +| [main.d](https://github.com/dlang/dmd/blob/master/compiler/src/dmd/main.d) | The entry point. Contains `main`. | +| [mars.d](https://github.com/dlang/dmd/blob/master/compiler/src/dmd/mars.d) | Argument parsing, path manipulation. | | [cli.d](https://github.com/dlang/dmd/blob/master/compiler/src/dmd/cli.d) | Define the command line interface | | [dmdparams.d](https://github.com/dlang/dmd/blob/master/compiler/src/dmd/dmdparams.d) | DMD-specific parameters | | [globals.d](https://github.com/dlang/dmd/blob/master/compiler/src/dmd/globals.d) | Define a structure storing command line options | diff --git a/gcc/d/dmd/VERSION b/gcc/d/dmd/VERSION index 6faa8d8..8012337 100644 --- a/gcc/d/dmd/VERSION +++ b/gcc/d/dmd/VERSION @@ -1 +1 @@ -v2.105.0-beta.1 +v2.105.0 diff --git a/gcc/d/dmd/access.d b/gcc/d/dmd/access.d index 668129a..ab9b5d9 100644 --- a/gcc/d/dmd/access.d +++ b/gcc/d/dmd/access.d @@ -21,7 +21,6 @@ import dmd.dscope; import dmd.dstruct; import dmd.dsymbol; import dmd.expression; -import dmd.globals; import dmd.location; import dmd.tokens; diff --git a/gcc/d/dmd/aggregate.d b/gcc/d/dmd/aggregate.d index 42b926b..4ae6b6b 100644 --- a/gcc/d/dmd/aggregate.d +++ b/gcc/d/dmd/aggregate.d @@ -64,7 +64,7 @@ enum ClassKind : ubyte * Returns: * 0-terminated string for `c` */ -const(char)* toChars(ClassKind c) +const(char)* toChars(ClassKind c) @safe { final switch (c) { diff --git a/gcc/d/dmd/aliasthis.d b/gcc/d/dmd/aliasthis.d index ce38459..a8933f6 100644 --- a/gcc/d/dmd/aliasthis.d +++ b/gcc/d/dmd/aliasthis.d @@ -23,7 +23,6 @@ import dmd.globals; import dmd.identifier; import dmd.location; import dmd.mtype; -import dmd.opover; import dmd.tokens; import dmd.visitor; @@ -38,7 +37,7 @@ extern (C++) final class AliasThis : Dsymbol /// Whether this `alias this` is deprecated or not bool isDeprecated_; - extern (D) this(const ref Loc loc, Identifier ident) + extern (D) this(const ref Loc loc, Identifier ident) @safe { super(loc, null); // it's anonymous (no identifier) this.ident = ident; diff --git a/gcc/d/dmd/arrayop.d b/gcc/d/dmd/arrayop.d index 908855e..d843073 100644 --- a/gcc/d/dmd/arrayop.d +++ b/gcc/d/dmd/arrayop.d @@ -22,14 +22,12 @@ import dmd.dsymbol; import dmd.expression; import dmd.expressionsem; import dmd.func; -import dmd.globals; import dmd.hdrgen; import dmd.id; import dmd.identifier; import dmd.location; import dmd.mtype; import dmd.common.outbuffer; -import dmd.statement; import dmd.tokens; import dmd.visitor; @@ -194,7 +192,7 @@ private Expressions* buildArrayOp(Scope* sc, Expression e, Objects* tiargs) Expressions* args; public: - extern (D) this(Scope* sc, Objects* tiargs) scope + extern (D) this(Scope* sc, Objects* tiargs) scope @safe { this.sc = sc; this.tiargs = tiargs; @@ -276,7 +274,7 @@ bool isArrayOpImplicitCast(TypeDArray tfrom, TypeDArray tto) /*********************************************** * Test if expression is a unary array op. */ -bool isUnaArrayOp(EXP op) +bool isUnaArrayOp(EXP op) @safe { switch (op) { @@ -292,7 +290,7 @@ bool isUnaArrayOp(EXP op) /*********************************************** * Test if expression is a binary array op. */ -bool isBinArrayOp(EXP op) +bool isBinArrayOp(EXP op) @safe { switch (op) { @@ -315,7 +313,7 @@ bool isBinArrayOp(EXP op) /*********************************************** * Test if expression is a binary assignment array op. */ -bool isBinAssignArrayOp(EXP op) +bool isBinAssignArrayOp(EXP op) @safe { switch (op) { diff --git a/gcc/d/dmd/attrib.d b/gcc/d/dmd/attrib.d index ff4ebe8..baabe93 100644 --- a/gcc/d/dmd/attrib.d +++ b/gcc/d/dmd/attrib.d @@ -45,7 +45,6 @@ import dmd.mtype; import dmd.objc; // for objc.addSymbols import dmd.common.outbuffer; import dmd.root.array; // for each -import dmd.tokens; import dmd.visitor; /*********************************************************** @@ -57,18 +56,18 @@ extern (C++) abstract class AttribDeclaration : Dsymbol { Dsymbols* decl; /// Dsymbol's affected by this AttribDeclaration - extern (D) this(Dsymbols* decl) + extern (D) this(Dsymbols* decl) @safe { this.decl = decl; } - extern (D) this(const ref Loc loc, Dsymbols* decl) + extern (D) this(const ref Loc loc, Dsymbols* decl) @safe { super(loc, null); this.decl = decl; } - extern (D) this(const ref Loc loc, Identifier ident, Dsymbols* decl) + extern (D) this(const ref Loc loc, Identifier ident, Dsymbols* decl) @safe { super(loc, ident); this.decl = decl; @@ -228,13 +227,13 @@ extern (C++) class StorageClassDeclaration : AttribDeclaration { StorageClass stc; - extern (D) this(StorageClass stc, Dsymbols* decl) + extern (D) this(StorageClass stc, Dsymbols* decl) @safe { super(decl); this.stc = stc; } - extern (D) this(const ref Loc loc, StorageClass stc, Dsymbols* decl) + extern (D) this(const ref Loc loc, StorageClass stc, Dsymbols* decl) @safe { super(loc, decl); this.stc = stc; @@ -347,7 +346,7 @@ extern (C++) final class DeprecatedDeclaration : StorageClassDeclaration Expression msg; /// deprecation message const(char)* msgstr; /// cached string representation of msg - extern (D) this(Expression msg, Dsymbols* decl) + extern (D) this(Expression msg, Dsymbols* decl) @safe { super(STC.deprecated_, decl); this.msg = msg; @@ -402,14 +401,14 @@ extern (C++) final class LinkDeclaration : AttribDeclaration { LINK linkage; /// either explicitly set or `default_` - extern (D) this(const ref Loc loc, LINK linkage, Dsymbols* decl) + extern (D) this(const ref Loc loc, LINK linkage, Dsymbols* decl) @safe { super(loc, null, decl); //printf("LinkDeclaration(linkage = %d, decl = %p)\n", linkage, decl); this.linkage = linkage; } - static LinkDeclaration create(const ref Loc loc, LINK p, Dsymbols* decl) + static LinkDeclaration create(const ref Loc loc, LINK p, Dsymbols* decl) @safe { return new LinkDeclaration(loc, p, decl); } @@ -454,7 +453,7 @@ extern (C++) final class CPPMangleDeclaration : AttribDeclaration { CPPMANGLE cppmangle; - extern (D) this(const ref Loc loc, CPPMANGLE cppmangle, Dsymbols* decl) + extern (D) this(const ref Loc loc, CPPMANGLE cppmangle, Dsymbols* decl) @safe { super(loc, null, decl); //printf("CPPMangleDeclaration(cppmangle = %d, decl = %p)\n", cppmangle, decl); @@ -524,19 +523,19 @@ extern (C++) final class CPPNamespaceDeclaration : AttribDeclaration /// CTFE-able expression, resolving to `TupleExp` or `StringExp` Expression exp; - extern (D) this(const ref Loc loc, Identifier ident, Dsymbols* decl) + extern (D) this(const ref Loc loc, Identifier ident, Dsymbols* decl) @safe { super(loc, ident, decl); } - extern (D) this(const ref Loc loc, Expression exp, Dsymbols* decl) + extern (D) this(const ref Loc loc, Expression exp, Dsymbols* decl) @safe { super(loc, null, decl); this.exp = exp; } extern (D) this(const ref Loc loc, Identifier ident, Expression exp, Dsymbols* decl, - CPPNamespaceDeclaration parent) + CPPNamespaceDeclaration parent) @safe { super(loc, ident, decl); this.exp = exp; @@ -597,7 +596,7 @@ extern (C++) final class VisibilityDeclaration : AttribDeclaration * visibility = visibility attribute data * decl = declarations which are affected by this visibility attribute */ - extern (D) this(const ref Loc loc, Visibility visibility, Dsymbols* decl) + extern (D) this(const ref Loc loc, Visibility visibility, Dsymbols* decl) @safe { super(loc, null, decl); this.visibility = visibility; @@ -720,13 +719,13 @@ extern (C++) final class AlignDeclaration : AttribDeclaration } } - extern (D) this(const ref Loc loc, Expressions* exps, Dsymbols* decl) + extern (D) this(const ref Loc loc, Expressions* exps, Dsymbols* decl) @safe { super(loc, null, decl); this.exps = exps; } - extern (D) this(const ref Loc loc, structalign_t salign, Dsymbols* decl) + extern (D) this(const ref Loc loc, structalign_t salign, Dsymbols* decl) @safe { super(loc, null, decl); this.salign = salign; @@ -762,7 +761,7 @@ extern (C++) final class AnonDeclaration : AttribDeclaration uint anonstructsize; /// size of anonymous struct uint anonalignsize; /// size of anonymous struct for alignment purposes - extern (D) this(const ref Loc loc, bool isunion, Dsymbols* decl) + extern (D) this(const ref Loc loc, bool isunion, Dsymbols* decl) @safe { super(loc, null, decl); this.isunion = isunion; @@ -882,7 +881,7 @@ extern (C++) final class PragmaDeclaration : AttribDeclaration { Expressions* args; /// parameters of this pragma - extern (D) this(const ref Loc loc, Identifier ident, Expressions* args, Dsymbols* decl) + extern (D) this(const ref Loc loc, Identifier ident, Expressions* args, Dsymbols* decl) @safe { super(loc, ident, decl); this.args = args; @@ -928,7 +927,7 @@ extern (C++) class ConditionalDeclaration : AttribDeclaration Condition condition; /// condition deciding whether decl or elsedecl applies Dsymbols* elsedecl; /// array of Dsymbol's for else block - extern (D) this(const ref Loc loc, Condition condition, Dsymbols* decl, Dsymbols* elsedecl) + extern (D) this(const ref Loc loc, Condition condition, Dsymbols* decl, Dsymbols* elsedecl) @safe { super(loc, null, decl); //printf("ConditionalDeclaration::ConditionalDeclaration()\n"); @@ -1006,7 +1005,7 @@ extern (C++) final class StaticIfDeclaration : ConditionalDeclaration private bool addisdone = false; /// true if members have been added to scope private bool onStack = false; /// true if a call to `include` is currently active - extern (D) this(const ref Loc loc, Condition condition, Dsymbols* decl, Dsymbols* elsedecl) + extern (D) this(const ref Loc loc, Condition condition, Dsymbols* decl, Dsymbols* elsedecl) @safe { super(loc, condition, decl, elsedecl); //printf("StaticIfDeclaration::StaticIfDeclaration()\n"); @@ -1120,7 +1119,7 @@ extern (C++) final class StaticForeachDeclaration : AttribDeclaration bool cached = false; Dsymbols* cache = null; - extern (D) this(StaticForeach sfe, Dsymbols* decl) + extern (D) this(StaticForeach sfe, Dsymbols* decl) @safe { super(sfe.loc, null, decl); this.sfe = sfe; @@ -1251,7 +1250,7 @@ extern(C++) final class ForwardingAttribDeclaration : AttribDeclaration { ForwardingScopeDsymbol sym = null; - this(Dsymbols* decl) + this(Dsymbols* decl) @safe { super(decl); sym = new ForwardingScopeDsymbol(); @@ -1299,7 +1298,7 @@ extern (C++) final class MixinDeclaration : AttribDeclaration ScopeDsymbol scopesym; bool compiled; - extern (D) this(const ref Loc loc, Expressions* exps) + extern (D) this(const ref Loc loc, Expressions* exps) @safe { super(loc, null, null); //printf("MixinDeclaration(loc = %d)\n", loc.linnum); @@ -1348,7 +1347,7 @@ extern (C++) final class UserAttributeDeclaration : AttribDeclaration { Expressions* atts; - extern (D) this(Expressions* atts, Dsymbols* decl) + extern (D) this(Expressions* atts, Dsymbols* decl) @safe { super(decl); this.atts = atts; diff --git a/gcc/d/dmd/blockexit.d b/gcc/d/dmd/blockexit.d index db738b4..bdc81f2 100644 --- a/gcc/d/dmd/blockexit.d +++ b/gcc/d/dmd/blockexit.d @@ -27,7 +27,6 @@ import dmd.location; import dmd.mtype; import dmd.statement; import dmd.tokens; -import dmd.visitor; /** * BE stands for BlockExit. diff --git a/gcc/d/dmd/canthrow.d b/gcc/d/dmd/canthrow.d index 89d5519..ba13eb0 100644 --- a/gcc/d/dmd/canthrow.d +++ b/gcc/d/dmd/canthrow.d @@ -26,7 +26,6 @@ import dmd.globals; import dmd.init; import dmd.mtype; import dmd.postordervisitor; -import dmd.root.rootobject; import dmd.tokens; import dmd.visitor; @@ -63,7 +62,7 @@ extern (C++) /* CT */ BE canThrow(Expression e, FuncDeclaration func, bool mustN CT result; public: - extern (D) this(FuncDeclaration func, bool mustNotThrow) scope + extern (D) this(FuncDeclaration func, bool mustNotThrow) scope @safe { this.func = func; this.mustNotThrow = mustNotThrow; diff --git a/gcc/d/dmd/common/file.d b/gcc/d/dmd/common/file.d index ae13c41..076f357 100644 --- a/gcc/d/dmd/common/file.d +++ b/gcc/d/dmd/common/file.d @@ -27,6 +27,14 @@ import dmd.common.string; nothrow: +version (Windows) +{ + import core.sys.windows.winnls : CP_ACP; + + // assume filenames encoded in system default Windows ANSI code page + enum CodePage = CP_ACP; +} + /** Encapsulated management of a memory-mapped file. diff --git a/gcc/d/dmd/common/outbuffer.d b/gcc/d/dmd/common/outbuffer.d index 007d301..b8ad785 100644 --- a/gcc/d/dmd/common/outbuffer.d +++ b/gcc/d/dmd/common/outbuffer.d @@ -61,7 +61,7 @@ struct OutBuffer /** Construct given size. */ - this(size_t initialSize) nothrow + this(size_t initialSize) nothrow @safe { reserve(initialSize); } @@ -527,7 +527,7 @@ struct OutBuffer * Returns: * slice of the allocated space to be filled in */ - extern (D) char[] allocate(size_t nbytes) pure nothrow + extern (D) char[] allocate(size_t nbytes) pure nothrow @safe { reserve(nbytes); offset += nbytes; @@ -711,8 +711,14 @@ struct OutBuffer return cast(char*)data.ptr; } + // Peek at slice of data without taking ownership + extern (D) ubyte[] peekSlice() pure nothrow + { + return data[0 .. offset]; + } + // Append terminating null if necessary and take ownership of data - extern (C++) char* extractChars() pure nothrow + extern (C++) char* extractChars() pure nothrow @safe { if (!offset || data[offset - 1] != '\0') writeByte(0); diff --git a/gcc/d/dmd/common/string.d b/gcc/d/dmd/common/string.d index 6de921e..9453a34 100644 --- a/gcc/d/dmd/common/string.d +++ b/gcc/d/dmd/common/string.d @@ -135,9 +135,8 @@ but is guaranteed to follow it. */ version(Windows) wchar[] toWStringz(const(char)[] narrow, ref SmallBuffer!wchar buffer) nothrow { - import core.sys.windows.winnls : CP_ACP, MultiByteToWideChar; - // assume filenames encoded in system default Windows ANSI code page - enum CodePage = CP_ACP; + import core.sys.windows.winnls : MultiByteToWideChar; + import dmd.common.file : CodePage; if (narrow is null) return null; diff --git a/gcc/d/dmd/cond.d b/gcc/d/dmd/cond.d index 467f9f1..360acf5 100644 --- a/gcc/d/dmd/cond.d +++ b/gcc/d/dmd/cond.d @@ -62,7 +62,7 @@ extern (C++) abstract class Condition : ASTNode return DYNCAST.condition; } - extern (D) this(const ref Loc loc) + extern (D) this(const ref Loc loc) @safe { this.loc = loc; } @@ -124,7 +124,7 @@ extern (C++) final class StaticForeach : RootObject */ bool needExpansion = false; - extern (D) this(const ref Loc loc, ForeachStatement aggrfe, ForeachRangeStatement rangefe) + extern (D) this(const ref Loc loc, ForeachStatement aggrfe, ForeachRangeStatement rangefe) @safe { assert(!!aggrfe ^ !!rangefe); @@ -279,7 +279,7 @@ extern (C++) final class StaticForeach : RootObject * An AST for the expression `Tuple(e)`. */ - private extern(D) Expression createTuple(const ref Loc loc, TypeStruct type, Expressions* e) + private extern(D) Expression createTuple(const ref Loc loc, TypeStruct type, Expressions* e) @safe { // TODO: move to druntime? return new CallExp(loc, new TypeExp(loc, type), e); } @@ -496,7 +496,7 @@ extern (C++) class DVCondition : Condition Identifier ident; Module mod; - extern (D) this(const ref Loc loc, Module mod, uint level, Identifier ident) + extern (D) this(const ref Loc loc, Module mod, uint level, Identifier ident) @safe { super(loc); this.mod = mod; @@ -563,7 +563,7 @@ extern (C++) final class DebugCondition : DVCondition * If `null`, this conditiion will use an integer level. * loc = Location in the source file */ - extern (D) this(const ref Loc loc, Module mod, uint level, Identifier ident) + extern (D) this(const ref Loc loc, Module mod, uint level, Identifier ident) @safe { super(loc, mod, level, ident); } @@ -637,7 +637,7 @@ extern (C++) final class VersionCondition : DVCondition * Returns: * `true` if it is reserved, `false` otherwise */ - extern(D) private static bool isReserved(const(char)[] ident) + extern(D) private static bool isReserved(const(char)[] ident) @safe { // This list doesn't include "D_*" versions, see the last return switch (ident) @@ -840,7 +840,7 @@ extern (C++) final class VersionCondition : DVCondition * If `null`, this conditiion will use an integer level. * loc = Location in the source file */ - extern (D) this(const ref Loc loc, Module mod, uint level, Identifier ident) + extern (D) this(const ref Loc loc, Module mod, uint level, Identifier ident) @safe { super(loc, mod, level, ident); } @@ -902,7 +902,7 @@ extern (C++) final class StaticIfCondition : Condition { Expression exp; - extern (D) this(const ref Loc loc, Expression exp) + extern (D) this(const ref Loc loc, Expression exp) @safe { super(loc); this.exp = exp; diff --git a/gcc/d/dmd/constfold.d b/gcc/d/dmd/constfold.d index 415606b..e5526a1 100644 --- a/gcc/d/dmd/constfold.d +++ b/gcc/d/dmd/constfold.d @@ -52,7 +52,7 @@ private Expression expType(Type type, Expression e) * Returns: * true if e is a constant */ -int isConst(Expression e) +int isConst(Expression e) @safe { //printf("Expression::isConst(): %s\n", e.toChars()); switch (e.op) @@ -1286,7 +1286,7 @@ UnionExp Slice(Type type, Expression e1, Expression lwr, Expression upr) /* Check whether slice `[newlwr .. newupr]` is in the range `[lwr .. upr]` */ -bool sliceBoundsCheck(uinteger_t lwr, uinteger_t upr, uinteger_t newlwr, uinteger_t newupr) pure +bool sliceBoundsCheck(uinteger_t lwr, uinteger_t upr, uinteger_t newlwr, uinteger_t newupr) pure @safe { assert(lwr <= upr); return !(newlwr <= newupr && diff --git a/gcc/d/dmd/cppmangle.d b/gcc/d/dmd/cppmangle.d index ee1340d..5d74ec4 100644 --- a/gcc/d/dmd/cppmangle.d +++ b/gcc/d/dmd/cppmangle.d @@ -139,7 +139,7 @@ private struct Context * Returns: * The previous state of this `Context` object */ - private Context push(lazy RootObject next) + private Context push(lazy RootObject next) @safe { auto r = this.res; if (r !is null) @@ -150,7 +150,7 @@ private struct Context /** * Reset the context to a previous one, making any adjustment necessary */ - private void pop(ref Context prev) + private void pop(ref Context prev) @safe { this.res = prev.res; } @@ -236,7 +236,7 @@ private final class CppMangleVisitor : Visitor * See-Also: * https://itanium-cxx-abi.github.io/cxx-abi/abi.html#mangle.seq-id */ - private void writeSequenceFromIndex(size_t idx) + private void writeSequenceFromIndex(size_t idx) @safe { if (idx) { @@ -1597,7 +1597,7 @@ private final class CppMangleVisitor : Visitor * or `params.length` if there wasn't any match. */ private static size_t templateParamIndex( - const ref Identifier ident, TemplateParameters* params) + const ref Identifier ident, TemplateParameters* params) @safe { foreach (idx, param; *params) if (param.ident == ident) @@ -2131,7 +2131,7 @@ private void visitObject(V : Visitor)(RootObject o, V this_) } /// Helper function to safely get a type out of a `RootObject` -private Type asType(RootObject o) +private Type asType(RootObject o) @safe { if (Type ta = isType(o)) return ta; @@ -2143,7 +2143,7 @@ private Type asType(RootObject o) } /// Helper function to safely get a `FuncDeclaration` out of a `RootObject` -private FuncDeclaration asFuncDecl(RootObject o) +private FuncDeclaration asFuncDecl(RootObject o) @safe { Dsymbol d = isDsymbol(o); assert(d !is null); @@ -2177,7 +2177,7 @@ private extern(C++) final class ComponentVisitor : Visitor /// Set to the result of the comparison private bool result; - public this(RootObject base) + public this(RootObject base) @safe { switch (base.dyncast()) { @@ -2353,7 +2353,7 @@ private bool isNamespaceEqual (CPPNamespaceDeclaration a, Nspace b, size_t idx = /// Returns: /// Whether two `CPPNamespaceDeclaration` are equals -private bool isNamespaceEqual (CPPNamespaceDeclaration a, CPPNamespaceDeclaration b) +private bool isNamespaceEqual (CPPNamespaceDeclaration a, CPPNamespaceDeclaration b) @safe { if (a is null || b is null) return false; @@ -2558,7 +2558,7 @@ void leftOver(TypeFunction tf, const(Array!StringExp)* previous, Array!StringExp private const(Array!StringExp)* ignore; /// - public this(const(Array!StringExp)* previous, Array!StringExp* toWrite) + public this(const(Array!StringExp)* previous, Array!StringExp* toWrite) @safe { this.ignore = previous; this.toWrite = toWrite; diff --git a/gcc/d/dmd/ctfeexpr.d b/gcc/d/dmd/ctfeexpr.d index 289ebeb..d355538 100644 --- a/gcc/d/dmd/ctfeexpr.d +++ b/gcc/d/dmd/ctfeexpr.d @@ -45,7 +45,7 @@ extern (C++) final class ClassReferenceExp : Expression { StructLiteralExp value; - extern (D) this(const ref Loc loc, StructLiteralExp lit, Type type) + extern (D) this(const ref Loc loc, StructLiteralExp lit, Type type) @safe { super(loc, EXP.classReference); assert(lit && lit.sd && lit.sd.isClassDeclaration()); @@ -112,7 +112,7 @@ extern (C++) final class ClassReferenceExp : Expression * Returns: * index of the field, or -1 if not found */ -int findFieldIndexByName(const StructDeclaration sd, const VarDeclaration v) pure +int findFieldIndexByName(const StructDeclaration sd, const VarDeclaration v) pure @safe { foreach (i, field; sd.fields) { @@ -130,7 +130,7 @@ extern (C++) final class ThrownExceptionExp : Expression { ClassReferenceExp thrown; // the thing being tossed - extern (D) this(const ref Loc loc, ClassReferenceExp victim) + extern (D) this(const ref Loc loc, ClassReferenceExp victim) @safe { super(loc, EXP.thrownException); this.thrown = victim; @@ -205,19 +205,19 @@ extern (C++) final class CTFEExp : Expression */ extern (D) __gshared CTFEExp showcontext; - extern (D) static bool isCantExp(const Expression e) + extern (D) static bool isCantExp(const Expression e) @safe { return e && e.op == EXP.cantExpression; } - extern (D) static bool isGotoExp(const Expression e) + extern (D) static bool isGotoExp(const Expression e) @safe { return e && e.op == EXP.goto_; } } // True if 'e' is CTFEExp::cantexp, or an exception -bool exceptionOrCantInterpret(const Expression e) +bool exceptionOrCantInterpret(const Expression e) @safe { return e && (e.op == EXP.cantExpression || e.op == EXP.thrownException || e.op == EXP.showCtfeContext); } @@ -1068,25 +1068,25 @@ private bool numCmp(N)(EXP op, N n1, N n2) } /// Returns cmp OP 0; where OP is ==, !=, <, >=, etc. Result is 0 or 1 -bool specificCmp(EXP op, int rawCmp) +bool specificCmp(EXP op, int rawCmp) @safe { return numCmp!int(op, rawCmp, 0); } /// Returns e1 OP e2; where OP is ==, !=, <, >=, etc. Result is 0 or 1 -bool intUnsignedCmp(EXP op, dinteger_t n1, dinteger_t n2) +bool intUnsignedCmp(EXP op, dinteger_t n1, dinteger_t n2) @safe { return numCmp!dinteger_t(op, n1, n2); } /// Returns e1 OP e2; where OP is ==, !=, <, >=, etc. Result is 0 or 1 -bool intSignedCmp(EXP op, sinteger_t n1, sinteger_t n2) +bool intSignedCmp(EXP op, sinteger_t n1, sinteger_t n2) @safe { return numCmp!sinteger_t(op, n1, n2); } /// Returns e1 OP e2; where OP is ==, !=, <, >=, etc. Result is 0 or 1 -bool realCmp(EXP op, real_t r1, real_t r2) +bool realCmp(EXP op, real_t r1, real_t r2) @safe { // Don't rely on compiler, handle NAN arguments separately if (CTFloat.isNaN(r1) || CTFloat.isNaN(r2)) // if unordered @@ -1176,7 +1176,7 @@ private int ctfeCmpArrays(const ref Loc loc, Expression e1, Expression e2, uinte /* Given a delegate expression e, return .funcptr. * If e is NullExp, return NULL. */ -private FuncDeclaration funcptrOf(Expression e) +private FuncDeclaration funcptrOf(Expression e) @safe { assert(e.type.ty == Tdelegate); if (auto de = e.isDelegateExp()) @@ -1187,7 +1187,7 @@ private FuncDeclaration funcptrOf(Expression e) return null; } -private bool isArray(const Expression e) +private bool isArray(const Expression e) @safe { return e.op == EXP.arrayLiteral || e.op == EXP.string_ || e.op == EXP.slice || e.op == EXP.null_; } diff --git a/gcc/d/dmd/ctorflow.d b/gcc/d/dmd/ctorflow.d index a3953af..128c698 100644 --- a/gcc/d/dmd/ctorflow.d +++ b/gcc/d/dmd/ctorflow.d @@ -71,7 +71,7 @@ struct CtorFlow * Params: * csx = bits to set */ - void orCSX(CSX csx) nothrow pure + void orCSX(CSX csx) nothrow pure @safe { callSuper |= csx; foreach (ref u; fieldinit) @@ -83,7 +83,7 @@ struct CtorFlow * Params: * ctorflow = bits to OR in */ - void OR(const ref CtorFlow ctorflow) pure nothrow + void OR(const ref CtorFlow ctorflow) pure nothrow @safe { callSuper |= ctorflow.callSuper; if (fieldinit.length && ctorflow.fieldinit.length) @@ -109,7 +109,7 @@ struct CtorFlow * Returns: * false means one of the paths skips construction */ -bool mergeCallSuper(ref CSX a, const CSX b) pure nothrow +bool mergeCallSuper(ref CSX a, const CSX b) pure nothrow @safe { // This does a primitive flow analysis to support the restrictions // regarding when and how constructors can appear. @@ -172,7 +172,7 @@ bool mergeCallSuper(ref CSX a, const CSX b) pure nothrow * Returns: * false means either `a` or `b` skips initialization */ -bool mergeFieldInit(ref CSX a, const CSX b) pure nothrow +bool mergeFieldInit(ref CSX a, const CSX b) pure nothrow @safe { if (b == a) return true; diff --git a/gcc/d/dmd/dclass.d b/gcc/d/dmd/dclass.d index 1b8e8ef..20cb82e 100644 --- a/gcc/d/dmd/dclass.d +++ b/gcc/d/dmd/dclass.d @@ -1130,7 +1130,7 @@ extern (C++) final class InterfaceDeclaration : ClassDeclaration * Returns: * true if the `bc` implements `id`, false otherwise **/ -private bool baseClassImplementsInterface(InterfaceDeclaration id, BaseClass* bc, int* poffset) pure nothrow @nogc +private bool baseClassImplementsInterface(InterfaceDeclaration id, BaseClass* bc, int* poffset) pure nothrow @nogc @safe { //printf("%s.InterfaceDeclaration.isBaseOf(bc = '%s')\n", id.toChars(), bc.sym.toChars()); for (size_t j = 0; j < bc.baseInterfaces.length; j++) diff --git a/gcc/d/dmd/declaration.d b/gcc/d/dmd/declaration.d index 5559b93..8a91a80 100644 --- a/gcc/d/dmd/declaration.d +++ b/gcc/d/dmd/declaration.d @@ -188,6 +188,15 @@ bool modifyFieldVar(Loc loc, Scope* sc, VarDeclaration var, Expression e1) MODtoChars(var.type.mod), var.kind(), var.toChars()); errorSupplemental(loc, "Use `shared static this` instead."); } + else if (fd.isStaticCtorDeclaration() && !fd.isSharedStaticCtorDeclaration() && + var.type.isConst()) + { + // @@@DEPRECATED_2.116@@@ + // Turn this into an error, merging with the branch above + .deprecation(loc, "%s %s `%s` initialization is not allowed in `static this`", + MODtoChars(var.type.mod), var.kind(), var.toChars()); + deprecationSupplemental(loc, "Use `shared static this` instead."); + } return result; } else @@ -242,13 +251,13 @@ extern (C++) abstract class Declaration : Dsymbol // overridden symbol with pragma(mangle, "...") const(char)[] mangleOverride; - final extern (D) this(Identifier ident) + final extern (D) this(Identifier ident) @safe { super(ident); visibility = Visibility(Visibility.Kind.undefined); } - final extern (D) this(const ref Loc loc, Identifier ident) + final extern (D) this(const ref Loc loc, Identifier ident) @safe { super(loc, ident); visibility = Visibility(Visibility.Kind.undefined); @@ -586,7 +595,7 @@ extern (C++) final class TupleDeclaration : Declaration bool isexp; // true: expression tuple bool building; // it's growing in AliasAssign semantic - extern (D) this(const ref Loc loc, Identifier ident, Objects* objects) + extern (D) this(const ref Loc loc, Identifier ident, Objects* objects) @safe { super(loc, ident); this.objects = objects; @@ -617,7 +626,7 @@ extern (C++) final class TupleDeclaration : Declaration for (size_t i = 0; i < objects.length; i++) { RootObject o = (*objects)[i]; - if (o.dyncast() != DYNCAST.type) + if (!o.isType()) { //printf("\tnot[%d], %p, %d\n", i, o, o.dyncast()); return null; @@ -737,7 +746,7 @@ extern (C++) final class AliasDeclaration : Declaration Dsymbol overnext; // next in overload list Dsymbol _import; // !=null if unresolved internal alias for selective import - extern (D) this(const ref Loc loc, Identifier ident, Type type) + extern (D) this(const ref Loc loc, Identifier ident, Type type) @safe { super(loc, ident); //printf("AliasDeclaration(id = '%s', type = %p)\n", ident.toChars(), type); @@ -746,7 +755,7 @@ extern (C++) final class AliasDeclaration : Declaration assert(type); } - extern (D) this(const ref Loc loc, Identifier ident, Dsymbol s) + extern (D) this(const ref Loc loc, Identifier ident, Dsymbol s) @safe { super(loc, ident); //printf("AliasDeclaration(id = '%s', s = %p)\n", ident.toChars(), s); @@ -755,7 +764,7 @@ extern (C++) final class AliasDeclaration : Declaration assert(s); } - static AliasDeclaration create(const ref Loc loc, Identifier id, Type type) + static AliasDeclaration create(const ref Loc loc, Identifier id, Type type) @safe { return new AliasDeclaration(loc, id, type); } @@ -1036,7 +1045,7 @@ extern (C++) final class OverDeclaration : Declaration Dsymbol overnext; // next in overload list Dsymbol aliassym; - extern (D) this(Identifier ident, Dsymbol s) + extern (D) this(Identifier ident, Dsymbol s) @safe { super(ident); this.aliassym = s; @@ -1158,10 +1167,11 @@ extern (C++) class VarDeclaration : Declaration bool inClosure; /// is inserted into a GC allocated closure bool inAlignSection; /// is inserted into an aligned section on stack } + bool systemInferred; /// @system was inferred from initializer } import dmd.common.bitfields : generateBitFields; - mixin(generateBitFields!(BitFields, ushort)); + mixin(generateBitFields!(BitFields, uint)); byte canassign; // it can be assigned to ubyte isdataseg; // private data for isDataseg 0 unset, 1 true, 2 false @@ -2003,7 +2013,7 @@ extern (C++) final class SymbolDeclaration : Declaration { AggregateDeclaration dsym; - extern (D) this(const ref Loc loc, AggregateDeclaration dsym) + extern (D) this(const ref Loc loc, AggregateDeclaration dsym) @safe { super(loc, dsym.ident); this.dsym = dsym; diff --git a/gcc/d/dmd/declaration.h b/gcc/d/dmd/declaration.h index 197091e..71f2baa 100644 --- a/gcc/d/dmd/declaration.h +++ b/gcc/d/dmd/declaration.h @@ -244,7 +244,7 @@ public: // The index of this variable on the CTFE stack, ~0u if not allocated unsigned ctfeAdrOnStack; private: - uint16_t bitFields; + uint32_t bitFields; public: int8_t canassign; // // it can be assigned to uint8_t isdataseg; // private data for isDataseg @@ -278,6 +278,8 @@ public: bool inAlignSection() const; // is inserted into aligned section on stack bool inAlignSection(bool v); #endif + bool systemInferred() const; + bool systemInferred(bool v); static VarDeclaration *create(const Loc &loc, Type *t, Identifier *id, Initializer *init, StorageClass storage_class = STCundefined); VarDeclaration *syntaxCopy(Dsymbol *) override; void setFieldOffset(AggregateDeclaration *ad, FieldState& fieldState, bool isunion) override final; diff --git a/gcc/d/dmd/delegatize.d b/gcc/d/dmd/delegatize.d index b135bfa..559f103 100644 --- a/gcc/d/dmd/delegatize.d +++ b/gcc/d/dmd/delegatize.d @@ -109,7 +109,7 @@ private void lambdaSetParent(Expression e, FuncDeclaration fd) } public: - extern (D) this(FuncDeclaration fd) scope + extern (D) this(FuncDeclaration fd) scope @safe { this.fd = fd; } @@ -205,7 +205,7 @@ bool lambdaCheckForNestedRef(Expression e, Scope* sc) Scope* sc; bool result; - extern (D) this(Scope* sc) scope + extern (D) this(Scope* sc) scope @safe { this.sc = sc; } diff --git a/gcc/d/dmd/dinterpret.d b/gcc/d/dmd/dinterpret.d index cb74a07..5948351 100644 --- a/gcc/d/dmd/dinterpret.d +++ b/gcc/d/dmd/dinterpret.d @@ -280,19 +280,19 @@ private: Expression localThis; // value of 'this', or NULL if none public: - size_t stackPointer() + size_t stackPointer() @safe { return values.length; } // The current value of 'this', or NULL if none - Expression getThis() + Expression getThis() @safe { return localThis; } // Largest number of stack positions we've used - size_t maxStackUsage() + size_t maxStackUsage() @safe { return maxStackPointer; } @@ -1646,7 +1646,7 @@ public: Expression result; UnionExp* pue; // storage for `result` - extern (D) this(UnionExp* pue, InterState* istate, CTFEGoal goal) scope + extern (D) this(UnionExp* pue, InterState* istate, CTFEGoal goal) scope @safe { this.pue = pue; this.istate = istate; @@ -3246,7 +3246,7 @@ public: */ // Returns the variable which is eventually modified, or NULL if an rvalue. // thisval is the current value of 'this'. - static VarDeclaration findParentVar(Expression e) + static VarDeclaration findParentVar(Expression e) @safe { for (;;) { @@ -6105,7 +6105,10 @@ public: result = interpret(&ue, e.msg, istate); if (exceptionOrCant(result)) return; - e.error("`%s`", result.toChars()); + if (StringExp se = result.isStringExp()) + e.error("%s", se.toStringz().ptr); + else + e.error("%s", result.toChars()); } else e.error("`%s` failed", e.toChars()); @@ -7703,7 +7706,7 @@ private void removeHookTraceImpl(ref CallExp ce, ref FuncDeclaration fd) // Get the Hook from the second template parameter TemplateInstance templateInstance = fd.parent.isTemplateInstance; RootObject hook = (*templateInstance.tiargs)[1]; - assert(hook.dyncast() == DYNCAST.dsymbol, "Expected _d_HookTraceImpl's second template parameter to be an alias to the hook!"); + assert(hook.isDsymbol(), "Expected _d_HookTraceImpl's second template parameter to be an alias to the hook!"); fd = (cast(Dsymbol)hook).isFuncDeclaration; // Remove the first three trace parameters diff --git a/gcc/d/dmd/dmangle.d b/gcc/d/dmd/dmangle.d index ad1e816..9b72308 100644 --- a/gcc/d/dmd/dmangle.d +++ b/gcc/d/dmd/dmangle.d @@ -25,14 +25,14 @@ extern (C++) const(char)* mangleExact(FuncDeclaration fd) { OutBuffer buf; auto backref = Backref(null); - scope Mangler v = new Mangler(&buf, &backref); + scope Mangler v = new Mangler(buf, &backref); v.mangleExact(fd); fd.mangleString = buf.extractChars(); } return fd.mangleString; } -extern (C++) void mangleToBuffer(Type t, OutBuffer* buf) +extern (C++) void mangleToBuffer(Type t, ref OutBuffer buf) { //printf("mangleToBuffer t()\n"); if (t.deco) @@ -45,7 +45,7 @@ extern (C++) void mangleToBuffer(Type t, OutBuffer* buf) } } -extern (C++) void mangleToBuffer(Expression e, OutBuffer* buf) +extern (C++) void mangleToBuffer(Expression e, ref OutBuffer buf) { //printf("mangleToBuffer e()\n"); auto backref = Backref(null); @@ -53,7 +53,7 @@ extern (C++) void mangleToBuffer(Expression e, OutBuffer* buf) e.accept(v); } -extern (C++) void mangleToBuffer(Dsymbol s, OutBuffer* buf) +extern (C++) void mangleToBuffer(Dsymbol s, ref OutBuffer buf) { //printf("mangleToBuffer s(%s)\n", s.toChars()); auto backref = Backref(null); @@ -61,7 +61,7 @@ extern (C++) void mangleToBuffer(Dsymbol s, OutBuffer* buf) s.accept(v); } -extern (C++) void mangleToBuffer(TemplateInstance ti, OutBuffer* buf) +extern (C++) void mangleToBuffer(TemplateInstance ti, ref OutBuffer buf) { //printf("mangleToBuffer ti()\n"); auto backref = Backref(null); @@ -249,7 +249,7 @@ unittest * buf = buffer to append mangling to * backref = state of back references (updated) */ -void mangleType(Type t, ubyte modMask, OutBuffer* buf, ref Backref backref) +void mangleType(Type t, ubyte modMask, ref OutBuffer buf, ref Backref backref) { void visitWithMask(Type t, ubyte modMask) { @@ -395,7 +395,7 @@ void mangleType(Type t, ubyte modMask, OutBuffer* buf, ref Backref backref) /************************************************************* */ -void mangleFuncType(TypeFunction t, TypeFunction ta, ubyte modMask, Type tret, OutBuffer* buf, ref Backref backref) +void mangleFuncType(TypeFunction t, TypeFunction ta, ubyte modMask, Type tret, ref OutBuffer buf, ref Backref backref) { //printf("mangleFuncType() %s\n", t.toChars()); if (t.inuse && tret) @@ -485,7 +485,7 @@ void mangleFuncType(TypeFunction t, TypeFunction ta, ubyte modMask, Type tret, O /************************************************************* */ -void mangleParameter(Parameter p, OutBuffer* buf, ref Backref backref) +void mangleParameter(Parameter p, ref OutBuffer buf, ref Backref backref) { // https://dlang.org/spec/abi.html#Parameter @@ -564,9 +564,9 @@ public: OutBuffer* buf; Backref* backref; - extern (D) this(OutBuffer* buf, Backref* backref) + extern (D) this(ref OutBuffer buf, Backref* backref) @trusted { - this.buf = buf; + this.buf = &buf; this.backref = backref; } @@ -577,8 +577,8 @@ public: void mangleIdentifier(Identifier id, Dsymbol s) { - if (!backref.addRefToIdentifier(buf, id)) - toBuffer(buf, id.toString(), s); + if (!backref.addRefToIdentifier(*buf, id)) + toBuffer(*buf, id.toString(), s); } //////////////////////////////////////////////////////////////////////////// @@ -593,7 +593,7 @@ public: } else if (sthis.type) { - mangleType(sthis.type, 0, buf, *backref); + mangleType(sthis.type, 0, *buf, *backref); } else assert(0); @@ -627,7 +627,7 @@ public: buf.writeByte('0'); if (localNum) - writeLocalParent(buf, localNum); + writeLocalParent(*buf, localNum); } } @@ -651,11 +651,11 @@ public: { TypeFunction tf = fd.type.isTypeFunction(); TypeFunction tfo = fd.originalType.isTypeFunction(); - mangleFuncType(tf, tfo, 0, null, buf, *backref); + mangleFuncType(tf, tfo, 0, null, *buf, *backref); } else { - mangleType(fd.type, 0, buf, *backref); + mangleType(fd.type, 0, *buf, *backref); } } @@ -856,7 +856,7 @@ public: if (ta) { buf.writeByte('T'); - mangleType(ta, 0, buf, *backref); + mangleType(ta, 0, *buf, *backref); } else if (ea) { @@ -899,7 +899,7 @@ public: /* Use type mangling that matches what it would be for a function parameter */ - mangleType(ea.type, 0, buf, *backref); + mangleType(ea.type, 0, *buf, *backref); ea.accept(this); } else if (sa) @@ -915,13 +915,13 @@ public: if (d.mangleOverride) { buf.writeByte('X'); - toBuffer(buf, d.mangleOverride, d); + toBuffer(*buf, d.mangleOverride, d); continue; } if (const id = externallyMangledIdentifier(d)) { buf.writeByte('X'); - toBuffer(buf, id, d); + toBuffer(*buf, id, d); continue; } if (!d.type || !d.type.deco) @@ -975,7 +975,7 @@ public: if (s.ident) mangleIdentifier(s.ident, s); else - toBuffer(buf, s.toString(), s); + toBuffer(*buf, s.toString(), s); //printf("Dsymbol.mangle() %s = %s\n", s.toChars(), id); } @@ -1003,15 +1003,15 @@ public: override void visit(RealExp e) { buf.writeByte('e'); - realToMangleBuffer(buf, e.value); + realToMangleBuffer(*buf, e.value); } override void visit(ComplexExp e) { buf.writeByte('c'); - realToMangleBuffer(buf, e.toReal()); + realToMangleBuffer(*buf, e.toReal()); buf.writeByte('c'); // separate the two - realToMangleBuffer(buf, e.toImaginary()); + realToMangleBuffer(*buf, e.toImaginary()); } override void visit(NullExp e) @@ -1145,7 +1145,7 @@ private struct Backref * true if the type was found. A back reference has been encoded. * false if the type was not found. The current position is saved for later back references. */ - bool addRefToType(OutBuffer* buf, Type t) + bool addRefToType(ref OutBuffer buf, Type t) { if (t.isTypeBasic()) return false; @@ -1184,14 +1184,14 @@ private struct Backref * true if the identifier was found. A back reference has been encoded. * false if the identifier was not found. The current position is saved for later back references. */ - bool addRefToIdentifier(OutBuffer* buf, Identifier id) + bool addRefToIdentifier(ref OutBuffer buf, Identifier id) { return backrefImpl(buf, idents, id); } private: - extern(D) bool backrefImpl(T)(OutBuffer* buf, ref AssocArray!(T, size_t) aa, T key) + extern(D) bool backrefImpl(T)(ref OutBuffer buf, ref AssocArray!(T, size_t) aa, T key) { auto p = aa.getLvalue(key); if (*p) @@ -1214,7 +1214,7 @@ private struct Backref * Mangle basic type ty to buf. */ -private void tyToDecoBuffer(OutBuffer* buf, int ty) +private void tyToDecoBuffer(ref OutBuffer buf, int ty) @safe { const c = mangleChar[ty]; buf.writeByte(c); @@ -1225,7 +1225,7 @@ private void tyToDecoBuffer(OutBuffer* buf, int ty) /********************************* * Mangling for mod. */ -private void MODtoDecoBuffer(OutBuffer* buf, MOD mod) +private void MODtoDecoBuffer(ref OutBuffer buf, MOD mod) @safe { switch (mod) { @@ -1274,7 +1274,7 @@ private void MODtoDecoBuffer(OutBuffer* buf, MOD mod) * pos = relative position to encode */ private -void writeBackRef(OutBuffer* buf, size_t pos) +void writeBackRef(ref OutBuffer buf, size_t pos) @safe { buf.writeByte('Q'); enum base = 26; @@ -1296,7 +1296,7 @@ void writeBackRef(OutBuffer* buf, size_t pos) * Write length prefixed string to buf. */ private -extern (D) void toBuffer(OutBuffer* buf, const(char)[] id, Dsymbol s) +extern (D) void toBuffer(ref OutBuffer buf, const(char)[] id, Dsymbol s) { const len = id.length; if (buf.length + len >= 8 * 1024 * 1024) // 8 megs ought be enough for anyone @@ -1321,7 +1321,7 @@ extern (D) void toBuffer(OutBuffer* buf, const(char)[] id, Dsymbol s) * localNum = local symbol number */ private -void writeLocalParent(OutBuffer* buf, uint localNum) +void writeLocalParent(ref OutBuffer buf, uint localNum) { uint ndigits = 1; auto n = localNum; @@ -1340,7 +1340,7 @@ void writeLocalParent(OutBuffer* buf, uint localNum) * value = real to write */ private -void realToMangleBuffer(OutBuffer* buf, real_t value) +void realToMangleBuffer(ref OutBuffer buf, real_t value) { /* Rely on %A to get portable mangling. * Must munge result to get only identifier characters. diff --git a/gcc/d/dmd/dmodule.d b/gcc/d/dmd/dmodule.d index f00dec7..4a2e15c 100644 --- a/gcc/d/dmd/dmodule.d +++ b/gcc/d/dmd/dmodule.d @@ -948,7 +948,7 @@ extern (C++) final class Module : Package * gets imported, it is unaffected by context. * Ignore prevsc. */ - Scope* sc = Scope.createGlobal(this); // create root scope + Scope* sc = Scope.createGlobal(this, global.errorSink); // create root scope if (md && md.msg) md.msg = semanticString(sc, md.msg, "deprecation message"); @@ -1380,7 +1380,7 @@ extern (C++) struct ModuleDeclaration bool isdeprecated; // if it is a deprecated module Expression msg; - extern (D) this(const ref Loc loc, Identifier[] packages, Identifier id, Expression msg, bool isdeprecated) + extern (D) this(const ref Loc loc, Identifier[] packages, Identifier id, Expression msg, bool isdeprecated) @safe { this.loc = loc; this.packages = packages; @@ -1389,7 +1389,7 @@ extern (C++) struct ModuleDeclaration this.isdeprecated = isdeprecated; } - extern (C++) const(char)* toChars() const + extern (C++) const(char)* toChars() const @safe { OutBuffer buf; foreach (pid; packages) diff --git a/gcc/d/dmd/doc.d b/gcc/d/dmd/doc.d index 3e60dc4..887fd6c 100644 --- a/gcc/d/dmd/doc.d +++ b/gcc/d/dmd/doc.d @@ -34,7 +34,7 @@ import dmd.dstruct; import dmd.dsymbol; import dmd.dsymbolsem; import dmd.dtemplate; -import dmd.errors; +import dmd.errorsink; import dmd.func; import dmd.globals; import dmd.hdrgen; @@ -62,7 +62,7 @@ struct Escape /*************************************** * Find character string to replace c with. */ - const(char)[] escapeChar(char c) + const(char)[] escapeChar(char c) @safe { version (all) { @@ -140,7 +140,7 @@ private class Section size_t o = buf.length; foreach (char c; name) buf.writeByte((c == '_') ? ' ' : c); - escapeStrayParenthesis(loc, buf, o, false); + escapeStrayParenthesis(loc, buf, o, false, sc.eSink); buf.writestring(")"); } else @@ -150,7 +150,7 @@ private class Section L1: size_t o = buf.length; buf.write(body_); - escapeStrayParenthesis(loc, buf, o, true); + escapeStrayParenthesis(loc, buf, o, true, sc.eSink); highlightText(sc, a, loc, *buf, o); buf.writestring(")"); } @@ -252,11 +252,11 @@ private final class ParamSection : Section } else if (!fparam) { - warning(s.loc, "Ddoc: function declaration has no parameter '%.*s'", cast(int)namelen, namestart); + sc.eSink.warning(s.loc, "Ddoc: function declaration has no parameter '%.*s'", cast(int)namelen, namestart); } buf.write(namestart[0 .. namelen]); } - escapeStrayParenthesis(loc, buf, o, true); + escapeStrayParenthesis(loc, buf, o, true, sc.eSink); highlightCode(sc, a, *buf, o); } buf.writestring(")"); @@ -264,7 +264,7 @@ private final class ParamSection : Section { size_t o = buf.length; buf.write(textstart[0 .. textlen]); - escapeStrayParenthesis(loc, buf, o, true); + escapeStrayParenthesis(loc, buf, o, true, sc.eSink); highlightText(sc, a, loc, *buf, o); } buf.writestring(")"); @@ -303,12 +303,12 @@ private final class ParamSection : Section cast(int)(tf.parameterList.varargs == VarArg.variadic); if (pcount != paramcount) { - warning(s.loc, "Ddoc: parameter count mismatch, expected %llu, got %llu", + sc.eSink.warning(s.loc, "Ddoc: parameter count mismatch, expected %llu, got %llu", cast(ulong) pcount, cast(ulong) paramcount); if (paramcount == 0) { // Chances are someone messed up the format - warningSupplemental(s.loc, "Note that the format is `param = description`"); + sc.eSink.warningSupplemental(s.loc, "Note that the format is `param = description`"); } } } @@ -355,7 +355,7 @@ private Dsymbol getEponymousMember(TemplateDeclaration td) @safe return null; } -private TemplateDeclaration getEponymousParent(Dsymbol s) +private TemplateDeclaration getEponymousParent(Dsymbol s) @safe { if (!s.parent) return null; @@ -371,7 +371,7 @@ private immutable ddoc_decl_dd_e = ")\n"; /**************************************************** */ -extern(C++) void gendocfile(Module m) +extern(C++) void gendocfile(Module m, ErrorSink eSink) { __gshared OutBuffer mbuf; __gshared int mbuf_done; @@ -397,7 +397,7 @@ extern(C++) void gendocfile(Module m) } } DocComment.parseMacros(m.escapetable, m.macrotable, mbuf[]); - Scope* sc = Scope.createGlobal(m); // create root scope + Scope* sc = Scope.createGlobal(m, eSink); // create root scope DocComment* dc = DocComment.parse(m, m.comment); dc.pmacrotable = &m.macrotable; dc.escapetable = m.escapetable; @@ -460,7 +460,7 @@ extern(C++) void gendocfile(Module m) const success = m.macrotable.expand(buf2, 0, end, null, global.recursionLimit); if (!success) - error(Loc.initial, "DDoc macro expansion limit exceeded; more than %d expansions.", global.recursionLimit); + eSink.error(Loc.initial, "DDoc macro expansion limit exceeded; more than %d expansions.", global.recursionLimit); version (all) { @@ -568,7 +568,7 @@ void escapeDdocString(OutBuffer* buf, size_t start) * directly preceeded by a backslash with $(LPAREN) or $(RPAREN) instead of * counting them as stray parentheses */ -private void escapeStrayParenthesis(Loc loc, OutBuffer* buf, size_t start, bool respectBackslashEscapes) +private void escapeStrayParenthesis(Loc loc, OutBuffer* buf, size_t start, bool respectBackslashEscapes, ErrorSink eSink) { uint par_open = 0; char inCode = 0; @@ -589,7 +589,7 @@ private void escapeStrayParenthesis(Loc loc, OutBuffer* buf, size_t start, bool if (par_open == 0) { //stray ')' - warning(loc, "Ddoc: Stray ')'. This may cause incorrect Ddoc output. Use $(RPAREN) instead for unpaired right parentheses."); + eSink.warning(loc, "Ddoc: Stray ')'. This may cause incorrect Ddoc output. Use $(RPAREN) instead for unpaired right parentheses."); buf.remove(u, 1); //remove the ) buf.insert(u, "$(RPAREN)"); //insert this instead u += 8; //skip over newly inserted macro @@ -667,7 +667,7 @@ private void escapeStrayParenthesis(Loc loc, OutBuffer* buf, size_t start, bool if (par_open == 0) { //stray '(' - warning(loc, "Ddoc: Stray '('. This may cause incorrect Ddoc output. Use $(LPAREN) instead for unpaired left parentheses."); + eSink.warning(loc, "Ddoc: Stray '('. This may cause incorrect Ddoc output. Use $(LPAREN) instead for unpaired left parentheses."); buf.remove(u, 1); //remove the ( buf.insert(u, "$(LPAREN)"); //insert this instead } @@ -683,7 +683,7 @@ private void escapeStrayParenthesis(Loc loc, OutBuffer* buf, size_t start, bool // Basically, this is to skip over things like private{} blocks in a struct or // class definition that don't add any components to the qualified name. -private Scope* skipNonQualScopes(Scope* sc) +private Scope* skipNonQualScopes(Scope* sc) @safe { while (sc && !sc.scopesym) sc = sc.enclosing; @@ -1398,7 +1398,7 @@ private void toDocBuffer(Dsymbol s, ref OutBuffer buf, Scope* sc) } } - static bool inSameModule(Dsymbol s, Dsymbol p) + static bool inSameModule(Dsymbol s, Dsymbol p) @safe { for (; s; s = s.parent) { @@ -1896,7 +1896,7 @@ struct DocComment buf.writestring("$(DDOC_SUMMARY "); size_t o = buf.length; buf.write(sec.body_); - escapeStrayParenthesis(loc, buf, o, true); + escapeStrayParenthesis(loc, buf, o, true, sc.eSink); highlightText(sc, a, loc, *buf, o); buf.writestring(")"); } @@ -1968,7 +1968,7 @@ private const(char)* skipwhitespace(const(char)* p) } /// Ditto -private const(char)[] skipwhitespace(const(char)[] p) +private const(char)[] skipwhitespace(const(char)[] p) @safe { foreach (idx, char c; p) { @@ -1993,7 +1993,7 @@ private const(char)[] skipwhitespace(const(char)[] p) * chars = the characters to skip; order is unimportant * Returns: the index after skipping characters. */ -private size_t skipChars(ref OutBuffer buf, size_t i, string chars) +private size_t skipChars(ref OutBuffer buf, size_t i, string chars) @safe { Outer: foreach (j, c; buf[][i..$]) @@ -2028,7 +2028,7 @@ unittest { * r = the string to replace `c` with * Returns: `s` with `c` replaced with `r` */ -private inout(char)[] replaceChar(inout(char)[] s, char c, string r) pure +private inout(char)[] replaceChar(inout(char)[] s, char c, string r) pure @safe { int count = 0; foreach (char sc; s) @@ -2070,7 +2070,7 @@ unittest * s = the string to lowercase * Returns: the lowercase version of the string or the original if already lowercase */ -private string toLowercase(string s) pure +private string toLowercase(string s) pure @safe { string lower; foreach (size_t i; 0..s.length) @@ -2112,7 +2112,7 @@ unittest * to = the index within `buf` to stop counting at, exclusive * Returns: the indent */ -private int getMarkdownIndent(ref OutBuffer buf, size_t from, size_t to) +private int getMarkdownIndent(ref OutBuffer buf, size_t from, size_t to) @safe { const slice = buf[]; if (to > slice.length) @@ -2129,7 +2129,7 @@ private int getMarkdownIndent(ref OutBuffer buf, size_t from, size_t to) * beginning of next line * end of buf */ -size_t skiptoident(ref OutBuffer buf, size_t i) +size_t skiptoident(ref OutBuffer buf, size_t i) @safe { const slice = buf[]; while (i < slice.length) @@ -2158,7 +2158,7 @@ size_t skiptoident(ref OutBuffer buf, size_t i) /************************************************ * Scan forward past end of identifier. */ -private size_t skippastident(ref OutBuffer buf, size_t i) +private size_t skippastident(ref OutBuffer buf, size_t i) @safe { const slice = buf[]; while (i < slice.length) @@ -2188,7 +2188,7 @@ private size_t skippastident(ref OutBuffer buf, size_t i) * Scan forward past end of an identifier that might * contain dots (e.g. `abc.def`) */ -private size_t skipPastIdentWithDots(ref OutBuffer buf, size_t i) +private size_t skipPastIdentWithDots(ref OutBuffer buf, size_t i) @safe { const slice = buf[]; bool lastCharWasDot; @@ -2356,7 +2356,7 @@ private bool replaceMarkdownThematicBreak(ref OutBuffer buf, ref size_t i, size_ * the detected heading level from 1 to 6, or * 0 if not at an ATX heading */ -private int detectAtxHeadingLevel(ref OutBuffer buf, const size_t i) +private int detectAtxHeadingLevel(ref OutBuffer buf, const size_t i) @safe { const iHeadingStart = i; const iAfterHashes = skipChars(buf, i, "#"); @@ -2566,7 +2566,7 @@ private size_t replaceMarkdownEmphasis(ref OutBuffer buf, const ref Loc loc, ref /**************************************************** */ -private bool isIdentifier(Dsymbols* a, const(char)[] s) +private bool isIdentifier(Dsymbols* a, const(char)[] s) @safe { foreach (member; *a) { @@ -2744,7 +2744,7 @@ private TemplateParameter isTemplateParameter(Dsymbols* a, const(char)* p, size_ * Return true if str is a reserved symbol name * that starts with a double underscore. */ -private bool isReservedName(const(char)[] str) +private bool isReservedName(const(char)[] str) @safe { immutable string[] table = [ @@ -2802,10 +2802,10 @@ private struct MarkdownDelimiter char type; /// the type of delimiter, defined by its starting character /// whether this describes a valid delimiter - @property bool isValid() const { return count != 0; } + @property bool isValid() const @safe { return count != 0; } /// flag this delimiter as invalid - void invalidate() { count = 0; } + void invalidate() @safe { count = 0; } } /**************************************************** @@ -2822,7 +2822,7 @@ private struct MarkdownList char type; /// the type of list, defined by its starting character /// whether this describes a valid list - @property bool isValid() const { return type != type.init; } + @property bool isValid() const @safe { return type != type.init; } /**************************************************** * Try to parse a list item, returning whether successful. @@ -2832,7 +2832,7 @@ private struct MarkdownList * i = the index within `buf` of the potential list item * Returns: the parsed list item. Its `isValid` property describes whether parsing succeeded. */ - static MarkdownList parseItem(ref OutBuffer buf, size_t iLineStart, size_t i) + static MarkdownList parseItem(ref OutBuffer buf, size_t iLineStart, size_t i) @safe { if (buf[i] == '+' || buf[i] == '-' || buf[i] == '*') return parseUnorderedListItem(buf, iLineStart, i); @@ -2848,7 +2848,7 @@ private struct MarkdownList * i = the index within `buf` of the list item * Returns: whether `i` is at a list item of the same type as this list */ - private bool isAtItemInThisList(ref OutBuffer buf, size_t iLineStart, size_t i) + private bool isAtItemInThisList(ref OutBuffer buf, size_t iLineStart, size_t i) @safe { MarkdownList item = (type == '.' || type == ')') ? parseOrderedListItem(buf, iLineStart, i) : @@ -2970,7 +2970,7 @@ private struct MarkdownList * i = the index within `buf` of the list item * Returns: the parsed list item, or a list item with type `.init` if no list item is available */ - private static MarkdownList parseUnorderedListItem(ref OutBuffer buf, size_t iLineStart, size_t i) + private static MarkdownList parseUnorderedListItem(ref OutBuffer buf, size_t iLineStart, size_t i) @safe { if (i+1 < buf.length && (buf[i] == '-' || @@ -2998,7 +2998,7 @@ private struct MarkdownList * i = the index within `buf` of the list item * Returns: the parsed list item, or a list item with type `.init` if no list item is available */ - private static MarkdownList parseOrderedListItem(ref OutBuffer buf, size_t iLineStart, size_t i) + private static MarkdownList parseOrderedListItem(ref OutBuffer buf, size_t iLineStart, size_t i) @safe { size_t iAfterNumbers = skipChars(buf, i, "0123456789"); if (iAfterNumbers - i > 0 && @@ -3156,7 +3156,7 @@ private struct MarkdownLink * delimiter = the delimiter that starts this link * Returns: the index at the end of parsing the link, or `i` if parsing failed. */ - private size_t parseReferenceLink(ref OutBuffer buf, size_t i, MarkdownDelimiter delimiter) + private size_t parseReferenceLink(ref OutBuffer buf, size_t i, MarkdownDelimiter delimiter) @safe { size_t iStart = i + 1; size_t iEnd = iStart; @@ -3233,7 +3233,7 @@ private struct MarkdownLink * If this function returns a non-empty label then `i` will point just after the ']' at the end of the label. * Returns: the parsed and normalized label, possibly empty */ - private bool parseLabel(ref OutBuffer buf, ref size_t i) + private bool parseLabel(ref OutBuffer buf, ref size_t i) @safe { if (buf[i] != '[') return false; @@ -3506,7 +3506,7 @@ private struct MarkdownLink * s = the string to remove escaping backslashes from * Returns: `s` without escaping backslashes in it */ - private static char[] removeEscapeBackslashes(char[] s) + private static char[] removeEscapeBackslashes(char[] s) @safe { if (!s.length) return s; @@ -3550,7 +3550,7 @@ private struct MarkdownLink * s = the string to percent-encode * Returns: `s` with special characters percent-encoded */ - private static inout(char)[] percentEncode(inout(char)[] s) pure + private static inout(char)[] percentEncode(inout(char)[] s) pure @safe { static bool shouldEncode(char c) { @@ -3591,7 +3591,7 @@ private struct MarkdownLink * If this function succeeds `i` will point after the newline. * Returns: whether a newline was skipped */ - private static bool skipOneNewline(ref OutBuffer buf, ref size_t i) pure + private static bool skipOneNewline(ref OutBuffer buf, ref size_t i) pure @safe { if (i < buf.length && buf[i] == '\r') ++i; @@ -3786,7 +3786,7 @@ private struct MarkdownLinkReferences * delimiter = the character to split by * Returns: the resulting array of strings */ - private static string[] split(string s, char delimiter) pure + private static string[] split(string s, char delimiter) pure @safe { string[] result; size_t iStart = 0; @@ -3893,7 +3893,7 @@ private enum TableColumnAlignment * columnAlignments = alignments to populate for each column * Returns: the index of the end of the parsed delimiter, or `0` if not found */ -private size_t parseTableDelimiterRow(ref OutBuffer buf, const size_t iStart, bool inQuote, ref TableColumnAlignment[] columnAlignments) +private size_t parseTableDelimiterRow(ref OutBuffer buf, const size_t iStart, bool inQuote, ref TableColumnAlignment[] columnAlignments) @safe { size_t i = skipChars(buf, iStart, inQuote ? ">| \t" : "| \t"); while (i < buf.length && buf[i] != '\r' && buf[i] != '\n') @@ -4417,7 +4417,7 @@ private void highlightText(Scope* sc, Dsymbols* a, Loc loc, ref OutBuffer buf, s codebuf.write(buf[iCodeStart + count .. i]); // escape the contents, but do not perform highlighting except for DDOC_PSYMBOL highlightCode(sc, a, codebuf, 0); - escapeStrayParenthesis(loc, &codebuf, 0, false); + escapeStrayParenthesis(loc, &codebuf, 0, false, sc.eSink); buf.remove(iCodeStart, i - iCodeStart + count); // also trimming off the current ` immutable pre = "$(DDOC_BACKQUOTED "; i = buf.insert(iCodeStart, pre); @@ -4626,7 +4626,7 @@ private void highlightText(Scope* sc, Dsymbols* a, Loc loc, ref OutBuffer buf, s highlightCode2(sc, a, codebuf, 0); else codebuf.remove(codebuf.length-1, 1); // remove the trailing 0 byte - escapeStrayParenthesis(loc, &codebuf, 0, false); + escapeStrayParenthesis(loc, &codebuf, 0, false, sc.eSink); buf.remove(iCodeStart, i - iCodeStart); i = buf.insert(iCodeStart, codebuf[]); i = buf.insert(i, ")\n"); @@ -4984,7 +4984,7 @@ private void highlightText(Scope* sc, Dsymbols* a, Loc loc, ref OutBuffer buf, s } if (inCode == '-') - error(loc, "unmatched `---` in DDoc comment"); + sc.eSink.error(loc, "unmatched `---` in DDoc comment"); else if (inCode) buf.insert(buf.length, ")"); @@ -5180,10 +5180,10 @@ private void highlightCode3(Scope* sc, ref OutBuffer buf, const(char)* p, const( */ private void highlightCode2(Scope* sc, Dsymbols* a, ref OutBuffer buf, size_t offset) { - uint errorsave = global.startGagging(); + scope eSinkNull = new ErrorSinkNull(); scope Lexer lex = new Lexer(null, cast(char*)buf[].ptr, 0, buf.length - 1, 0, 1, - global.errorSink, + eSinkNull, // ignore errors &global.compileEnv); OutBuffer res; const(char)* lastp = cast(char*)buf[].ptr; @@ -5247,7 +5247,6 @@ private void highlightCode2(Scope* sc, Dsymbols* a, ref OutBuffer buf, size_t of } buf.setsize(offset); buf.write(&res); - global.endGagging(errorsave); } /**************************************** diff --git a/gcc/d/dmd/doc.h b/gcc/d/dmd/doc.h index d16806b..669e308 100644 --- a/gcc/d/dmd/doc.h +++ b/gcc/d/dmd/doc.h @@ -11,5 +11,6 @@ #pragma once class Module; +class ErrorSink; -void gendocfile(Module *m); +void gendocfile(Module *m, ErrorSink *eSink); diff --git a/gcc/d/dmd/dscope.d b/gcc/d/dmd/dscope.d index 95cfec9..c2c0628 100644 --- a/gcc/d/dmd/dscope.d +++ b/gcc/d/dmd/dscope.d @@ -29,6 +29,7 @@ import dmd.dsymbolsem; import dmd.dtemplate; import dmd.expression; import dmd.errors; +import dmd.errorsink; import dmd.func; import dmd.globals; import dmd.id; @@ -96,6 +97,7 @@ extern (C++) struct Scope bool inLoop; /// true if inside a loop (where constructor calls aren't allowed) int intypeof; /// in typeof(exp) VarDeclaration lastVar; /// Previous symbol used to prevent goto-skips-init + ErrorSink eSink; /// sink for error messages /* If minst && !tinst, it's in definitely non-speculative scope (eg. module member scope). * If !minst && !tinst, it's in definitely speculative scope (eg. template constraint). @@ -158,7 +160,7 @@ extern (C++) struct Scope return new Scope(); } - extern (D) static Scope* createGlobal(Module _module) + extern (D) static Scope* createGlobal(Module _module, ErrorSink eSink) { Scope* sc = Scope.alloc(); *sc = Scope.init; @@ -166,6 +168,7 @@ extern (C++) struct Scope sc.minst = _module; sc.scopesym = new ScopeDsymbol(); sc.scopesym.symtab = new DsymbolTable(); + sc.eSink = eSink; // Add top level package as member of this global scope Dsymbol m = _module; while (m.parent) @@ -614,7 +617,7 @@ extern (C++) struct Scope * Returns: * innermost scope, null if none */ - extern (D) Scope* inner() return + extern (D) Scope* inner() return @safe { for (Scope* sc = &this; sc; sc = sc.enclosing) { @@ -670,7 +673,7 @@ extern (C++) struct Scope /******************************************** * Search enclosing scopes for ScopeDsymbol. */ - extern (D) ScopeDsymbol getScopesym() + extern (D) ScopeDsymbol getScopesym() @safe { for (Scope* sc = &this; sc; sc = sc.enclosing) { @@ -683,7 +686,7 @@ extern (C++) struct Scope /******************************************** * Search enclosing scopes for ClassDeclaration. */ - extern (D) ClassDeclaration getClassScope() + extern (D) ClassDeclaration getClassScope() @safe { for (Scope* sc = &this; sc; sc = sc.enclosing) { @@ -698,7 +701,7 @@ extern (C++) struct Scope /******************************************** * Search enclosing scopes for ClassDeclaration or StructDeclaration. */ - extern (D) AggregateDeclaration getStructClassScope() + extern (D) AggregateDeclaration getStructClassScope() @safe { for (Scope* sc = &this; sc; sc = sc.enclosing) { @@ -742,7 +745,7 @@ extern (C++) struct Scope * where it was declared. So mark the Scope as not * to be free'd. */ - extern (D) void setNoFree() + extern (D) void setNoFree() @safe { //int i = 0; //printf("Scope::setNoFree(this = %p)\n", this); diff --git a/gcc/d/dmd/dsymbol.d b/gcc/d/dmd/dsymbol.d index 2373313..0fa4dbc 100644 --- a/gcc/d/dmd/dsymbol.d +++ b/gcc/d/dmd/dsymbol.d @@ -113,7 +113,7 @@ struct Ungag { uint oldgag; - extern (D) this(uint old) nothrow + extern (D) this(uint old) nothrow @safe { this.oldgag = old; } @@ -177,7 +177,7 @@ struct Visibility /** * Checks if `this` is absolutely identical visibility attribute to `other` */ - bool opEquals(ref const Visibility other) const + bool opEquals(ref const Visibility other) const @safe { if (this.kind == other.kind) { @@ -264,27 +264,27 @@ extern (C++) class Dsymbol : ASTNode PASS semanticRun = PASS.initial; ushort localNum; /// perturb mangled name to avoid collisions with those in FuncDeclaration.localsymtab - final extern (D) this() nothrow + final extern (D) this() nothrow @safe { //printf("Dsymbol::Dsymbol(%p)\n", this); loc = Loc(null, 0, 0); } - final extern (D) this(Identifier ident) nothrow + final extern (D) this(Identifier ident) nothrow @safe { //printf("Dsymbol::Dsymbol(%p, ident)\n", this); this.loc = Loc(null, 0, 0); this.ident = ident; } - final extern (D) this(const ref Loc loc, Identifier ident) nothrow + final extern (D) this(const ref Loc loc, Identifier ident) nothrow @safe { //printf("Dsymbol::Dsymbol(%p, ident)\n", this); this.loc = loc; this.ident = ident; } - static Dsymbol create(Identifier ident) nothrow + static Dsymbol create(Identifier ident) nothrow @safe { return new Dsymbol(ident); } @@ -353,9 +353,9 @@ extern (C++) class Dsymbol : ASTNode { if (this == o) return true; - if (o.dyncast() != DYNCAST.dsymbol) + const s = o.isDsymbol(); + if (!s) return false; - auto s = cast(Dsymbol)o; // Overload sets don't have an ident // Function-local declarations may have identical names // if they are declared in different scopes @@ -381,7 +381,7 @@ extern (C++) class Dsymbol : ASTNode { va_list ap; va_start(ap, format); - .verror(loc, format, ap, kind(), prettyFormatHelper().ptr); + .verrorReport(loc, format, ap, ErrorKind.error, kind(), prettyFormatHelper().ptr); va_end(ap); } @@ -390,7 +390,7 @@ extern (C++) class Dsymbol : ASTNode va_list ap; va_start(ap, format); const loc = getLoc(); - .verror(loc, format, ap, kind(), prettyFormatHelper().ptr); + .verrorReport(loc, format, ap, ErrorKind.error, kind(), prettyFormatHelper().ptr); va_end(ap); } @@ -398,7 +398,7 @@ extern (C++) class Dsymbol : ASTNode { va_list ap; va_start(ap, format); - .vdeprecation(loc, format, ap, kind(), prettyFormatHelper().ptr); + .verrorReport(loc, format, ap, ErrorKind.deprecation, kind(), prettyFormatHelper().ptr); va_end(ap); } @@ -407,7 +407,7 @@ extern (C++) class Dsymbol : ASTNode va_list ap; va_start(ap, format); const loc = getLoc(); - .vdeprecation(loc, format, ap, kind(), prettyFormatHelper().ptr); + .verrorReport(loc, format, ap, ErrorKind.deprecation, kind(), prettyFormatHelper().ptr); va_end(ap); } } @@ -417,7 +417,7 @@ extern (C++) class Dsymbol : ASTNode { va_list ap; va_start(ap, format); - .verror(loc, format, ap, kind(), prettyFormatHelper().ptr); + .verrorReport(loc, format, ap, ErrorKind.error, kind(), prettyFormatHelper().ptr); va_end(ap); } @@ -426,7 +426,7 @@ extern (C++) class Dsymbol : ASTNode va_list ap; va_start(ap, format); const loc = getLoc(); - .verror(loc, format, ap, kind(), prettyFormatHelper().ptr); + .verrorReport(loc, format, ap, ErrorKind.error, kind(), prettyFormatHelper().ptr); va_end(ap); } @@ -434,7 +434,7 @@ extern (C++) class Dsymbol : ASTNode { va_list ap; va_start(ap, format); - .vdeprecation(loc, format, ap, kind(), prettyFormatHelper().ptr); + .verrorReport(loc, format, ap, ErrorKind.deprecation, kind(), prettyFormatHelper().ptr); va_end(ap); } @@ -443,7 +443,7 @@ extern (C++) class Dsymbol : ASTNode va_list ap; va_start(ap, format); const loc = getLoc(); - .vdeprecation(loc, format, ap, kind(), prettyFormatHelper().ptr); + .verrorReport(loc, format, ap, ErrorKind.deprecation, kind(), prettyFormatHelper().ptr); va_end(ap); } } @@ -1430,16 +1430,16 @@ private: BitArray accessiblePackages, privateAccessiblePackages;// whitelists of accessible (imported) packages public: - final extern (D) this() nothrow + final extern (D) this() nothrow @safe { } - final extern (D) this(Identifier ident) nothrow + final extern (D) this(Identifier ident) nothrow @safe { super(ident); } - final extern (D) this(const ref Loc loc, Identifier ident) nothrow + final extern (D) this(const ref Loc loc, Identifier ident) nothrow @safe { super(loc, ident); } @@ -1919,7 +1919,7 @@ extern (C++) final class WithScopeSymbol : ScopeDsymbol { WithStatement withstate; - extern (D) this(WithStatement withstate) nothrow + extern (D) this(WithStatement withstate) nothrow @safe { this.withstate = withstate; } @@ -1979,7 +1979,7 @@ extern (C++) final class ArrayScopeSymbol : ScopeDsymbol private RootObject arrayContent; Scope* sc; - extern (D) this(Scope* sc, Expression exp) nothrow + extern (D) this(Scope* sc, Expression exp) nothrow @safe { super(exp.loc, null); assert(exp.op == EXP.index || exp.op == EXP.slice || exp.op == EXP.array); @@ -1987,13 +1987,13 @@ extern (C++) final class ArrayScopeSymbol : ScopeDsymbol this.arrayContent = exp; } - extern (D) this(Scope* sc, TypeTuple type) nothrow + extern (D) this(Scope* sc, TypeTuple type) nothrow @safe { this.sc = sc; this.arrayContent = type; } - extern (D) this(Scope* sc, TupleDeclaration td) nothrow + extern (D) this(Scope* sc, TupleDeclaration td) nothrow @safe { this.sc = sc; this.arrayContent = td; @@ -2242,7 +2242,7 @@ extern (C++) final class OverloadSet : Dsymbol */ extern (C++) final class ForwardingScopeDsymbol : ScopeDsymbol { - extern (D) this() nothrow + extern (D) this() nothrow @safe { super(); } @@ -2328,7 +2328,7 @@ extern (C++) final class ForwardingScopeDsymbol : ScopeDsymbol extern (C++) final class ExpressionDsymbol : Dsymbol { Expression exp; - this(Expression exp) nothrow + this(Expression exp) nothrow @safe { super(); this.exp = exp; @@ -2353,7 +2353,7 @@ extern (C++) final class AliasAssign : Dsymbol Dsymbol aliassym; /// replace previous RHS of AliasDeclaration with `aliassym` /// only one of type and aliassym can be != null - extern (D) this(const ref Loc loc, Identifier ident, Type type, Dsymbol aliassym) nothrow + extern (D) this(const ref Loc loc, Identifier ident, Type type, Dsymbol aliassym) nothrow @safe { super(loc, null); this.ident = ident; diff --git a/gcc/d/dmd/dsymbolsem.d b/gcc/d/dmd/dsymbolsem.d index 7a800bd..378d3e6 100644 --- a/gcc/d/dmd/dsymbolsem.d +++ b/gcc/d/dmd/dsymbolsem.d @@ -274,7 +274,7 @@ private extern(C++) final class DsymbolSemanticVisitor : Visitor alias visit = Visitor.visit; Scope* sc; - this(Scope* sc) scope + this(Scope* sc) scope @safe { this.sc = sc; } @@ -320,11 +320,6 @@ private extern(C++) final class DsymbolSemanticVisitor : Visitor return; } - // @@@DEPRECATED_2.121@@@ - // Deprecated in 2.101 - Can be removed in 2.121 - if (ad.isClassDeclaration() || ad.isInterfaceDeclaration()) - deprecation(dsym.loc, "alias this for classes/interfaces is deprecated"); - assert(ad.members); Dsymbol s = ad.search(dsym.loc, dsym.ident); if (!s) @@ -1125,16 +1120,12 @@ private extern(C++) final class DsymbolSemanticVisitor : Visitor */ if (ne.member && !(ne.member.storage_class & STC.scope_)) { - if (sc.func.isSafe()) - { - // @@@DEPRECATED_2.112@@@ - deprecation(dsym.loc, - "`scope` allocation of `%s` requires that constructor be annotated with `scope`", - dsym.toChars()); - deprecationSupplemental(ne.member.loc, "is the location of the constructor"); - } - else - sc.func.setUnsafe(); + import dmd.escape : setUnsafeDIP1000; + const inSafeFunc = sc.func && sc.func.isSafeBypassingInference(); + if (sc.setUnsafeDIP1000(false, dsym.loc, "`scope` allocation of `%s` requires that constructor be annotated with `scope`", dsym)) + errorSupplemental(ne.member.loc, "is the location of the constructor"); + else if (global.params.obsolete && inSafeFunc) + warningSupplemental(ne.member.loc, "is the location of the constructor"); } ne.onstack = 1; dsym.onstack = true; @@ -1224,8 +1215,11 @@ private extern(C++) final class DsymbolSemanticVisitor : Visitor bool needctfe = dsym.isDataseg() || (dsym.storage_class & STC.manifest); if (needctfe) sc = sc.startCTFE(); + sc = sc.push(); + sc.varDecl = dsym; // https://issues.dlang.org/show_bug.cgi?id=24051 exp = exp.expressionSemantic(sc); exp = resolveProperties(sc, exp); + sc = sc.pop(); if (needctfe) sc = sc.endCTFE(); ei.exp = exp; @@ -2098,7 +2092,7 @@ private extern(C++) final class DsymbolSemanticVisitor : Visitor Scope* sc = m._scope; // see if already got one from importAll() if (!sc) { - sc = Scope.createGlobal(m); // create root scope + sc = Scope.createGlobal(m, global.errorSink); // create root scope } //printf("Module = %p, linkage = %d\n", sc.scopesym, sc.linkage); @@ -6087,7 +6081,7 @@ void templateInstanceSemantic(TemplateInstance tempinst, Scope* sc, ArgumentList alias visit = Visitor.visit; TemplateInstance inst; - extern (D) this(TemplateInstance inst) scope + extern (D) this(TemplateInstance inst) scope @safe { this.inst = inst; } diff --git a/gcc/d/dmd/dtemplate.d b/gcc/d/dmd/dtemplate.d index f2ab694..e492c7e 100644 --- a/gcc/d/dmd/dtemplate.d +++ b/gcc/d/dmd/dtemplate.d @@ -84,7 +84,7 @@ private enum LOG = false; enum IDX_NOTFOUND = 0x12345678; -pure nothrow @nogc +pure nothrow @nogc @safe { /******************************************** @@ -3507,7 +3507,7 @@ MATCH deduceType(RootObject o, Scope* sc, Type tparam, TemplateParameters* param bool ignoreAliasThis; MATCH result; - extern (D) this(Scope* sc, Type tparam, TemplateParameters* parameters, Objects* dedtypes, uint* wm, size_t inferStart, bool ignoreAliasThis) + extern (D) this(Scope* sc, Type tparam, TemplateParameters* parameters, Objects* dedtypes, uint* wm, size_t inferStart, bool ignoreAliasThis) @safe { this.sc = sc; this.tparam = tparam; @@ -5091,7 +5091,7 @@ private bool reliesOnTemplateParameters(Expression e, TemplateParameter[] tparam TemplateParameter[] tparams; bool result; - extern (D) this(TemplateParameter[] tparams) + extern (D) this(TemplateParameter[] tparams) @safe { this.tparams = tparams; } @@ -5358,7 +5358,7 @@ extern (C++) class TemplateParameter : ASTNode bool dependent; /* ======================== TemplateParameter =============================== */ - extern (D) this(const ref Loc loc, Identifier ident) + extern (D) this(const ref Loc loc, Identifier ident) @safe { this.loc = loc; this.ident = ident; @@ -5433,7 +5433,7 @@ extern (C++) class TemplateTypeParameter : TemplateParameter extern (D) __gshared Type tdummy = null; - extern (D) this(const ref Loc loc, Identifier ident, Type specType, Type defaultType) + extern (D) this(const ref Loc loc, Identifier ident, Type specType, Type defaultType) @safe { super(loc, ident); this.specType = specType; @@ -5521,7 +5521,7 @@ extern (C++) class TemplateTypeParameter : TemplateParameter */ extern (C++) final class TemplateThisParameter : TemplateTypeParameter { - extern (D) this(const ref Loc loc, Identifier ident, Type specType, Type defaultType) + extern (D) this(const ref Loc loc, Identifier ident, Type specType, Type defaultType) @safe { super(loc, ident, specType, defaultType); } @@ -5556,7 +5556,7 @@ extern (C++) final class TemplateValueParameter : TemplateParameter extern (D) __gshared Expression[void*] edummies; extern (D) this(const ref Loc loc, Identifier ident, Type valType, - Expression specValue, Expression defaultValue) + Expression specValue, Expression defaultValue) @safe { super(loc, ident); this.valType = valType; @@ -5683,7 +5683,7 @@ extern (C++) final class TemplateAliasParameter : TemplateParameter extern (D) __gshared Dsymbol sdummy = null; - extern (D) this(const ref Loc loc, Identifier ident, Type specType, RootObject specAlias, RootObject defaultAlias) + extern (D) this(const ref Loc loc, Identifier ident, Type specType, RootObject specAlias, RootObject defaultAlias) @safe { super(loc, ident); this.specType = specType; @@ -5768,7 +5768,7 @@ extern (C++) final class TemplateAliasParameter : TemplateParameter */ extern (C++) final class TemplateTupleParameter : TemplateParameter { - extern (D) this(const ref Loc loc, Identifier ident) + extern (D) this(const ref Loc loc, Identifier ident) @safe { super(loc, ident); } @@ -7542,7 +7542,7 @@ extern (C++) class TemplateInstance : ScopeDsymbol //printf("TemplateInstance.genIdent('%s')\n", tempdecl.ident.toChars()); assert(args is tiargs); OutBuffer buf; - mangleToBuffer(this, &buf); + mangleToBuffer(this, buf); //printf("\tgenIdent = %s\n", buf.peekChars()); return Identifier.idPool(buf[]); } @@ -7717,7 +7717,7 @@ void unSpeculative(Scope* sc, RootObject o) * Return false if it might be an alias or tuple. * (Note that even in this case, it could still turn out to be a value). */ -bool definitelyValueParameter(Expression e) +bool definitelyValueParameter(Expression e) @safe { // None of these can be value parameters if (e.op == EXP.tuple || e.op == EXP.scope_ || diff --git a/gcc/d/dmd/dtoh.d b/gcc/d/dmd/dtoh.d index b9bbad0..6a7442a 100644 --- a/gcc/d/dmd/dtoh.d +++ b/gcc/d/dmd/dtoh.d @@ -295,7 +295,7 @@ public: // Generates getter-setter methods to replace the use of alias this // This should be replaced by a `static foreach` once the gdc tester // gets upgraded to version 10 (to support `static foreach`). - private extern(D) static string generateMembers() + private extern(D) static string generateMembers() @safe { string result = ""; foreach(member; __traits(allMembers, Context)) @@ -304,7 +304,6 @@ public: } return result; } - mixin(generateMembers()); this(OutBuffer* fwdbuf, OutBuffer* donebuf, OutBuffer* buf) scope @@ -396,7 +395,7 @@ public: } /// Writes a final `;` and insert an empty line outside of aggregates - private void writeDeclEnd() + private void writeDeclEnd() @safe { buf.writestringln(";"); @@ -1213,7 +1212,7 @@ public: buf.writestringln("};"); } - private bool memberField(AST.VarDeclaration vd) + private bool memberField(AST.VarDeclaration vd) @safe { if (!vd.type || !vd.type.deco || !vd.ident) return false; @@ -1411,7 +1410,7 @@ public: /// Ends a custom alignment section using `#pragma pack` if /// `alignment` specifies a custom alignment - private void popAlignToBuffer(structalign_t alignment) + private void popAlignToBuffer(structalign_t alignment) @safe { if (alignment.isDefault() || (tdparent && alignment.isUnknown())) return; @@ -3038,7 +3037,7 @@ public: } /// Returns: Explicit mangling for `sym` if present - extern(D) static const(char)[] getMangleOverride(const AST.Dsymbol sym) + extern(D) static const(char)[] getMangleOverride(const AST.Dsymbol sym) @safe { if (auto decl = sym.isDeclaration()) return decl.mangleOverride; @@ -3090,34 +3089,34 @@ void initialize() } /// Writes `#if <content>` into the supplied buffer -void hashIf(ref OutBuffer buf, string content) +void hashIf(ref OutBuffer buf, string content) @safe { buf.writestring("#if "); buf.writestringln(content); } /// Writes `#elif <content>` into the supplied buffer -void hashElIf(ref OutBuffer buf, string content) +void hashElIf(ref OutBuffer buf, string content) @safe { buf.writestring("#elif "); buf.writestringln(content); } /// Writes `#endif` into the supplied buffer -void hashEndIf(ref OutBuffer buf) +void hashEndIf(ref OutBuffer buf) @safe { buf.writestringln("#endif"); } /// Writes `#define <content>` into the supplied buffer -void hashDefine(ref OutBuffer buf, string content) +void hashDefine(ref OutBuffer buf, string content) @safe { buf.writestring("#define "); buf.writestringln(content); } /// Writes `#include <content>` into the supplied buffer -void hashInclude(ref OutBuffer buf, string content) +void hashInclude(ref OutBuffer buf, string content) @safe { buf.writestring("#include "); buf.writestringln(content); @@ -3232,7 +3231,7 @@ ASTCodegen.Dsymbol outermostSymbol(ASTCodegen.Dsymbol sym) /// Fetches the symbol for user-defined types from the type `t` /// if `t` is either `TypeClass`, `TypeStruct` or `TypeEnum` -ASTCodegen.Dsymbol symbolFromType(ASTCodegen.Type t) +ASTCodegen.Dsymbol symbolFromType(ASTCodegen.Type t) @safe { if (auto tc = t.isTypeClass()) return tc.sym; diff --git a/gcc/d/dmd/dversion.d b/gcc/d/dmd/dversion.d index 259f85c5..0945b54 100644 --- a/gcc/d/dmd/dversion.d +++ b/gcc/d/dmd/dversion.d @@ -35,12 +35,12 @@ extern (C++) final class DebugSymbol : Dsymbol { uint level; - extern (D) this(const ref Loc loc, Identifier ident) + extern (D) this(const ref Loc loc, Identifier ident) @safe { super(loc, ident); } - extern (D) this(const ref Loc loc, uint level) + extern (D) this(const ref Loc loc, uint level) @safe { super(loc, null); this.level = level; @@ -129,12 +129,12 @@ extern (C++) final class VersionSymbol : Dsymbol { uint level; - extern (D) this(const ref Loc loc, Identifier ident) + extern (D) this(const ref Loc loc, Identifier ident) @safe { super(loc, ident); } - extern (D) this(const ref Loc loc, uint level) + extern (D) this(const ref Loc loc, uint level) @safe { super(loc, null); this.level = level; diff --git a/gcc/d/dmd/errors.d b/gcc/d/dmd/errors.d index 1f7a78e..542b97b 100644 --- a/gcc/d/dmd/errors.d +++ b/gcc/d/dmd/errors.d @@ -18,6 +18,16 @@ import dmd.location; nothrow: +/// Constants used to discriminate kinds of error messages. +enum ErrorKind +{ + warning, + deprecation, + error, + tip, + message, +} + /*************************** * Error message sink for D compiler. */ @@ -31,7 +41,7 @@ class ErrorSinkCompiler : ErrorSink { va_list ap; va_start(ap, format); - verror(loc, format, ap); + verrorReport(loc, format, ap, ErrorKind.error); va_end(ap); } @@ -39,7 +49,7 @@ class ErrorSinkCompiler : ErrorSink { va_list ap; va_start(ap, format); - verrorSupplemental(loc, format, ap); + verrorReportSupplemental(loc, format, ap, ErrorKind.error); va_end(ap); } @@ -47,7 +57,15 @@ class ErrorSinkCompiler : ErrorSink { va_list ap; va_start(ap, format); - vwarning(loc, format, ap); + verrorReport(loc, format, ap, ErrorKind.warning); + va_end(ap); + } + + void warningSupplemental(const ref Loc loc, const(char)* format, ...) + { + va_list ap; + va_start(ap, format); + verrorReportSupplemental(loc, format, ap, ErrorKind.warning); va_end(ap); } @@ -55,7 +73,7 @@ class ErrorSinkCompiler : ErrorSink { va_list ap; va_start(ap, format); - vdeprecation(loc, format, ap); + verrorReport(loc, format, ap, ErrorKind.deprecation); va_end(ap); } @@ -63,7 +81,7 @@ class ErrorSinkCompiler : ErrorSink { va_list ap; va_start(ap, format); - vdeprecationSupplemental(loc, format, ap); + verrorReportSupplemental(loc, format, ap, ErrorKind.deprecation); va_end(ap); } @@ -71,7 +89,7 @@ class ErrorSinkCompiler : ErrorSink { va_list ap; va_start(ap, format); - vmessage(loc, format, ap); + verrorReport(loc, format, ap, ErrorKind.message); va_end(ap); } } @@ -160,7 +178,7 @@ static if (__VERSION__ < 2092) { va_list ap; va_start(ap, format); - verror(loc, format, ap); + verrorReport(loc, format, ap, ErrorKind.error); va_end(ap); } else @@ -168,7 +186,7 @@ else { va_list ap; va_start(ap, format); - verror(loc, format, ap); + verrorReport(loc, format, ap, ErrorKind.error); va_end(ap); } @@ -187,7 +205,7 @@ static if (__VERSION__ < 2092) const loc = Loc(filename, linnum, charnum); va_list ap; va_start(ap, format); - verror(loc, format, ap); + verrorReport(loc, format, ap, ErrorKind.error); va_end(ap); } else @@ -196,7 +214,7 @@ else const loc = Loc(filename, linnum, charnum); va_list ap; va_start(ap, format); - verror(loc, format, ap); + verrorReport(loc, format, ap, ErrorKind.error); va_end(ap); } @@ -213,7 +231,7 @@ static if (__VERSION__ < 2092) { va_list ap; va_start(ap, format); - verrorSupplemental(loc, format, ap); + verrorReportSupplemental(loc, format, ap, ErrorKind.error); va_end(ap); } else @@ -221,7 +239,7 @@ else { va_list ap; va_start(ap, format); - verrorSupplemental(loc, format, ap); + verrorReportSupplemental(loc, format, ap, ErrorKind.error); va_end(ap); } @@ -237,7 +255,7 @@ static if (__VERSION__ < 2092) { va_list ap; va_start(ap, format); - vwarning(loc, format, ap); + verrorReport(loc, format, ap, ErrorKind.warning); va_end(ap); } else @@ -245,7 +263,7 @@ else { va_list ap; va_start(ap, format); - vwarning(loc, format, ap); + verrorReport(loc, format, ap, ErrorKind.warning); va_end(ap); } @@ -262,7 +280,7 @@ static if (__VERSION__ < 2092) { va_list ap; va_start(ap, format); - vwarningSupplemental(loc, format, ap); + verrorReportSupplemental(loc, format, ap, ErrorKind.warning); va_end(ap); } else @@ -270,7 +288,7 @@ else { va_list ap; va_start(ap, format); - vwarningSupplemental(loc, format, ap); + verrorReportSupplemental(loc, format, ap, ErrorKind.warning); va_end(ap); } @@ -287,7 +305,7 @@ static if (__VERSION__ < 2092) { va_list ap; va_start(ap, format); - vdeprecation(loc, format, ap); + verrorReport(loc, format, ap, ErrorKind.deprecation); va_end(ap); } else @@ -295,7 +313,7 @@ else { va_list ap; va_start(ap, format); - vdeprecation(loc, format, ap); + verrorReport(loc, format, ap, ErrorKind.deprecation); va_end(ap); } @@ -312,7 +330,7 @@ static if (__VERSION__ < 2092) { va_list ap; va_start(ap, format); - vdeprecationSupplemental(loc, format, ap); + verrorReportSupplemental(loc, format, ap, ErrorKind.deprecation); va_end(ap); } else @@ -320,7 +338,7 @@ else { va_list ap; va_start(ap, format); - vdeprecationSupplemental(loc, format, ap); + verrorReportSupplemental(loc, format, ap, ErrorKind.deprecation); va_end(ap); } @@ -337,7 +355,7 @@ static if (__VERSION__ < 2092) { va_list ap; va_start(ap, format); - vmessage(loc, format, ap); + verrorReport(loc, format, ap, ErrorKind.message); va_end(ap); } else @@ -345,7 +363,7 @@ else { va_list ap; va_start(ap, format); - vmessage(loc, format, ap); + verrorReport(loc, format, ap, ErrorKind.message); va_end(ap); } @@ -360,7 +378,7 @@ static if (__VERSION__ < 2092) { va_list ap; va_start(ap, format); - vmessage(Loc.initial, format, ap); + verrorReport(Loc.initial, format, ap, ErrorKind.message); va_end(ap); } else @@ -368,13 +386,13 @@ else { va_list ap; va_start(ap, format); - vmessage(Loc.initial, format, ap); + verrorReport(Loc.initial, format, ap, ErrorKind.message); va_end(ap); } /** * The type of the diagnostic handler - * see verrorPrint for arguments + * see verrorReport for arguments * Returns: true if error handling is done, false to continue printing to stderr */ alias DiagnosticHandler = bool delegate(const ref Loc location, Color headerColor, const(char)* header, const(char)* messageFormat, va_list args, const(char)* prefix1, const(char)* prefix2); @@ -397,7 +415,7 @@ static if (__VERSION__ < 2092) { va_list ap; va_start(ap, format); - vtip(format, ap); + verrorReport(Loc.initial, format, ap, ErrorKind.tip); va_end(ap); } else @@ -405,104 +423,38 @@ else { va_list ap; va_start(ap, format); - vtip(format, ap); + verrorReport(Loc.initial, format, ap, ErrorKind.tip); va_end(ap); } /** - * Same as $(D error), but takes a va_list parameter, and optionally additional message prefixes. + * Implements $(D error), $(D warning), $(D deprecation), $(D message), and + * $(D tip). Report a diagnostic error, taking a va_list parameter, and + * optionally additional message prefixes. Whether the message gets printed + * depends on runtime values of DiagnosticReporting and global gagging. * Params: - * loc = location of error - * format = printf-style format specification - * ap = printf-style variadic arguments - * p1 = additional message prefix - * p2 = additional message prefix - * header = title of error message + * loc = location of error + * format = printf-style format specification + * ap = printf-style variadic arguments + * kind = kind of error being printed + * p1 = additional message prefix + * p2 = additional message prefix */ -extern (C++) void verror(const ref Loc loc, const(char)* format, va_list ap, const(char)* p1 = null, const(char)* p2 = null, const(char)* header = "Error: "); +extern (C++) void verrorReport(const ref Loc loc, const(char)* format, va_list ap, ErrorKind kind, const(char)* p1 = null, const(char)* p2 = null); /** - * Same as $(D errorSupplemental), but takes a va_list parameter. + * Implements $(D errorSupplemental), $(D warningSupplemental), and + * $(D deprecationSupplemental). Report an addition diagnostic error, taking a + * va_list parameter. Whether the message gets printed depends on runtime + * values of DiagnosticReporting and global gagging. * Params: - * loc = location of error - * format = printf-style format specification - * ap = printf-style variadic arguments - */ -static if (__VERSION__ < 2092) - extern (C++) void verrorSupplemental(const ref Loc loc, const(char)* format, va_list ap); -else - pragma(printf) extern (C++) void verrorSupplemental(const ref Loc loc, const(char)* format, va_list ap); - -/** - * Same as $(D warning), but takes a va_list parameter. - * Params: - * loc = location of warning - * format = printf-style format specification - * ap = printf-style variadic arguments - */ -static if (__VERSION__ < 2092) - extern (C++) void vwarning(const ref Loc loc, const(char)* format, va_list ap); -else - pragma(printf) extern (C++) void vwarning(const ref Loc loc, const(char)* format, va_list ap); - -/** - * Same as $(D warningSupplemental), but takes a va_list parameter. - * Params: - * loc = location of warning - * format = printf-style format specification - * ap = printf-style variadic arguments + * loc = location of error + * format = printf-style format specification + * ap = printf-style variadic arguments + * kind = kind of error being printed */ -static if (__VERSION__ < 2092) - extern (C++) void vwarningSupplemental(const ref Loc loc, const(char)* format, va_list ap); -else - pragma(printf) extern (C++) void vwarningSupplemental(const ref Loc loc, const(char)* format, va_list ap); - -/** - * Same as $(D deprecation), but takes a va_list parameter, and optionally additional message prefixes. - * Params: - * loc = location of deprecation - * format = printf-style format specification - * ap = printf-style variadic arguments - * p1 = additional message prefix - * p2 = additional message prefix - */ -extern (C++) void vdeprecation(const ref Loc loc, const(char)* format, va_list ap, const(char)* p1 = null, const(char)* p2 = null); - -/** - * Same as $(D message), but takes a va_list parameter. - * Params: - * loc = location of message - * format = printf-style format specification - * ap = printf-style variadic arguments - */ -static if (__VERSION__ < 2092) - extern (C++) void vmessage(const ref Loc loc, const(char)* format, va_list ap); -else - pragma(printf) extern (C++) void vmessage(const ref Loc loc, const(char)* format, va_list ap); - -/** - * Same as $(D tip), but takes a va_list parameter. - * Params: - * format = printf-style format specification - * ap = printf-style variadic arguments - */ -static if (__VERSION__ < 2092) - extern (C++) void vtip(const(char)* format, va_list ap); -else - pragma(printf) extern (C++) void vtip(const(char)* format, va_list ap); - -/** - * Same as $(D deprecationSupplemental), but takes a va_list parameter. - * Params: - * loc = location of deprecation - * format = printf-style format specification - * ap = printf-style variadic arguments - */ -static if (__VERSION__ < 2092) - extern (C++) void vdeprecationSupplemental(const ref Loc loc, const(char)* format, va_list ap); -else - pragma(printf) extern (C++) void vdeprecationSupplemental(const ref Loc loc, const(char)* format, va_list ap); +extern (C++) void verrorReportSupplemental(const ref Loc loc, const(char)* format, va_list ap, ErrorKind kind); /** * The type of the fatal error handler @@ -526,4 +478,4 @@ extern (C++) void fatal(); * Try to stop forgetting to remove the breakpoints from * release builds. */ -extern (C++) void halt(); +extern (C++) void halt() @safe; diff --git a/gcc/d/dmd/errors.h b/gcc/d/dmd/errors.h index cc72811..c6b5975 100644 --- a/gcc/d/dmd/errors.h +++ b/gcc/d/dmd/errors.h @@ -14,6 +14,15 @@ struct Loc; +enum class ErrorKind +{ + warning = 0, + deprecation = 1, + error = 2, + tip = 3, + message = 4, +}; + bool isConsoleColorSupported(); #if defined(__GNUC__) @@ -30,17 +39,12 @@ D_ATTRIBUTE_FORMAT(2, 3) void deprecationSupplemental(const Loc& loc, const char D_ATTRIBUTE_FORMAT(2, 3) void error(const Loc& loc, const char *format, ...); D_ATTRIBUTE_FORMAT(4, 5) void error(const char *filename, unsigned linnum, unsigned charnum, const char *format, ...); D_ATTRIBUTE_FORMAT(2, 3) void errorSupplemental(const Loc& loc, const char *format, ...); -D_ATTRIBUTE_FORMAT(2, 0) void verror(const Loc& loc, const char *format, va_list ap, const char *p1 = NULL, const char *p2 = NULL, const char *header = "Error: "); -D_ATTRIBUTE_FORMAT(2, 0) void verrorSupplemental(const Loc& loc, const char *format, va_list ap); -D_ATTRIBUTE_FORMAT(2, 0) void vwarning(const Loc& loc, const char *format, va_list); -D_ATTRIBUTE_FORMAT(2, 0) void vwarningSupplemental(const Loc& loc, const char *format, va_list ap); -D_ATTRIBUTE_FORMAT(2, 0) void vdeprecation(const Loc& loc, const char *format, va_list ap, const char *p1 = NULL, const char *p2 = NULL); -D_ATTRIBUTE_FORMAT(2, 0) void vdeprecationSupplemental(const Loc& loc, const char *format, va_list ap); D_ATTRIBUTE_FORMAT(1, 2) void message(const char *format, ...); D_ATTRIBUTE_FORMAT(2, 3) void message(const Loc& loc, const char *format, ...); -D_ATTRIBUTE_FORMAT(2, 0) void vmessage(const Loc& loc, const char *format, va_list ap); D_ATTRIBUTE_FORMAT(1, 2) void tip(const char *format, ...); -D_ATTRIBUTE_FORMAT(1, 0) void vtip(const char *format, va_list ap); + +D_ATTRIBUTE_FORMAT(2, 0) void verrorReport(const Loc& loc, const char *format, va_list ap, const char *p1 = NULL, const char *p2 = NULL); +D_ATTRIBUTE_FORMAT(2, 0) void verrorReportSupplemental(const Loc& loc, const char* format, va_list ap, ErrorKind kind); #if defined(__GNUC__) || defined(__clang__) #define D_ATTRIBUTE_NORETURN __attribute__((noreturn)) diff --git a/gcc/d/dmd/errorsink.d b/gcc/d/dmd/errorsink.d index e57c2b6..e14829e 100644 --- a/gcc/d/dmd/errorsink.d +++ b/gcc/d/dmd/errorsink.d @@ -27,6 +27,8 @@ abstract class ErrorSink void warning(const ref Loc loc, const(char)* format, ...); + void warningSupplemental(const ref Loc loc, const(char)* format, ...); + void message(const ref Loc loc, const(char)* format, ...); void deprecation(const ref Loc loc, const(char)* format, ...); @@ -49,6 +51,8 @@ class ErrorSinkNull : ErrorSink void warning(const ref Loc loc, const(char)* format, ...) { } + void warningSupplemental(const ref Loc loc, const(char)* format, ...) { } + void message(const ref Loc loc, const(char)* format, ...) { } void deprecation(const ref Loc loc, const(char)* format, ...) { } @@ -104,6 +108,8 @@ class ErrorSinkStderr : ErrorSink va_end(ap); } + void warningSupplemental(const ref Loc loc, const(char)* format, ...) { } + void deprecation(const ref Loc loc, const(char)* format, ...) { fputs("Deprecation: ", stderr); diff --git a/gcc/d/dmd/escape.d b/gcc/d/dmd/escape.d index efd6bea..f817a4e 100644 --- a/gcc/d/dmd/escape.d +++ b/gcc/d/dmd/escape.d @@ -2561,7 +2561,7 @@ private void addMaybe(VarDeclaration va, VarDeclaration v) } // `setUnsafePreview` partially evaluated for dip1000 -private bool setUnsafeDIP1000(Scope* sc, bool gag, Loc loc, const(char)* msg, +bool setUnsafeDIP1000(Scope* sc, bool gag, Loc loc, const(char)* msg, RootObject arg0 = null, RootObject arg1 = null, RootObject arg2 = null) { return setUnsafePreview(sc, global.params.useDIP1000, gag, loc, msg, arg0, arg1, arg2); diff --git a/gcc/d/dmd/expression.d b/gcc/d/dmd/expression.d index 9477867..07cc8d4 100644 --- a/gcc/d/dmd/expression.d +++ b/gcc/d/dmd/expression.d @@ -421,7 +421,7 @@ int expandAliasThisTuples(Expressions* exps, size_t starti = 0) * Returns: * template for that function, otherwise null */ -TemplateDeclaration getFuncTemplateDecl(Dsymbol s) +TemplateDeclaration getFuncTemplateDecl(Dsymbol s) @safe { FuncDeclaration f = s.isFuncDeclaration(); if (f && f.parent) @@ -636,7 +636,7 @@ private: * true if x1 is x2 * else false */ -bool RealIdentical(real_t x1, real_t x2) +bool RealIdentical(real_t x1, real_t x2) @safe { return (CTFloat.isNaN(x1) && CTFloat.isNaN(x2)) || CTFloat.isIdentical(x1, x2); } @@ -648,7 +648,7 @@ bool RealIdentical(real_t x1, real_t x2) * (foo).size * cast(foo).size */ -DotIdExp typeDotIdExp(const ref Loc loc, Type type, Identifier ident) +DotIdExp typeDotIdExp(const ref Loc loc, Type type, Identifier ident) @safe { return new DotIdExp(loc, new TypeExp(loc, type), ident); } @@ -738,7 +738,7 @@ extern (C++) abstract class Expression : ASTNode Loc loc; // file location const EXP op; // to minimize use of dynamic_cast - extern (D) this(const ref Loc loc, EXP op) scope + extern (D) this(const ref Loc loc, EXP op) scope @safe { //printf("Expression::Expression(op = %d) this = %p\n", op, this); this.loc = loc; @@ -825,7 +825,7 @@ extern (C++) abstract class Expression : ASTNode { va_list ap; va_start(ap, format); - .verror(loc, format, ap); + .verrorReport(loc, format, ap, ErrorKind.error); va_end(ap); } } @@ -837,7 +837,7 @@ extern (C++) abstract class Expression : ASTNode va_list ap; va_start(ap, format); - .verrorSupplemental(loc, format, ap); + .verrorReportSupplemental(loc, format, ap, ErrorKind.error); va_end(ap); } @@ -847,7 +847,7 @@ extern (C++) abstract class Expression : ASTNode { va_list ap; va_start(ap, format); - .vwarning(loc, format, ap); + .verrorReport(loc, format, ap, ErrorKind.warning); va_end(ap); } } @@ -858,7 +858,7 @@ extern (C++) abstract class Expression : ASTNode { va_list ap; va_start(ap, format); - .vdeprecation(loc, format, ap); + .verrorReport(loc, format, ap, ErrorKind.deprecation); va_end(ap); } } @@ -871,7 +871,7 @@ extern (C++) abstract class Expression : ASTNode { va_list ap; va_start(ap, format); - .verror(loc, format, ap); + .verrorReport(loc, format, ap, ErrorKind.error); va_end(ap); } } @@ -883,7 +883,7 @@ extern (C++) abstract class Expression : ASTNode va_list ap; va_start(ap, format); - .verrorSupplemental(loc, format, ap); + .verrorReportSupplemental(loc, format, ap, ErrorKind.error); va_end(ap); } @@ -893,7 +893,7 @@ extern (C++) abstract class Expression : ASTNode { va_list ap; va_start(ap, format); - .vwarning(loc, format, ap); + .verrorReport(loc, format, ap, ErrorKind.warning); va_end(ap); } } @@ -904,7 +904,7 @@ extern (C++) abstract class Expression : ASTNode { va_list ap; va_start(ap, format); - .vdeprecation(loc, format, ap); + .verrorReport(loc, format, ap, ErrorKind.deprecation); va_end(ap); } } @@ -913,7 +913,7 @@ extern (C++) abstract class Expression : ASTNode /********************************** * Combine e1 and e2 by CommaExp if both are not NULL. */ - extern (D) static Expression combine(Expression e1, Expression e2) + extern (D) static Expression combine(Expression e1, Expression e2) @safe { if (e1) { @@ -928,12 +928,12 @@ extern (C++) abstract class Expression : ASTNode return e1; } - extern (D) static Expression combine(Expression e1, Expression e2, Expression e3) + extern (D) static Expression combine(Expression e1, Expression e2, Expression e3) @safe { return combine(combine(e1, e2), e3); } - extern (D) static Expression combine(Expression e1, Expression e2, Expression e3, Expression e4) + extern (D) static Expression combine(Expression e1, Expression e2, Expression e3, Expression e4) @safe { return combine(combine(e1, e2), combine(e3, e4)); } @@ -944,7 +944,7 @@ extern (C++) abstract class Expression : ASTNode * is returned via e0. * Otherwise 'e' is directly returned and e0 is set to NULL. */ - extern (D) static Expression extractLast(Expression e, out Expression e0) + extern (D) static Expression extractLast(Expression e, out Expression e0) @safe { if (e.op != EXP.comma) { @@ -1485,6 +1485,7 @@ extern (C++) abstract class Expression : ASTNode else { sc.varDecl.storage_class |= STC.system; + sc.varDecl.systemInferred = true; } } return false; @@ -1620,7 +1621,9 @@ extern (C++) abstract class Expression : ASTNode { //printf("checkRightThis sc.intypeof = %d, ad = %p, func = %p, fdthis = %p\n", // sc.intypeof, sc.getStructClassScope(), func, fdthis); - error("need `this` for `%s` of type `%s`", ve.var.toChars(), ve.var.type.toChars()); + auto t = ve.var.isThis(); + assert(t); + error("accessing non-static variable `%s` requires an instance of `%s`", ve.var.toChars(), t.toChars()); return true; } } @@ -2157,7 +2160,7 @@ extern (C++) final class VoidInitExp : Expression VarDeclaration var; /// the variable from where the void value came from, null if not known /// Useful for error messages - extern (D) this(VarDeclaration var) + extern (D) this(VarDeclaration var) @safe { super(var.loc, EXP.void_); this.var = var; @@ -2183,7 +2186,7 @@ extern (C++) final class RealExp : Expression { real_t value; - extern (D) this(const ref Loc loc, real_t value, Type type) + extern (D) this(const ref Loc loc, real_t value, Type type) @safe { super(loc, EXP.float64); //printf("RealExp::RealExp(%Lg)\n", value); @@ -2191,7 +2194,7 @@ extern (C++) final class RealExp : Expression this.type = type; } - static RealExp create(const ref Loc loc, real_t value, Type type) + static RealExp create(const ref Loc loc, real_t value, Type type) @safe { return new RealExp(loc, value, type); } @@ -2266,7 +2269,7 @@ extern (C++) final class ComplexExp : Expression { complex_t value; - extern (D) this(const ref Loc loc, complex_t value, Type type) + extern (D) this(const ref Loc loc, complex_t value, Type type) @safe { super(loc, EXP.complex80); this.value = value; @@ -2274,7 +2277,7 @@ extern (C++) final class ComplexExp : Expression //printf("ComplexExp::ComplexExp(%s)\n", toChars()); } - static ComplexExp create(const ref Loc loc, complex_t value, Type type) + static ComplexExp create(const ref Loc loc, complex_t value, Type type) @safe { return new ComplexExp(loc, value, type); } @@ -2358,13 +2361,13 @@ extern (C++) class IdentifierExp : Expression Identifier ident; bool parens; // if it appears as (identifier) - extern (D) this(const ref Loc loc, Identifier ident) scope + extern (D) this(const ref Loc loc, Identifier ident) scope @safe { super(loc, EXP.identifier); this.ident = ident; } - static IdentifierExp create(const ref Loc loc, Identifier ident) + static IdentifierExp create(const ref Loc loc, Identifier ident) @safe { return new IdentifierExp(loc, ident); } @@ -2411,7 +2414,7 @@ extern (C++) final class DsymbolExp : Expression Dsymbol s; bool hasOverloads; - extern (D) this(const ref Loc loc, Dsymbol s, bool hasOverloads = true) + extern (D) this(const ref Loc loc, Dsymbol s, bool hasOverloads = true) @safe { super(loc, EXP.dSymbol); this.s = s; @@ -2441,13 +2444,13 @@ extern (C++) class ThisExp : Expression { VarDeclaration var; - extern (D) this(const ref Loc loc) + extern (D) this(const ref Loc loc) @safe { super(loc, EXP.this_); //printf("ThisExp::ThisExp() loc = %d\n", loc.linnum); } - this(const ref Loc loc, const EXP tok) + this(const ref Loc loc, const EXP tok) @safe { super(loc, tok); //printf("ThisExp::ThisExp() loc = %d\n", loc.linnum); @@ -2489,7 +2492,7 @@ extern (C++) class ThisExp : Expression */ extern (C++) final class SuperExp : ThisExp { - extern (D) this(const ref Loc loc) + extern (D) this(const ref Loc loc) @safe { super(loc, EXP.super_); } @@ -2519,7 +2522,7 @@ extern (C++) final class SuperExp : ThisExp */ extern (C++) final class NullExp : Expression { - extern (D) this(const ref Loc loc, Type type = null) scope + extern (D) this(const ref Loc loc, Type type = null) scope @safe { super(loc, EXP.null_); this.type = type; @@ -2983,7 +2986,7 @@ extern (C++) final class TupleExp : Expression Expressions* exps; - extern (D) this(const ref Loc loc, Expression e0, Expressions* exps) + extern (D) this(const ref Loc loc, Expression e0, Expressions* exps) @safe { super(loc, EXP.tuple); //printf("TupleExp(this = %p)\n", this); @@ -2991,7 +2994,7 @@ extern (C++) final class TupleExp : Expression this.exps = exps; } - extern (D) this(const ref Loc loc, Expressions* exps) + extern (D) this(const ref Loc loc, Expressions* exps) @safe { super(loc, EXP.tuple); //printf("TupleExp(this = %p)\n", this); @@ -3032,7 +3035,7 @@ extern (C++) final class TupleExp : Expression } } - static TupleExp create(const ref Loc loc, Expressions* exps) + static TupleExp create(const ref Loc loc, Expressions* exps) @safe { return new TupleExp(loc, exps); } @@ -3088,7 +3091,7 @@ extern (C++) final class ArrayLiteralExp : Expression Expressions* elements; - extern (D) this(const ref Loc loc, Type type, Expressions* elements) + extern (D) this(const ref Loc loc, Type type, Expressions* elements) @safe { super(loc, EXP.arrayLiteral); this.type = type; @@ -3103,7 +3106,7 @@ extern (C++) final class ArrayLiteralExp : Expression elements.push(e); } - extern (D) this(const ref Loc loc, Type type, Expression basis, Expressions* elements) + extern (D) this(const ref Loc loc, Type type, Expression basis, Expressions* elements) @safe { super(loc, EXP.arrayLiteral); this.type = type; @@ -3111,7 +3114,7 @@ extern (C++) final class ArrayLiteralExp : Expression this.elements = elements; } - static ArrayLiteralExp create(const ref Loc loc, Expressions* elements) + static ArrayLiteralExp create(const ref Loc loc, Expressions* elements) @safe { return new ArrayLiteralExp(loc, null, elements); } @@ -3248,7 +3251,7 @@ extern (C++) final class AssocArrayLiteralExp : Expression Expressions* keys; Expressions* values; - extern (D) this(const ref Loc loc, Expressions* keys, Expressions* values) + extern (D) this(const ref Loc loc, Expressions* keys, Expressions* values) @safe { super(loc, EXP.assocArrayLiteral); assert(keys.length == values.length); @@ -3347,7 +3350,7 @@ extern (C++) final class StructLiteralExp : Expression bool isOriginal = false; /// used when moving instances to indicate `this is this.origin` OwnedBy ownedByCtfe = OwnedBy.code; - extern (D) this(const ref Loc loc, StructDeclaration sd, Expressions* elements, Type stype = null) + extern (D) this(const ref Loc loc, StructDeclaration sd, Expressions* elements, Type stype = null) @safe { super(loc, EXP.structLiteral); this.sd = sd; @@ -3526,7 +3529,7 @@ extern (C++) final class CompoundLiteralExp : Expression { Initializer initializer; /// initializer-list - extern (D) this(const ref Loc loc, Type type_name, Initializer initializer) + extern (D) this(const ref Loc loc, Type type_name, Initializer initializer) @safe { super(loc, EXP.compoundLiteral); super.type = type_name; @@ -3547,7 +3550,7 @@ extern (C++) final class TypeExp : Expression { bool parens; // if this is a parenthesized expression - extern (D) this(const ref Loc loc, Type type) + extern (D) this(const ref Loc loc, Type type) @safe { super(loc, EXP.type); //printf("TypeExp::TypeExp(%s)\n", type.toChars()); @@ -3589,7 +3592,7 @@ extern (C++) final class ScopeExp : Expression { ScopeDsymbol sds; - extern (D) this(const ref Loc loc, ScopeDsymbol sds) + extern (D) this(const ref Loc loc, ScopeDsymbol sds) @safe { super(loc, EXP.scope_); //printf("ScopeExp::ScopeExp(sds = '%s')\n", sds.toChars()); @@ -3644,7 +3647,7 @@ extern (C++) final class TemplateExp : Expression TemplateDeclaration td; FuncDeclaration fd; - extern (D) this(const ref Loc loc, TemplateDeclaration td, FuncDeclaration fd = null) + extern (D) this(const ref Loc loc, TemplateDeclaration td, FuncDeclaration fd = null) @safe { super(loc, EXP.template_); //printf("TemplateExp(): %s\n", td.toChars()); @@ -3705,7 +3708,7 @@ extern (C++) final class NewExp : Expression /// The fields are still separate for backwards compatibility extern (D) ArgumentList argumentList() { return ArgumentList(arguments, names); } - extern (D) this(const ref Loc loc, Expression thisexp, Type newtype, Expressions* arguments, Identifiers* names = null) + extern (D) this(const ref Loc loc, Expression thisexp, Type newtype, Expressions* arguments, Identifiers* names = null) @safe { super(loc, EXP.new_); this.thisexp = thisexp; @@ -3714,7 +3717,7 @@ extern (C++) final class NewExp : Expression this.names = names; } - static NewExp create(const ref Loc loc, Expression thisexp, Type newtype, Expressions* arguments) + static NewExp create(const ref Loc loc, Expression thisexp, Type newtype, Expressions* arguments) @safe { return new NewExp(loc, thisexp, newtype, arguments); } @@ -3743,7 +3746,7 @@ extern (C++) final class NewAnonClassExp : Expression ClassDeclaration cd; // class being instantiated Expressions* arguments; // Array of Expression's to call class constructor - extern (D) this(const ref Loc loc, Expression thisexp, ClassDeclaration cd, Expressions* arguments) + extern (D) this(const ref Loc loc, Expression thisexp, ClassDeclaration cd, Expressions* arguments) @safe { super(loc, EXP.newAnonymousClass); this.thisexp = thisexp; @@ -3770,7 +3773,7 @@ extern (C++) class SymbolExp : Expression Dsymbol originalScope; // original scope before inlining bool hasOverloads; - extern (D) this(const ref Loc loc, EXP op, Declaration var, bool hasOverloads) + extern (D) this(const ref Loc loc, EXP op, Declaration var, bool hasOverloads) @safe { super(loc, op); assert(var); @@ -3798,7 +3801,11 @@ extern (C++) final class SymOffExp : SymbolExp // FIXME: This error report will never be handled anyone. // It should be done before the SymOffExp construction. if (v.needThis()) - .error(loc, "need `this` for address of `%s`", v.toChars()); + { + auto t = v.isThis(); + assert(t); + .error(loc, "taking the address of non-static variable `%s` requires an instance of `%s`", v.toChars(), t.toChars()); + } hasOverloads = false; } super(loc, EXP.symbolOffset, var, hasOverloads); @@ -3822,7 +3829,7 @@ extern (C++) final class SymOffExp : SymbolExp extern (C++) final class VarExp : SymbolExp { bool delegateWasExtracted; - extern (D) this(const ref Loc loc, Declaration var, bool hasOverloads = true) + extern (D) this(const ref Loc loc, Declaration var, bool hasOverloads = true) @safe { if (var.isVarDeclaration()) hasOverloads = false; @@ -3833,7 +3840,7 @@ extern (C++) final class VarExp : SymbolExp this.type = var.type; } - static VarExp create(const ref Loc loc, Declaration var, bool hasOverloads = true) + static VarExp create(const ref Loc loc, Declaration var, bool hasOverloads = true) @safe { return new VarExp(loc, var, hasOverloads); } @@ -4242,7 +4249,7 @@ extern (C++) final class DeclarationExp : Expression { Dsymbol declaration; - extern (D) this(const ref Loc loc, Dsymbol declaration) + extern (D) this(const ref Loc loc, Dsymbol declaration) @safe { super(loc, EXP.declaration); this.declaration = declaration; @@ -4275,7 +4282,7 @@ extern (C++) final class TypeidExp : Expression { RootObject obj; - extern (D) this(const ref Loc loc, RootObject o) + extern (D) this(const ref Loc loc, RootObject o) @safe { super(loc, EXP.typeid_); this.obj = o; @@ -4300,7 +4307,7 @@ extern (C++) final class TraitsExp : Expression Identifier ident; Objects* args; - extern (D) this(const ref Loc loc, Identifier ident, Objects* args) + extern (D) this(const ref Loc loc, Identifier ident, Objects* args) @safe { super(loc, EXP.traits); this.ident = ident; @@ -4325,7 +4332,7 @@ extern (C++) final class TraitsExp : Expression */ extern (C++) final class HaltExp : Expression { - extern (D) this(const ref Loc loc) + extern (D) this(const ref Loc loc) @safe { super(loc, EXP.halt); } @@ -4349,7 +4356,7 @@ extern (C++) final class IsExp : Expression TOK tok; // ':' or '==' TOK tok2; // 'struct', 'union', etc. - extern (D) this(const ref Loc loc, Type targ, Identifier id, TOK tok, Type tspec, TOK tok2, TemplateParameters* parameters) scope + extern (D) this(const ref Loc loc, Type targ, Identifier id, TOK tok, Type tspec, TOK tok2, TemplateParameters* parameters) scope @safe { super(loc, EXP.is_); this.targ = targ; @@ -4388,7 +4395,7 @@ extern (C++) abstract class UnaExp : Expression { Expression e1; - extern (D) this(const ref Loc loc, EXP op, Expression e1) scope + extern (D) this(const ref Loc loc, EXP op, Expression e1) scope @safe { super(loc, op); this.e1 = e1; @@ -4461,7 +4468,7 @@ extern (C++) abstract class BinExp : Expression Type att1; // Save alias this type to detect recursion Type att2; // Save alias this type to detect recursion - extern (D) this(const ref Loc loc, EXP op, Expression e1, Expression e2) scope + extern (D) this(const ref Loc loc, EXP op, Expression e1, Expression e2) scope @safe { super(loc, op); this.e1 = e1; @@ -4752,7 +4759,7 @@ extern (C++) abstract class BinExp : Expression */ extern (C++) class BinAssignExp : BinExp { - extern (D) this(const ref Loc loc, EXP op, Expression e1, Expression e2) scope + extern (D) this(const ref Loc loc, EXP op, Expression e1, Expression e2) scope @safe { super(loc, op, e1, e2); } @@ -4789,7 +4796,7 @@ extern (C++) final class MixinExp : Expression { Expressions* exps; - extern (D) this(const ref Loc loc, Expressions* exps) + extern (D) this(const ref Loc loc, Expressions* exps) @safe { super(loc, EXP.mixin_); this.exps = exps; @@ -4837,7 +4844,7 @@ extern (C++) final class MixinExp : Expression */ extern (C++) final class ImportExp : UnaExp { - extern (D) this(const ref Loc loc, Expression e) + extern (D) this(const ref Loc loc, Expression e) @safe { super(loc, EXP.import_, e); } @@ -4857,7 +4864,7 @@ extern (C++) final class AssertExp : UnaExp { Expression msg; - extern (D) this(const ref Loc loc, Expression e, Expression msg = null) + extern (D) this(const ref Loc loc, Expression e, Expression msg = null) @safe { super(loc, EXP.assert_, e); this.msg = msg; @@ -4908,13 +4915,13 @@ extern (C++) final class DotIdExp : UnaExp bool wantsym; // do not replace Symbol with its initializer during semantic() bool arrow; // ImportC: if -> instead of . - extern (D) this(const ref Loc loc, Expression e, Identifier ident) + extern (D) this(const ref Loc loc, Expression e, Identifier ident) @safe { super(loc, EXP.dotIdentifier, e); this.ident = ident; } - static DotIdExp create(const ref Loc loc, Expression e, Identifier ident) + static DotIdExp create(const ref Loc loc, Expression e, Identifier ident) @safe { return new DotIdExp(loc, e, ident); } @@ -4932,7 +4939,7 @@ extern (C++) final class DotTemplateExp : UnaExp { TemplateDeclaration td; - extern (D) this(const ref Loc loc, Expression e, TemplateDeclaration td) + extern (D) this(const ref Loc loc, Expression e, TemplateDeclaration td) @safe { super(loc, EXP.dotTemplateDeclaration, e); this.td = td; @@ -4963,7 +4970,7 @@ extern (C++) final class DotVarExp : UnaExp Declaration var; bool hasOverloads; - extern (D) this(const ref Loc loc, Expression e, Declaration var, bool hasOverloads = true) + extern (D) this(const ref Loc loc, Expression e, Declaration var, bool hasOverloads = true) @safe { if (var.isVarDeclaration()) hasOverloads = false; @@ -5054,7 +5061,7 @@ extern (C++) final class DotTemplateInstanceExp : UnaExp this.ti = new TemplateInstance(loc, name, tiargs); } - extern (D) this(const ref Loc loc, Expression e, TemplateInstance ti) + extern (D) this(const ref Loc loc, Expression e, TemplateInstance ti) @safe { super(loc, EXP.dotTemplateInstance, e); this.ti = ti; @@ -5147,7 +5154,7 @@ extern (C++) final class DelegateExp : UnaExp bool hasOverloads; VarDeclaration vthis2; // container for multi-context - extern (D) this(const ref Loc loc, Expression e, FuncDeclaration f, bool hasOverloads = true, VarDeclaration vthis2 = null) + extern (D) this(const ref Loc loc, Expression e, FuncDeclaration f, bool hasOverloads = true, VarDeclaration vthis2 = null) @safe { super(loc, EXP.delegate_, e); this.func = f; @@ -5167,7 +5174,7 @@ extern (C++) final class DotTypeExp : UnaExp { Dsymbol sym; // symbol that represents a type - extern (D) this(const ref Loc loc, Expression e, Dsymbol s) + extern (D) this(const ref Loc loc, Expression e, Dsymbol s) @safe { super(loc, EXP.dotType, e); this.sym = s; @@ -5222,14 +5229,14 @@ extern (C++) final class CallExp : UnaExp /// The fields are still separate for backwards compatibility extern (D) ArgumentList argumentList() { return ArgumentList(arguments, names); } - extern (D) this(const ref Loc loc, Expression e, Expressions* exps, Identifiers* names = null) + extern (D) this(const ref Loc loc, Expression e, Expressions* exps, Identifiers* names = null) @safe { super(loc, EXP.call, e); this.arguments = exps; this.names = names; } - extern (D) this(const ref Loc loc, Expression e) + extern (D) this(const ref Loc loc, Expression e) @safe { super(loc, EXP.call, e); } @@ -5264,12 +5271,12 @@ extern (C++) final class CallExp : UnaExp this.f = fd; } - static CallExp create(const ref Loc loc, Expression e, Expressions* exps) + static CallExp create(const ref Loc loc, Expression e, Expressions* exps) @safe { return new CallExp(loc, e, exps); } - static CallExp create(const ref Loc loc, Expression e) + static CallExp create(const ref Loc loc, Expression e) @safe { return new CallExp(loc, e); } @@ -5377,7 +5384,7 @@ TypeFunction calledFunctionType(CallExp ce) return null; } -FuncDeclaration isFuncAddress(Expression e, bool* hasOverloads = null) +FuncDeclaration isFuncAddress(Expression e, bool* hasOverloads = null) @safe { if (auto ae = e.isAddrExp()) { @@ -5418,12 +5425,12 @@ FuncDeclaration isFuncAddress(Expression e, bool* hasOverloads = null) */ extern (C++) final class AddrExp : UnaExp { - extern (D) this(const ref Loc loc, Expression e) + extern (D) this(const ref Loc loc, Expression e) @safe { super(loc, EXP.address, e); } - extern (D) this(const ref Loc loc, Expression e, Type t) + extern (D) this(const ref Loc loc, Expression e, Type t) @safe { this(loc, e); type = t; @@ -5440,14 +5447,14 @@ extern (C++) final class AddrExp : UnaExp */ extern (C++) final class PtrExp : UnaExp { - extern (D) this(const ref Loc loc, Expression e) + extern (D) this(const ref Loc loc, Expression e) @safe { super(loc, EXP.star, e); //if (e.type) // type = ((TypePointer *)e.type).next; } - extern (D) this(const ref Loc loc, Expression e, Type t) + extern (D) this(const ref Loc loc, Expression e, Type t) @safe { super(loc, EXP.star, e); type = t; @@ -5493,7 +5500,7 @@ extern (C++) final class PtrExp : UnaExp */ extern (C++) final class NegExp : UnaExp { - extern (D) this(const ref Loc loc, Expression e) + extern (D) this(const ref Loc loc, Expression e) @safe { super(loc, EXP.negate, e); } @@ -5509,7 +5516,7 @@ extern (C++) final class NegExp : UnaExp */ extern (C++) final class UAddExp : UnaExp { - extern (D) this(const ref Loc loc, Expression e) scope + extern (D) this(const ref Loc loc, Expression e) scope @safe { super(loc, EXP.uadd, e); } @@ -5525,7 +5532,7 @@ extern (C++) final class UAddExp : UnaExp */ extern (C++) final class ComExp : UnaExp { - extern (D) this(const ref Loc loc, Expression e) + extern (D) this(const ref Loc loc, Expression e) @safe { super(loc, EXP.tilde, e); } @@ -5541,7 +5548,7 @@ extern (C++) final class ComExp : UnaExp */ extern (C++) final class NotExp : UnaExp { - extern (D) this(const ref Loc loc, Expression e) + extern (D) this(const ref Loc loc, Expression e) @safe { super(loc, EXP.not, e); } @@ -5561,7 +5568,7 @@ extern (C++) final class DeleteExp : UnaExp { bool isRAII; // true if called automatically as a result of scoped destruction - extern (D) this(const ref Loc loc, Expression e, bool isRAII) + extern (D) this(const ref Loc loc, Expression e, bool isRAII) @safe { super(loc, EXP.delete_, e); this.isRAII = isRAII; @@ -5585,7 +5592,7 @@ extern (C++) final class CastExp : UnaExp Type to; // type to cast to ubyte mod = cast(ubyte)~0; // MODxxxxx - extern (D) this(const ref Loc loc, Expression e, Type t) + extern (D) this(const ref Loc loc, Expression e, Type t) @safe { super(loc, EXP.cast_, e); this.to = t; @@ -5593,7 +5600,7 @@ extern (C++) final class CastExp : UnaExp /* For cast(const) and cast(immutable) */ - extern (D) this(const ref Loc loc, Expression e, ubyte mod) + extern (D) this(const ref Loc loc, Expression e, ubyte mod) @safe { super(loc, EXP.cast_, e); this.mod = mod; @@ -5647,14 +5654,14 @@ extern (C++) final class VectorExp : UnaExp uint dim = ~0; // number of elements in the vector OwnedBy ownedByCtfe = OwnedBy.code; - extern (D) this(const ref Loc loc, Expression e, Type t) + extern (D) this(const ref Loc loc, Expression e, Type t) @safe { super(loc, EXP.vector, e); assert(t.ty == Tvector); to = cast(TypeVector)t; } - static VectorExp create(const ref Loc loc, Expression e, Type t) + static VectorExp create(const ref Loc loc, Expression e, Type t) @safe { return new VectorExp(loc, e, t); } @@ -5683,7 +5690,7 @@ extern (C++) final class VectorExp : UnaExp */ extern (C++) final class VectorArrayExp : UnaExp { - extern (D) this(const ref Loc loc, Expression e1) + extern (D) this(const ref Loc loc, Expression e1) @safe { super(loc, EXP.vectorArray, e1); } @@ -5727,14 +5734,14 @@ extern (C++) final class SliceExp : UnaExp mixin(generateBitFields!(BitFields, ubyte)); /************************************************************/ - extern (D) this(const ref Loc loc, Expression e1, IntervalExp ie) + extern (D) this(const ref Loc loc, Expression e1, IntervalExp ie) @safe { super(loc, EXP.slice, e1); this.upr = ie ? ie.upr : null; this.lwr = ie ? ie.lwr : null; } - extern (D) this(const ref Loc loc, Expression e1, Expression lwr, Expression upr) + extern (D) this(const ref Loc loc, Expression e1, Expression lwr, Expression upr) @safe { super(loc, EXP.slice, e1); this.upr = upr; @@ -5784,7 +5791,7 @@ extern (C++) final class SliceExp : UnaExp */ extern (C++) final class ArrayLengthExp : UnaExp { - extern (D) this(const ref Loc loc, Expression e1) + extern (D) this(const ref Loc loc, Expression e1) @safe { super(loc, EXP.arrayLength, e1); } @@ -5815,7 +5822,7 @@ extern (C++) final class ArrayExp : UnaExp arguments.push(index); } - extern (D) this(const ref Loc loc, Expression e1, Expressions* args) + extern (D) this(const ref Loc loc, Expression e1, Expressions* args) @safe { super(loc, EXP.array, e1); arguments = args; @@ -5852,7 +5859,7 @@ extern (C++) final class ArrayExp : UnaExp */ extern (C++) final class DotExp : BinExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.dot, e1, e2); } @@ -5878,7 +5885,7 @@ extern (C++) final class CommaExp : BinExp bool allowCommaExp; - extern (D) this(const ref Loc loc, Expression e1, Expression e2, bool generated = true) + extern (D) this(const ref Loc loc, Expression e1, Expression e2, bool generated = true) @safe { super(loc, EXP.comma, e1, e2); allowCommaExp = isGenerated = generated; @@ -5931,7 +5938,7 @@ extern (C++) final class CommaExp : BinExp * exp = An expression that discards its result. * If the argument is null or not a CommaExp, nothing happens. */ - static void allow(Expression exp) + static void allow(Expression exp) @safe { if (exp) if (auto ce = exp.isCommaExp()) @@ -5947,7 +5954,7 @@ extern (C++) final class IntervalExp : Expression Expression lwr; Expression upr; - extern (D) this(const ref Loc loc, Expression lwr, Expression upr) + extern (D) this(const ref Loc loc, Expression lwr, Expression upr) @safe { super(loc, EXP.interval); this.lwr = lwr; @@ -5972,7 +5979,7 @@ extern (C++) final class IntervalExp : Expression */ extern (C++) final class DelegatePtrExp : UnaExp { - extern (D) this(const ref Loc loc, Expression e1) + extern (D) this(const ref Loc loc, Expression e1) @safe { super(loc, EXP.delegatePointer, e1); } @@ -6010,7 +6017,7 @@ extern (C++) final class DelegatePtrExp : UnaExp */ extern (C++) final class DelegateFuncptrExp : UnaExp { - extern (D) this(const ref Loc loc, Expression e1) + extern (D) this(const ref Loc loc, Expression e1) @safe { super(loc, EXP.delegateFunctionPointer, e1); } @@ -6050,13 +6057,13 @@ extern (C++) final class IndexExp : BinExp bool modifiable = false; // assume it is an rvalue bool indexIsInBounds; // true if 0 <= e2 && e2 <= e1.length - 1 - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.index, e1, e2); //printf("IndexExp::IndexExp('%s')\n", toChars()); } - extern (D) this(const ref Loc loc, Expression e1, Expression e2, bool indexIsInBounds) + extern (D) this(const ref Loc loc, Expression e1, Expression e2, bool indexIsInBounds) @safe { super(loc, EXP.index, e1, e2); this.indexIsInBounds = indexIsInBounds; @@ -6150,7 +6157,7 @@ extern (C++) final class PostExp : BinExp */ extern (C++) final class PreExp : UnaExp { - extern (D) this(EXP op, const ref Loc loc, Expression e) + extern (D) this(EXP op, const ref Loc loc, Expression e) @safe { super(loc, op, e); assert(op == EXP.preMinusMinus || op == EXP.prePlusPlus); @@ -6180,12 +6187,12 @@ extern (C++) class AssignExp : BinExp /************************************************************/ /* op can be EXP.assign, EXP.construct, or EXP.blit */ - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.assign, e1, e2); } - this(const ref Loc loc, EXP tok, Expression e1, Expression e2) + this(const ref Loc loc, EXP tok, Expression e1, Expression e2) @safe { super(loc, tok, e1, e2); } @@ -6231,7 +6238,7 @@ extern (C++) class AssignExp : BinExp extern (C++) final class LoweredAssignExp : AssignExp { Expression lowering; - extern (D) this(AssignExp exp, Expression lowering) + extern (D) this(AssignExp exp, Expression lowering) @safe { super(exp.loc, EXP.loweredAssignExp, exp.e1, exp.e2); this.lowering = lowering; @@ -6251,14 +6258,14 @@ extern (C++) final class LoweredAssignExp : AssignExp */ extern (C++) final class ConstructExp : AssignExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.construct, e1, e2); } // Internal use only. If `v` is a reference variable, the assignment // will become a reference initialization automatically. - extern (D) this(const ref Loc loc, VarDeclaration v, Expression e2) + extern (D) this(const ref Loc loc, VarDeclaration v, Expression e2) @safe { auto ve = new VarExp(loc, v); assert(v.type && ve.type); @@ -6280,14 +6287,14 @@ extern (C++) final class ConstructExp : AssignExp */ extern (C++) final class BlitExp : AssignExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.blit, e1, e2); } // Internal use only. If `v` is a reference variable, the assinment // will become a reference rebinding automatically. - extern (D) this(const ref Loc loc, VarDeclaration v, Expression e2) + extern (D) this(const ref Loc loc, VarDeclaration v, Expression e2) @safe { auto ve = new VarExp(loc, v); assert(v.type && ve.type); @@ -6309,7 +6316,7 @@ extern (C++) final class BlitExp : AssignExp */ extern (C++) final class AddAssignExp : BinAssignExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.addAssign, e1, e2); } @@ -6325,7 +6332,7 @@ extern (C++) final class AddAssignExp : BinAssignExp */ extern (C++) final class MinAssignExp : BinAssignExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.minAssign, e1, e2); } @@ -6341,7 +6348,7 @@ extern (C++) final class MinAssignExp : BinAssignExp */ extern (C++) final class MulAssignExp : BinAssignExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.mulAssign, e1, e2); } @@ -6357,7 +6364,7 @@ extern (C++) final class MulAssignExp : BinAssignExp */ extern (C++) final class DivAssignExp : BinAssignExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.divAssign, e1, e2); } @@ -6373,7 +6380,7 @@ extern (C++) final class DivAssignExp : BinAssignExp */ extern (C++) final class ModAssignExp : BinAssignExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.modAssign, e1, e2); } @@ -6389,7 +6396,7 @@ extern (C++) final class ModAssignExp : BinAssignExp */ extern (C++) final class AndAssignExp : BinAssignExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.andAssign, e1, e2); } @@ -6405,7 +6412,7 @@ extern (C++) final class AndAssignExp : BinAssignExp */ extern (C++) final class OrAssignExp : BinAssignExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.orAssign, e1, e2); } @@ -6421,7 +6428,7 @@ extern (C++) final class OrAssignExp : BinAssignExp */ extern (C++) final class XorAssignExp : BinAssignExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.xorAssign, e1, e2); } @@ -6437,7 +6444,7 @@ extern (C++) final class XorAssignExp : BinAssignExp */ extern (C++) final class PowAssignExp : BinAssignExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.powAssign, e1, e2); } @@ -6453,7 +6460,7 @@ extern (C++) final class PowAssignExp : BinAssignExp */ extern (C++) final class ShlAssignExp : BinAssignExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.leftShiftAssign, e1, e2); } @@ -6469,7 +6476,7 @@ extern (C++) final class ShlAssignExp : BinAssignExp */ extern (C++) final class ShrAssignExp : BinAssignExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.rightShiftAssign, e1, e2); } @@ -6485,7 +6492,7 @@ extern (C++) final class ShrAssignExp : BinAssignExp */ extern (C++) final class UshrAssignExp : BinAssignExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.unsignedRightShiftAssign, e1, e2); } @@ -6510,12 +6517,12 @@ extern (C++) final class UshrAssignExp : BinAssignExp */ extern (C++) class CatAssignExp : BinAssignExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.concatenateAssign, e1, e2); } - extern (D) this(const ref Loc loc, EXP tok, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, EXP tok, Expression e1, Expression e2) @safe { super(loc, tok, e1, e2); } @@ -6531,7 +6538,7 @@ extern (C++) class CatAssignExp : BinAssignExp */ extern (C++) final class CatElemAssignExp : CatAssignExp { - extern (D) this(const ref Loc loc, Type type, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Type type, Expression e1, Expression e2) @safe { super(loc, EXP.concatenateElemAssign, e1, e2); this.type = type; @@ -6548,7 +6555,7 @@ extern (C++) final class CatElemAssignExp : CatAssignExp */ extern (C++) final class CatDcharAssignExp : CatAssignExp { - extern (D) this(const ref Loc loc, Type type, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Type type, Expression e1, Expression e2) @safe { super(loc, EXP.concatenateDcharAssign, e1, e2); this.type = type; @@ -6567,7 +6574,7 @@ extern (C++) final class CatDcharAssignExp : CatAssignExp */ extern (C++) final class AddExp : BinExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.add, e1, e2); } @@ -6585,7 +6592,7 @@ extern (C++) final class AddExp : BinExp */ extern (C++) final class MinExp : BinExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.min, e1, e2); } @@ -6605,7 +6612,7 @@ extern (C++) final class CatExp : BinExp { Expression lowering; // call to druntime hook `_d_arraycatnTX` - extern (D) this(const ref Loc loc, Expression e1, Expression e2) scope + extern (D) this(const ref Loc loc, Expression e1, Expression e2) scope @safe { super(loc, EXP.concatenate, e1, e2); } @@ -6630,7 +6637,7 @@ extern (C++) final class CatExp : BinExp */ extern (C++) final class MulExp : BinExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.mul, e1, e2); } @@ -6648,7 +6655,7 @@ extern (C++) final class MulExp : BinExp */ extern (C++) final class DivExp : BinExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.div, e1, e2); } @@ -6666,7 +6673,7 @@ extern (C++) final class DivExp : BinExp */ extern (C++) final class ModExp : BinExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.mod, e1, e2); } @@ -6684,7 +6691,7 @@ extern (C++) final class ModExp : BinExp */ extern (C++) final class PowExp : BinExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.pow, e1, e2); } @@ -6702,7 +6709,7 @@ extern (C++) final class PowExp : BinExp */ extern (C++) final class ShlExp : BinExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.leftShift, e1, e2); } @@ -6720,7 +6727,7 @@ extern (C++) final class ShlExp : BinExp */ extern (C++) final class ShrExp : BinExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.rightShift, e1, e2); } @@ -6738,7 +6745,7 @@ extern (C++) final class ShrExp : BinExp */ extern (C++) final class UshrExp : BinExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.unsignedRightShift, e1, e2); } @@ -6756,7 +6763,7 @@ extern (C++) final class UshrExp : BinExp */ extern (C++) final class AndExp : BinExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.and, e1, e2); } @@ -6774,7 +6781,7 @@ extern (C++) final class AndExp : BinExp */ extern (C++) final class OrExp : BinExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.or, e1, e2); } @@ -6792,7 +6799,7 @@ extern (C++) final class OrExp : BinExp */ extern (C++) final class XorExp : BinExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.xor, e1, e2); } @@ -6811,7 +6818,7 @@ extern (C++) final class XorExp : BinExp */ extern (C++) final class LogicalExp : BinExp { - extern (D) this(const ref Loc loc, EXP op, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, EXP op, Expression e1, Expression e2) @safe { super(loc, op, e1, e2); assert(op == EXP.andAnd || op == EXP.orOr); @@ -6833,7 +6840,7 @@ extern (C++) final class LogicalExp : BinExp */ extern (C++) final class CmpExp : BinExp { - extern (D) this(EXP op, const ref Loc loc, Expression e1, Expression e2) + extern (D) this(EXP op, const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, op, e1, e2); assert(op == EXP.lessThan || op == EXP.lessOrEqual || op == EXP.greaterThan || op == EXP.greaterOrEqual); @@ -6854,7 +6861,7 @@ extern (C++) final class CmpExp : BinExp */ extern (C++) final class InExp : BinExp { - extern (D) this(const ref Loc loc, Expression e1, Expression e2) + extern (D) this(const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, EXP.in_, e1, e2); } @@ -6893,7 +6900,7 @@ extern (C++) final class RemoveExp : BinExp */ extern (C++) final class EqualExp : BinExp { - extern (D) this(EXP op, const ref Loc loc, Expression e1, Expression e2) + extern (D) this(EXP op, const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, op, e1, e2); assert(op == EXP.equal || op == EXP.notEqual); @@ -6914,7 +6921,7 @@ extern (C++) final class EqualExp : BinExp */ extern (C++) final class IdentityExp : BinExp { - extern (D) this(EXP op, const ref Loc loc, Expression e1, Expression e2) + extern (D) this(EXP op, const ref Loc loc, Expression e1, Expression e2) @safe { super(loc, op, e1, e2); assert(op == EXP.identity || op == EXP.notIdentity); @@ -6935,7 +6942,7 @@ extern (C++) final class CondExp : BinExp { Expression econd; - extern (D) this(const ref Loc loc, Expression econd, Expression e1, Expression e2) scope + extern (D) this(const ref Loc loc, Expression econd, Expression e1, Expression e2) scope @safe { super(loc, EXP.question, e1, e2); this.econd = econd; @@ -6984,7 +6991,7 @@ extern (C++) final class CondExp : BinExp VarDeclaration vcond; bool isThen; - extern (D) this(Scope* sc, CondExp ce) + extern (D) this(Scope* sc, CondExp ce) @safe { this.sc = sc; this.ce = ce; @@ -7075,7 +7082,7 @@ bool isDefaultInitOp(EXP op) pure nothrow @safe @nogc */ extern (C++) class DefaultInitExp : Expression { - extern (D) this(const ref Loc loc, EXP op) + extern (D) this(const ref Loc loc, EXP op) @safe { super(loc, op); } @@ -7091,7 +7098,7 @@ extern (C++) class DefaultInitExp : Expression */ extern (C++) final class FileInitExp : DefaultInitExp { - extern (D) this(const ref Loc loc, EXP tok) + extern (D) this(const ref Loc loc, EXP tok) @safe { super(loc, tok); } @@ -7120,7 +7127,7 @@ extern (C++) final class FileInitExp : DefaultInitExp */ extern (C++) final class LineInitExp : DefaultInitExp { - extern (D) this(const ref Loc loc) + extern (D) this(const ref Loc loc) @safe { super(loc, EXP.line); } @@ -7142,7 +7149,7 @@ extern (C++) final class LineInitExp : DefaultInitExp */ extern (C++) final class ModuleInitExp : DefaultInitExp { - extern (D) this(const ref Loc loc) + extern (D) this(const ref Loc loc) @safe { super(loc, EXP.moduleString); } @@ -7165,7 +7172,7 @@ extern (C++) final class ModuleInitExp : DefaultInitExp */ extern (C++) final class FuncInitExp : DefaultInitExp { - extern (D) this(const ref Loc loc) + extern (D) this(const ref Loc loc) @safe { super(loc, EXP.functionString); } @@ -7194,7 +7201,7 @@ extern (C++) final class FuncInitExp : DefaultInitExp */ extern (C++) final class PrettyFuncInitExp : DefaultInitExp { - extern (D) this(const ref Loc loc) + extern (D) this(const ref Loc loc) @safe { super(loc, EXP.prettyFunction); } @@ -7262,7 +7269,7 @@ extern (C++) final class GenericExp : Expression Types* types; /// type-names for generic associations (null entry for `default`) Expressions* exps; /// 1:1 mapping of typeNames to exps - extern (D) this(const ref Loc loc, Expression cntlExp, Types* types, Expressions* exps) + extern (D) this(const ref Loc loc, Expression cntlExp, Types* types, Expressions* exps) @safe { super(loc, EXP._Generic); this.cntlExp = cntlExp; diff --git a/gcc/d/dmd/expression.h b/gcc/d/dmd/expression.h index 8c6393f..1f04c6c 100644 --- a/gcc/d/dmd/expression.h +++ b/gcc/d/dmd/expression.h @@ -955,6 +955,7 @@ public: private: uint8_t bitFields; +public: SliceExp *syntaxCopy() override; bool isLvalue() override; Expression *toLvalue(Scope *sc, Expression *e) override; diff --git a/gcc/d/dmd/expressionsem.d b/gcc/d/dmd/expressionsem.d index 25f755b..69999cb 100644 --- a/gcc/d/dmd/expressionsem.d +++ b/gcc/d/dmd/expressionsem.d @@ -875,6 +875,13 @@ Lagain: if (sc.setUnsafePreview(global.params.systemVariables, false, loc, "cannot access `@system` variable `%s` in @safe code", sd)) { + if (auto v = sd.isVarDeclaration()) + { + if (v.systemInferred) + errorSupplemental(v.loc, "`%s` is inferred to be `@system` from its initializer here", v.toChars()); + else + errorSupplemental(v.loc, "`%s` is declared here", v.toChars()); + } return ErrorExp.get(); } } @@ -1582,7 +1589,7 @@ private Type arrayExpressionToCommonType(Scope* sc, ref Expressions exps) return t0; } -private Expression opAssignToOp(const ref Loc loc, EXP op, Expression e1, Expression e2) +private Expression opAssignToOp(const ref Loc loc, EXP op, Expression e1, Expression e2) @safe { Expression e; switch (op) @@ -2609,7 +2616,7 @@ private extern (C++) final class ExpressionSemanticVisitor : Visitor Scope* sc; Expression result; - this(Scope* sc) scope + this(Scope* sc) scope @safe { this.sc = sc; } @@ -2619,6 +2626,14 @@ private extern (C++) final class ExpressionSemanticVisitor : Visitor result = ErrorExp.get(); } + private void needThisError(Loc loc, FuncDeclaration f) + { + auto t = f.isThis(); + assert(t); + .error(loc, "calling non-static function `%s` requires an instance of type `%s`", f.toChars(), t.toChars()); + setError(); + } + /************************** * Semantically analyze Expression. * Determine types, fold constants, etc. @@ -3721,12 +3736,13 @@ private extern (C++) final class ExpressionSemanticVisitor : Visitor if (cd.isAbstract()) { exp.error("cannot create instance of abstract class `%s`", cd.toChars()); + errorSupplemental(cd.loc, "class `%s` is declared here", cd.toChars()); for (size_t i = 0; i < cd.vtbl.length; i++) { FuncDeclaration fd = cd.vtbl[i].isFuncDeclaration(); if (fd && fd.isAbstract()) { - errorSupplemental(exp.loc, "function `%s` is not implemented", + errorSupplemental(fd.loc, "function `%s` is not implemented", fd.toFullSignature()); } } @@ -5242,8 +5258,7 @@ private extern (C++) final class ExpressionSemanticVisitor : Visitor } else if (isNeedThisScope(sc, exp.f)) { - exp.error("need `this` for `%s` of type `%s`", exp.f.toChars(), exp.f.type.toChars()); - return setError(); + return needThisError(exp.loc, exp.f); } } exp.e1 = new VarExp(exp.e1.loc, exp.f, false); @@ -5386,8 +5401,7 @@ private extern (C++) final class ExpressionSemanticVisitor : Visitor // If no error is printed, it means that `f` is the single matching overload // and it needs `this`. - exp.error("need `this` for `%s` of type `%s`", exp.f.toChars(), exp.f.type.toChars()); - return setError(); + return needThisError(exp.loc, exp.f); } } @@ -5958,18 +5972,20 @@ private extern (C++) final class ExpressionSemanticVisitor : Visitor break; case TOK.function_: + if (e.targ.ty != Tfunction) + return no(); + goto case; case TOK.parameters: { - if (e.targ.ty != Tfunction) + if (auto tf = e.targ.isFunction_Delegate_PtrToFunction()) + tded = tf; + else return no(); - tded = e.targ; /* Generate tuple from function parameter types. */ - assert(tded.ty == Tfunction); - auto tdedf = tded.isTypeFunction(); auto args = new Parameters(); - foreach (i, arg; tdedf.parameterList) + foreach (i, arg; tded.isTypeFunction().parameterList) { assert(arg && arg.type); /* If one of the default arguments was an error, @@ -6267,7 +6283,10 @@ private extern (C++) final class ExpressionSemanticVisitor : Visitor if (p.token.value != TOK.endOfFile) { - exp.error("incomplete mixin expression `%s`", str.ptr); + e.error("unexpected token `%s` after %s expression", + p.token.toChars(), EXPtoString(e.op).ptr); + e.errorSupplemental("while parsing string mixin expression `%s`", + str.ptr); return null; } return e; @@ -6632,7 +6651,7 @@ private extern (C++) final class ExpressionSemanticVisitor : Visitor else { OutBuffer buf; - buf.printf("%s failed", exp.toChars()); + buf.printf("`%s` failed", exp.toChars()); exp.msg = new StringExp(Loc.initial, buf.extractSlice()); goto LSkip; } @@ -12911,7 +12930,7 @@ private Expression dotIdSemanticPropX(DotIdExp exp, Scope* sc) } } OutBuffer buf; - mangleToBuffer(ds, &buf); + mangleToBuffer(ds, buf); Expression e = new StringExp(loc, buf.extractSlice()); return e.expressionSemantic(sc); } diff --git a/gcc/d/dmd/foreachvar.d b/gcc/d/dmd/foreachvar.d index 1293057..8af2a95 100644 --- a/gcc/d/dmd/foreachvar.d +++ b/gcc/d/dmd/foreachvar.d @@ -56,7 +56,7 @@ void foreachVar(Expression e, void delegate(VarDeclaration) dgVar) alias visit = typeof(super).visit; extern (D) void delegate(VarDeclaration) dgVar; - extern (D) this(void delegate(VarDeclaration) dgVar) scope + extern (D) this(void delegate(VarDeclaration) dgVar) scope @safe { this.dgVar = dgVar; } diff --git a/gcc/d/dmd/func.d b/gcc/d/dmd/func.d index 6045735..73f1ba7 100644 --- a/gcc/d/dmd/func.d +++ b/gcc/d/dmd/func.d @@ -2509,7 +2509,7 @@ extern (C++) class FuncDeclaration : Declaration * Returns: * true found an 'out' contract */ - static bool needsFensure(FuncDeclaration fd) + static bool needsFensure(FuncDeclaration fd) @safe { if (fd.fensures) return true; @@ -4558,9 +4558,10 @@ bool setUnsafe(Scope* sc, .error(loc, fmt, arg0 ? arg0.toChars() : "", arg1 ? arg1.toChars() : "", arg2 ? arg2.toChars() : ""); return true; } - else if (!(sc.varDecl.storage_class & STC.system)) + else if (!(sc.varDecl.storage_class & STC.trusted)) { sc.varDecl.storage_class |= STC.system; + sc.varDecl.systemInferred = true; } } return false; @@ -4606,6 +4607,7 @@ bool setUnsafe(Scope* sc, bool setUnsafePreview(Scope* sc, FeatureState fs, bool gag, Loc loc, const(char)* msg, RootObject arg0 = null, RootObject arg1 = null, RootObject arg2 = null) { + //printf("setUnsafePreview() fs:%d %s\n", fs, msg); with (FeatureState) final switch (fs) { case disabled: @@ -4620,9 +4622,10 @@ bool setUnsafePreview(Scope* sc, FeatureState fs, bool gag, Loc loc, const(char) if (sc.func.isSafeBypassingInference()) { if (!gag) - previewErrorFunc(sc.isDeprecated(), fs)( - loc, msg, arg0 ? arg0.toChars() : "", arg1 ? arg1.toChars() : "", arg2 ? arg2.toChars() : "" - ); + { + if (!sc.isDeprecated() && global.params.obsolete) + warning(loc, msg, arg0 ? arg0.toChars() : "", arg1 ? arg1.toChars() : "", arg2 ? arg2.toChars() : ""); + } } else if (!sc.func.safetyViolation) { @@ -4706,9 +4709,9 @@ void errorSupplementalInferredAttr(FuncDeclaration fd, int maxDepth, bool deprec s.arg0 ? s.arg0.toChars() : "", s.arg1 ? s.arg1.toChars() : "", s.arg2 ? s.arg2.toChars() : ""); } } - else if (s.arg0.dyncast() == DYNCAST.dsymbol) + else if (auto sa = s.arg0.isDsymbol()) { - if (FuncDeclaration fd2 = (cast(Dsymbol) s.arg0).isFuncDeclaration()) + if (FuncDeclaration fd2 = sa.isFuncDeclaration()) { if (maxDepth > 0) { diff --git a/gcc/d/dmd/globals.d b/gcc/d/dmd/globals.d index 9071e6a..af711a0 100644 --- a/gcc/d/dmd/globals.d +++ b/gcc/d/dmd/globals.d @@ -133,7 +133,7 @@ extern (C++) struct Param bool useModuleInfo = true; // generate runtime module information bool useTypeInfo = true; // generate runtime type information bool useExceptions = true; // support exception handling - bool useGC = true; // support features that require the GC + bool useGC = true; // support features that require the D runtime GC bool betterC; // be a "better C" compiler; no dependency on D runtime bool addMain; // add a default main() function bool allInst; // generate code for all template instantiations @@ -297,7 +297,7 @@ extern (C++) struct Global * * Returns: the current number of gagged errors, which should later be passed to `endGagging` */ - extern (C++) uint startGagging() + extern (C++) uint startGagging() @safe { ++gag; gaggedWarnings = 0; @@ -311,7 +311,7 @@ extern (C++) struct Global * oldGagged = the previous number of errors, as returned by `startGagging` * Returns: true if errors occurred while gagged. */ - extern (C++) bool endGagging(uint oldGagged) + extern (C++) bool endGagging(uint oldGagged) @safe { bool anyErrs = (gaggedErrors != oldGagged); --gag; @@ -327,7 +327,7 @@ extern (C++) struct Global * * An error message may or may not have been printed. */ - extern (C++) void increaseErrorCount() + extern (C++) void increaseErrorCount() @safe { if (gag) ++gaggedErrors; @@ -344,8 +344,8 @@ extern (C++) struct Global compileEnv.vendor = "Digital Mars D"; // -color=auto is the default value - import dmd.console : detectTerminal; - params.color = detectTerminal(); + import dmd.console : detectTerminal, detectColorPreference; + params.color = detectTerminal() && detectColorPreference(); } else version (IN_GCC) { @@ -397,7 +397,7 @@ extern (C++) struct Global /** * Computes the version number __VERSION__ from the compiler version string. */ - extern (D) private static uint parseVersionNumber(string version_) + extern (D) private static uint parseVersionNumber(string version_) @safe { // // parse _version @@ -429,7 +429,7 @@ extern (C++) struct Global /** Returns: the version as the number that would be returned for __VERSION__ */ - extern(C++) uint versionNumber() + extern(C++) uint versionNumber() @safe { return compileEnv.versionNumber; } @@ -437,7 +437,7 @@ extern (C++) struct Global /** Returns: compiler version string. */ - extern(D) string versionString() + extern(D) string versionString() @safe { return _version; } diff --git a/gcc/d/dmd/globals.h b/gcc/d/dmd/globals.h index 0dad5dd..0ef9eed 100644 --- a/gcc/d/dmd/globals.h +++ b/gcc/d/dmd/globals.h @@ -128,7 +128,7 @@ struct Param d_bool useModuleInfo; // generate runtime module information d_bool useTypeInfo; // generate runtime type information d_bool useExceptions; // support exception handling - d_bool useGC; // support features that require the GC + d_bool useGC; // support features that require the D runtime GC d_bool betterC; // be a "better C" compiler; no dependency on D runtime d_bool addMain; // add a default main() function d_bool allInst; // generate code for all template instantiations diff --git a/gcc/d/dmd/hdrgen.d b/gcc/d/dmd/hdrgen.d index 62e0d49..33cbc19 100644 --- a/gcc/d/dmd/hdrgen.d +++ b/gcc/d/dmd/hdrgen.d @@ -805,7 +805,7 @@ public: OutBuffer* buf; HdrGenState* hgs; - extern (D) this(OutBuffer* buf, HdrGenState* hgs) scope + extern (D) this(OutBuffer* buf, HdrGenState* hgs) scope @safe { this.buf = buf; this.hgs = hgs; @@ -2775,7 +2775,7 @@ public: OutBuffer* buf; HdrGenState* hgs; - extern (D) this(OutBuffer* buf, HdrGenState* hgs) scope + extern (D) this(OutBuffer* buf, HdrGenState* hgs) scope @safe { this.buf = buf; this.hgs = hgs; @@ -2856,7 +2856,7 @@ public: OutBuffer* buf; HdrGenState* hgs; - extern (D) this(OutBuffer* buf, HdrGenState* hgs) scope + extern (D) this(OutBuffer* buf, HdrGenState* hgs) scope @safe { this.buf = buf; this.hgs = hgs; @@ -2920,7 +2920,7 @@ void toCBuffer(const Initializer iz, OutBuffer* buf, HdrGenState* hgs) initializerToBuffer(cast() iz, buf, hgs); } -bool stcToBuffer(OutBuffer* buf, StorageClass stc) +bool stcToBuffer(OutBuffer* buf, StorageClass stc) @safe { //printf("stc: %llx\n", stc); bool result = false; @@ -2980,7 +2980,7 @@ bool stcToBuffer(OutBuffer* buf, StorageClass stc) * and return a string representation of it. * stc is reduced by the one picked. */ -string stcToString(ref StorageClass stc) +string stcToString(ref StorageClass stc) @safe { static struct SCstring { @@ -3039,7 +3039,7 @@ string stcToString(ref StorageClass stc) return null; } -private void linkageToBuffer(OutBuffer* buf, LINK linkage) +private void linkageToBuffer(OutBuffer* buf, LINK linkage) @safe { const s = linkageToString(linkage); if (s.length) @@ -3056,7 +3056,7 @@ const(char)* linkageToChars(LINK linkage) return linkageToString(linkage).ptr; } -string linkageToString(LINK linkage) pure nothrow +string linkageToString(LINK linkage) pure nothrow @safe { final switch (linkage) { @@ -3099,7 +3099,7 @@ const(char)* visibilityToChars(Visibility.Kind kind) } /// Ditto -extern (D) string visibilityToString(Visibility.Kind kind) nothrow pure +extern (D) string visibilityToString(Visibility.Kind kind) nothrow pure @safe { final switch (kind) { diff --git a/gcc/d/dmd/id.d b/gcc/d/dmd/id.d index a2daf60..43b2e5f 100644 --- a/gcc/d/dmd/id.d +++ b/gcc/d/dmd/id.d @@ -575,7 +575,7 @@ struct Msgtable * Returns: the name to use in the D executable, `name_` if non-empty, * otherwise `ident` */ - string name() + string name() @safe { return name_ ? name_ : ident; } @@ -602,19 +602,19 @@ string generate(immutable(Msgtable)[] msgtable, string function(Msgtable) dg) } // Used to generate the code for each identifier. -string identifier(Msgtable m) +string identifier(Msgtable m) @safe { return "Identifier " ~ m.ident ~ ";"; } // Used to generate the code for each initializer. -string initializer(Msgtable m) +string initializer(Msgtable m) @safe { return m.ident ~ ` = Identifier.idPool("` ~ m.name ~ `");`; } // Used to generate the code for each deinitializer. -string deinitializer(Msgtable m) +string deinitializer(Msgtable m) @safe { return m.ident ~ " = Identifier.init;"; } diff --git a/gcc/d/dmd/identifier.d b/gcc/d/dmd/identifier.d index b1c421c..3173445 100644 --- a/gcc/d/dmd/identifier.d +++ b/gcc/d/dmd/identifier.d @@ -64,13 +64,13 @@ nothrow: } /// ditto - extern (D) this(const(char)[] name, int value) + extern (D) this(const(char)[] name, int value) @safe { //printf("Identifier('%.*s', %d)\n", cast(int)name.length, name.ptr, value); this(name, value, false); } - extern (D) private this(const(char)[] name, int value, bool isAnonymous) + extern (D) private this(const(char)[] name, int value, bool isAnonymous) @safe { //printf("Identifier('%.*s', %d, %d)\n", cast(int)name.length, name.ptr, value, isAnonymous); this.name = name; @@ -315,7 +315,7 @@ nothrow: /********************************** * ditto */ - extern (D) static bool isValidIdentifier(const(char)[] str) + extern (D) static bool isValidIdentifier(const(char)[] str) @safe { if (str.length == 0 || (str[0] >= '0' && str[0] <= '9')) // beware of isdigit() on signed chars diff --git a/gcc/d/dmd/imphint.d b/gcc/d/dmd/imphint.d index 913de9f..9e9466a 100644 --- a/gcc/d/dmd/imphint.d +++ b/gcc/d/dmd/imphint.d @@ -20,7 +20,7 @@ module dmd.imphint; * Not meant to be a comprehensive list of names in each module, * just the most common ones. */ -const(char)[] importHint(const(char)[] s) +const(char)[] importHint(const(char)[] s) @safe { if (auto entry = s in hints) return *entry; diff --git a/gcc/d/dmd/init.d b/gcc/d/dmd/init.d index 6f20a3c..e7cf905 100644 --- a/gcc/d/dmd/init.d +++ b/gcc/d/dmd/init.d @@ -51,7 +51,7 @@ extern (C++) class Initializer : ASTNode } - extern (D) this(const ref Loc loc, InitKind kind) + extern (D) this(const ref Loc loc, InitKind kind) @safe { this.loc = loc; this.kind = kind; @@ -108,7 +108,7 @@ extern (C++) final class VoidInitializer : Initializer { Type type; // type that this will initialize to - extern (D) this(const ref Loc loc) + extern (D) this(const ref Loc loc) @safe { super(loc, InitKind.void_); } @@ -123,7 +123,7 @@ extern (C++) final class VoidInitializer : Initializer */ extern (C++) final class ErrorInitializer : Initializer { - extern (D) this() + extern (D) this() @safe { super(Loc.initial, InitKind.error); } @@ -206,7 +206,7 @@ extern (C++) final class ExpInitializer : Initializer bool expandTuples; Expression exp; - extern (D) this(const ref Loc loc, Expression exp) + extern (D) this(const ref Loc loc, Expression exp) @safe { super(loc, InitKind.exp); this.exp = exp; @@ -226,8 +226,8 @@ struct Designator Expression exp; /// [ constant-expression ] Identifier ident; /// . identifier - this(Expression exp) { this.exp = exp; } - this(Identifier ident) { this.ident = ident; } + this(Expression exp) @safe { this.exp = exp; } + this(Identifier ident) @safe { this.ident = ident; } } /********************************************* @@ -377,7 +377,7 @@ mixin template VisitInitializer(Result) * handler = string for the name of the visit handler * Returns: boilerplate code for a case */ -pure string visitCase(string handler) +string visitCase(string handler) pure @safe { if (__ctfe) { diff --git a/gcc/d/dmd/intrange.d b/gcc/d/dmd/intrange.d index d67e0f5..442668f 100644 --- a/gcc/d/dmd/intrange.d +++ b/gcc/d/dmd/intrange.d @@ -18,7 +18,7 @@ import dmd.mtype; import dmd.expression; import dmd.globals; -private uinteger_t copySign(uinteger_t x, bool sign) +private uinteger_t copySign(uinteger_t x, bool sign) @safe { // return sign ? -x : x; return (x - cast(uinteger_t)sign) ^ -cast(uinteger_t)sign; @@ -29,37 +29,37 @@ struct SignExtendedNumber uinteger_t value; bool negative; - static SignExtendedNumber fromInteger(uinteger_t value_) + static SignExtendedNumber fromInteger(uinteger_t value_) @safe { return SignExtendedNumber(value_, value_ >> 63); } - static SignExtendedNumber extreme(bool minimum) + static SignExtendedNumber extreme(bool minimum) @safe { return SignExtendedNumber(minimum - 1, minimum); } - static SignExtendedNumber max() + static SignExtendedNumber max() @safe { return SignExtendedNumber(ulong.max, false); } - static SignExtendedNumber min() + static SignExtendedNumber min() @safe { return SignExtendedNumber(0, true); } - bool isMinimum() const + bool isMinimum() const @safe { return negative && value == 0; } - bool opEquals(const ref SignExtendedNumber a) const + bool opEquals(const ref SignExtendedNumber a) const @safe { return value == a.value && negative == a.negative; } - int opCmp(const ref SignExtendedNumber a) const + int opCmp(const ref SignExtendedNumber a) const @safe { if (negative != a.negative) { @@ -297,19 +297,19 @@ struct IntRange { SignExtendedNumber imin, imax; - this(IntRange another) + this(IntRange another) @safe { imin = another.imin; imax = another.imax; } - this(SignExtendedNumber a) + this(SignExtendedNumber a) @safe { imin = a; imax = a; } - this(SignExtendedNumber lower, SignExtendedNumber upper) + this(SignExtendedNumber lower, SignExtendedNumber upper) @safe { imin = lower; imax = upper; @@ -358,12 +358,12 @@ struct IntRange return ab; } - static IntRange widest() + static IntRange widest() @safe { return IntRange(SignExtendedNumber.min(), SignExtendedNumber.max()); } - IntRange castSigned(uinteger_t mask) + IntRange castSigned(uinteger_t mask) @safe { // .... 0x1e7f ] [0x1e80 .. 0x1f7f] [0x1f80 .. 0x7f] [0x80 .. 0x17f] [0x180 .... // @@ -405,7 +405,7 @@ struct IntRange return this; } - IntRange castUnsigned(uinteger_t mask) + IntRange castUnsigned(uinteger_t mask) @safe { // .... 0x1eff ] [0x1f00 .. 0x1fff] [0 .. 0xff] [0x100 .. 0x1ff] [0x200 .... // @@ -430,7 +430,7 @@ struct IntRange return this; } - IntRange castDchar() + IntRange castDchar() @safe { // special case for dchar. Casting to dchar means "I'll ignore all // invalid characters." @@ -464,18 +464,18 @@ struct IntRange return castUnsigned(type.sizemask()); } - bool contains(IntRange a) + bool contains(IntRange a) @safe { return imin <= a.imin && imax >= a.imax; } - bool containsZero() const + bool containsZero() const @safe { return (imin.negative && !imax.negative) || (!imin.negative && imin.value == 0); } - IntRange absNeg() const + IntRange absNeg() const @safe { if (imax.negative) return this; @@ -489,13 +489,13 @@ struct IntRange } } - IntRange unionWith(const ref IntRange other) const + IntRange unionWith(const ref IntRange other) const @safe { return IntRange(imin < other.imin ? imin : other.imin, imax > other.imax ? imax : other.imax); } - void unionOrAssign(IntRange other, ref bool union_) + void unionOrAssign(IntRange other, ref bool union_) @safe { if (!union_ || imin > other.imin) imin = other.imin; @@ -513,7 +513,7 @@ struct IntRange return this; } - void splitBySign(ref IntRange negRange, ref bool hasNegRange, ref IntRange nonNegRange, ref bool hasNonNegRange) const + void splitBySign(ref IntRange negRange, ref bool hasNegRange, ref IntRange nonNegRange, ref bool hasNonNegRange) const @safe { hasNegRange = imin.negative; if (hasNegRange) @@ -785,7 +785,7 @@ struct IntRange private: // Credits to Timon Gehr maxOr, minOr, maxAnd, minAnd // https://github.com/tgehr/d-compiler/blob/master/vrange.d - static SignExtendedNumber maxOr(const IntRange lhs, const IntRange rhs) + static SignExtendedNumber maxOr(const IntRange lhs, const IntRange rhs) @safe { uinteger_t x = 0; auto sign = false; @@ -856,14 +856,14 @@ private: // Credits to Timon Gehr maxOr, minOr, maxAnd, minAnd // https://github.com/tgehr/d-compiler/blob/master/vrange.d - static SignExtendedNumber minOr(const IntRange lhs, const IntRange rhs) + static SignExtendedNumber minOr(const IntRange lhs, const IntRange rhs) @safe { return ~maxAnd(~lhs, ~rhs); } // Credits to Timon Gehr maxOr, minOr, maxAnd, minAnd // https://github.com/tgehr/d-compiler/blob/master/vrange.d - static SignExtendedNumber maxAnd(const IntRange lhs, const IntRange rhs) + static SignExtendedNumber maxAnd(const IntRange lhs, const IntRange rhs) @safe { uinteger_t x = 0; bool sign = false; @@ -905,7 +905,7 @@ private: // Credits to Timon Gehr maxOr, minOr, maxAnd, minAnd // https://github.com/tgehr/d-compiler/blob/master/vrange.d - static SignExtendedNumber minAnd(const IntRange lhs, const IntRange rhs) + static SignExtendedNumber minAnd(const IntRange lhs, const IntRange rhs) @safe { return ~maxOr(~lhs, ~rhs); } diff --git a/gcc/d/dmd/json.d b/gcc/d/dmd/json.d index dcf53b8..9689986 100644 --- a/gcc/d/dmd/json.d +++ b/gcc/d/dmd/json.d @@ -54,7 +54,7 @@ public: int indentLevel; const(char)[] filename; - extern (D) this(OutBuffer* buf) scope + extern (D) this(OutBuffer* buf) scope @safe { this.buf = buf; } diff --git a/gcc/d/dmd/lambdacomp.d b/gcc/d/dmd/lambdacomp.d index 885a27a..ec070d8 100644 --- a/gcc/d/dmd/lambdacomp.d +++ b/gcc/d/dmd/lambdacomp.d @@ -395,7 +395,7 @@ public: if (s) { OutBuffer mangledName; - mangleToBuffer(s, &mangledName); + mangleToBuffer(s, mangledName); buf.writestring(mangledName[]); buf.writeByte('_'); } diff --git a/gcc/d/dmd/lexer.d b/gcc/d/dmd/lexer.d index 9cce7c5..c28fe5c 100644 --- a/gcc/d/dmd/lexer.d +++ b/gcc/d/dmd/lexer.d @@ -193,7 +193,7 @@ class Lexer /****************** * Used for unittests for a mock Lexer */ - this(ErrorSink errorSink) scope { assert(errorSink); this.eSink = errorSink; } + this(ErrorSink errorSink) scope @safe { assert(errorSink); this.eSink = errorSink; } /************************************** * Reset lexer to lex #define's diff --git a/gcc/d/dmd/location.d b/gcc/d/dmd/location.d index b2b3661..0f3b9a7 100644 --- a/gcc/d/dmd/location.d +++ b/gcc/d/dmd/location.d @@ -64,7 +64,7 @@ nothrow: this.messageStyle = messageStyle; } - extern (D) this(const(char)* filename, uint linnum, uint charnum) + extern (D) this(const(char)* filename, uint linnum, uint charnum) @safe { this._linnum = linnum; this._charnum = cast(ushort) charnum; @@ -108,7 +108,7 @@ nothrow: * Params: * name = file name for location, null for no file name */ - extern (C++) void filename(const(char)* name) + extern (C++) void filename(const(char)* name) @trusted { if (name) { @@ -205,7 +205,7 @@ nothrow: * Returns: * true if Loc has been set to other than the default initialization */ - bool isValid() const pure + bool isValid() const pure @safe { return fileIndex != 0; } diff --git a/gcc/d/dmd/mangle.h b/gcc/d/dmd/mangle.h index 37953c2..aa24698 100644 --- a/gcc/d/dmd/mangle.h +++ b/gcc/d/dmd/mangle.h @@ -28,7 +28,7 @@ const char *cppTypeInfoMangleMSVC(Dsymbol *s); // In dmangle.d const char *mangleExact(FuncDeclaration *fd); -void mangleToBuffer(Type *s, OutBuffer *buf); -void mangleToBuffer(Expression *s, OutBuffer *buf); -void mangleToBuffer(Dsymbol *s, OutBuffer *buf); -void mangleToBuffer(TemplateInstance *s, OutBuffer *buf); +void mangleToBuffer(Type *s, OutBuffer& buf); +void mangleToBuffer(Expression *s, OutBuffer& buf); +void mangleToBuffer(Dsymbol *s, OutBuffer& buf); +void mangleToBuffer(TemplateInstance *s, OutBuffer& buf); diff --git a/gcc/d/dmd/mtype.d b/gcc/d/dmd/mtype.d index 7ecd402..9d83db1 100644 --- a/gcc/d/dmd/mtype.d +++ b/gcc/d/dmd/mtype.d @@ -157,7 +157,7 @@ MOD MODmerge(MOD mod1, MOD mod2) pure nothrow @nogc @safe /********************************* * Store modifier name into buf. */ -void MODtoBuffer(OutBuffer* buf, MOD mod) nothrow +void MODtoBuffer(OutBuffer* buf, MOD mod) nothrow @safe { buf.writestring(MODtoString(mod)); } @@ -174,7 +174,7 @@ const(char)* MODtoChars(MOD mod) nothrow pure } /// Ditto -string MODtoString(MOD mod) nothrow pure +string MODtoString(MOD mod) nothrow pure @safe { final switch (mod) { @@ -457,7 +457,7 @@ extern (C++) abstract class Type : ASTNode return sizeTy; }(); - final extern (D) this(TY ty) scope + final extern (D) this(TY ty) scope @safe { this.ty = ty; } @@ -2434,7 +2434,7 @@ extern (C++) abstract class Type : ASTNode // _init_10TypeInfo_%s OutBuffer buf; buf.reserve(32); - mangleToBuffer(this, &buf); + mangleToBuffer(this, buf); const slice = buf[]; @@ -2780,7 +2780,7 @@ extern (C++) abstract class Type : ASTNode */ extern (C++) final class TypeError : Type { - extern (D) this() + extern (D) this() @safe { super(Terror); } @@ -2818,7 +2818,7 @@ extern (C++) abstract class TypeNext : Type { Type next; - final extern (D) this(TY ty, Type next) + final extern (D) this(TY ty, Type next) @safe { super(ty); this.next = next; @@ -3517,13 +3517,13 @@ extern (C++) final class TypeVector : Type { Type basetype; - extern (D) this(Type basetype) + extern (D) this(Type basetype) @safe { super(Tvector); this.basetype = basetype; } - static TypeVector create(Type basetype) + static TypeVector create(Type basetype) @safe { return new TypeVector(basetype); } @@ -3632,7 +3632,7 @@ extern (C++) final class TypeVector : Type */ extern (C++) abstract class TypeArray : TypeNext { - final extern (D) this(TY ty, Type next) + final extern (D) this(TY ty, Type next) @safe { super(ty, next); } @@ -3650,7 +3650,7 @@ extern (C++) final class TypeSArray : TypeArray { Expression dim; - extern (D) this(Type t, Expression dim) + extern (D) this(Type t, Expression dim) @safe { super(Tsarray, t); //printf("TypeSArray(%s)\n", dim.toChars()); @@ -3874,7 +3874,7 @@ extern (C++) final class TypeSArray : TypeArray */ extern (C++) final class TypeDArray : TypeArray { - extern (D) this(Type t) + extern (D) this(Type t) @safe { super(Tarray, t); //printf("TypeDArray(t = %p)\n", t); @@ -3972,13 +3972,13 @@ extern (C++) final class TypeAArray : TypeArray Type index; // key type Loc loc; - extern (D) this(Type t, Type index) + extern (D) this(Type t, Type index) @safe { super(Taarray, t); this.index = index; } - static TypeAArray create(Type t, Type index) + static TypeAArray create(Type t, Type index) @safe { return new TypeAArray(t, index); } @@ -4066,12 +4066,12 @@ extern (C++) final class TypeAArray : TypeArray */ extern (C++) final class TypePointer : TypeNext { - extern (D) this(Type t) + extern (D) this(Type t) @safe { super(Tpointer, t); } - static TypePointer create(Type t) + static TypePointer create(Type t) @safe { return new TypePointer(t); } @@ -4173,7 +4173,7 @@ extern (C++) final class TypePointer : TypeNext */ extern (C++) final class TypeReference : TypeNext { - extern (D) this(Type t) + extern (D) this(Type t) @safe { super(Treference, t); // BUG: what about references to static arrays? @@ -4263,7 +4263,7 @@ extern (C++) final class TypeFunction : TypeNext byte inuse; Expressions* fargs; // function arguments - extern (D) this(ParameterList pl, Type treturn, LINK linkage, StorageClass stc = 0) + extern (D) this(ParameterList pl, Type treturn, LINK linkage, StorageClass stc = 0) @safe { super(Tfunction, treturn); //if (!treturn) *(char*)0=0; @@ -4305,7 +4305,7 @@ extern (C++) final class TypeFunction : TypeNext this.trust = TRUST.trusted; } - static TypeFunction create(Parameters* parameters, Type treturn, ubyte varargs, LINK linkage, StorageClass stc = 0) + static TypeFunction create(Parameters* parameters, Type treturn, ubyte varargs, LINK linkage, StorageClass stc = 0) @safe { return new TypeFunction(ParameterList(parameters, cast(VarArg)varargs), treturn, linkage, stc); } @@ -5013,13 +5013,13 @@ extern (C++) final class TypeDelegate : TypeNext { // .next is a TypeFunction - extern (D) this(TypeFunction t) + extern (D) this(TypeFunction t) @safe { super(Tfunction, t); ty = Tdelegate; } - static TypeDelegate create(TypeFunction t) + static TypeDelegate create(TypeFunction t) @safe { return new TypeDelegate(t); } @@ -5114,7 +5114,7 @@ extern (C++) final class TypeTraits : Type /// Cached type/symbol after semantic analysis. RootObject obj; - final extern (D) this(const ref Loc loc, TraitsExp exp) + final extern (D) this(const ref Loc loc, TraitsExp exp) @safe { super(Ttraits); this.loc = loc; @@ -5170,7 +5170,7 @@ extern (C++) final class TypeMixin : Type Expressions* exps; RootObject obj; // cached result of semantic analysis. - extern (D) this(const ref Loc loc, Expressions* exps) + extern (D) this(const ref Loc loc, Expressions* exps) @safe { super(Tmixin); this.loc = loc; @@ -5494,13 +5494,13 @@ extern (C++) final class TypeStruct : Type AliasThisRec att = AliasThisRec.fwdref; bool inuse = false; // struct currently subject of recursive method call - extern (D) this(StructDeclaration sym) + extern (D) this(StructDeclaration sym) @safe { super(Tstruct); this.sym = sym; } - static TypeStruct create(StructDeclaration sym) + static TypeStruct create(StructDeclaration sym) @safe { return new TypeStruct(sym); } @@ -5830,7 +5830,7 @@ extern (C++) final class TypeEnum : Type { EnumDeclaration sym; - extern (D) this(EnumDeclaration sym) + extern (D) this(EnumDeclaration sym) @safe { super(Tenum); this.sym = sym; @@ -6008,7 +6008,7 @@ extern (C++) final class TypeClass : Type AliasThisRec att = AliasThisRec.fwdref; CPPMANGLE cppmangle = CPPMANGLE.def; - extern (D) this(ClassDeclaration sym) + extern (D) this(ClassDeclaration sym) @safe { super(Tclass); this.sym = sym; @@ -6184,7 +6184,7 @@ extern (C++) final class TypeTuple : Type Parameters* arguments; // types making up the tuple - extern (D) this(Parameters* arguments) + extern (D) this(Parameters* arguments) @safe { super(Ttuple); //printf("TypeTuple(this = %p)\n", this); @@ -6226,7 +6226,7 @@ extern (C++) final class TypeTuple : Type //printf("TypeTuple() %p, %s\n", this, toChars()); } - static TypeTuple create(Parameters* arguments) + static TypeTuple create(Parameters* arguments) @safe { return new TypeTuple(arguments); } @@ -6234,7 +6234,7 @@ extern (C++) final class TypeTuple : Type /******************************************* * Type tuple with 0, 1 or 2 types in it. */ - extern (D) this() + extern (D) this() @safe { super(Ttuple); arguments = new Parameters(); @@ -6255,7 +6255,7 @@ extern (C++) final class TypeTuple : Type arguments.push(new Parameter(0, t2, null, null, null)); } - static TypeTuple create() + static TypeTuple create() @safe { return new TypeTuple(); } @@ -6343,7 +6343,7 @@ extern (C++) final class TypeSlice : TypeNext Expression lwr; Expression upr; - extern (D) this(Type next, Expression lwr, Expression upr) + extern (D) this(Type next, Expression lwr, Expression upr) @safe { super(Tslice, next); //printf("TypeSlice[%s .. %s]\n", lwr.toChars(), upr.toChars()); @@ -6373,7 +6373,7 @@ extern (C++) final class TypeSlice : TypeNext */ extern (C++) final class TypeNull : Type { - extern (D) this() + extern (D) this() @safe { //printf("TypeNull %p\n", this); super(Tnull); @@ -6438,7 +6438,7 @@ extern (C++) final class TypeNull : Type */ extern (C++) final class TypeNoreturn : Type { - extern (D) this() + extern (D) this() @safe { //printf("TypeNoreturn %p\n", this); super(Tnoreturn); @@ -6520,7 +6520,7 @@ extern (C++) final class TypeTag : Type /// struct S { int a; } s1, *s2; MOD mod; /// modifiers to apply after type is resolved (only MODFlags.const_ at the moment) - extern (D) this(const ref Loc loc, TOK tok, Identifier id, structalign_t packalign, Type base, Dsymbols* members) + extern (D) this(const ref Loc loc, TOK tok, Identifier id, structalign_t packalign, Type base, Dsymbols* members) @safe { //printf("TypeTag ctor %s %p\n", id ? id.toChars() : "null".ptr, this); super(Ttag); @@ -6564,7 +6564,7 @@ extern (C++) struct ParameterList VarArg varargs = VarArg.none; bool hasIdentifierList; // true if C identifier-list style - this(Parameters* parameters, VarArg varargs = VarArg.none, StorageClass stc = 0) + this(Parameters* parameters, VarArg varargs = VarArg.none, StorageClass stc = 0) @safe { this.parameters = parameters; this.varargs = varargs; @@ -6667,7 +6667,7 @@ extern (C++) final class Parameter : ASTNode Expression defaultArg; UserAttributeDeclaration userAttribDecl; // user defined attributes - extern (D) this(StorageClass storageClass, Type type, Identifier ident, Expression defaultArg, UserAttributeDeclaration userAttribDecl) + extern (D) this(StorageClass storageClass, Type type, Identifier ident, Expression defaultArg, UserAttributeDeclaration userAttribDecl) @safe { this.type = type; this.ident = ident; @@ -6676,7 +6676,7 @@ extern (C++) final class Parameter : ASTNode this.userAttribDecl = userAttribDecl; } - static Parameter create(StorageClass storageClass, Type type, Identifier ident, Expression defaultArg, UserAttributeDeclaration userAttribDecl) + static Parameter create(StorageClass storageClass, Type type, Identifier ident, Expression defaultArg, UserAttributeDeclaration userAttribDecl) @safe { return new Parameter(storageClass, type, ident, defaultArg, userAttribDecl); } @@ -7646,7 +7646,7 @@ mixin template VisitType(Result) * handler = string for the name of the visit handler * Returns: boilerplate code for a case */ -pure string visitTYCase(string handler) +pure string visitTYCase(string handler) @safe { if (__ctfe) { diff --git a/gcc/d/dmd/mtype.h b/gcc/d/dmd/mtype.h index fbfd766..457b91f 100644 --- a/gcc/d/dmd/mtype.h +++ b/gcc/d/dmd/mtype.h @@ -123,8 +123,9 @@ enum VarArgValues { VARARGnone = 0, /// fixed number of arguments VARARGvariadic = 1, /// T t, ...) can be C-style (core.stdc.stdarg) or D-style (core.vararg) - VARARGtypesafe = 2 /// T t ...) typesafe https://dlang.org/spec/function.html#typesafe_variadic_functions + VARARGtypesafe = 2, /// T t ...) typesafe https://dlang.org/spec/function.html#typesafe_variadic_functions /// or https://dlang.org/spec/function.html#typesafe_variadic_functions + VARARGKRvariadic = 3 /// K+R C style variadics (no function prototype) }; typedef unsigned char VarArg; diff --git a/gcc/d/dmd/mustuse.d b/gcc/d/dmd/mustuse.d index 11cc3b8d..844f719 100644 --- a/gcc/d/dmd/mustuse.d +++ b/gcc/d/dmd/mustuse.d @@ -18,11 +18,11 @@ import dmd.identifier; import dmd.location; // Used in isIncrementOrDecrement -private static const StringExp plusPlus, minusMinus; +private const StringExp plusPlus, minusMinus; // Loc.initial cannot be used in static initializers, so // these need a static constructor. -static this() +shared static this() { plusPlus = new StringExp(Loc.initial, "++"); minusMinus = new StringExp(Loc.initial, "--"); diff --git a/gcc/d/dmd/nogc.d b/gcc/d/dmd/nogc.d index d7a2820..01a6832 100644 --- a/gcc/d/dmd/nogc.d +++ b/gcc/d/dmd/nogc.d @@ -19,6 +19,7 @@ import dmd.aggregate; import dmd.astenums; import dmd.declaration; import dmd.dscope; +import dmd.dtemplate : isDsymbol; import dmd.errors; import dmd.expression; import dmd.func; @@ -40,7 +41,7 @@ public: bool checkOnly; // don't print errors bool err; - extern (D) this(FuncDeclaration f) scope + extern (D) this(FuncDeclaration f) scope @safe { this.f = f; } @@ -263,6 +264,7 @@ private FuncDeclaration stripHookTraceImpl(FuncDeclaration fd) // Get the Hook from the second template parameter auto templateInstance = fd.parent.isTemplateInstance; RootObject hook = (*templateInstance.tiargs)[1]; - assert(hook.dyncast() == DYNCAST.dsymbol, "Expected _d_HookTraceImpl's second template parameter to be an alias to the hook!"); - return (cast(Dsymbol)hook).isFuncDeclaration; + Dsymbol s = hook.isDsymbol(); + assert(s, "Expected _d_HookTraceImpl's second template parameter to be an alias to the hook!"); + return s.isFuncDeclaration; } diff --git a/gcc/d/dmd/ob.d b/gcc/d/dmd/ob.d index 56243a0..4774d1f 100644 --- a/gcc/d/dmd/ob.d +++ b/gcc/d/dmd/ob.d @@ -145,7 +145,7 @@ enum ObType : ubyte fend, } -string toString(ObType obtype) +string toString(ObType obtype) @safe { return obtype == ObType.goto_ ? "goto " : obtype == ObType.return_ ? "ret " : @@ -202,7 +202,7 @@ const(char)* toChars(PtrState state) return toString(state).ptr; } -string toString(PtrState state) +string toString(PtrState state) @safe { return ["Initial", "Undefined", "Owner", "Borrowed", "Readonly"][state]; } @@ -1012,7 +1012,7 @@ void insertFinallyBlockGotos(ref ObNodes obnodes) * Set the `index` field of each ObNode * to its index in the `obnodes[]` array. */ -void numberNodes(ref ObNodes obnodes) +void numberNodes(ref ObNodes obnodes) @safe { //printf("numberNodes()\n"); foreach (i, ob; obnodes) diff --git a/gcc/d/dmd/objc.d b/gcc/d/dmd/objc.d index c493323..623a362 100644 --- a/gcc/d/dmd/objc.d +++ b/gcc/d/dmd/objc.d @@ -58,7 +58,7 @@ struct ObjcSelector stringtable._init(); } - extern (D) this(const(char)* sv, size_t len, size_t pcount) + extern (D) this(const(char)* sv, size_t len, size_t pcount) @safe { stringvalue = sv; stringlen = len; @@ -119,7 +119,7 @@ struct ObjcSelector buf.writeByte('_'); foreach (i, fparam; ftype.parameterList) { - mangleToBuffer(fparam.type, &buf); + mangleToBuffer(fparam.type, buf); buf.writeByte(':'); } } @@ -167,12 +167,12 @@ extern (C++) struct ObjcClassDeclaration /// List of non-inherited methods. FuncDeclaration[] methodList; - extern (D) this(ClassDeclaration classDeclaration) + extern (D) this(ClassDeclaration classDeclaration) @safe { this.classDeclaration = classDeclaration; } - bool isRootClass() const + bool isRootClass() const @safe { return classDeclaration.classKind == ClassKind.objc && !metaclass && diff --git a/gcc/d/dmd/opover.d b/gcc/d/dmd/opover.d index 8b42a91..457e8b6 100644 --- a/gcc/d/dmd/opover.d +++ b/gcc/d/dmd/opover.d @@ -43,7 +43,7 @@ import dmd.visitor; * Determine if operands of binary op can be reversed * to fit operator overload. */ -bool isCommutative(EXP op) +bool isCommutative(EXP op) @safe { switch (op) { @@ -1840,7 +1840,7 @@ private bool matchParamsToOpApply(TypeFunction tf, Parameters* parameters, bool * Returns: * reverse of op */ -private EXP reverseRelation(EXP op) pure +private EXP reverseRelation(EXP op) pure @safe { switch (op) { diff --git a/gcc/d/dmd/parse.d b/gcc/d/dmd/parse.d index d15e448..13bba4f 100644 --- a/gcc/d/dmd/parse.d +++ b/gcc/d/dmd/parse.d @@ -1222,7 +1222,10 @@ class Parser(AST, Lexer = dmd.lexer.Lexer) : Lexer (orig & STC.scope_) ? "scope".ptr : "ref".ptr); } else if (added & STC.ref_) - deprecation("using `in ref` is deprecated, use `-preview=in` and `in` instead"); + { + // accept for legacy compatibility + //deprecation("using `in ref` is deprecated, use `-preview=in` and `in` instead"); + } else error("attribute `scope` cannot be applied with `in`, use `-preview=in` instead"); return orig; @@ -1240,7 +1243,10 @@ class Parser(AST, Lexer = dmd.lexer.Lexer) : Lexer stc_str, stc_str); } else if (orig & STC.ref_) - deprecation("using `ref in` is deprecated, use `-preview=in` and `in` instead"); + { + // accept for legacy compatibility + //deprecation("using `in ref` is deprecated, use `-preview=in` and `in` instead"); + } else error("attribute `in` cannot be added after `scope`: remove `scope` and use `-preview=in`"); return orig; @@ -3042,7 +3048,6 @@ class Parser(AST, Lexer = dmd.lexer.Lexer) : Lexer else if (token.value == TOK.leftCurly) { bool isAnonymousEnum = !id; - TOK prevTOK; //printf("enum definition\n"); e.members = new AST.Dsymbols(); @@ -3065,9 +3070,8 @@ class Parser(AST, Lexer = dmd.lexer.Lexer) : Lexer StorageClass stc; AST.Expression deprecationMessage; enum attributeErrorMessage = "`%s` is not a valid attribute for enum members"; - while(token.value != TOK.rightCurly - && token.value != TOK.comma - && token.value != TOK.assign) + Lattrs: + while (1) { switch (token.value) { @@ -3082,7 +3086,6 @@ class Parser(AST, Lexer = dmd.lexer.Lexer) : Lexer AST.stcToBuffer(&buf, _stc); error(attributeErrorMessage, buf.peekChars()); } - prevTOK = token.value; nextToken(); } break; @@ -3090,94 +3093,86 @@ class Parser(AST, Lexer = dmd.lexer.Lexer) : Lexer stc |= STC.deprecated_; if (!parseDeprecatedAttribute(deprecationMessage)) { - prevTOK = token.value; - nextToken(); - } - break; - case TOK.identifier: - const tv = peekNext(); - if (tv == TOK.assign || tv == TOK.comma || tv == TOK.rightCurly) - { - ident = token.ident; - type = null; - prevTOK = token.value; nextToken(); } - else - { - if (isAnonymousEnum) - goto default; // maybe `Type identifier` - - prevTOK = token.value; - nextToken(); - error("expected `,` or `=` after identifier, not `%s`", token.toChars()); - } break; default: - if (isAnonymousEnum) - { - if (type) - { - error("expected identifier after type, not `%s`", token.toChars()); - type = null; - break; - } - type = parseType(&ident, null); - if (type == AST.Type.terror) - { - type = null; - prevTOK = token.value; - nextToken(); - } - else - { - prevTOK = TOK.identifier; - const tv = token.value; - if (ident && tv != TOK.assign && tv != TOK.comma && tv != TOK.rightCurly) - { - error("expected `,` or `=` after identifier, not `%s`", token.toChars()); - } - } - } - else - { - error(attributeErrorMessage, token.toChars()); - prevTOK = token.value; - nextToken(); - } - break; + break Lattrs; } - if (token.value == TOK.comma) + } + if (token.value == TOK.identifier) + { + const tv = peekNext(); + if (tv == TOK.assign || tv == TOK.comma || tv == TOK.rightCurly) { - prevTOK = token.value; + ident = token.ident; + type = null; + nextToken(); } - } + else + { + if (isAnonymousEnum) + goto Ltype; - if (type && type != AST.Type.terror) - { - if (!ident) - error("no identifier for declarator `%s`", type.toChars()); - if (!isAnonymousEnum) - error("type only allowed if anonymous enum and no enum type"); + nextToken(); + error("expected `,` or `=` after identifier, not `%s`", token.toChars()); + } } - AST.Expression value; - if (token.value == TOK.assign) + else { - if (prevTOK == TOK.identifier) + if (isAnonymousEnum) { - nextToken(); - value = parseAssignExp(); + Ltype: + // Type identifier + type = parseType(&ident, null); + if (type == AST.Type.terror) + { + type = null; + nextToken(); + } + else if (!ident) + { + error("no identifier for declarator `%s`", type.toChars()); + type = null; + } + else + { + const tv = token.value; + if (tv != TOK.assign && tv != TOK.comma && tv != TOK.rightCurly) + { + error("expected `,` or `=` after identifier, not `%s`", token.toChars()); + nextToken(); + } + } } else { - error("assignment must be preceded by an identifier"); - nextToken(); + Token* t = &token; + if (isBasicType(&t)) + { + error("named enum cannot declare member with type", (*t).toChars()); + nextToken(); + } + else + check(TOK.identifier); + + // avoid extra error messages + const tv = token.value; + if (tv != TOK.assign && tv != TOK.comma && tv != TOK.rightCurly && tv != TOK.endOfFile) + continue; } } + + AST.Expression value; + if (token.value == TOK.assign) + { + nextToken(); + value = parseAssignExp(); + } else { value = null; - if (type && type != AST.Type.terror && isAnonymousEnum) + if (type && isAnonymousEnum) error("initializer required after `%s` when type is specified", ident.toChars()); } @@ -3197,10 +3192,7 @@ class Parser(AST, Lexer = dmd.lexer.Lexer) : Lexer em.userAttribDecl = uad; } - if (token.value == TOK.rightCurly) - { - } - else + if (token.value != TOK.rightCurly) { addComment(em, comment); comment = null; @@ -3218,8 +3210,10 @@ class Parser(AST, Lexer = dmd.lexer.Lexer) : Lexer nextToken(); } else - error("enum declaration is invalid"); - + { + nextToken(); + error("expected `{`, not `%s` for enum declaration", token.toChars()); + } //printf("-parseEnum() %s\n", e.toChars()); return e; } @@ -4611,6 +4605,13 @@ class Parser(AST, Lexer = dmd.lexer.Lexer) : Lexer */ if (tpl) { + // @@@DEPRECATED_2.114@@@ + // Both deprecated in 2.104, change to error + if (storage_class & STC.override_) + deprecation(loc, "a function template is not virtual so cannot be marked `override`"); + else if (storage_class & STC.abstract_) + deprecation(loc, "a function template is not virtual so cannot be marked `abstract`"); + // Wrap a template around the function declaration auto decldefs = new AST.Dsymbols(); decldefs.push(s); @@ -5622,60 +5623,61 @@ class Parser(AST, Lexer = dmd.lexer.Lexer) : Lexer AST.Parameter param = null; StorageClass storageClass = 0; StorageClass stc = 0; -LagainStc: - if (stc) - { - storageClass = appendStorageClass(storageClass, stc); - nextToken(); - } - switch (token.value) + Lwhile: + while (1) { - case TOK.ref_: - stc = STC.ref_; - goto LagainStc; + switch (token.value) + { + // parse ref for better error + case TOK.ref_: + stc = STC.ref_; + break; - case TOK.scope_: - stc = STC.scope_; - goto LagainStc; + case TOK.scope_: + stc = STC.scope_; + break; - case TOK.auto_: - stc = STC.auto_; - goto LagainStc; + case TOK.auto_: + stc = STC.auto_; + break; - case TOK.const_: - if (peekNext() != TOK.leftParenthesis) - { - stc = STC.const_; - goto LagainStc; - } - break; + case TOK.const_: + if (peekNext() != TOK.leftParenthesis) + { + stc = STC.const_; + break; + } + goto default; - case TOK.immutable_: - if (peekNext() != TOK.leftParenthesis) - { - stc = STC.immutable_; - goto LagainStc; - } - break; + case TOK.immutable_: + if (peekNext() != TOK.leftParenthesis) + { + stc = STC.immutable_; + break; + } + goto default; - case TOK.shared_: - if (peekNext() != TOK.leftParenthesis) - { - stc = STC.shared_; - goto LagainStc; - } - break; + case TOK.shared_: + if (peekNext() != TOK.leftParenthesis) + { + stc = STC.shared_; + break; + } + goto default; - case TOK.inout_: - if (peekNext() != TOK.leftParenthesis) - { - stc = STC.wild; - goto LagainStc; - } - break; + case TOK.inout_: + if (peekNext() != TOK.leftParenthesis) + { + stc = STC.wild; + break; + } + goto default; - default: - break; + default: + break Lwhile; + } + storageClass = appendStorageClass(storageClass, stc); + nextToken(); } auto n = peek(&token); if (storageClass != 0 && token.value == TOK.identifier && n.value == TOK.assign) @@ -8709,7 +8711,8 @@ LagainStc: nextToken(); if (token.value != TOK.identifier) { - error("identifier expected following `(type)`."); + error("identifier expected following `%s.`, not `%s`", + t.toChars(), token.toChars()); return AST.ErrorExp.get(); } e = new AST.DotIdExp(loc, new AST.TypeExp(loc, t), token.ident); @@ -8721,7 +8724,8 @@ LagainStc: e = new AST.TypeExp(loc, t); if (token.value != TOK.leftParenthesis) { - error("`(arguments)` expected following `%s`", t.toChars()); + error("`(arguments)` expected following `%s`, not `%s`", + t.toChars(), token.toChars()); return e; } e = new AST.CallExp(loc, e, parseArguments()); diff --git a/gcc/d/dmd/postordervisitor.d b/gcc/d/dmd/postordervisitor.d index a0c7115..70bd130 100644 --- a/gcc/d/dmd/postordervisitor.d +++ b/gcc/d/dmd/postordervisitor.d @@ -40,7 +40,7 @@ private extern (C++) final class PostorderExpressionVisitor : StoppableVisitor public: StoppableVisitor v; - extern (D) this(StoppableVisitor v) scope + extern (D) this(StoppableVisitor v) scope @safe { this.v = v; } diff --git a/gcc/d/dmd/printast.d b/gcc/d/dmd/printast.d index 8c01095..e43ffad 100644 --- a/gcc/d/dmd/printast.d +++ b/gcc/d/dmd/printast.d @@ -39,7 +39,7 @@ extern (C++) final class PrintASTVisitor : Visitor int indent; - extern (D) this(int indent) scope + extern (D) this(int indent) scope @safe { this.indent = indent; } diff --git a/gcc/d/dmd/root/complex.d b/gcc/d/dmd/root/complex.d index fc93bd7..57d1e34 100644 --- a/gcc/d/dmd/root/complex.d +++ b/gcc/d/dmd/root/complex.d @@ -29,7 +29,7 @@ extern (C++) struct complex_t this(re, CTFloat.zero); } - this(real_t re, real_t im) + this(real_t re, real_t im) @safe { this.re = re; this.im = im; @@ -99,18 +99,18 @@ extern (C++) struct complex_t return re || im; } - int opEquals(complex_t y) const + int opEquals(complex_t y) const @safe { return re == y.re && im == y.im; } } -extern (C++) real_t creall(complex_t x) +extern (C++) real_t creall(complex_t x) @safe { return x.re; } -extern (C++) real_t cimagl(complex_t x) +extern (C++) real_t cimagl(complex_t x) @safe { return x.im; } diff --git a/gcc/d/dmd/root/filename.d b/gcc/d/dmd/root/filename.d index 3873615..987c793 100644 --- a/gcc/d/dmd/root/filename.d +++ b/gcc/d/dmd/root/filename.d @@ -41,9 +41,6 @@ version (Windows) extern (Windows) DWORD GetFullPathNameW(LPCWSTR, DWORD, LPWSTR, LPWSTR*) nothrow @nogc; extern (Windows) void SetLastError(DWORD) nothrow @nogc; extern (C) char* getcwd(char* buffer, size_t maxlen) nothrow; - - // assume filenames encoded in system default Windows ANSI code page - private enum CodePage = CP_ACP; } version (CRuntime_Glibc) @@ -127,7 +124,7 @@ nothrow: } /// Ditto - extern (D) static bool absolute(const(char)[] name) pure @nogc + extern (D) static bool absolute(const(char)[] name) pure @nogc @safe { if (!name.length) return false; @@ -280,7 +277,7 @@ nothrow: } /// Ditto - extern (D) static const(char)[] name(const(char)[] str) pure @nogc + extern (D) static const(char)[] name(const(char)[] str) pure @nogc @safe { foreach_reverse (idx, char e; str) { @@ -1147,6 +1144,8 @@ version(Windows) */ char[] toNarrowStringz(const(wchar)[] wide, char[] buffer = null) nothrow { + import dmd.common.file : CodePage; + if (wide is null) return null; diff --git a/gcc/d/dmd/root/longdouble.d b/gcc/d/dmd/root/longdouble.d index 5bbed22..8702365 100644 --- a/gcc/d/dmd/root/longdouble.d +++ b/gcc/d/dmd/root/longdouble.d @@ -25,12 +25,15 @@ import core.stdc.stdint; extern(C++): nothrow: @nogc: +pure: +@trusted: // Type used by the front-end for compile-time reals struct longdouble { nothrow: @nogc: +pure: extern (D) this(T)(T r) { this.set(cast(SetType!T)r); diff --git a/gcc/d/dmd/root/rmem.d b/gcc/d/dmd/root/rmem.d index 9b1d9fb..cff5c4c 100644 --- a/gcc/d/dmd/root/rmem.d +++ b/gcc/d/dmd/root/rmem.d @@ -110,7 +110,7 @@ extern (C++) struct Mem * Returns: * p if not null */ - static void* check(void* p) pure nothrow @nogc + static void* check(void* p) pure nothrow @nogc @safe { return p ? p : error(); } diff --git a/gcc/d/dmd/root/utf.d b/gcc/d/dmd/root/utf.d index c9781a4..d7ba17f 100644 --- a/gcc/d/dmd/root/utf.d +++ b/gcc/d/dmd/root/utf.d @@ -11,7 +11,7 @@ module dmd.root.utf; -nothrow pure @nogc: +@nogc nothrow pure @safe: /// The Unicode code space is the range of code points [0x000000,0x10FFFF] /// except the UTF-16 surrogate pairs in the range [0xD800,0xDFFF] @@ -337,7 +337,7 @@ int utf_codeLength(int sz, dchar c) return 1; } -void utf_encodeChar(char* s, dchar c) +void utf_encodeChar(char* s, dchar c) @system { assert(s !is null); assert(utf_isValidDchar(c)); @@ -367,7 +367,7 @@ void utf_encodeChar(char* s, dchar c) assert(0); } -void utf_encodeWchar(wchar* s, dchar c) +void utf_encodeWchar(wchar* s, dchar c) @system { assert(s !is null); assert(utf_isValidDchar(c)); @@ -382,7 +382,7 @@ void utf_encodeWchar(wchar* s, dchar c) } } -void utf_encode(int sz, void* s, dchar c) +void utf_encode(int sz, void* s, dchar c) @system { if (sz == 1) utf_encodeChar(cast(char*)s, c); @@ -399,7 +399,7 @@ void utf_encode(int sz, void* s, dchar c) * Checks whether an Unicode code point is a bidirectional * control character. */ -@safe bool isBidiControl(dchar c) +bool isBidiControl(dchar c) { // Source: https://www.unicode.org/versions/Unicode15.0.0, table 23-3. switch(c) diff --git a/gcc/d/dmd/sapply.d b/gcc/d/dmd/sapply.d index ef01516..13fe691 100644 --- a/gcc/d/dmd/sapply.d +++ b/gcc/d/dmd/sapply.d @@ -37,7 +37,7 @@ private extern (C++) final class PostorderStatementVisitor : StoppableVisitor public: StoppableVisitor v; - extern (D) this(StoppableVisitor v) scope + extern (D) this(StoppableVisitor v) scope @safe { this.v = v; } diff --git a/gcc/d/dmd/scope.h b/gcc/d/dmd/scope.h index da11428..3c4ae49 100644 --- a/gcc/d/dmd/scope.h +++ b/gcc/d/dmd/scope.h @@ -10,6 +10,7 @@ #pragma once +class ErrorSink; class Identifier; class Module; class Statement; @@ -85,6 +86,7 @@ struct Scope d_bool inLoop; // true if inside a loop (where constructor calls aren't allowed) int intypeof; // in typeof(exp) VarDeclaration *lastVar; // Previous symbol used to prevent goto-skips-init + ErrorSink *eSink; // sink for error messages /* If minst && !tinst, it's in definitely non-speculative scope (eg. module member scope). * If !minst && !tinst, it's in definitely speculative scope (eg. template constraint). diff --git a/gcc/d/dmd/semantic2.d b/gcc/d/dmd/semantic2.d index 3cbf14f..53c8714 100644 --- a/gcc/d/dmd/semantic2.d +++ b/gcc/d/dmd/semantic2.d @@ -83,7 +83,7 @@ private extern(C++) final class Semantic2Visitor : Visitor { alias visit = Visitor.visit; Scope* sc; - this(Scope* sc) scope + this(Scope* sc) scope @safe { this.sc = sc; } @@ -245,8 +245,9 @@ private extern(C++) final class Semantic2Visitor : Visitor return; //printf("VarDeclaration::semantic2('%s')\n", toChars()); + sc = sc.push(); sc.varDecl = vd; - scope(exit) sc.varDecl = null; + scope(exit) sc = sc.pop(); if (vd.aliasTuple) // if it's a tuple { @@ -345,7 +346,7 @@ private extern(C++) final class Semantic2Visitor : Visitor // Note that modules get their own scope, from scratch. // This is so regardless of where in the syntax a module // gets imported, it is unaffected by context. - Scope* sc = Scope.createGlobal(mod); // create root scope + Scope* sc = Scope.createGlobal(mod, global.errorSink); // create root scope //printf("Module = %p\n", sc.scopesym); if (mod.members) { diff --git a/gcc/d/dmd/semantic3.d b/gcc/d/dmd/semantic3.d index c7d1219..bff89f8 100644 --- a/gcc/d/dmd/semantic3.d +++ b/gcc/d/dmd/semantic3.d @@ -88,7 +88,7 @@ private extern(C++) final class Semantic3Visitor : Visitor alias visit = Visitor.visit; Scope* sc; - this(Scope* sc) scope + this(Scope* sc) scope @safe { this.sc = sc; } @@ -193,7 +193,7 @@ private extern(C++) final class Semantic3Visitor : Visitor // Note that modules get their own scope, from scratch. // This is so regardless of where in the syntax a module // gets imported, it is unaffected by context. - Scope* sc = Scope.createGlobal(mod); // create root scope + Scope* sc = Scope.createGlobal(mod, global.errorSink); // create root scope //printf("Module = %p\n", sc.scopesym); if (mod.members) { @@ -705,7 +705,7 @@ private extern(C++) final class Semantic3Visitor : Visitor } sc2.ctorflow.freeFieldinit(); - if (cd && !(sc2.ctorflow.callSuper & CSX.any_ctor) && cd.baseClass && cd.baseClass.ctor) + if (cd && !(sc2.ctorflow.callSuper & (CSX.any_ctor | CSX.halt)) && cd.baseClass && cd.baseClass.ctor) { sc2.ctorflow.callSuper = CSX.none; @@ -1423,7 +1423,7 @@ private extern(C++) final class Semantic3Visitor : Visitor */ AggregateDeclaration ad = ctor.isMemberDecl(); if (!ctor.fbody || !ad || !ad.fieldDtor || - global.params.dtorFields == FeatureState.disabled || !global.params.useExceptions || ctor.type.toTypeFunction.isnothrow) + global.params.dtorFields == FeatureState.disabled || !global.params.useExceptions || ctor.type.toTypeFunction.isnothrow) return visit(cast(FuncDeclaration)ctor); /* Generate: @@ -1602,7 +1602,7 @@ private struct FuncDeclSem3 // Scope of analysis Scope* sc; - this(FuncDeclaration fd,Scope* s) scope + this(FuncDeclaration fd,Scope* s) scope @safe { funcdecl = fd; sc = s; diff --git a/gcc/d/dmd/sideeffect.d b/gcc/d/dmd/sideeffect.d index 90b86df..30921c6 100644 --- a/gcc/d/dmd/sideeffect.d +++ b/gcc/d/dmd/sideeffect.d @@ -37,7 +37,7 @@ extern (C++) bool isTrivialExp(Expression e) { alias visit = typeof(super).visit; public: - extern (D) this() scope + extern (D) this() scope @safe { } @@ -75,7 +75,7 @@ extern (C++) bool hasSideEffect(Expression e, bool assumeImpureCalls = false) { alias visit = typeof(super).visit; public: - extern (D) this() scope + extern (D) this() scope @safe { } diff --git a/gcc/d/dmd/statement.d b/gcc/d/dmd/statement.d index 3ccf228..607dd51 100644 --- a/gcc/d/dmd/statement.d +++ b/gcc/d/dmd/statement.d @@ -84,7 +84,7 @@ extern (C++) abstract class Statement : ASTNode return DYNCAST.statement; } - final extern (D) this(const ref Loc loc, STMT stmt) + final extern (D) this(const ref Loc loc, STMT stmt) @safe { this.loc = loc; this.stmt = stmt; @@ -129,7 +129,7 @@ extern (C++) abstract class Statement : ASTNode { va_list ap; va_start(ap, format); - .verror(loc, format, ap); + .verrorReport(loc, format, ap, ErrorKind.error); va_end(ap); } @@ -137,7 +137,7 @@ extern (C++) abstract class Statement : ASTNode { va_list ap; va_start(ap, format); - .vwarning(loc, format, ap); + .verrorReport(loc, format, ap, ErrorKind.warning); va_end(ap); } @@ -145,7 +145,7 @@ extern (C++) abstract class Statement : ASTNode { va_list ap; va_start(ap, format); - .vdeprecation(loc, format, ap); + .verrorReport(loc, format, ap, ErrorKind.deprecation); va_end(ap); } } @@ -155,7 +155,7 @@ extern (C++) abstract class Statement : ASTNode { va_list ap; va_start(ap, format); - .verror(loc, format, ap); + .verrorReport(loc, format, ap, ErrorKind.error); va_end(ap); } @@ -163,7 +163,7 @@ extern (C++) abstract class Statement : ASTNode { va_list ap; va_start(ap, format); - .vwarning(loc, format, ap); + .verrorReport(loc, format, ap, ErrorKind.warning); va_end(ap); } @@ -171,7 +171,7 @@ extern (C++) abstract class Statement : ASTNode { va_list ap; va_start(ap, format); - .vdeprecation(loc, format, ap); + .verrorReport(loc, format, ap, ErrorKind.deprecation); va_end(ap); } } @@ -447,7 +447,7 @@ extern (C++) final class PeelStatement : Statement { Statement s; - extern (D) this(Statement s) + extern (D) this(Statement s) @safe { super(s.loc, STMT.Peel); this.s = s; @@ -467,25 +467,25 @@ extern (C++) class ExpStatement : Statement { Expression exp; - final extern (D) this(const ref Loc loc, Expression exp) + final extern (D) this(const ref Loc loc, Expression exp) @safe { super(loc, STMT.Exp); this.exp = exp; } - final extern (D) this(const ref Loc loc, Expression exp, STMT stmt) + final extern (D) this(const ref Loc loc, Expression exp, STMT stmt) @safe { super(loc, stmt); this.exp = exp; } - final extern (D) this(const ref Loc loc, Dsymbol declaration) + final extern (D) this(const ref Loc loc, Dsymbol declaration) @safe { super(loc, STMT.Exp); this.exp = new DeclarationExp(loc, declaration); } - static ExpStatement create(const ref Loc loc, Expression exp) + static ExpStatement create(const ref Loc loc, Expression exp) @safe { return new ExpStatement(loc, exp); } @@ -508,7 +508,7 @@ extern (C++) final class DtorExpStatement : ExpStatement // Wraps an expression that is the destruction of 'var' VarDeclaration var; - extern (D) this(const ref Loc loc, Expression exp, VarDeclaration var) + extern (D) this(const ref Loc loc, Expression exp, VarDeclaration var) @safe { super(loc, exp, STMT.DtorExp); this.var = var; @@ -540,7 +540,7 @@ extern (C++) final class MixinStatement : Statement this(loc, exps); } - extern (D) this(const ref Loc loc, Expressions* exps) + extern (D) this(const ref Loc loc, Expressions* exps) @safe { super(loc, STMT.Mixin); this.exps = exps; @@ -571,13 +571,13 @@ extern (C++) class CompoundStatement : Statement * loc = Instantiation information * statements = An array of `Statement`s, that will referenced by this class */ - final extern (D) this(const ref Loc loc, Statements* statements) + final extern (D) this(const ref Loc loc, Statements* statements) @safe { super(loc, STMT.Compound); this.statements = statements; } - final extern (D) this(const ref Loc loc, Statements* statements, STMT stmt) + final extern (D) this(const ref Loc loc, Statements* statements, STMT stmt) @safe { super(loc, stmt); this.statements = statements; @@ -649,7 +649,7 @@ extern (C++) class CompoundStatement : Statement */ extern (C++) final class CompoundDeclarationStatement : CompoundStatement { - extern (D) this(const ref Loc loc, Statements* statements) + extern (D) this(const ref Loc loc, Statements* statements) @safe { super(loc, statements, STMT.CompoundDeclaration); } @@ -678,7 +678,7 @@ extern (C++) final class UnrolledLoopStatement : Statement { Statements* statements; - extern (D) this(const ref Loc loc, Statements* statements) + extern (D) this(const ref Loc loc, Statements* statements) @safe { super(loc, STMT.UnrolledLoop); this.statements = statements; @@ -717,7 +717,7 @@ extern (C++) final class ScopeStatement : Statement Statement statement; Loc endloc; // location of closing curly bracket - extern (D) this(const ref Loc loc, Statement statement, Loc endloc) + extern (D) this(const ref Loc loc, Statement statement, Loc endloc) @safe { super(loc, STMT.Scope); this.statement = statement; @@ -767,7 +767,7 @@ extern (C++) final class ForwardingStatement : Statement /// The wrapped statement. Statement statement; - extern (D) this(const ref Loc loc, ForwardingScopeDsymbol sym, Statement statement) + extern (D) this(const ref Loc loc, ForwardingScopeDsymbol sym, Statement statement) @safe { super(loc, STMT.Forwarding); this.sym = sym; @@ -775,7 +775,7 @@ extern (C++) final class ForwardingStatement : Statement this.statement = statement; } - extern (D) this(const ref Loc loc, Statement statement) + extern (D) this(const ref Loc loc, Statement statement) @safe { auto sym = new ForwardingScopeDsymbol(); sym.symtab = new DsymbolTable(); @@ -804,7 +804,7 @@ extern (C++) final class WhileStatement : Statement Statement _body; Loc endloc; // location of closing curly bracket - extern (D) this(const ref Loc loc, Expression condition, Statement _body, Loc endloc, Parameter param = null) + extern (D) this(const ref Loc loc, Expression condition, Statement _body, Loc endloc, Parameter param = null) @safe { super(loc, STMT.While); this.condition = condition; @@ -846,7 +846,7 @@ extern (C++) final class DoStatement : Statement Expression condition; Loc endloc; // location of ';' after while - extern (D) this(const ref Loc loc, Statement _body, Expression condition, Loc endloc) + extern (D) this(const ref Loc loc, Statement _body, Expression condition, Loc endloc) @safe { super(loc, STMT.Do); this._body = _body; @@ -894,7 +894,7 @@ extern (C++) final class ForStatement : Statement // treat that label as referring to this loop. Statement relatedLabeled; - extern (D) this(const ref Loc loc, Statement _init, Expression condition, Expression increment, Statement _body, Loc endloc) + extern (D) this(const ref Loc loc, Statement _init, Expression condition, Expression increment, Statement _body, Loc endloc) @safe { super(loc, STMT.For); this._init = _init; @@ -955,7 +955,7 @@ extern (C++) final class ForeachStatement : Statement Statements* cases; // put breaks, continues, gotos and returns here ScopeStatements* gotos; // forward referenced goto's go here - extern (D) this(const ref Loc loc, TOK op, Parameters* parameters, Expression aggr, Statement _body, Loc endloc) + extern (D) this(const ref Loc loc, TOK op, Parameters* parameters, Expression aggr, Statement _body, Loc endloc) @safe { super(loc, STMT.Foreach); this.op = op; @@ -1004,7 +1004,7 @@ extern (C++) final class ForeachRangeStatement : Statement VarDeclaration key; - extern (D) this(const ref Loc loc, TOK op, Parameter prm, Expression lwr, Expression upr, Statement _body, Loc endloc) + extern (D) this(const ref Loc loc, TOK op, Parameter prm, Expression lwr, Expression upr, Statement _body, Loc endloc) @safe { super(loc, STMT.ForeachRange); this.op = op; @@ -1048,7 +1048,7 @@ extern (C++) final class IfStatement : Statement VarDeclaration match; // for MatchExpression results Loc endloc; // location of closing curly bracket - extern (D) this(const ref Loc loc, Parameter prm, Expression condition, Statement ifbody, Statement elsebody, Loc endloc) + extern (D) this(const ref Loc loc, Parameter prm, Expression condition, Statement ifbody, Statement elsebody, Loc endloc) @safe { super(loc, STMT.If); this.prm = prm; @@ -1093,7 +1093,7 @@ extern (C++) final class ConditionalStatement : Statement Statement ifbody; Statement elsebody; - extern (D) this(const ref Loc loc, Condition condition, Statement ifbody, Statement elsebody) + extern (D) this(const ref Loc loc, Condition condition, Statement ifbody, Statement elsebody) @safe { super(loc, STMT.Conditional); this.condition = condition; @@ -1128,7 +1128,7 @@ extern (C++) final class StaticForeachStatement : Statement { StaticForeach sfe; - extern (D) this(const ref Loc loc, StaticForeach sfe) + extern (D) this(const ref Loc loc, StaticForeach sfe) @safe { super(loc, STMT.StaticForeach); this.sfe = sfe; @@ -1154,7 +1154,7 @@ extern (C++) final class PragmaStatement : Statement Expressions* args; // array of Expression's Statement _body; - extern (D) this(const ref Loc loc, const Identifier ident, Expressions* args, Statement _body) + extern (D) this(const ref Loc loc, const Identifier ident, Expressions* args, Statement _body) @safe { super(loc, STMT.Pragma); this.ident = ident; @@ -1180,7 +1180,7 @@ extern (C++) final class StaticAssertStatement : Statement { StaticAssert sa; - extern (D) this(StaticAssert sa) + extern (D) this(StaticAssert sa) @safe { super(sa.loc, STMT.StaticAssert); this.sa = sa; @@ -1291,7 +1291,7 @@ extern (C++) final class CaseStatement : Statement VarDeclaration lastVar; void* extra; // for use by Statement_toIR() - extern (D) this(const ref Loc loc, Expression exp, Statement statement) + extern (D) this(const ref Loc loc, Expression exp, Statement statement) @safe { super(loc, STMT.Case); this.exp = exp; @@ -1318,7 +1318,7 @@ extern (C++) final class CaseRangeStatement : Statement Expression last; Statement statement; - extern (D) this(const ref Loc loc, Expression first, Expression last, Statement statement) + extern (D) this(const ref Loc loc, Expression first, Expression last, Statement statement) @safe { super(loc, STMT.CaseRange); this.first = first; @@ -1346,7 +1346,7 @@ extern (C++) final class DefaultStatement : Statement VarDeclaration lastVar; - extern (D) this(const ref Loc loc, Statement statement) + extern (D) this(const ref Loc loc, Statement statement) @safe { super(loc, STMT.Default); this.statement = statement; @@ -1370,7 +1370,7 @@ extern (C++) final class GotoDefaultStatement : Statement { SwitchStatement sw; - extern (D) this(const ref Loc loc) + extern (D) this(const ref Loc loc) @safe { super(loc, STMT.GotoDefault); } @@ -1395,7 +1395,7 @@ extern (C++) final class GotoCaseStatement : Statement CaseStatement cs; // case statement it resolves to - extern (D) this(const ref Loc loc, Expression exp) + extern (D) this(const ref Loc loc, Expression exp) @safe { super(loc, STMT.GotoCase); this.exp = exp; @@ -1418,12 +1418,12 @@ extern (C++) final class SwitchErrorStatement : Statement { Expression exp; - extern (D) this(const ref Loc loc) + extern (D) this(const ref Loc loc) @safe { super(loc, STMT.SwitchError); } - final extern (D) this(const ref Loc loc, Expression exp) + final extern (D) this(const ref Loc loc, Expression exp) @safe { super(loc, STMT.SwitchError); this.exp = exp; @@ -1443,7 +1443,7 @@ extern (C++) final class ReturnStatement : Statement Expression exp; size_t caseDim; - extern (D) this(const ref Loc loc, Expression exp) + extern (D) this(const ref Loc loc, Expression exp) @safe { super(loc, STMT.Return); this.exp = exp; @@ -1472,7 +1472,7 @@ extern (C++) final class BreakStatement : Statement { Identifier ident; - extern (D) this(const ref Loc loc, Identifier ident) + extern (D) this(const ref Loc loc, Identifier ident) @safe { super(loc, STMT.Break); this.ident = ident; @@ -1496,7 +1496,7 @@ extern (C++) final class ContinueStatement : Statement { Identifier ident; - extern (D) this(const ref Loc loc, Identifier ident) + extern (D) this(const ref Loc loc, Identifier ident) @safe { super(loc, STMT.Continue); this.ident = ident; @@ -1521,7 +1521,7 @@ extern (C++) final class SynchronizedStatement : Statement Expression exp; Statement _body; - extern (D) this(const ref Loc loc, Expression exp, Statement _body) + extern (D) this(const ref Loc loc, Expression exp, Statement _body) @safe { super(loc, STMT.Synchronized); this.exp = exp; @@ -1559,7 +1559,7 @@ extern (C++) final class WithStatement : Statement VarDeclaration wthis; Loc endloc; - extern (D) this(const ref Loc loc, Expression exp, Statement _body, Loc endloc) + extern (D) this(const ref Loc loc, Expression exp, Statement _body, Loc endloc) @safe { super(loc, STMT.With); this.exp = exp; @@ -1588,7 +1588,7 @@ extern (C++) final class TryCatchStatement : Statement Statement tryBody; /// set to enclosing TryCatchStatement or TryFinallyStatement if in _body portion - extern (D) this(const ref Loc loc, Statement _body, Catches* catches) + extern (D) this(const ref Loc loc, Statement _body, Catches* catches) @safe { super(loc, STMT.TryCatch); this._body = _body; @@ -1632,7 +1632,7 @@ extern (C++) final class Catch : RootObject // was generated by the compiler, wasn't present in source code bool internalCatch; - extern (D) this(const ref Loc loc, Type type, Identifier ident, Statement handler) + extern (D) this(const ref Loc loc, Type type, Identifier ident, Statement handler) @safe { //printf("Catch(%s, loc = %s)\n", id.toChars(), loc.toChars()); this.loc = loc; @@ -1660,7 +1660,7 @@ extern (C++) final class TryFinallyStatement : Statement Statement tryBody; /// set to enclosing TryCatchStatement or TryFinallyStatement if in _body portion bool bodyFallsThru; /// true if _body falls through to finally - extern (D) this(const ref Loc loc, Statement _body, Statement finalbody) + extern (D) this(const ref Loc loc, Statement _body, Statement finalbody) @safe { super(loc, STMT.TryFinally); this._body = _body; @@ -1668,7 +1668,7 @@ extern (C++) final class TryFinallyStatement : Statement this.bodyFallsThru = true; // assume true until statementSemantic() } - static TryFinallyStatement create(const ref Loc loc, Statement _body, Statement finalbody) + static TryFinallyStatement create(const ref Loc loc, Statement _body, Statement finalbody) @safe { return new TryFinallyStatement(loc, _body, finalbody); } @@ -1702,7 +1702,7 @@ extern (C++) final class ScopeGuardStatement : Statement TOK tok; Statement statement; - extern (D) this(const ref Loc loc, TOK tok, Statement statement) + extern (D) this(const ref Loc loc, TOK tok, Statement statement) @safe { super(loc, STMT.ScopeGuard); this.tok = tok; @@ -1730,7 +1730,7 @@ extern (C++) final class ThrowStatement : Statement // was generated by the compiler, wasn't present in source code bool internalThrow; - extern (D) this(const ref Loc loc, Expression exp) + extern (D) this(const ref Loc loc, Expression exp) @safe { super(loc, STMT.Throw); this.exp = exp; @@ -1755,7 +1755,7 @@ extern (C++) final class DebugStatement : Statement { Statement statement; - extern (D) this(const ref Loc loc, Statement statement) + extern (D) this(const ref Loc loc, Statement statement) @safe { super(loc, STMT.Debug); this.statement = statement; @@ -1785,7 +1785,7 @@ extern (C++) final class GotoStatement : Statement VarDeclaration lastVar; bool inCtfeBlock; /// set if goto is inside an `if (__ctfe)` block - extern (D) this(const ref Loc loc, Identifier ident) + extern (D) this(const ref Loc loc, Identifier ident) @safe { super(loc, STMT.Goto); this.ident = ident; @@ -1900,7 +1900,7 @@ extern (C++) final class LabelStatement : Statement bool breaks; // someone did a 'break ident' bool inCtfeBlock; // inside a block dominated by `if (__ctfe)` - extern (D) this(const ref Loc loc, Identifier ident, Statement statement) + extern (D) this(const ref Loc loc, Identifier ident, Statement statement) @safe { super(loc, STMT.Label); this.ident = ident; @@ -1927,12 +1927,16 @@ extern (C++) final class LabelDsymbol : Dsymbol bool deleted; // set if rewritten to return in foreach delegate bool iasm; // set if used by inline assembler - extern (D) this(Identifier ident, const ref Loc loc = Loc.initial) + // set if label was defined multiple times, to avoid duplicate errors + // can be removed if generic error message deduplication is implemented + bool duplicated; + + extern (D) this(Identifier ident, const ref Loc loc = Loc.initial) @safe { super(loc, ident); } - static LabelDsymbol create(Identifier ident) + static LabelDsymbol create(Identifier ident) @safe { return new LabelDsymbol(ident); } @@ -1956,13 +1960,13 @@ extern (C++) class AsmStatement : Statement { Token* tokens; - extern (D) this(const ref Loc loc, Token* tokens) + extern (D) this(const ref Loc loc, Token* tokens) @safe { super(loc, STMT.Asm); this.tokens = tokens; } - extern (D) this(const ref Loc loc, Token* tokens, STMT stmt) + extern (D) this(const ref Loc loc, Token* tokens, STMT stmt) @safe { super(loc, stmt); this.tokens = tokens; @@ -1990,7 +1994,7 @@ extern (C++) final class InlineAsmStatement : AsmStatement bool refparam; // true if function parameter is referenced bool naked; // true if function is to be naked - extern (D) this(const ref Loc loc, Token* tokens) + extern (D) this(const ref Loc loc, Token* tokens) @safe { super(loc, tokens, STMT.InlineAsm); } @@ -2022,7 +2026,7 @@ extern (C++) final class GccAsmStatement : AsmStatement Identifiers* labels; // list of goto labels GotoStatements* gotos; // of the goto labels, the equivalent statements they represent - extern (D) this(const ref Loc loc, Token* tokens) + extern (D) this(const ref Loc loc, Token* tokens) @safe { super(loc, tokens, STMT.GccAsm); } @@ -2045,7 +2049,7 @@ extern (C++) final class CompoundAsmStatement : CompoundStatement { StorageClass stc; // postfix attributes like nothrow/pure/@trusted - extern (D) this(const ref Loc loc, Statements* statements, StorageClass stc) + extern (D) this(const ref Loc loc, Statements* statements, StorageClass stc) @safe { super(loc, statements, STMT.CompoundAsm); this.stc = stc; @@ -2074,7 +2078,7 @@ extern (C++) final class ImportStatement : Statement { Dsymbols* imports; // Array of Import's - extern (D) this(const ref Loc loc, Dsymbols* imports) + extern (D) this(const ref Loc loc, Dsymbols* imports) @safe { super(loc, STMT.Import); this.imports = imports; @@ -2157,7 +2161,7 @@ mixin template VisitStatement(Result) * handler = string for the name of the visit handler * Returns: boilerplate code for a case */ -pure string visitStmtCase(string handler) +pure string visitStmtCase(string handler) @safe { if (__ctfe) { diff --git a/gcc/d/dmd/statement.h b/gcc/d/dmd/statement.h index b7403b5..eb4849d 100644 --- a/gcc/d/dmd/statement.h +++ b/gcc/d/dmd/statement.h @@ -699,6 +699,7 @@ public: d_bool deleted; // set if rewritten to return in foreach delegate d_bool iasm; // set if used by inline assembler + d_bool duplicated; // set if multiply defined, to avoid duplicate error messages static LabelDsymbol *create(Identifier *ident); LabelDsymbol *isLabel() override; diff --git a/gcc/d/dmd/statementsem.d b/gcc/d/dmd/statementsem.d index 2def253..178cef5 100644 --- a/gcc/d/dmd/statementsem.d +++ b/gcc/d/dmd/statementsem.d @@ -21,7 +21,6 @@ import dmd.arrayop; import dmd.arraytypes; import dmd.astcodegen; import dmd.astenums; -import dmd.ast_node; import dmd.attrib; import dmd.blockexit; import dmd.clone; @@ -39,7 +38,6 @@ import dmd.dsymbol; import dmd.dsymbolsem; import dmd.dtemplate; import dmd.errors; -import dmd.errorsink; import dmd.escape; import dmd.expression; import dmd.expressionsem; @@ -57,7 +55,6 @@ import dmd.mustuse; import dmd.nogc; import dmd.opover; import dmd.parse; -import dmd.printast; import dmd.common.outbuffer; import dmd.root.string; import dmd.semantic2; @@ -68,7 +65,6 @@ import dmd.target; import dmd.tokens; import dmd.typesem; import dmd.visitor; -import dmd.compiler; version (DMDLIB) { @@ -109,7 +105,7 @@ private Identifier fixupLabelName(Scope* sc, Identifier ident) * Returns: * if `true`, then the `LabelStatement`, otherwise `null` */ -private LabelStatement checkLabeledLoop(Scope* sc, Statement statement) +private LabelStatement checkLabeledLoop(Scope* sc, Statement statement) @safe { if (sc.slabel && sc.slabel.statement == statement) { @@ -142,6 +138,8 @@ private Expression checkAssignmentAsCondition(Expression e, Scope* sc) // Performs semantic analysis in Statement AST nodes extern(C++) Statement statementSemantic(Statement s, Scope* sc) { + import dmd.compiler; + version (CallbackAPI) Compiler.onStatementSemanticStart(s, sc); @@ -2758,6 +2756,12 @@ Statement statementSemanticVisit(Statement s, Scope* sc) { if (e0) rs.error("expected return type of `%s`, not `%s`", tret.toChars(), resType.toChars()); + else if (tbret.isTypeNoreturn()) + { + rs.error("cannot return from `noreturn` function"); + .errorSupplemental(rs.loc, + "Consider adding an endless loop, `assert(0)`, or another `noreturn` expression"); + } else rs.error("`return` expression expected"); } @@ -3547,9 +3551,19 @@ Statement statementSemanticVisit(Statement s, Scope* sc) ls.inCtfeBlock = (sc.flags & SCOPE.ctfeBlock) != 0; LabelDsymbol ls2 = fd.searchLabel(ls.ident, ls.loc); - if (ls2.statement) + if (ls2.statement && !ls2.duplicated) { - ls.error("label `%s` already defined", ls2.toChars()); + if (ls.loc == ls2.loc) + { + ls2.duplicated = true; + ls.error("label `%s` is duplicated", ls2.toChars()); + .errorSupplemental(ls2.loc, "labels cannot be used in a static foreach with more than 1 iteration"); + } + else + { + ls.error("label `%s` is already defined", ls2.toChars()); + .errorSupplemental(ls2.loc, "first definition is here"); + } return setError(); } else @@ -4068,8 +4082,8 @@ void catchSemantic(Catch c, Scope* sc) } else if (!c.type.isNaked() && !c.type.isConst()) { - // @@@DEPRECATED_2.113@@@ - // Deprecated in 2.103, change into an error & uncomment in 2.113 + // @@@DEPRECATED_2.115@@@ + // Deprecated in 2.105, change into an error & uncomment assign in 2.115 deprecation(c.loc, "can only catch mutable or const qualified types, not `%s`", c.type.toChars()); //c.errors = true; } diff --git a/gcc/d/dmd/target.d b/gcc/d/dmd/target.d index 81ff84f..aba3319 100644 --- a/gcc/d/dmd/target.d +++ b/gcc/d/dmd/target.d @@ -159,7 +159,7 @@ extern (C++) struct Target * This can be used to restore the state set by `_init` to its original * state. */ - void deinitialize() + void deinitialize() @safe { this = this.init; } @@ -203,7 +203,7 @@ extern (C++) struct Target * 2 vector element type is not supported * 3 vector size is not supported */ - extern (C++) int isVectorTypeSupported(int sz, Type type); + extern (C++) int isVectorTypeSupported(int sz, Type type) @safe; /** * Checks whether the target supports the given operation for vectors. @@ -221,7 +221,7 @@ extern (C++) struct Target * Returns: * `LINK` to use for `extern(System)` */ - extern (C++) LINK systemLinkage(); + extern (C++) LINK systemLinkage() @safe; /** * Describes how an argument type is passed to a function on target. @@ -270,7 +270,7 @@ extern (C++) struct Target * tf = type of function being called * Returns: `true` if the callee invokes destructors for arguments. */ - extern (C++) bool isCalleeDestroyingArgs(TypeFunction tf); + extern (C++) bool isCalleeDestroyingArgs(TypeFunction tf) @safe; /** * Returns true if the implementation for object monitors is always defined @@ -288,7 +288,7 @@ extern (C++) struct Target * Returns: * `false` if the target does not support `pragma(linkerDirective)`. */ - extern (C++) bool supportsLinkerDirective() const; + extern (C++) bool supportsLinkerDirective() const @safe; } //////////////////////////////////////////////////////////////////////////////// diff --git a/gcc/d/dmd/templateparamsem.d b/gcc/d/dmd/templateparamsem.d index 1a9d252..6b8f949 100644 --- a/gcc/d/dmd/templateparamsem.d +++ b/gcc/d/dmd/templateparamsem.d @@ -50,7 +50,7 @@ private extern (C++) final class TemplateParameterSemanticVisitor : Visitor TemplateParameters* parameters; bool result; - this(Scope* sc, TemplateParameters* parameters) scope + this(Scope* sc, TemplateParameters* parameters) scope @safe { this.sc = sc; this.parameters = parameters; diff --git a/gcc/d/dmd/tokens.d b/gcc/d/dmd/tokens.d index 5871762..950c830 100644 --- a/gcc/d/dmd/tokens.d +++ b/gcc/d/dmd/tokens.d @@ -898,7 +898,7 @@ extern (C++) struct Token nothrow: - int isKeyword() const + int isKeyword() const @safe { foreach (kw; keywords) { diff --git a/gcc/d/dmd/typesem.d b/gcc/d/dmd/typesem.d index d092395..a80aa80 100644 --- a/gcc/d/dmd/typesem.d +++ b/gcc/d/dmd/typesem.d @@ -530,12 +530,10 @@ extern(C++) Type typeSemantic(Type type, const ref Loc loc, Scope* sc) } RootObject o = (*tup.objects)[cast(size_t)d]; - if (o.dyncast() != DYNCAST.type) - { - .error(loc, "`%s` is not a type", mtype.toChars()); - return error(); - } - return (cast(Type)o).addMod(mtype.mod); + if (auto tt = o.isType()) + return tt.addMod(mtype.mod); + .error(loc, "`%s` is not a type", mtype.toChars()); + return error(); } if (t && t.ty == Terror) @@ -2006,7 +2004,7 @@ extern (C++) Type merge(Type type) OutBuffer buf; buf.reserve(32); - mangleToBuffer(type, &buf); + mangleToBuffer(type, buf); auto sv = type.stringtable.update(buf[]); if (sv.value) @@ -5015,7 +5013,10 @@ RootObject compileTypeMixin(TypeMixin tm, ref const Loc loc, Scope* sc) } if (p.token.value != TOK.endOfFile) { - .error(loc, "incomplete mixin type `%s`", str.ptr); + .error(loc, "unexpected token `%s` after type `%s`", + p.token.toChars(), o.toChars()); + .errorSupplemental(loc, "while parsing string mixin type `%s`", + str.ptr); return null; } diff --git a/gcc/d/dmd/visitor.d b/gcc/d/dmd/visitor.d index 7b059a0..591d3c0 100644 --- a/gcc/d/dmd/visitor.d +++ b/gcc/d/dmd/visitor.d @@ -255,7 +255,7 @@ extern (C++) class StoppableVisitor : Visitor public: bool stop; - final extern (D) this() scope + final extern (D) this() scope @safe { } } diff --git a/gcc/d/intrinsics.cc b/gcc/d/intrinsics.cc index aaf04e5..583d5a9 100644 --- a/gcc/d/intrinsics.cc +++ b/gcc/d/intrinsics.cc @@ -123,7 +123,7 @@ maybe_set_intrinsic (FuncDeclaration *decl) return; OutBuffer buf; - mangleToBuffer (fd->type, &buf); + mangleToBuffer (fd->type, buf); tdeco = buf.extractChars (); } diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ba7984b..4085fc9 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -2766,8 +2766,9 @@ can be omitted, to use a target-specific default value. @cindex OpenMP parallel @item -fopenmp Enable handling of OpenMP directives @code{#pragma omp} in C/C++, -@code{[[omp::directive(...)]]} and @code{[[omp::sequence(...)]]} in C++ and -@code{!$omp} in Fortran. When @option{-fopenmp} is specified, the +@code{[[omp::directive(...)]]}, @code{[[omp::sequence(...)]]} and +@code{[[omp::decl(...)]]} in C++ and @code{!$omp} in Fortran. +When @option{-fopenmp} is specified, the compiler generates parallel code according to the OpenMP Application Program Interface v4.5 @w{@uref{https://www.openmp.org}}. This option implies @option{-pthread}, and thus is only supported on targets that @@ -2779,11 +2780,14 @@ have support for @option{-pthread}. @option{-fopenmp} implies @cindex SIMD @item -fopenmp-simd Enable handling of OpenMP's @code{simd}, @code{declare simd}, -@code{declare reduction}, @code{assume}, @code{ordered}, @code{scan}, -@code{loop} directives and combined or composite directives with +@code{declare reduction}, @code{assume}, @code{ordered}, @code{scan} +and @code{loop} directive, and of combined or composite directives with @code{simd} as constituent with @code{#pragma omp} in C/C++, -@code{[[omp::directive(...)]]} and @code{[[omp::sequence(...)]]} in C++ -and @code{!$omp} in Fortran. Other OpenMP directives are ignored. +@code{[[omp::directive(...)]]}, @code{[[omp::sequence(...)]]} and +@code{[[omp::decl(...)]]} in C++ and @code{!$omp} in Fortran. +Other OpenMP directives are ignored. Unless @option{-fopenmp} is +additionally specified, the @code{loop} region binds to the current +task region, independent of the specified @code{bind} clause. @opindex fopenmp-target-simd-clone @cindex OpenMP target SIMD clone @@ -16508,6 +16512,26 @@ Use both Advanced SIMD and SVE. Prefer SVE when the costs are deemed equal. @end table The default value is 0. +@item aarch64-ldp-policy +Fine-grained policy for load pairs. +With @option{--param=aarch64-ldp-policy=default}, use the policy of the +tuning structure. This is the current default. +With @option{--param=aarch64-ldp-policy=always}, emit ldp regardless +of alignment. +With @option{--param=aarch64-ldp-policy=never}, do not emit ldp. +With @option{--param=aarch64-ldp-policy=aligned}, emit ldp only if the +source pointer is aligned to at least double the alignment of the type. + +@item aarch64-stp-policy +Fine-grained policy for store pairs. +With @option{--param=aarch64-stp-policy=default}, use the policy of the +tuning structure. This is the current default. +With @option{--param=aarch64-stp-policy=always}, emit stp regardless +of alignment. +With @option{--param=aarch64-stp-policy=never}, do not emit stp. +With @option{--param=aarch64-stp-policy=aligned}, emit stp only if the +source pointer is aligned to at least double the alignment of the type. + @item aarch64-loop-vect-issue-rate-niters The tuning for some AArch64 CPUs tries to take both latencies and issue rates into account when deciding whether a loop should be vectorized @@ -26159,10 +26183,12 @@ The default code model is @code{normal}. @itemx -mno-explicit-relocs Use or do not use assembler relocation operators when dealing with symbolic addresses. The alternative is to use assembler macros instead, which may -limit optimization. The default value for the option is determined during -GCC build-time by detecting corresponding assembler support: -@code{-mexplicit-relocs} if said support is present, -@code{-mno-explicit-relocs} otherwise. This option is mostly useful for +limit instruction scheduling but allow linker relaxation. The default +value for the option is determined during GCC build-time by detecting +corresponding assembler support: +@code{-mno-explicit-relocs} if the assembler supports relaxation or it +does not support relocation operators at all, +@code{-mexplicit-relocs} otherwise. This option is mostly useful for debugging, or interoperation with assemblers different from the build-time one. @@ -1733,7 +1733,8 @@ find_shift_sequence (poly_int64 access_size, /* If a constant was stored into memory, try to simplify it here, otherwise the cost of the shift might preclude this optimization e.g. at -Os, even when no actual shift will be needed. */ - if (store_info->const_rhs) + if (store_info->const_rhs + && known_le (access_size, GET_MODE_SIZE (MAX_MODE_INT))) { auto new_mode = smallest_int_mode_for_size (access_size * BITS_PER_UNIT); auto byte = subreg_lowpart_offset (new_mode, store_mode); diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 6e773d9..657dc91 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,22 @@ +2023-09-24 Paul Thomas <pault@gcc.gnu.org> + + PR fortran/68155 + PR fortran/111271 + * decl.cc (fix_initializer_charlen): New function broken out of + add_init_expr_to_sym. + (add_init_expr_to_sym, build_struct): Call the new function. + * trans-expr.cc (gfc_conv_intrinsic_to_class): Remove repeated + condition. + +2023-09-23 Harald Anlauf <anlauf@gmx.de> + + PR fortran/95710 + * class.cc (gfc_build_class_symbol): Do not try to build class + container for invalid typespec. + * resolve.cc (resolve_fl_var_and_proc): Prevent NULL pointer + dereference. + (resolve_symbol): Likewise. + 2023-09-19 Harald Anlauf <anlauf@gmx.de> PR fortran/70231 diff --git a/gcc/fortran/class.cc b/gcc/fortran/class.cc index 9d0c802..5c43b77 100644 --- a/gcc/fortran/class.cc +++ b/gcc/fortran/class.cc @@ -647,6 +647,10 @@ gfc_build_class_symbol (gfc_typespec *ts, symbol_attribute *attr, gcc_assert (as); + /* We cannot build the class container now. */ + if (attr->class_ok && (!ts->u.derived || !ts->u.derived->components)) + return false; + /* Class container has already been built with same name. */ if (attr->class_ok && ts->u.derived->components->attr.dimension >= attr->dimension diff --git a/gcc/fortran/decl.cc b/gcc/fortran/decl.cc index 8182ef2..4a3c5b8 100644 --- a/gcc/fortran/decl.cc +++ b/gcc/fortran/decl.cc @@ -1960,6 +1960,45 @@ gfc_free_enum_history (void) } +/* Function to fix initializer character length if the length of the + symbol or component is constant. */ + +static bool +fix_initializer_charlen (gfc_typespec *ts, gfc_expr *init) +{ + if (!gfc_specification_expr (ts->u.cl->length)) + return false; + + int k = gfc_validate_kind (BT_INTEGER, gfc_charlen_int_kind, false); + + /* resolve_charlen will complain later on if the length + is too large. Just skip the initialization in that case. */ + if (mpz_cmp (ts->u.cl->length->value.integer, + gfc_integer_kinds[k].huge) <= 0) + { + HOST_WIDE_INT len + = gfc_mpz_get_hwi (ts->u.cl->length->value.integer); + + if (init->expr_type == EXPR_CONSTANT) + gfc_set_constant_character_len (len, init, -1); + else if (init->expr_type == EXPR_ARRAY) + { + gfc_constructor *cons; + + /* Build a new charlen to prevent simplification from + deleting the length before it is resolved. */ + init->ts.u.cl = gfc_new_charlen (gfc_current_ns, NULL); + init->ts.u.cl->length = gfc_copy_expr (ts->u.cl->length); + cons = gfc_constructor_first (init->value.constructor); + for (; cons; cons = gfc_constructor_next (cons)) + gfc_set_constant_character_len (len, cons->expr, -1); + } + } + + return true; +} + + /* Function called by variable_decl() that adds an initialization expression to a symbol. */ @@ -2073,40 +2112,10 @@ add_init_expr_to_sym (const char *name, gfc_expr **initp, locus *var_locus) gfc_copy_expr (init->ts.u.cl->length); } } - /* Update initializer character length according symbol. */ - else if (sym->ts.u.cl->length->expr_type == EXPR_CONSTANT) - { - if (!gfc_specification_expr (sym->ts.u.cl->length)) - return false; - - int k = gfc_validate_kind (BT_INTEGER, gfc_charlen_int_kind, - false); - /* resolve_charlen will complain later on if the length - is too large. Just skeep the initialization in that case. */ - if (mpz_cmp (sym->ts.u.cl->length->value.integer, - gfc_integer_kinds[k].huge) <= 0) - { - HOST_WIDE_INT len - = gfc_mpz_get_hwi (sym->ts.u.cl->length->value.integer); - - if (init->expr_type == EXPR_CONSTANT) - gfc_set_constant_character_len (len, init, -1); - else if (init->expr_type == EXPR_ARRAY) - { - gfc_constructor *c; - - /* Build a new charlen to prevent simplification from - deleting the length before it is resolved. */ - init->ts.u.cl = gfc_new_charlen (gfc_current_ns, NULL); - init->ts.u.cl->length - = gfc_copy_expr (sym->ts.u.cl->length); - - for (c = gfc_constructor_first (init->value.constructor); - c; c = gfc_constructor_next (c)) - gfc_set_constant_character_len (len, c->expr, -1); - } - } - } + /* Update initializer character length according to symbol. */ + else if (sym->ts.u.cl->length->expr_type == EXPR_CONSTANT + && !fix_initializer_charlen (&sym->ts, init)) + return false; } if (sym->attr.flavor == FL_PARAMETER && sym->attr.dimension && sym->as @@ -2369,6 +2378,13 @@ build_struct (const char *name, gfc_charlen *cl, gfc_expr **init, c->initializer = *init; *init = NULL; + /* Update initializer character length according to component. */ + if (c->ts.type == BT_CHARACTER && c->ts.u.cl->length + && c->ts.u.cl->length->expr_type == EXPR_CONSTANT + && c->initializer && c->initializer->ts.type == BT_CHARACTER + && !fix_initializer_charlen (&c->ts, c->initializer)) + return false; + c->as = *as; if (c->as != NULL) { diff --git a/gcc/fortran/resolve.cc b/gcc/fortran/resolve.cc index 1042b8c..861f69a 100644 --- a/gcc/fortran/resolve.cc +++ b/gcc/fortran/resolve.cc @@ -13326,6 +13326,7 @@ resolve_fl_var_and_proc (gfc_symbol *sym, int mp_flag) && sym->ts.u.derived && !sym->attr.select_type_temporary && !UNLIMITED_POLY (sym) + && CLASS_DATA (sym) && CLASS_DATA (sym)->ts.u.derived && !gfc_type_is_extensible (CLASS_DATA (sym)->ts.u.derived)) { @@ -16068,7 +16069,8 @@ resolve_symbol (gfc_symbol *sym) specification_expr = saved_specification_expr; } - if (sym->ts.type == BT_CLASS && sym->attr.class_ok && sym->ts.u.derived) + if (sym->ts.type == BT_CLASS && sym->attr.class_ok && sym->ts.u.derived + && CLASS_DATA (sym)) { as = CLASS_DATA (sym)->as; class_attr = CLASS_DATA (sym)->attr; diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc index 244126c..cca2f4e 100644 --- a/gcc/fortran/trans-expr.cc +++ b/gcc/fortran/trans-expr.cc @@ -1131,13 +1131,7 @@ gfc_conv_intrinsic_to_class (gfc_se *parmse, gfc_expr *e, gfc_add_modify (&parmse->pre, ctree, fold_convert (TREE_TYPE (ctree), tmp)); } - else if (unlimited_poly) - { - ctree = gfc_class_len_get (var); - gfc_add_modify (&parmse->pre, ctree, - fold_convert (TREE_TYPE (ctree), - integer_zero_node)); - } + /* Pass the address of the class object. */ parmse->expr = gfc_build_addr_expr (NULL_TREE, var); } diff --git a/gcc/function.cc b/gcc/function.cc index dd2c113..e92384a 100644 --- a/gcc/function.cc +++ b/gcc/function.cc @@ -2429,15 +2429,7 @@ assign_parm_find_data_types (struct assign_parm_data_all *all, tree parm, { int unsignedp; -#ifndef BROKEN_VALUE_INITIALIZATION *data = assign_parm_data_one (); -#else - /* Old versions of GCC used to miscompile the above by only initializing - the members with explicit constructors and copying garbage - to the other members. */ - assign_parm_data_one zero_data = {}; - *data = zero_data; -#endif /* NAMED_ARG is a misnomer. We really mean 'non-variadic'. */ if (!cfun->stdarg) diff --git a/gcc/gimple-range-gori.cc b/gcc/gimple-range-gori.cc index 51fb542..2694e55 100644 --- a/gcc/gimple-range-gori.cc +++ b/gcc/gimple-range-gori.cc @@ -876,6 +876,7 @@ gori_compute::logical_combine (vrange &r, enum tree_code code, r.dump (dump_file); fputc ('\n', dump_file); } + return res; } switch (code) diff --git a/gcc/gimple-ssa-backprop.cc b/gcc/gimple-ssa-backprop.cc index 65a6559..dcb15ed 100644 --- a/gcc/gimple-ssa-backprop.cc +++ b/gcc/gimple-ssa-backprop.cc @@ -694,7 +694,6 @@ strip_sign_op_1 (tree rhs) switch (gimple_assign_rhs_code (assign)) { case ABS_EXPR: - case ABSU_EXPR: case NEGATE_EXPR: return gimple_assign_rhs1 (assign); diff --git a/gcc/gimple.cc b/gcc/gimple.cc index d5a4f63..46f2878 100644 --- a/gcc/gimple.cc +++ b/gcc/gimple.cc @@ -2163,6 +2163,7 @@ gimple_copy (gimple *stmt) case GIMPLE_OMP_SECTION: case GIMPLE_OMP_MASTER: + case GIMPLE_OMP_STRUCTURED_BLOCK: copy_omp_body: new_seq = gimple_seq_copy (gimple_omp_body (stmt)); gimple_omp_set_body (copy, new_seq); diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc index 3aaa490..76a1393 100644 --- a/gcc/lra-constraints.cc +++ b/gcc/lra-constraints.cc @@ -5424,6 +5424,11 @@ lra_constraints (bool first_p) loc_equivalence_callback, curr_insn); if (old != *curr_id->operand_loc[0]) { + /* If we substitute pseudo by shared equivalence, we can fail + to update LRA reg info and this can result in many + unexpected consequences. So keep rtl unshared: */ + *curr_id->operand_loc[0] + = copy_rtx (*curr_id->operand_loc[0]); lra_update_insn_regno_info (curr_insn); changed_p = true; } @@ -2579,9 +2579,8 @@ lra (FILE *f) if (inserted_p) commit_edge_insertions (); - /* Replacing pseudos with their memory equivalents might have - created shared rtx. Subsequent passes would get confused - by this, so unshare everything here. */ + /* Subsequent passes expect that rtl is unshared, so unshare everything + here. */ unshare_all_rtl_again (get_insns ()); if (flag_checking) diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog index 41165cc..cd18211 100644 --- a/gcc/m2/ChangeLog +++ b/gcc/m2/ChangeLog @@ -1,3 +1,14 @@ +2023-09-26 Gaius Mulley <gaiusmod2@gmail.com> + + PR modula2/111510 + * gm2-compiler/M2GenGCC.mod (IsExportedGcc): Minor spacing changes. + (BuildTrashTreeFromInterface): Minor spacing changes. + * gm2-compiler/M2Options.mod (GetRuntimeModuleOverride): Call + string to generate a nul terminated C style string. + * gm2-compiler/M2Quads.mod (BuildStringAdrParam): New procedure. + (BuildM2InitFunction): Replace inline parameter generation with + calls to BuildStringAdrParam. + 2023-09-19 Gaius Mulley <gaiusmod2@gmail.com> * Make-lang.in (host_mc_longreal): Detect hosting on powerpc64le diff --git a/gcc/m2/gm2-compiler/M2GenGCC.mod b/gcc/m2/gm2-compiler/M2GenGCC.mod index c023eda..e0b024d 100644 --- a/gcc/m2/gm2-compiler/M2GenGCC.mod +++ b/gcc/m2/gm2-compiler/M2GenGCC.mod @@ -391,7 +391,7 @@ BEGIN IF WholeProgram THEN scope := GetScope (sym) ; - WHILE scope#NulSym DO + WHILE scope # NulSym DO IF IsDefImp (scope) THEN RETURN IsExported (scope, sym) @@ -771,7 +771,7 @@ VAR tree: Tree ; BEGIN tree := Tree (NIL) ; - IF sym#NulSym + IF sym # NulSym THEN i := 1 ; REPEAT diff --git a/gcc/m2/gm2-compiler/M2Options.mod b/gcc/m2/gm2-compiler/M2Options.mod index 1a64cf0..9d72a10 100644 --- a/gcc/m2/gm2-compiler/M2Options.mod +++ b/gcc/m2/gm2-compiler/M2Options.mod @@ -1326,7 +1326,7 @@ END SetRuntimeModuleOverride ; PROCEDURE GetRuntimeModuleOverride () : ADDRESS ; BEGIN - RETURN RuntimeModuleOverride + RETURN string (RuntimeModuleOverride) END GetRuntimeModuleOverride ; diff --git a/gcc/m2/gm2-compiler/M2Quads.mod b/gcc/m2/gm2-compiler/M2Quads.mod index 0cea540..95ca15a 100644 --- a/gcc/m2/gm2-compiler/M2Quads.mod +++ b/gcc/m2/gm2-compiler/M2Quads.mod @@ -2581,6 +2581,23 @@ END BuildM2MainFunction ; (* + BuildStringAdrParam - push the address of a nul terminated string onto the quad stack. +*) + +PROCEDURE BuildStringAdrParam (tok: CARDINAL; name: Name); +VAR + str, m2strnul: CARDINAL ; +BEGIN + PushTF (Adr, Address) ; + str := MakeConstLitString (tok, name) ; + m2strnul := MakeConstStringM2nul (tok, str) ; + PushTtok (m2strnul, tok) ; + PushT (1) ; + BuildAdrFunction +END BuildAdrFunction ; + + +(* BuildM2InitFunction - *) @@ -2620,22 +2637,9 @@ BEGIN (* ConstructModules (module_name, argc, argv, envp); *) PushTtok (constructModules, tok) ; - PushTF(Adr, Address) ; - PushTtok (MakeConstLitString (tok, GetSymName (moduleSym)), tok) ; - PushT(1) ; - BuildAdrFunction ; - - PushTF(Adr, Address) ; - PushTtok (MakeConstLitString (tok, GetLibName (moduleSym)), tok) ; - PushT(1) ; - BuildAdrFunction ; - - PushTF(Adr, Address) ; - PushTtok (MakeConstLitString (tok, - makekey (GetRuntimeModuleOverride ())), - tok) ; - PushT(1) ; - BuildAdrFunction ; + BuildStringAdrParam (tok, GetSymName (moduleSym)) ; + BuildStringAdrParam (tok, GetLibName (moduleSym)) ; + BuildStringAdrParam (tok, makekey (GetRuntimeModuleOverride ())) ; PushTtok (SafeRequestSym (tok, MakeKey ("argc")), tok) ; PushTtok (SafeRequestSym (tok, MakeKey ("argv")), tok) ; diff --git a/gcc/match.pd b/gcc/match.pd index 0aa815f..f0be325 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -1806,6 +1806,23 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (simplify (bit_xor:c (convert1? (bit_xor:c @0 @@1)) (convert2? @1)) (convert @0)) + +/* (X & ~Y) & Y -> 0 */ +(simplify + (bit_and:c (bit_and @0 @1) @2) + (with { bool wascmp; } + (if (bitwise_inverted_equal_p (@0, @2, wascmp) + || bitwise_inverted_equal_p (@1, @2, wascmp)) + { wascmp ? constant_boolean_node (false, type) : build_zero_cst (type); }))) +/* (X | ~Y) | Y -> -1 */ +(simplify + (bit_ior:c (bit_ior @0 @1) @2) + (with { bool wascmp; } + (if ((bitwise_inverted_equal_p (@0, @2, wascmp) + || bitwise_inverted_equal_p (@1, @2, wascmp)) + && (!wascmp || element_precision (type) == 1)) + { build_all_ones_cst (TREE_TYPE (@0)); }))) + /* (X & Y) & (X & Z) -> (X & Y) & Z (X | Y) | (X | Z) -> (X | Y) | Z */ (for op (bit_and bit_ior) @@ -2949,7 +2966,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) && TYPE_OVERFLOW_WRAPS (TREE_TYPE (@1))) (gt @0 (minus @1 { build_int_cst (TREE_TYPE (@1), 1); })))) -/* Convert (X == CST1) && (X OP2 CST2) to a known value +/* Convert (X == CST1) && ((other)X OP2 CST2) to a known value based on CST1 OP2 CST2. Similarly for (X != CST1). */ /* Convert (X == Y) && (X OP2 Y) to a known value if X is an integral type. Similarly for (X != Y). */ @@ -2957,26 +2974,30 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (for code1 (eq ne) (for code2 (eq ne lt gt le ge) (simplify - (bit_and:c (code1@3 @0 @1) (code2@4 @0 @2)) + (bit_and:c (code1:c@3 @0 @1) (code2:c@4 (convert?@c0 @0) @2)) (if ((TREE_CODE (@1) == INTEGER_CST && TREE_CODE (@2) == INTEGER_CST) || ((INTEGRAL_TYPE_P (TREE_TYPE (@1)) || POINTER_TYPE_P (TREE_TYPE (@1))) - && operand_equal_p (@1, @2))) + && bitwise_equal_p (@1, @2))) (with { bool one_before = false; bool one_after = false; int cmp = 0; + bool allbits = true; if (TREE_CODE (@1) == INTEGER_CST && TREE_CODE (@2) == INTEGER_CST) { - cmp = tree_int_cst_compare (@1, @2); + allbits = TYPE_PRECISION (TREE_TYPE (@1)) <= TYPE_PRECISION (TREE_TYPE (@2)); + auto t1 = wi::to_wide (fold_convert (TREE_TYPE (@2), @1)); + auto t2 = wi::to_wide (@2); + cmp = wi::cmp (t1, t2, TYPE_SIGN (TREE_TYPE (@2))); if (cmp < 0 - && wi::to_wide (@1) == wi::to_wide (@2) - 1) + && t1 == t2 - 1) one_before = true; if (cmp > 0 - && wi::to_wide (@1) == wi::to_wide (@2) + 1) + && t1 == t2 + 1) one_after = true; } bool val; @@ -2994,25 +3015,29 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (switch (if (code1 == EQ_EXPR && val) @3) (if (code1 == EQ_EXPR && !val) { constant_boolean_node (false, type); }) - (if (code1 == NE_EXPR && !val) @4) + (if (code1 == NE_EXPR && !val && allbits) @4) (if (code1 == NE_EXPR && code2 == GE_EXPR - && cmp == 0) - (gt @0 @1)) + && cmp == 0 + && allbits) + (gt @c0 (convert @1))) (if (code1 == NE_EXPR && code2 == LE_EXPR - && cmp == 0) - (lt @0 @1)) + && cmp == 0 + && allbits) + (lt @c0 (convert @1))) /* (a != (b+1)) & (a > b) -> a > (b+1) */ (if (code1 == NE_EXPR && code2 == GT_EXPR - && one_after) - (gt @0 @1)) + && one_after + && allbits) + (gt @c0 (convert @1))) /* (a != (b-1)) & (a < b) -> a < (b-1) */ (if (code1 == NE_EXPR && code2 == LT_EXPR - && one_before) - (lt @0 @1)) + && one_before + && allbits) + (lt @c0 (convert @1))) ) ) ) @@ -3076,26 +3101,30 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (for code1 (eq ne) (for code2 (eq ne lt gt le ge) (simplify - (bit_ior:c (code1@3 @0 @1) (code2@4 @0 @2)) + (bit_ior:c (code1:c@3 @0 @1) (code2:c@4 (convert?@c0 @0) @2)) (if ((TREE_CODE (@1) == INTEGER_CST && TREE_CODE (@2) == INTEGER_CST) || ((INTEGRAL_TYPE_P (TREE_TYPE (@1)) || POINTER_TYPE_P (TREE_TYPE (@1))) - && operand_equal_p (@1, @2))) + && bitwise_equal_p (@1, @2))) (with { bool one_before = false; bool one_after = false; int cmp = 0; + bool allbits = true; if (TREE_CODE (@1) == INTEGER_CST && TREE_CODE (@2) == INTEGER_CST) { - cmp = tree_int_cst_compare (@1, @2); + allbits = TYPE_PRECISION (TREE_TYPE (@1)) <= TYPE_PRECISION (TREE_TYPE (@2)); + auto t1 = wi::to_wide (fold_convert (TREE_TYPE (@2), @1)); + auto t2 = wi::to_wide (@2); + cmp = wi::cmp (t1, t2, TYPE_SIGN (TREE_TYPE (@2))); if (cmp < 0 - && wi::to_wide (@1) == wi::to_wide (@2) - 1) + && t1 == t2 - 1) one_before = true; if (cmp > 0 - && wi::to_wide (@1) == wi::to_wide (@2) + 1) + && t1 == t2 + 1) one_after = true; } bool val; @@ -3112,26 +3141,30 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) } (switch (if (code1 == EQ_EXPR && val) @4) - (if (code1 == NE_EXPR && val) { constant_boolean_node (true, type); }) - (if (code1 == NE_EXPR && !val) @3) + (if (code1 == NE_EXPR && val && allbits) { constant_boolean_node (true, type); }) + (if (code1 == NE_EXPR && !val && allbits) @3) (if (code1 == EQ_EXPR && code2 == GT_EXPR - && cmp == 0) - (ge @0 @1)) + && cmp == 0 + && allbits) + (ge @c0 @2)) (if (code1 == EQ_EXPR && code2 == LT_EXPR - && cmp == 0) - (le @0 @1)) + && cmp == 0 + && allbits) + (le @c0 @2)) /* (a == (b-1)) | (a >= b) -> a >= (b-1) */ (if (code1 == EQ_EXPR && code2 == GE_EXPR - && one_before) - (ge @0 @1)) + && one_before + && allbits) + (ge @c0 (convert @1))) /* (a == (b+1)) | (a <= b) -> a <= (b-1) */ (if (code1 == EQ_EXPR && code2 == LE_EXPR - && one_after) - (le @0 @1)) + && one_after + && allbits) + (le @c0 (convert @1))) ) ) ) @@ -7412,6 +7445,11 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (COPYSIGN_ALL @0 tree_expr_nonnegative_p@1) (abs @0)) +(simplify + /* fabs (copysign(x, y)) -> fabs (x). */ + (abs (COPYSIGN_ALL @0 @1)) + (abs @0)) + (for scale (LDEXP SCALBN SCALBLN) /* ldexp(0, x) -> 0. */ (simplify @@ -8846,8 +8884,26 @@ and, c = mask1 && mask2 ? d + b : d. */ (simplify - (IFN_COND_ADD @0 @1 (vec_cond @2 @3 integer_zerop) @1) - (IFN_COND_ADD (bit_and @0 @2) @1 @3 @1)) + (IFN_COND_ADD @0 @1 (vec_cond @2 @3 zerop@4) @1) + (if (ANY_INTEGRAL_TYPE_P (type) + || (FLOAT_TYPE_P (type) + && fold_real_zero_addition_p (type, NULL_TREE, @4, 0))) + (IFN_COND_ADD (bit_and @0 @2) @1 @3 @1))) + +/* Detect simplication for a conditional length reduction where + + a = mask ? b : 0 + c = i < len + bias ? d + a : d + + is turned into + + c = mask && i < len + bias ? d + b : d. */ +(simplify + (IFN_COND_LEN_ADD integer_truep @0 (vec_cond @1 @2 zerop@5) @0 @3 @4) + (if (ANY_INTEGRAL_TYPE_P (type) + || (FLOAT_TYPE_P (type) + && fold_real_zero_addition_p (type, NULL_TREE, @5, 0))) + (IFN_COND_LEN_ADD @1 @0 @2 @0 @3 @4))) /* For pointers @0 and @2 and nonnegative constant offset @1, look for expressions like: diff --git a/gcc/optabs.cc b/gcc/optabs.cc index 8b96f23..e1898da 100644 --- a/gcc/optabs.cc +++ b/gcc/optabs.cc @@ -7080,25 +7080,17 @@ expand_atomic_test_and_set (rtx target, rtx mem, enum memmodel model) /* Recall that the legacy lock_test_and_set optab was allowed to do magic things with the value 1. Thus we try again without trueval. */ if (!ret && targetm.atomic_test_and_set_trueval != 1) - ret = maybe_emit_sync_lock_test_and_set (subtarget, mem, const1_rtx, model); - - /* Failing all else, assume a single threaded environment and simply - perform the operation. */ - if (!ret) { - /* If the result is ignored skip the move to target. */ - if (subtarget != const0_rtx) - emit_move_insn (subtarget, mem); + ret = maybe_emit_sync_lock_test_and_set (subtarget, mem, const1_rtx, model); - emit_move_insn (mem, trueval); - ret = subtarget; + if (ret) + { + /* Rectify the not-one trueval. */ + ret = emit_store_flag_force (target, NE, ret, const0_rtx, mode, 0, 1); + gcc_assert (ret); + } } - /* Recall that have to return a boolean value; rectify if trueval - is not exactly one. */ - if (targetm.atomic_test_and_set_trueval != 1) - ret = emit_store_flag_force (target, NE, ret, const0_rtx, mode, 0, 1); - return ret; } diff --git a/gcc/rust/ChangeLog b/gcc/rust/ChangeLog index bbcbc29..6d69819 100644 --- a/gcc/rust/ChangeLog +++ b/gcc/rust/ChangeLog @@ -1,3 +1,24 @@ +2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org> + + * rust-session-manager.cc (Session::init): Call + targetrustm.rust_os_info. + * rust-target.def (rust_os_info): New hook. + +2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org> + + * rust-lang.cc (rust_add_target_info): Remove sorry. + * rust-session-manager.cc: Replace include of target.h with + include of tm.h and rust-target.h. + (Session::init): Call targetrustm.rust_cpu_info. + * rust-target.def (rust_cpu_info): New hook. + * rust-target.h (rust_add_target_info): Declare. + +2023-09-21 Iain Buclaw <ibuclaw@gdcproject.org> + + * rust-target-def.h: New file. + * rust-target.def: New file. + * rust-target.h: New file. + 2023-09-11 Parthib <94271200+Parthib314@users.noreply.github.com> * Make-lang.in: Removed rust-gcc-diagnostics object file. diff --git a/gcc/system.h b/gcc/system.h index 5109c60..e924152 100644 --- a/gcc/system.h +++ b/gcc/system.h @@ -905,12 +905,6 @@ extern void fancy_abort (const char *, int, const char *) /* Some compilers do not allow the use of unsigned char in bitfields. */ #define BOOL_BITFIELD unsigned int -/* GCC older than 4.4 have broken C++ value initialization handling, see - PR11309, PR30111, PR33916, PR82939 and PR84405 for more details. */ -#if GCC_VERSION > 0 && GCC_VERSION < 4004 && !defined(__clang__) -# define BROKEN_VALUE_INITIALIZATION -#endif - /* As the last action in this file, we poison the identifiers that shouldn't be used. Note, luckily gcc-3.0's token-based integrated preprocessor won't trip on poisoned identifiers that arrive from diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index cc53d4c..8cf00a8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,1036 @@ +2023-09-28 Richard Biener <rguenther@suse.de> + + PR tree-optimization/111614 + * gcc.dg/torture/pr111614.c: New testcase. + +2023-09-28 Joern Rennecke <joern.rennecke@embecosm.com> + + * lib/target-supports.exp (check_effective_target_riscv_vector): + Delete. Changed all users to use *riscv_v instead. + * g++.target/riscv/rvv/base/bug-10.C: Use riscv_v target selector. + * g++.target/riscv/rvv/base/bug-11.C: Likewise. + * g++.target/riscv/rvv/base/bug-13.C: Likewise. + * g++.target/riscv/rvv/base/bug-15.C: Likewise. + * g++.target/riscv/rvv/base/bug-16.C: Likewise. + * g++.target/riscv/rvv/base/bug-17.C: Likewise. + * g++.target/riscv/rvv/base/bug-2.C: Likewise. + * g++.target/riscv/rvv/base/bug-4.C: Likewise. + * g++.target/riscv/rvv/base/bug-5.C: Likewise. + * g++.target/riscv/rvv/base/bug-6.C: Likewise. + * g++.target/riscv/rvv/base/bug-7.C: Likewise. + * g++.target/riscv/rvv/base/bug-9.C: Likewise. + * g++.target/riscv/rvv/base/bug-12.C: Likewise. + * g++.target/riscv/rvv/base/bug-14.C: Likewise. + * g++.target/riscv/rvv/base/bug-18.C: Likewise. + * g++.target/riscv/rvv/base/bug-19.C: Likewise. + * g++.target/riscv/rvv/base/bug-20.C: Likewise. + * g++.target/riscv/rvv/base/bug-21.C: Likewise. + * g++.target/riscv/rvv/base/bug-22.C: Likewise. + * g++.target/riscv/rvv/base/bug-23.C: Likewise. + * g++.target/riscv/rvv/base/bug-3.C: Likewise. + * g++.target/riscv/rvv/base/bug-8.C: Likewise. + * gcc.dg/vect/pr88598-1.c: Likewise. + * gcc.dg/vect/pr88598-2.c: Likewise. + * gcc.dg/vect/pr88598-3.c: Likewise. + * gcc.dg/vect/slp-26.c: Likewise. + * gcc.dg/vect/slp-reduc-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/copysign-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/shift-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vand-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vor-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c: Likewise. + * gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c: Likewise. + * gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-10.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-11.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-12.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-13.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-14.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-15.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-16.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-17.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-18.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-19.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-8.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/slp_run-9.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/live_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/partial/live_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/series_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c: Likewise. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c: Likewise. + * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/unop/vnot-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/unop/math-ceil-run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/unop/math-ceil-run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/unop/math-floor-run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/unop/math-floor-run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/unop/math-nearbyint-run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/unop/math-nearbyint-run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/unop/math-rint-run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/unop/math-rint-run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/unop/math-round-run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/unop/math-round-run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/unop/math-trunc-run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/unop/math-trunc-run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-runu.c: Likewise. + * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run-10.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run-11.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run-12.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-10.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-11.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-9.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-10.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-11.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-8.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-9.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-10.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-9.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-10.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-9.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/strided_store_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/strided_store_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-8.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-8.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-8.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c: Likewise. + * gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/reduc_run-9.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c: Likewise. + * gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c: Likewise. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c: Likewise. + * gcc.target/riscv/rvv/base/bug-3.c: Likewise. + * gcc.target/riscv/rvv/base/bug-4.c: Likewise. + * gcc.target/riscv/rvv/base/bug-5.c: Likewise. + * gcc.target/riscv/rvv/base/float-point-frm-run-1.c: Likewise. + * gcc.target/riscv/rvv/base/float-point-frm-run-2.c: Likewise. + * gcc.target/riscv/rvv/base/float-point-frm-run-3.c: Likewise. + * gcc.target/riscv/rvv/base/float-point-frm-run-4.c: Likewise. + * gcc.target/riscv/rvv/base/float-point-frm-run-5.c: Likewise. + * gcc.target/riscv/rvv/base/abi-call-args-1-run.c: Likewise. + * gcc.target/riscv/rvv/base/abi-call-args-2-run.c: Likewise. + * gcc.target/riscv/rvv/base/abi-call-args-3-run.c: Likewise. + * gcc.target/riscv/rvv/base/abi-call-args-4-run.c: Likewise. + * gcc.target/riscv/rvv/base/abi-call-return-run.c: Likewise. + * gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c: Likewise. + +2023-09-28 xuli <xuli1@eswincomputing.com> + + PR target/111533 + * gcc.target/riscv/rvv/base/pr111533-1.c: New test. + * gcc.target/riscv/rvv/base/pr111533-2.c: New test. + +2023-09-27 Manos Anagnostakis <manos.anagnostakis@vrull.eu> + Philipp Tomsich <philipp.tomsich@vrull.eu> + Manolis Tsamis <manolis.tsamis@vrull.eu> + + * gcc.target/aarch64/ampere1-no_ldp_combine.c: Removed. + * gcc.target/aarch64/ldp_aligned.c: New test. + * gcc.target/aarch64/ldp_always.c: New test. + * gcc.target/aarch64/ldp_never.c: New test. + * gcc.target/aarch64/stp_aligned.c: New test. + * gcc.target/aarch64/stp_always.c: New test. + * gcc.target/aarch64/stp_never.c: New test. + +2023-09-27 Andre Vieira <andre.simoesdiasvieira@arm.com> + + * gcc.dg/vect/vect-simd-clone-19.c: New test. + +2023-09-27 Richard Biener <rguenther@suse.de> + + * gcc.dg/fold-abs-6.c: New testcase. + +2023-09-27 Joern Rennecke <joern.rennecke@embecosm.com> + + * gcc.target/riscv/shift-shift-1.c: Avoid spurious pattern matches. + * gcc.target/riscv/shift-shift-3.c: Likewise. + * gcc.target/riscv/zba-shNadd-01.c: Likewise. + * gcc.target/riscv/zba-shNadd-02.c: Likewise. + * gcc.target/riscv/zbb-andn-orn-xnor-01.c: Likewise. + * gcc.target/riscv/zbb-andn-orn-xnor-02.c: Likewise. + * gcc.target/riscv/zbb-min-max.c: Likewise. + * gcc.target/riscv/zero-extend-1.c: Likewise. + * gcc.target/riscv/zero-extend-2.c: Likewise. + * gcc.target/riscv/zero-extend-3.c: Likewise. + * gcc.target/riscv/zero-extend-4.c: Likewise. + * gcc.target/riscv/zero-extend-5.c: Likewise. + * gcc.target/riscv/_Float16-soft-2.c: Likewise. + * gcc.target/riscv/_Float16-soft-3.c: Likewise. + * gcc.target/riscv/_Float16-zfh-1.c: Likewise. + * gcc.target/riscv/_Float16-zfh-2.c: Likewise. + * gcc.target/riscv/_Float16-zfh-3.c: Likewise. + * gcc.target/riscv/and-extend-1.c: Likewise. + * gcc.target/riscv/and-extend-2.c: Likewise. + * gcc.target/riscv/pr108987.c: Likewise. + * gcc.target/riscv/ret-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/align-1.c: Likewise. + * gcc.target/riscv/rvv/autovec/align-2.c: Likewise. + * gcc.target/riscv/zba-shNadd-04.c: Likewise. + * gcc.target/riscv/zba-shNadd-07.c: Likewise. + * gcc.target/riscv/zbb-rol-ror-02.c: Likewise. + * gcc.target/riscv/zbbw.c: Likewise. + * gcc.target/riscv/zbc32.c: Likewise. + * gcc.target/riscv/zbc64.c: Likewise. + * gcc.target/riscv/zbkb32.c: Likewise. + * gcc.target/riscv/zbkb64.c: Likewise. + * gcc.target/riscv/zbkc32.c: Likewise. + * gcc.target/riscv/zbkc64.c: Likewise. + * gcc.target/riscv/zbkx32.c: Likewise. + * gcc.target/riscv/zbkx64.c: Likewise. + * gcc.target/riscv/zfa-fleq-fltq.c: Likewise. + * gcc.target/riscv/zfa-fli-zfh.c: Likewise. + * gcc.target/riscv/zfa-fli.c: Likewise. + * gcc.target/riscv/zknd64.c: Likewise. + * gcc.target/riscv/zksed32.c: Likewise. + * gcc.target/riscv/zksed64.c: Likewise. + * gcc.target/riscv/zksh32.c: Likewise. + * gcc.target/riscv/zksh64.c: Likewise. + * gcc.target/riscv/_Float16-soft-1.c: Likewise. + * gcc.target/riscv/_Float16-zfhmin-1.c: Likewise. + * gcc.target/riscv/_Float16-zfhmin-2.c: Likewise. + * gcc.target/riscv/_Float16-zfhmin-3.c: Likewise. + * gcc.target/riscv/_Float16-zhinxmin-1.c: Likewise. + * gcc.target/riscv/_Float16-zhinxmin-2.c: Likewise. + * gcc.target/riscv/_Float16-zhinxmin-3.c: Likewise. + * gcc.target/riscv/fle-ieee.c: Likewise. + * gcc.target/riscv/fle-snan.c: Likewise. + * gcc.target/riscv/flef-ieee.c: Likewise. + * gcc.target/riscv/flef-snan.c: Likewise. + * gcc.target/riscv/flt-ieee.c: Likewise. + * gcc.target/riscv/flt-snan.c: Likewise. + * gcc.target/riscv/fltf-ieee.c: Likewise. + * gcc.target/riscv/fltf-snan.c: Likewise. + * gcc.target/riscv/interrupt-1.c: Likewise. + * gcc.target/riscv/interrupt-mmode.c: Likewise. + * gcc.target/riscv/interrupt-smode.c: Likewise. + * gcc.target/riscv/interrupt-umode.c: Likewise. + * gcc.target/riscv/pr106888.c: Likewise. + * gcc.target/riscv/pr89835.c: Likewise. + * gcc.target/riscv/shift-and-1.c: Likewise. + * gcc.target/riscv/shift-and-2.c: Likewise. + * gcc.target/riscv/shift-shift-2.c: Likewise. + * gcc.target/riscv/shift-shift-4.c: Likewise. + * gcc.target/riscv/shift-shift-5.c: Likewise. + * gcc.target/riscv/shorten-memrefs-7.c: Likewise. + * gcc.target/riscv/sign-extend.c: Likewise. + * gcc.target/riscv/switch-qi.c: Likewise. + * gcc.target/riscv/switch-si.c: Likewise. + * gcc.target/riscv/xtheadbb-ext-1.c: Likewise. + * gcc.target/riscv/xtheadbb-ext.c: Likewise. + * gcc.target/riscv/xtheadbb-extu-1.c: Likewise. + * gcc.target/riscv/xtheadbb-extu.c: Likewise. + * gcc.target/riscv/xtheadbb-strlen.c: Likewise. + * gcc.target/riscv/xtheadbs-tst.c: Likewise. + * gcc.target/riscv/xtheadfmv-fmv.c: Likewise. + * gcc.target/riscv/xventanacondops-primitiveSemantics.c: Likewise. + * gcc.target/riscv/zba-adduw.c: Likewise. + * gcc.target/riscv/zba-shadd.c: Likewise. + * gcc.target/riscv/zba-slliuw.c: Likewise. + * gcc.target/riscv/zba-zextw.c: Likewise. + * gcc.target/riscv/zbb-min-max-02.c: Likewise. + * gcc.target/riscv/zbb-min-max-03.c: Likewise. + * gcc.target/riscv/zbb-rol-ror-01.c: Likewise. + * gcc.target/riscv/zbb-rol-ror-03.c: Likewise. + * gcc.target/riscv/zbb-rol-ror-04.c: Likewise. + * gcc.target/riscv/zbb-rol-ror-05.c: Likewise. + * gcc.target/riscv/zbb-rol-ror-06.c: Likewise. + * gcc.target/riscv/zbb-rol-ror-07.c: Likewise. + * gcc.target/riscv/zbb-rol-ror-08.c: Likewise. + * gcc.target/riscv/zbb-rol-ror-09.c: Likewise. + * gcc.target/riscv/zbb-strlen.c: Likewise. + * gcc.target/riscv/zbb_32_bswap-1.c: Likewise. + * gcc.target/riscv/zbb_32_bswap-2.c: Likewise. + * gcc.target/riscv/zbb_bswap-1.c: Likewise. + * gcc.target/riscv/zbb_bswap-2.c: Likewise. + * gcc.target/riscv/zbs-bclr.c: Likewise. + * gcc.target/riscv/zbs-bext-02.c: Likewise. + * gcc.target/riscv/zbs-bext.c: Likewise. + * gcc.target/riscv/zbs-binv.c: Likewise. + * gcc.target/riscv/zbs-bset.c: Likewise. + * gcc.target/riscv/zero-scratch-regs-2.c: Likewise. + * gcc.target/riscv/zicond-primitiveSemantics.c: Likewise. + * gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c: Likewise. + * gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c: Likewise. + * gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c: Likewise. + * gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c: Likewise. + +2023-09-27 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/unop/math-roundeven-0.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-roundeven-1.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-roundeven-2.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-roundeven-3.c: New test. + * gcc.target/riscv/rvv/autovec/vls/math-roundeven-1.c: New test. + +2023-09-27 Joern Rennecke <joern.rennecke@embecosm.com> + + * lib/target-supports.exp (check_effective_target_rv_float_abi_soft): + New proc. + (check_effective_target_riscv_d): Likewise. + (check_effective_target_riscv_v): Likewise. + (check_effective_target_riscv_zfh): Likewise. + (check_effective_target_riscv_v_ok): likewise. + (check_effective_target_riscv_zfh_ok): Likewise. + (riscv_get_arch, add_options_for_riscv_v): Likewise. + (add_options_for_riscv_zfh): Likewise. + (add_options_for_riscv_d): Likewise. + +2023-09-27 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/unop/math-trunc-0.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-trunc-1.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-trunc-2.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-trunc-3.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-trunc-run-1.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-trunc-run-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c: New test. + +2023-09-26 Andrew Pinski <pinskia@gmail.com> + + PR testsuite/111603 + * gcc.dg/tree-ssa/pr111456-1.c: Use `signed char` instead of plain `char`. + +2023-09-26 Xiao Zeng <zengxiao@eswincomputing.com> + Jeff Law <jlaw@ventanamicro.com> + + * gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c: New test. + * gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c: New test. + * gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c: New test. + * gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c: New test. + +2023-09-26 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/111599 + * gcc.dg/pr111599.c: New. + +2023-09-26 Andrew Pinski <apinski@marvell.com> + + PR tree-optimization/106164 + PR tree-optimization/111456 + * gcc.dg/tree-ssa/cmpbit-6.c: New test. + * gcc.dg/tree-ssa/cmpbit-7.c: New test. + * gcc.dg/tree-ssa/pr111456-1.c: New test. + +2023-09-26 Andrew Pinski <apinski@marvell.com> + + PR tree-optimization/111469 + * gcc.c-torture/execute/pr111469-1.c: New test. + +2023-09-26 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + PR tree-optimization/111594 + PR tree-optimization/110660 + * gcc.target/riscv/rvv/autovec/cond/cond_reduc-1.c: New test. + * gcc.target/riscv/rvv/autovec/cond/pr111594.c: New test. + +2023-09-26 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/unop/math-round-0.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-round-1.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-round-2.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-round-3.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-round-run-1.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-round-run-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/math-round-1.c: New test. + +2023-09-26 Maciej W. Rozycki <macro@embecosm.com> + + * gcc.target/riscv/rvv/autovec/vmv-imm-template.h: Remove + <assert.h> inclusion. + +2023-09-26 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/unop/math-rint-0.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-rint-1.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-rint-2.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-rint-3.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-rint-run-1.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-rint-run-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/math-rint-1.c: New test. + +2023-09-26 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/unop/test-math.h: Add helper function. + * gcc.target/riscv/rvv/autovec/unop/math-nearbyint-0.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-nearbyint-1.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-nearbyint-2.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-nearbyint-3.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-nearbyint-run-1.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-nearbyint-run-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c: New test. + +2023-09-25 Vladimir N. Makarov <vmakarov@redhat.com> + + PR middle-end/111497 + * g++.target/i386/pr111497.C: new test. + +2023-09-25 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/opt102.adb:New test. + * gnat.dg/opt102_pkg.adb, gnat.dg/opt102_pkg.ads: New helper. + +2023-09-25 Andrew Pinski <apinski@marvell.com> + + PR tree-optimization/110386 + * gcc.c-torture/compile/pr110386-1.c: New test. + * gcc.c-torture/compile/pr110386-2.c: New test. + +2023-09-25 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + PR target/111548 + * gcc.target/riscv/rvv/autovec/pr111548.c: New test. + +2023-09-25 Kewen Lin <linkw@linux.ibm.com> + + PR target/111366 + * g++.target/powerpc/pr111366.C: New test. + +2023-09-25 Kewen Lin <linkw@linux.ibm.com> + + PR target/111380 + * gcc.target/powerpc/pr111380-1.c: New test. + * gcc.target/powerpc/pr111380-2.c: New test. + +2023-09-25 Guo Jie <guojie@loongson.cn> + + * gcc.target/loongarch/vector/lasx/lasx-vec-construct-opt.c: New test. + * gcc.target/loongarch/vector/lsx/lsx-vec-construct-opt.c: New test. + +2023-09-24 Paul Thomas <pault@gcc.gnu.org> + + PR fortran/68155 + * gfortran.dg/pr68155.f90: New test. + +2023-09-24 Andrew Pinski <apinski@marvell.com> + + PR tree-optimization/111543 + * gcc.dg/tree-ssa/bitops-4.c: New test. + +2023-09-24 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * gcc.target/riscv/rvv/autovec/vls/def.h: + * gcc.target/riscv/rvv/autovec/vls/cond_convert-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_convert-10.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_convert-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_convert-3.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_convert-4.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_convert-5.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_convert-6.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_convert-7.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_convert-8.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_convert-9.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_copysign-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_narrow-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_narrow-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_trunc-4.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_trunc-5.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_wfnma-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c: New test. + * gcc.target/riscv/rvv/autovec/vls/narrow-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/narrow-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/narrow-3.c: New test. + * gcc.target/riscv/rvv/autovec/vls/wred-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/wred-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/wred-3.c: New test. + +2023-09-23 Harald Anlauf <anlauf@gmx.de> + + PR fortran/95710 + * gfortran.dg/pr95710.f90: New test. + +2023-09-23 Jakub Jelinek <jakub@redhat.com> + + PR c++/111455 + * g++.dg/ext/integer-pack8.C: New test. + +2023-09-23 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c: New test. + +2023-09-23 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/unop/math-floor-0.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-floor-1.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-floor-2.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-floor-3.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-floor-run-1.c: New test. + * gcc.target/riscv/rvv/autovec/unop/math-floor-run-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/math-floor-1.c: New test. + +2023-09-23 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/unop/math-ceil-run-0.c: Remove. + +2023-09-22 Jason Merrill <jason@redhat.com> + + * g++.dg/cpp2a/constexpr-union7.C: New test. + +2023-09-22 Jason Merrill <jason@redhat.com> + + PR c++/111529 + * g++.dg/ext/unroll-4.C: New test. + +2023-09-22 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/unop/math-ceil-0.c: Adjust body check. + * gcc.target/riscv/rvv/autovec/unop/math-ceil-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/unop/math-ceil-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/unop/math-ceil-3.c: Ditto. + +2023-09-22 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS modes. + * gcc.target/riscv/rvv/autovec/vls/wfma-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/wfma-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/wfma-3.c: New test. + * gcc.target/riscv/rvv/autovec/vls/wfms-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/wfnma-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/wfnms-1.c: New test. + +2023-09-22 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS modes cond tests. + * gcc.target/riscv/rvv/autovec/vls/wadd-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/wadd-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/wadd-3.c: New test. + * gcc.target/riscv/rvv/autovec/vls/wadd-4.c: New test. + * gcc.target/riscv/rvv/autovec/vls/wmul-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/wmul-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/wmul-3.c: New test. + * gcc.target/riscv/rvv/autovec/vls/wsub-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/wsub-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/wsub-3.c: New test. + * gcc.target/riscv/rvv/autovec/vls/wsub-4.c: New test. + +2023-09-22 Patrick Palka <ppalka@redhat.com> + + PR c++/111493 + * g++.dg/cpp23/subscript15.C: New test. + +2023-09-22 Patrick Palka <ppalka@redhat.com> + + PR c++/111485 + * g++.dg/cpp2a/concepts-ttp5.C: New test. + * g++.dg/cpp2a/concepts-ttp6.C: New test. + +2023-09-22 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/math-ceil-0.c: Moved to... + * gcc.target/riscv/rvv/autovec/unop/math-ceil-0.c: ...here. + * gcc.target/riscv/rvv/autovec/math-ceil-1.c: Moved to... + * gcc.target/riscv/rvv/autovec/unop/math-ceil-1.c: ...here. + * gcc.target/riscv/rvv/autovec/math-ceil-2.c: Moved to... + * gcc.target/riscv/rvv/autovec/unop/math-ceil-2.c: ...here. + * gcc.target/riscv/rvv/autovec/math-ceil-3.c: Moved to... + * gcc.target/riscv/rvv/autovec/unop/math-ceil-3.c: ...here. + * gcc.target/riscv/rvv/autovec/math-ceil-run-0.c: Moved to... + * gcc.target/riscv/rvv/autovec/unop/math-ceil-run-0.c: ...here. + * gcc.target/riscv/rvv/autovec/math-ceil-run-1.c: Moved to... + * gcc.target/riscv/rvv/autovec/unop/math-ceil-run-1.c: ...here. + * gcc.target/riscv/rvv/autovec/math-ceil-run-2.c: Moved to... + * gcc.target/riscv/rvv/autovec/unop/math-ceil-run-2.c: ...here. + * gcc.target/riscv/rvv/autovec/test-math.h: Moved to... + * gcc.target/riscv/rvv/autovec/unop/test-math.h: ...here. + +2023-09-22 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS conditional tests. + * gcc.target/riscv/rvv/autovec/vls/cond_add-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_add-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_and-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_div-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_div-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_max-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_max-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_min-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_min-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_not-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c: New test. + +2023-09-22 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/test-math.h: Rename. + * gcc.target/riscv/rvv/autovec/math-ceil-0.c: Ditto. + * gcc.target/riscv/rvv/autovec/math-ceil-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/math-ceil-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/math-ceil-3.c: Ditto. + * gcc.target/riscv/rvv/autovec/math-ceil-run-0.c: Ditto. + * gcc.target/riscv/rvv/autovec/math-ceil-run-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/math-ceil-run-2.c: Ditto. + +2023-09-22 xuli <xuli1@eswincomputing.com> + + PR target/111451 + * gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Adjust case. + * gcc.target/riscv/rvv/autovec/vls/perm-4.c: Ditto. + +2023-09-22 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/math-ceil-run-0.c: Remove arch and abi. + * gcc.target/riscv/rvv/autovec/math-ceil-run-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/math-ceil-run-2.c: Ditto. + +2023-09-22 Lehua Ding <lehua.ding@rivai.ai> + + * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c: New test. + * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: New test. + * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c: New test. + * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c: New test. + +2023-09-22 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c: + Remove reference to math.h. + * gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c: Ditto. + * gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c: Ditto. + +2023-09-22 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/math-ceil-0.c: New test. + * gcc.target/riscv/rvv/autovec/math-ceil-1.c: New test. + * gcc.target/riscv/rvv/autovec/math-ceil-2.c: New test. + * gcc.target/riscv/rvv/autovec/math-ceil-3.c: New test. + * gcc.target/riscv/rvv/autovec/math-ceil-run-0.c: New test. + * gcc.target/riscv/rvv/autovec/math-ceil-run-1.c: New test. + * gcc.target/riscv/rvv/autovec/math-ceil-run-2.c: New test. + * gcc.target/riscv/rvv/autovec/test-math.h: New test. + * gcc.target/riscv/rvv/autovec/vls/math-ceil-1.c: New test. + +2023-09-21 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * gcc.target/riscv/rvv/autovec/vls/abs-2.c: New test. + +2023-09-21 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * gcc.target/riscv/rvv/autovec/vls/abs-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/not-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/sqrt-1.c: New test. + +2023-09-21 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS mult high. + * gcc.target/riscv/rvv/autovec/vls/mulh-1.c: New test. + +2023-09-21 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + PR target/110751 + * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Adapt test. + * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c: Ditto. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c: Ditto. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c: Ditto. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c: Ditto. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c: Ditto. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c: Ditto. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c: Ditto. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c: Ditto. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c: Ditto. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c: Ditto. + +2023-09-21 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + PR target/111486 + * gcc.target/riscv/rvv/autovec/pr111486.c: New test. + +2023-09-21 Jiufu Guo <guojiufu@linux.ibm.com> + + PR tree-optimization/111355 + * gcc.dg/pr111355.c: New test. + +2023-09-21 xuli <xuli1@eswincomputing.com> + + PR target/111450 + * gcc.target/riscv/rvv/base/pr111450.c: New test. + +2023-09-21 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * gcc.target/riscv/rvv/autovec/vls/convert-1.c: New test. + * gcc.target/riscv/rvv/autovec/vls/convert-10.c: New test. + * gcc.target/riscv/rvv/autovec/vls/convert-11.c: New test. + * gcc.target/riscv/rvv/autovec/vls/convert-12.c: New test. + * gcc.target/riscv/rvv/autovec/vls/convert-2.c: New test. + * gcc.target/riscv/rvv/autovec/vls/convert-3.c: New test. + * gcc.target/riscv/rvv/autovec/vls/convert-4.c: New test. + * gcc.target/riscv/rvv/autovec/vls/convert-5.c: New test. + * gcc.target/riscv/rvv/autovec/vls/convert-6.c: New test. + * gcc.target/riscv/rvv/autovec/vls/convert-7.c: New test. + * gcc.target/riscv/rvv/autovec/vls/convert-8.c: New test. + * gcc.target/riscv/rvv/autovec/vls/convert-9.c: New test. + 2023-09-20 Lewis Hyatt <lhyatt@gmail.com> PR preprocessor/90400 diff --git a/gcc/testsuite/g++.dg/cpp23/subscript15.C b/gcc/testsuite/g++.dg/cpp23/subscript15.C new file mode 100644 index 0000000..fece96b --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp23/subscript15.C @@ -0,0 +1,25 @@ +// PR c++/111493 +// { dg-do compile { target c++23 } } + +template<class T, class... Ts> +concept CartesianIndexable = requires(T t, Ts... ts) { t[ts...]; }; + +static_assert(!CartesianIndexable<int>); +static_assert(!CartesianIndexable<int, int>); +static_assert(!CartesianIndexable<int, int, int>); + +static_assert(!CartesianIndexable<int*>); +static_assert(CartesianIndexable<int*, int>); +static_assert(!CartesianIndexable<int*, int, int>); +static_assert(!CartesianIndexable<int*, int*>); + +template<class... Ts> +struct A { + void operator[](Ts...); +}; + +static_assert(!CartesianIndexable<A<>, int>); +static_assert(CartesianIndexable<A<int>, int>); +static_assert(!CartesianIndexable<A<int>>); +static_assert(!CartesianIndexable<A<int>, int, int>); +static_assert(CartesianIndexable<A<int, int>, int, int>); diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-ttp5.C b/gcc/testsuite/g++.dg/cpp2a/concepts-ttp5.C new file mode 100644 index 0000000..abc22ce --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp2a/concepts-ttp5.C @@ -0,0 +1,24 @@ +// PR c++/111485 +// { dg-do compile { target c++20 } } + +template<class T> constexpr bool always_true = true; + +template<class T> concept C = always_true<T>; +template<class T> concept D = C<T> || true; + +template<template<C> class TT> struct example; +template<template<D> class UU> using example_t = example<UU>; + +template<class T> +struct A { + template<template<C> class TT> struct example; + + template<template<D> class UU> using example_t = example<UU>; + + template<class U> + struct B { + template<template<D> class UU> using example_t = example<UU>; + }; +}; + +template struct A<int>::B<int>; diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-ttp6.C b/gcc/testsuite/g++.dg/cpp2a/concepts-ttp6.C new file mode 100644 index 0000000..6396e99 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp2a/concepts-ttp6.C @@ -0,0 +1,17 @@ +// PR c++/111485 +// { dg-do compile { target c++20 } } + +template<class T, bool V> constexpr bool always_true = true; + +template<class T, bool V> concept C = always_true<T, V>; + +template<bool V, template<class T> requires C<T, V> class TT> +void f(); + +template<class T> requires C<T, true> +struct A; + +int main() { + f<true, A>(); + f<false, A>(); // { dg-error "no match|constraint mismatch" } +} diff --git a/gcc/testsuite/g++.dg/cpp2a/constexpr-union7.C b/gcc/testsuite/g++.dg/cpp2a/constexpr-union7.C new file mode 100644 index 0000000..230fa6e --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp2a/constexpr-union7.C @@ -0,0 +1,6 @@ +// { dg-do compile { target c++14 } } +// { dg-options "" } + +union U { int i; float f; }; +constexpr auto g (U u) { return (u.i = 42); } // { dg-error "active member" "" { target c++17_down } } +static_assert (g({.f = 3.14}) == 42); // { dg-error "non-constant" "" { target c++17_down } } diff --git a/gcc/testsuite/g++.dg/ext/integer-pack8.C b/gcc/testsuite/g++.dg/ext/integer-pack8.C new file mode 100644 index 0000000..ad15cc3 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/integer-pack8.C @@ -0,0 +1,37 @@ +// PR c++/111455 +// { dg-do compile { target c++11 } } + +namespace std +{ + template <typename T, T... I> + struct integer_sequence {}; + + template <typename T, T N> + using make_integer_sequence + = integer_sequence <T, __integer_pack (N)...>; +} + +template <long... V> +void foo (std::integer_sequence <long, V...>) +{} + +template <typename ...T> +struct U +{ + static constexpr long value = 1; + constexpr operator int () = delete; + constexpr operator long () { return value; } +}; + +template <typename T> +struct R +{ + using S = std::make_integer_sequence <long, U <T> {}>; + R () noexcept (noexcept (foo (S ()))) {} +}; + +int +main () +{ + R <long>(); +} diff --git a/gcc/testsuite/g++.dg/ext/unroll-4.C b/gcc/testsuite/g++.dg/ext/unroll-4.C new file mode 100644 index 0000000..d488aca --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/unroll-4.C @@ -0,0 +1,16 @@ +// PR c++/111529 +// { dg-do compile { target c++11 } } +// { dg-additional-options -Wno-c++20-extensions } + +template <int> +void f() { + []<int>() { + #pragma GCC unroll 9 + for (int i = 1; i; --i) { + } + }; +} + +int main() { + f<0>(); +} diff --git a/gcc/testsuite/g++.target/i386/pr111497.C b/gcc/testsuite/g++.target/i386/pr111497.C new file mode 100644 index 0000000..a645bb9 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/pr111497.C @@ -0,0 +1,22 @@ +// { dg-do compile { target ia32 } } +// { dg-options "-march=i686 -mtune=generic -fPIC -O2 -g" } + +class A; +struct B { const char *b1; int b2; }; +struct C : B { C (const char *x, int y) { b1 = x; b2 = y; } }; +struct D : C { D (B x) : C (x.b1, x.b2) {} }; +struct E { E (A *); }; +struct F : E { D f1, f2, f3, f4, f5, f6; F (A *, const B &, const B &, const B &); }; +struct G : F { G (A *, const B &, const B &, const B &); }; +struct H { int h; }; +struct I { H i; }; +struct J { I *j; }; +struct A : J {}; +inline F::F (A *x, const B &y, const B &z, const B &w) + : E(x), f1(y), f2(z), f3(w), f4(y), f5(z), f6(w) {} +G::G (A *x, const B &y, const B &z, const B &w) : F(x, y, z, w) +{ + H *h = &x->j->i; + if (h) + h->h++; +} diff --git a/gcc/testsuite/g++.target/powerpc/pr111366.C b/gcc/testsuite/g++.target/powerpc/pr111366.C new file mode 100644 index 0000000..6d3d8eb --- /dev/null +++ b/gcc/testsuite/g++.target/powerpc/pr111366.C @@ -0,0 +1,48 @@ +/* { dg-do compile } */ +/* Use -Wno-attributes to suppress the possible warning on always_inline. */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -Wno-attributes" } */ + +/* Verify it doesn't emit any error messages. */ + +#include <stddef.h> +#define HWY_PRAGMA(tokens) _Pragma (#tokens) +#define HWY_PUSH_ATTRIBUTES(targets_str) HWY_PRAGMA (GCC target targets_str) +__attribute__ ((always_inline)) void +PreventElision () +{ + asm(""); +} +#define HWY_BEFORE_NAMESPACE() HWY_PUSH_ATTRIBUTES (",cpu=power10") +HWY_BEFORE_NAMESPACE () namespace detail +{ + template <typename, size_t, int> struct CappedTagChecker + { + }; +} +template <typename T, size_t kLimit, int kPow2 = 0> +using CappedTag = detail::CappedTagChecker<T, kLimit, kPow2>; +template <typename, size_t, size_t kMinArg, class Test> struct ForeachCappedR +{ + static void Do (size_t, size_t) + { + CappedTag<int, kMinArg> d; + Test () (int(), d); + } +}; +template <class Test> struct ForPartialVectors +{ + template <typename T> void operator() (T) + { + ForeachCappedR<T, 1, 1, Test>::Do (1, 1); + } +}; +struct TestFloorLog2 +{ + template <class T, class DF> void operator() (T, DF) { PreventElision (); } +}; +void +TestAllFloorLog2 () +{ + ForPartialVectors<TestFloorLog2> () (float()); +} + diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-10.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-10.C index 503b6c3..4fe7fd3 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-10.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-10.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-11.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-11.C index 151d736..a916d72 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-11.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-11.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C index 8ff6959..daa0e3b 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-12.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-13.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-13.C index 2a31e3d..4b96899 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-13.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-13.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C index a9935c1..bf0c7bd 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-14.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { { {riscv_vector} && {rv64} } } } } */ +/* { dg-do run { target { { {riscv_v} && {rv64} } } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-15.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-15.C index 627aa92..da95400 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-15.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-15.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C index d90d2d4..5e749d5 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-17.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-17.C index c29d637..32b8b2f 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-17.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-17.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-18.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-18.C index 868ec1e..8d88a9e 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-18.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-18.C @@ -1,4 +1,4 @@ -/* { dg-do compile { target { riscv_vector } } } */ +/* { dg-do compile { target { riscv_v } } } */ #include <iostream> #include "riscv_vector.h" diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-19.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-19.C index a6ba958..dfd9044 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-19.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-19.C @@ -1,4 +1,4 @@ -/* { dg-do compile { target { riscv_vector } } } */ +/* { dg-do compile { target { riscv_v } } } */ #include<cmath> #include<iomanip> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-2.C index 48529c3..475280f 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-2.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-2.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-20.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-20.C index 2a8591f..36eeeb4 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-20.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-20.C @@ -1,4 +1,4 @@ -/* { dg-do compile { target { riscv_vector } } } */ +/* { dg-do compile { target { riscv_v } } } */ #include<cmath> #include<iomanip> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-21.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-21.C index 77e06bf..12408c6 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-21.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-21.C @@ -1,4 +1,4 @@ -/* { dg-do compile { target { riscv_vector } } } */ +/* { dg-do compile { target { riscv_v } } } */ #include<cmath> #include<iomanip> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-22.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-22.C index 8ba18a0..9f15ac5 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-22.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-22.C @@ -1,4 +1,4 @@ -/* { dg-do compile { target { riscv_vector } } } */ +/* { dg-do compile { target { riscv_v } } } */ #include<cmath> #include<iomanip> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-23.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-23.C index 061063b..134ed83 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-23.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-23.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-3.C index 47e3188..b0ca43f 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-3.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-3.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-4.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-4.C index 400aea4..7ba1c1a2 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-4.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-4.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-5.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-5.C index caa826a..8d4615c 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-5.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-5.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-6.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-6.C index ec6e290..005d00d 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-6.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-6.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-7.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-7.C index a3ab397..411bd17 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-7.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-7.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-8.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-8.C index 7e1d6db..371d797 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-8.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-8.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-9.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-9.C index 119ec0e..8d17883 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-9.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-9.C @@ -1,4 +1,4 @@ -/* { dg-do run { target { { {riscv_vector} && {rv64} } } } } */ +/* { dg-do run { target { { {riscv_v} && {rv64} } } } } */ /* { dg-options "-O2" } */ #include<cstdalign> diff --git a/gcc/testsuite/gcc.c-torture/compile/pr110386-1.c b/gcc/testsuite/gcc.c-torture/compile/pr110386-1.c new file mode 100644 index 0000000..4fcc977 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr110386-1.c @@ -0,0 +1,9 @@ + +int f(int a) +{ + int c = c < 0 ? c : -c; + c = -c; + unsigned b = c; + unsigned t = b*a; + return t*t; +} diff --git a/gcc/testsuite/gcc.c-torture/compile/pr110386-2.c b/gcc/testsuite/gcc.c-torture/compile/pr110386-2.c new file mode 100644 index 0000000..c60e1b6 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr110386-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target i?86-*-* x86_64-*-* } } */ +/* { dg-options "-mavx" } */ + +#include <immintrin.h> + +__m128i do_stuff(__m128i XMM0) { + __m128i ABS0 = _mm_abs_epi32(XMM0); + __m128i MUL0 = _mm_mullo_epi32(ABS0, XMM0); + __m128i MUL1 = _mm_mullo_epi32(MUL0, MUL0); + return MUL1; +} diff --git a/gcc/testsuite/gcc.c-torture/execute/pr111469-1.c b/gcc/testsuite/gcc.c-torture/execute/pr111469-1.c new file mode 100644 index 0000000..b68d598 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr111469-1.c @@ -0,0 +1,38 @@ +/* PR tree-optimization/111469 */ + +long f; +char *g; +__attribute__((noinline)) +char o() { + char l; + while (f) + ; + l = *g; + return l; +} + +/* factor_out_conditional_conversion is able to remove the casts + from the 2 bbs (correctly) + but then minmax_replacement should not optimize this to a MIN_EXPR + as o has side effects. */ + +__attribute__((noinline)) +unsigned short gg(unsigned short a, unsigned short b) +{ + short d; + if (a > b) + { + d= b; + } + else + { + o(); + d = a; + } + return d; +} + +int main(void) +{ + gg(3, 2); +} diff --git a/gcc/testsuite/gcc.dg/fold-abs-6.c b/gcc/testsuite/gcc.dg/fold-abs-6.c new file mode 100644 index 0000000..42ef923 --- /dev/null +++ b/gcc/testsuite/gcc.dg/fold-abs-6.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fdump-tree-original" } */ + +float foo (float x, float y) +{ + return __builtin_fabsf (__builtin_copysignf (x, y)); +} + +/* { dg-final { scan-tree-dump "return ABS_EXPR <x>;" "original" } } */ diff --git a/gcc/testsuite/gcc.dg/pr111599.c b/gcc/testsuite/gcc.dg/pr111599.c new file mode 100644 index 0000000..25880b7 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr111599.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -fno-inline-functions-called-once -fno-inline-small-functions -fno-tree-dce -fno-tree-forwprop -fno-tree-fre" } */ + +int h(void); +void l(int); +void func_56(int p_57, unsigned p_58) { + // p_57 = 0x101BC642L; + if (p_57 || h()) { + int *l_105[2]; + l_105[0] = &p_57; + l(p_57); + } +} +void func_31(int p_33) { + func_56(0x101BC642L, (p_33)); +} diff --git a/gcc/testsuite/gcc.dg/torture/pr111614.c b/gcc/testsuite/gcc.dg/torture/pr111614.c new file mode 100644 index 0000000..0f3ecba --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr111614.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ + +int a, b, c, d, e; +static void f() { + int *g = &b; + b = 1; + for (; b >= 0; b--) { + c = 0; + for (; c <= 1; c++) + e = 0; + for (; e <= 1; e++) { + int h, i = h = 13; + for (; h; h--) + i = i << a; + d &= i + c + 9 + *g; + } + } +} +int main() { + f(); + for (;;) + ; +} diff --git a/gcc/testsuite/gcc.dg/tree-ssa/bitops-4.c b/gcc/testsuite/gcc.dg/tree-ssa/bitops-4.c new file mode 100644 index 0000000..73c8f39 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/bitops-4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -fdump-tree-optimized -fdump-tree-ccp1" } */ +/* PR tree-optimization/111543 */ + +void f_or(int a, int b, int *por) +{ + int c = ~a; + *por = (c | b) | a; +} +void f_and(int a, int b, int *pand) +{ + int c = ~a; + *pand = (c & b) & a; +} +/* { dg-final { scan-tree-dump-times "pand_\[0-9\]+.D. = 0" 1 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "por_\[0-9\]+.D. = -1" 1 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "pand_\[0-9\]+.D. = 0" 1 "ccp1" } } */ +/* { dg-final { scan-tree-dump-times "por_\[0-9\]+.D. = -1" 1 "ccp1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/cmpbit-6.c b/gcc/testsuite/gcc.dg/tree-ssa/cmpbit-6.c new file mode 100644 index 0000000..4ec73f0 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/cmpbit-6.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ +/* PR tree-optimization/106164 */ +/* PR tree-optimization/111456 */ + +_Bool iu(int a) +{ + _Bool t = a == 0; + unsigned t1 = a; + _Bool t2 = t1 >= 3; + return t & t2; +} + +_Bool is(int a) +{ + _Bool t = a == 0; + short t1 = a; + _Bool t2 = t1 >= 3; + return t & t2; +} + +/* { dg-final { scan-tree-dump-times "return 0" 2 "optimized" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/cmpbit-7.c b/gcc/testsuite/gcc.dg/tree-ssa/cmpbit-7.c new file mode 100644 index 0000000..ee04ebb --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/cmpbit-7.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-forwprop1" } */ +/* PR tree-optimization/106164 */ +/* PR tree-optimization/111456 */ + +_Bool f(int a) +{ + _Bool t = a == 3; + unsigned t1 = a; + _Bool t2 = t1 >= 3; + return t | t2; +} + +/* Should be able to optimize down to just `a > 2` during forwprop1 */ +/* { dg-final { scan-tree-dump-not "a_\[0-9\]+.D. == 3" "forwprop1" } } */ + +_Bool f1(int b) +{ + _Bool t = b == 3; + short t1 = b; + _Bool t2 = t1 >= 3; + return t | t2; +} + +/* Should be able to optimize down to just `a > 2` during forwprop1 as `((short)a) >= 3` is + true already when `a == 3`. */ +/* { dg-final { scan-tree-dump-not "b_\[0-9\]+.D. == 3" "forwprop1" } } */ +/* { dg-final { scan-tree-dump-times "_\[0-9\]+ > 2" 2 "forwprop1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr111456-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr111456-1.c new file mode 100644 index 0000000..ffff664 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr111456-1.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ +/* PR tree-optimization/111456 */ + +void foo(void); +static int i; +static int *j = &i; +static signed char l; +static void(a)(signed char) {} +static short(b)(short c, short d) { return c - d; } +static short(e)(short f, int g) { + return f < 0 || g < 0 || g >= 32 ? f : f >> g; +} +static short(h)(short f, int g) { return g >= 2 ?: f >> g; } +static signed char k(signed char m, short n) { + short o; + int *p = &i; + if (!(((m) >= 1) && ((m) <= 1))) { + __builtin_unreachable(); + } + o = e(i, i); + if (h(1, o)) + ; + else { + m = 0; + for (; m >= -20; m = b(m, 9)) + if (a(i), n) { + if (*p) + ; + else + foo(); + ; + } else + return l; + } + return i; +} +int main() { k(0 <= 0 > *j, i); } + + +/* { dg-final { scan-tree-dump-not "foo " "optimized" } } */ +/* { dg-final { scan-tree-dump "return 0;" "optimized" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/pr88598-1.c b/gcc/testsuite/gcc.dg/vect/pr88598-1.c index ddcebb0..d4a0014 100644 --- a/gcc/testsuite/gcc.dg/vect/pr88598-1.c +++ b/gcc/testsuite/gcc.dg/vect/pr88598-1.c @@ -51,4 +51,4 @@ main () /* ??? We need more constant folding for this to work with fully-masked loops. */ -/* { dg-final { scan-tree-dump-not {REDUC_PLUS} "optimized" { xfail { aarch64_sve || riscv_vector } } } } */ +/* { dg-final { scan-tree-dump-not {REDUC_PLUS} "optimized" { xfail { aarch64_sve || riscv_v } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr88598-2.c b/gcc/testsuite/gcc.dg/vect/pr88598-2.c index ef5ea8a..57d0c885 100644 --- a/gcc/testsuite/gcc.dg/vect/pr88598-2.c +++ b/gcc/testsuite/gcc.dg/vect/pr88598-2.c @@ -51,4 +51,4 @@ main () /* ??? We need more constant folding for this to work with fully-masked loops. */ -/* { dg-final { scan-tree-dump-not {REDUC_PLUS} "optimized" { xfail { aarch64_sve || riscv_vector } } } } */ +/* { dg-final { scan-tree-dump-not {REDUC_PLUS} "optimized" { xfail { aarch64_sve || riscv_v } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr88598-3.c b/gcc/testsuite/gcc.dg/vect/pr88598-3.c index 75b8d02..ee3a9ef 100644 --- a/gcc/testsuite/gcc.dg/vect/pr88598-3.c +++ b/gcc/testsuite/gcc.dg/vect/pr88598-3.c @@ -51,4 +51,4 @@ main () /* ??? We need more constant folding for this to work with fully-masked loops. */ -/* { dg-final { scan-tree-dump-not {REDUC_PLUS} "optimized" { xfail { aarch64_sve || riscv_vector } } } } */ +/* { dg-final { scan-tree-dump-not {REDUC_PLUS} "optimized" { xfail { aarch64_sve || riscv_v } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/slp-26.c b/gcc/testsuite/gcc.dg/vect/slp-26.c index 196981d..c964635 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-26.c +++ b/gcc/testsuite/gcc.dg/vect/slp-26.c @@ -47,7 +47,7 @@ int main (void) return 0; } -/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { mips_msa || { amdgcn-*-* || riscv_vector } } } } } } */ -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { mips_msa || { amdgcn-*-* || riscv_vector } } } } } */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! { mips_msa || { amdgcn-*-* || riscv_vector } } } } } } */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { mips_msa || { amdgcn-*-* || riscv_vector } } } } } */ +/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { mips_msa || { amdgcn-*-* || riscv_v } } } } } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { mips_msa || { amdgcn-*-* || riscv_v } } } } } */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! { mips_msa || { amdgcn-*-* || riscv_v } } } } } } */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { mips_msa || { amdgcn-*-* || riscv_v } } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/slp-reduc-7.c b/gcc/testsuite/gcc.dg/vect/slp-reduc-7.c index a8528ab..8b52635 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-reduc-7.c +++ b/gcc/testsuite/gcc.dg/vect/slp-reduc-7.c @@ -57,5 +57,5 @@ int main (void) /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail vect_no_int_add } } } */ /* For variable-length SVE, the number of scalar statements in the reduction exceeds the number of elements in a 128-bit granule. */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { xfail { vect_no_int_add || { { aarch64_sve && vect_variable_length } || { riscv_vector && vect_variable_length } } } } } } */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { xfail { vect_no_int_add || { { aarch64_sve && vect_variable_length } || { riscv_v && vect_variable_length } } } } } } */ /* { dg-final { scan-tree-dump-times "VEC_PERM_EXPR" 0 "vect" { xfail { aarch64_sve && vect_variable_length } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-19.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-19.c new file mode 100644 index 0000000..e7ed56c --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-19.c @@ -0,0 +1,22 @@ +/* { dg-require-effective-target vect_simd_clones } */ +/* { dg-do compile } */ + +int __attribute__ ((__simd__, const)) fn (int); + +void test (int * __restrict__ a, int * __restrict__ b, int n) +{ + for (int i = 0; i < n; ++i) + { + int a_; + if (b[i] > 0) + a_ = fn (b[i]); + else + a_ = b[i] + 5; + a[i] = a_; + } +} + +/* { dg-final { scan-tree-dump-not {loop contains function calls or data references} "vect" } } */ + +/* The LTO test produces two dump files and we scan the wrong one. */ +/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/ampere1-no_ldp_combine.c b/gcc/testsuite/gcc.target/aarch64/ampere1-no_ldp_combine.c deleted file mode 100644 index bc871f4..0000000 --- a/gcc/testsuite/gcc.target/aarch64/ampere1-no_ldp_combine.c +++ /dev/null @@ -1,11 +0,0 @@ -/* { dg-options "-O3 -mtune=ampere1" } */ - -long -foo (long a[]) -{ - return a[0] + a[1]; -} - -/* We should see two ldrs instead of one ldp. */ -/* { dg-final { scan-assembler {\tldr\t} } } */ -/* { dg-final { scan-assembler-not {\tldp\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_aligned.c b/gcc/testsuite/gcc.target/aarch64/ldp_aligned.c new file mode 100644 index 0000000..f44f961 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ldp_aligned.c @@ -0,0 +1,66 @@ +/* { dg-options "-O2 --param=aarch64-ldp-policy=aligned -mcpu=generic" } */ + +#include <stdlib.h> +#include <stdint.h> + +typedef int v4si __attribute__ ((vector_size (16))); + +#define LDP_TEST_ALIGNED(TYPE) \ +TYPE ldp_aligned_##TYPE(char* ptr){ \ + TYPE a_0, a_1; \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + a_0 = arr[0]; \ + a_1 = arr[1]; \ + return a_0 + a_1; \ +} + +#define LDP_TEST_UNALIGNED(TYPE) \ +TYPE ldp_unaligned_##TYPE(char* ptr){ \ + TYPE a_0, a_1; \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + TYPE *a = arr+1; \ + a_0 = a[0]; \ + a_1 = a[1]; \ + return a_0 + a_1; \ +} + +#define LDP_TEST_ADJUST_ALIGNED(TYPE) \ +TYPE ldp_aligned_adjust_##TYPE(char* ptr){ \ + TYPE a_0, a_1, a_2, a_3, a_4; \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + a_0 = arr[100]; \ + a_1 = arr[101]; \ + a_2 = arr[102]; \ + a_3 = arr[103]; \ + a_4 = arr[110]; \ + return a_0 + a_1 + a_2 + a_3 + a_4; \ +} + +#define LDP_TEST_ADJUST_UNALIGNED(TYPE) \ +TYPE ldp_unaligned_adjust_##TYPE(char* ptr){ \ + TYPE a_0, a_1, a_2, a_3, a_4; \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + TYPE *a = arr+1; \ + a_0 = a[100]; \ + a_1 = a[101]; \ + a_2 = a[102]; \ + a_3 = a[103]; \ + a_4 = a[110]; \ + return a_0 + a_1 + a_2 + a_3 + a_4; \ +} + +LDP_TEST_ALIGNED(int32_t); +LDP_TEST_ALIGNED(int64_t); +LDP_TEST_ALIGNED(v4si); +LDP_TEST_UNALIGNED(int32_t); +LDP_TEST_UNALIGNED(int64_t); +LDP_TEST_UNALIGNED(v4si); +LDP_TEST_ADJUST_ALIGNED(int32_t); +LDP_TEST_ADJUST_ALIGNED(int64_t); +LDP_TEST_ADJUST_UNALIGNED(int32_t); +LDP_TEST_ADJUST_UNALIGNED(int64_t); + +/* { dg-final { scan-assembler-times "ldp\tw\[0-9\]+, w\[0-9\]" 3 } } */ +/* { dg-final { scan-assembler-times "ldp\tx\[0-9\]+, x\[0-9\]" 3 } } */ +/* { dg-final { scan-assembler-times "ldp\tq\[0-9\]+, q\[0-9\]" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_always.c b/gcc/testsuite/gcc.target/aarch64/ldp_always.c new file mode 100644 index 0000000..9cada57 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ldp_always.c @@ -0,0 +1,66 @@ +/* { dg-options "-O2 --param=aarch64-ldp-policy=always -mcpu=generic" } */ + +#include <stdlib.h> +#include <stdint.h> + +typedef int v4si __attribute__ ((vector_size (16))); + +#define LDP_TEST_ALIGNED(TYPE) \ +TYPE ldp_aligned_##TYPE(char* ptr){ \ + TYPE a_0, a_1; \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + a_0 = arr[0]; \ + a_1 = arr[1]; \ + return a_0 + a_1; \ +} + +#define LDP_TEST_UNALIGNED(TYPE) \ +TYPE ldp_unaligned_##TYPE(char* ptr){ \ + TYPE a_0, a_1; \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + TYPE *a = arr+1; \ + a_0 = a[0]; \ + a_1 = a[1]; \ + return a_0 + a_1; \ +} + +#define LDP_TEST_ADJUST_ALIGNED(TYPE) \ +TYPE ldp_aligned_adjust_##TYPE(char* ptr){ \ + TYPE a_0, a_1, a_2, a_3, a_4; \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + a_0 = arr[100]; \ + a_1 = arr[101]; \ + a_2 = arr[102]; \ + a_3 = arr[103]; \ + a_4 = arr[110]; \ + return a_0 + a_1 + a_2 + a_3 + a_4; \ +} + +#define LDP_TEST_ADJUST_UNALIGNED(TYPE) \ +TYPE ldp_unaligned_adjust_##TYPE(char* ptr){ \ + TYPE a_0, a_1, a_2, a_3, a_4; \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + TYPE *a = arr+1; \ + a_0 = a[100]; \ + a_1 = a[101]; \ + a_2 = a[102]; \ + a_3 = a[103]; \ + a_4 = a[110]; \ + return a_0 + a_1 + a_2 + a_3 + a_4; \ +} + +LDP_TEST_ALIGNED(int32_t); +LDP_TEST_ALIGNED(int64_t); +LDP_TEST_ALIGNED(v4si); +LDP_TEST_UNALIGNED(int32_t); +LDP_TEST_UNALIGNED(int64_t); +LDP_TEST_UNALIGNED(v4si); +LDP_TEST_ADJUST_ALIGNED(int32_t); +LDP_TEST_ADJUST_ALIGNED(int64_t); +LDP_TEST_ADJUST_UNALIGNED(int32_t); +LDP_TEST_ADJUST_UNALIGNED(int64_t); + +/* { dg-final { scan-assembler-times "ldp\tw\[0-9\]+, w\[0-9\]" 6 } } */ +/* { dg-final { scan-assembler-times "ldp\tx\[0-9\]+, x\[0-9\]" 6 } } */ +/* { dg-final { scan-assembler-times "ldp\tq\[0-9\]+, q\[0-9\]" 2 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_never.c b/gcc/testsuite/gcc.target/aarch64/ldp_never.c new file mode 100644 index 0000000..64f5043 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ldp_never.c @@ -0,0 +1,66 @@ +/* { dg-options "-O2 --param=aarch64-ldp-policy=never -mcpu=generic" } */ + +#include <stdlib.h> +#include <stdint.h> + +typedef int v4si __attribute__ ((vector_size (16))); + +#define LDP_TEST_ALIGNED(TYPE) \ +TYPE ldp_aligned_##TYPE(char* ptr){ \ + TYPE a_0, a_1; \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + a_0 = arr[0]; \ + a_1 = arr[1]; \ + return a_0 + a_1; \ +} + +#define LDP_TEST_UNALIGNED(TYPE) \ +TYPE ldp_unaligned_##TYPE(char* ptr){ \ + TYPE a_0, a_1; \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + TYPE *a = arr+1; \ + a_0 = a[0]; \ + a_1 = a[1]; \ + return a_0 + a_1; \ +} + +#define LDP_TEST_ADJUST_ALIGNED(TYPE) \ +TYPE ldp_aligned_adjust_##TYPE(char* ptr){ \ + TYPE a_0, a_1, a_2, a_3, a_4; \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + a_0 = arr[100]; \ + a_1 = arr[101]; \ + a_2 = arr[102]; \ + a_3 = arr[103]; \ + a_4 = arr[110]; \ + return a_0 + a_1 + a_2 + a_3 + a_4; \ +} + +#define LDP_TEST_ADJUST_UNALIGNED(TYPE) \ +TYPE ldp_unaligned_adjust_##TYPE(char* ptr){ \ + TYPE a_0, a_1, a_2, a_3, a_4; \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + TYPE *a = arr+1; \ + a_0 = a[100]; \ + a_1 = a[101]; \ + a_2 = a[102]; \ + a_3 = a[103]; \ + a_4 = a[110]; \ + return a_0 + a_1 + a_2 + a_3 + a_4; \ +} + +LDP_TEST_ALIGNED(int32_t); +LDP_TEST_ALIGNED(int64_t); +LDP_TEST_ALIGNED(v4si); +LDP_TEST_UNALIGNED(int32_t); +LDP_TEST_UNALIGNED(int64_t); +LDP_TEST_UNALIGNED(v4si); +LDP_TEST_ADJUST_ALIGNED(int32_t); +LDP_TEST_ADJUST_ALIGNED(int64_t); +LDP_TEST_ADJUST_UNALIGNED(int32_t); +LDP_TEST_ADJUST_UNALIGNED(int64_t); + +/* { dg-final { scan-assembler-times "ldp\tw\[0-9\]+, w\[0-9\]" 0 } } */ +/* { dg-final { scan-assembler-times "ldp\tx\[0-9\]+, x\[0-9\]" 0 } } */ +/* { dg-final { scan-assembler-times "ldp\tq\[0-9\]+, q\[0-9\]" 0 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/stp_aligned.c b/gcc/testsuite/gcc.target/aarch64/stp_aligned.c new file mode 100644 index 0000000..ab9c2f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/stp_aligned.c @@ -0,0 +1,60 @@ +/* { dg-options "-O2 --param=aarch64-stp-policy=aligned -mcpu=generic" } */ + +#include <stdlib.h> +#include <stdint.h> + +typedef int v4si __attribute__ ((vector_size (16))); + +#define STP_TEST_ALIGNED(TYPE) \ +TYPE *stp_aligned_##TYPE(char* ptr, TYPE x){ \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + arr[0] = x; \ + arr[1] = x; \ + return arr; \ +} + +#define STP_TEST_UNALIGNED(TYPE) \ +TYPE *stp_unaligned_##TYPE(char* ptr, TYPE x){ \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + TYPE *a = arr+1; \ + a[0] = x; \ + a[1] = x; \ + return a; \ +} + +#define STP_TEST_ADJUST_ALIGNED(TYPE) \ +TYPE *stp_aligned_adjust_##TYPE(char* ptr, TYPE x){ \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + arr[100] = x; \ + arr[101] = x; \ + arr[102] = x; \ + arr[103] = x; \ + return arr; \ +} + +#define STP_TEST_ADJUST_UNALIGNED(TYPE) \ +TYPE *stp_unaligned_adjust_##TYPE(char* ptr, TYPE x){ \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + TYPE *a = arr+1; \ + a[100] = x; \ + a[101] = x; \ + a[102] = x; \ + a[103] = x; \ + return a; \ +} + +STP_TEST_ALIGNED(int32_t); +STP_TEST_ALIGNED(int64_t); +STP_TEST_ALIGNED(v4si); +STP_TEST_UNALIGNED(int32_t); +STP_TEST_UNALIGNED(int64_t); +STP_TEST_UNALIGNED(v4si); +STP_TEST_ADJUST_ALIGNED(int32_t); +STP_TEST_ADJUST_ALIGNED(int64_t); +STP_TEST_ADJUST_UNALIGNED(int32_t); +STP_TEST_ADJUST_UNALIGNED(int64_t); + +/* { dg-final { scan-assembler-times "stp\tw\[0-9\]+, w\[0-9\]" 3 } } */ +/* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\]" 3 } } */ +/* { dg-final { scan-assembler-times "stp\tq\[0-9\]+, q\[0-9\]" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/stp_always.c b/gcc/testsuite/gcc.target/aarch64/stp_always.c new file mode 100644 index 0000000..3787e23 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/stp_always.c @@ -0,0 +1,60 @@ +/* { dg-options "-O2 --param=aarch64-stp-policy=always -mcpu=generic" } */ + +#include <stdlib.h> +#include <stdint.h> + +typedef int v4si __attribute__ ((vector_size (16))); + +#define STP_TEST_ALIGNED(TYPE) \ +TYPE *stp_aligned_##TYPE(char* ptr, TYPE x){ \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + arr[0] = x; \ + arr[1] = x; \ + return arr; \ +} + +#define STP_TEST_UNALIGNED(TYPE) \ +TYPE *stp_unaligned_##TYPE(char* ptr, TYPE x){ \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + TYPE *a = arr+1; \ + a[0] = x; \ + a[1] = x; \ + return a; \ +} + +#define STP_TEST_ADJUST_ALIGNED(TYPE) \ +TYPE *stp_aligned_adjust_##TYPE(char* ptr, TYPE x){ \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + arr[100] = x; \ + arr[101] = x; \ + arr[102] = x; \ + arr[103] = x; \ + return arr; \ +} + +#define STP_TEST_ADJUST_UNALIGNED(TYPE) \ +TYPE *stp_unaligned_adjust_##TYPE(char* ptr, TYPE x){ \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + TYPE *a = arr+1; \ + a[100] = x; \ + a[101] = x; \ + a[102] = x; \ + a[103] = x; \ + return a; \ +} + +STP_TEST_ALIGNED(int32_t); +STP_TEST_ALIGNED(int64_t); +STP_TEST_ALIGNED(v4si); +STP_TEST_UNALIGNED(int32_t); +STP_TEST_UNALIGNED(int64_t); +STP_TEST_UNALIGNED(v4si); +STP_TEST_ADJUST_ALIGNED(int32_t); +STP_TEST_ADJUST_ALIGNED(int64_t); +STP_TEST_ADJUST_UNALIGNED(int32_t); +STP_TEST_ADJUST_UNALIGNED(int64_t); + +/* { dg-final { scan-assembler-times "stp\tw\[0-9\]+, w\[0-9\]" 6 } } */ +/* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\]" 6 } } */ +/* { dg-final { scan-assembler-times "stp\tq\[0-9\]+, q\[0-9\]" 2 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/stp_never.c b/gcc/testsuite/gcc.target/aarch64/stp_never.c new file mode 100644 index 0000000..f0f1ea5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/stp_never.c @@ -0,0 +1,60 @@ +/* { dg-options "-O2 --param=aarch64-stp-policy=never -mcpu=generic" } */ + +#include <stdlib.h> +#include <stdint.h> + +typedef int v4si __attribute__ ((vector_size (16))); + +#define STP_TEST_ALIGNED(TYPE) \ +TYPE *stp_aligned_##TYPE(char* ptr, TYPE x){ \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + arr[0] = x; \ + arr[1] = x; \ + return arr; \ +} + +#define STP_TEST_UNALIGNED(TYPE) \ +TYPE *stp_unaligned_##TYPE(char* ptr, TYPE x){ \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + TYPE *a = arr+1; \ + a[0] = x; \ + a[1] = x; \ + return a; \ +} + +#define STP_TEST_ADJUST_ALIGNED(TYPE) \ +TYPE *stp_aligned_adjust_##TYPE(char* ptr, TYPE x){ \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + arr[100] = x; \ + arr[101] = x; \ + arr[102] = x; \ + arr[103] = x; \ + return arr; \ +} + +#define STP_TEST_ADJUST_UNALIGNED(TYPE) \ +TYPE *stp_unaligned_adjust_##TYPE(char* ptr, TYPE x){ \ + TYPE *arr = (TYPE*) ((uintptr_t)ptr & ~(2 * 8 * _Alignof(TYPE) - 1)); \ + TYPE *a = arr+1; \ + a[100] = x; \ + a[101] = x; \ + a[102] = x; \ + a[103] = x; \ + return a; \ +} + +STP_TEST_ALIGNED(int32_t); +STP_TEST_ALIGNED(int64_t); +STP_TEST_ALIGNED(v4si); +STP_TEST_UNALIGNED(int32_t); +STP_TEST_UNALIGNED(int64_t); +STP_TEST_UNALIGNED(v4si); +STP_TEST_ADJUST_ALIGNED(int32_t); +STP_TEST_ADJUST_ALIGNED(int64_t); +STP_TEST_ADJUST_UNALIGNED(int32_t); +STP_TEST_ADJUST_UNALIGNED(int64_t); + +/* { dg-final { scan-assembler-times "stp\tw\[0-9\]+, w\[0-9\]" 0 } } */ +/* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\]" 0 } } */ +/* { dg-final { scan-assembler-times "stp\tq\[0-9\]+, q\[0-9\]" 0 } } */ + diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vec-construct-opt.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vec-construct-opt.c new file mode 100644 index 0000000..487816a --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vec-construct-opt.c @@ -0,0 +1,102 @@ +/* { dg-do compile } */ +/* { dg-options "-mlasx -O3" } */ + +#include <lasxintrin.h> + +extern long long *x_di; +extern int *x_si; +extern short int *x_hi; +extern char *x_qi; +extern double *y_df; +extern float *y_sf; + +/* Remove some unnecessary vinsgr2vr.d as the corresponding elements + have already been set. */ +/* { dg-final { scan-assembler-not "v4i64:.*\tvinsgr2vr\\.d.*v4i64" } } */ +/* { dg-final { scan-assembler-times "v4i64:.*\txvldrepl\\.d.*v4i64" 1 } } */ +v4i64 +vec_construct_v4i64 () +{ + v4i64 res = + { x_di[0], x_di[0], x_di[1], x_di[1] } + ; + return res; +} + +/* Remove some unnecessary vinsgr2vr.w as the corresponding elements + have already been set. */ +/* { dg-final { scan-assembler-not "v8i32:.*\tvinsgr2vr\\.w.*v8i32" } } */ +/* { dg-final { scan-assembler-times "v8i32:.*\txvreplgr2vr\\.w.*v8i32" 1 } } */ +v8i32 +vec_construct_v8i32 () +{ + v8i32 res = + { x_si[0], x_si[0], x_si[0], x_si[0], + x_si[0], x_si[2], x_si[0], x_si[0] } + ; + return res; +} + +/* Remove some unnecessary vinsgr2vr.h as the corresponding elements + have already been set. */ +/* { dg-final { scan-assembler-not "v16i16:.*\tvori\\.b.*v16i16" } } */ +/* { dg-final { scan-assembler-times "v16i16:.*\txvreplgr2vr\\.h.*v16i1" 1 } } */ +v16i16 +vec_construct_v16i16 () +{ + v16i16 res = + { x_hi[1], x_hi[2], x_hi[1], x_hi[1], + x_hi[1], x_hi[1], x_hi[1], x_hi[1], + x_hi[1], x_hi[1], x_hi[1], x_hi[1], + x_hi[1], x_hi[1], x_hi[1], x_hi[2] } + ; + return res; +} + +/* Remove some unnecessary vinsgr2vr.b as the corresponding elements + have already been set. */ +/* { dg-final { scan-assembler-not "v32i8:.*\tvori\\.b.*v32i8" } } */ +/* { dg-final { scan-assembler-times "v32i8:.*\txvreplgr2vr\\.b.*v32i8" 1 } } */ +v32i8 +vec_construct_v32i8 () +{ + v32i8 res = + { x_qi[0], x_qi[0], x_qi[0], x_qi[0], + x_qi[0], x_qi[0], x_qi[0], x_qi[0], + x_qi[0], x_qi[0], x_qi[0], x_qi[0], + x_qi[0], x_qi[0], x_qi[0], x_qi[2], + x_qi[0], x_qi[0], x_qi[0], x_qi[0], + x_qi[0], x_qi[0], x_qi[0], x_qi[0], + x_qi[0], x_qi[0], x_qi[0], x_qi[0], + x_qi[0], x_qi[0], x_qi[0], x_qi[3] } + ; + return res; +} + +/* Set 2 elements of a vector simultaneously by vilvl.d + and reducing more vextrins.d. */ +/* { dg-final { scan-assembler-not "v4f64:.*\tvori\\.b.*v4f64" } } */ +/* { dg-final { scan-assembler-not "v4f64:.*\tvextrins\\.d.*v4f64" } } */ +/* { dg-final { scan-assembler-times "v4f64:.*\tvilvl\\.d.*v4f64" 1 } } */ +v4f64 +vec_construct_v4f64 () +{ + v4f64 res = + { y_df[0], y_df[2], y_df[0], y_df[0]} + ; + return res; +} + +/* Set 2 elements of a vector simultaneously by vilvl.w + and reducing more vextrins.w. */ +/* { dg-final { scan-assembler-not "v8f32:.*\tvextrins\\.w.*v8f32" } } */ +/* { dg-final { scan-assembler-times "v8f32:.*\txvilvl\\.w.*v8f32" 1 } } */ +v8f32 +vec_construct_v8f32 () +{ + v8f32 res = + { y_sf[2], y_sf[1], y_sf[2], y_sf[3], + y_sf[2], y_sf[1], y_sf[2], y_sf[3] } + ; + return res; +} diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vec-construct-opt.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vec-construct-opt.c new file mode 100644 index 0000000..92da1c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vec-construct-opt.c @@ -0,0 +1,85 @@ +/* { dg-do compile } */ +/* { dg-options "-mlsx -O3" } */ + +#include <lsxintrin.h> + +extern long long *x_di; +extern int *x_si; +extern short int *x_hi; +extern char *x_qi; +extern double *y_df; +extern float *y_sf; + +/* No change for V2DI mode. */ +v2i64 +vec_construct_v2i64 () +{ + v2i64 res = + { x_di[1], x_di[0]} + ; + return res; +} + +/* Only load the lowest 2 elements and directly copy them to high half-part, + reducing more vinsgr2vr.w. */ +/* { dg-final { scan-assembler-times "v4i32:.*\tvreplvei\\.d.*v4i32" 1 } } */ +v4i32 +vec_construct_v4i32 () +{ + v4i32 res = + { x_si[0], x_si[1], x_si[0], x_si[1]} + ; + return res; +} + +/* Only load the lowest 4 elements and directly copy them to high half-part, + reducing more vinsgr2vr.h. */ +/* { dg-final { scan-assembler-times "v8i16:.*\tvreplvei\\.d.*v8i16" 1 } } */ +v8i16 +vec_construct_v8i16 () +{ + v8i16 res = + { x_hi[0], x_hi[0], x_hi[0], x_hi[1], + x_hi[0], x_hi[0], x_hi[0], x_hi[1] } + ; + return res; +} + +/* Only load the lowest 8 elements and directly copy them to high half-part, + reducing more vinsgr2vr.b. */ +/* { dg-final { scan-assembler-times "v16i8:.*\tvreplvei\\.d.*v16i8" 1 } } */ +v16i8 +vec_construct_v16i8 () +{ + v16i8 res = + { x_qi[0], x_qi[1], x_qi[0], x_qi[2], + x_qi[0], x_qi[0], x_qi[0], x_qi[3], + x_qi[0], x_qi[1], x_qi[0], x_qi[2], + x_qi[0], x_qi[0], x_qi[0], x_qi[3] } + ; + return res; +} + +/* Set 2 elements of a vector simultaneously by vilvl.d. */ +/* { dg-final { scan-assembler-not "v2f64:.*\tvextrins\\.d.*v2f64" } } */ +/* { dg-final { scan-assembler-times "v2f64:.*\tvilvl\\.d.*v2f64" 1 } } */ +v2f64 +vec_construct_v2f64 () +{ + v2f64 res = + { y_df[0], y_df[2] } + ; + return res; +} + +/* Set 2 elements of a vector simultaneously by vilvl.w + and reducing more vextrins.w. */ +/* { dg-final { scan-assembler-times "v4f32:.*\tvilvl\\.w.*v4f32" 1 } } */ +v4f32 +vec_construct_v4f32 () +{ + v4f32 res = + { y_sf[0], y_sf[1], y_sf[0], y_sf[0] } + ; + return res; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr111380-1.c b/gcc/testsuite/gcc.target/powerpc/pr111380-1.c new file mode 100644 index 0000000..57ae75e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr111380-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target vect_int } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ + +/* Verify it emits error message on inlining even without LTO. */ + +vector int c, a, b; + +static inline void __attribute__ ((__always_inline__)) +foo () /* { dg-error "inlining failed in call to .* target specific option mismatch" } */ +{ + c = a + b; +} + +__attribute__ ((target ("cpu=power8"))) +int main () +{ + foo (); /* { dg-message "called from here" } */ + c = a + b; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr111380-2.c b/gcc/testsuite/gcc.target/powerpc/pr111380-2.c new file mode 100644 index 0000000..7b36394 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr111380-2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target vect_int } */ +/* { dg-options "-O2 -mno-vsx" } */ + +/* Verify it emits error message on inlining even without LTO. */ + +vector int c, a, b; + +static inline void __attribute__ ((__always_inline__)) +foo () /* { dg-error "inlining failed in call to .* target specific option mismatch" } */ +{ + c = a + b; +} + +__attribute__ ((target ("vsx"))) +int main () +{ + foo (); /* { dg-message "called from here" } */ + c = a + b; +} diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-soft-1.c b/gcc/testsuite/gcc.target/riscv/_Float16-soft-1.c index 0622588..ba56dda 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-soft-1.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-soft-1.c @@ -6,4 +6,4 @@ _Float16 test_soft_move (_Float16 a, _Float16 b) return b; } -/* { dg-final { scan-assembler-not "fmv.h" } } */ +/* { dg-final { scan-assembler-not {\mfmv\.h\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-soft-2.c b/gcc/testsuite/gcc.target/riscv/_Float16-soft-2.c index 3d37823..e1a841e 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-soft-2.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-soft-2.c @@ -7,7 +7,7 @@ _Float16 test_soft_add (_Float16 a, _Float16 b) /* { dg-final { scan-assembler-times "call\t__extendhfsf2" 2 } } */ return a + b; /* { dg-final { scan-assembler-not "call\t__addhf3" } } */ - /* { dg-final { scan-assembler-times "fadd.s" 1 } } */ + /* { dg-final { scan-assembler-times {\mfadd\.s\M} 1 } } */ /* { dg-final { scan-assembler-times "call\t__truncsfhf2" 1 } } */ } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-soft-3.c b/gcc/testsuite/gcc.target/riscv/_Float16-soft-3.c index ecce364..66c5a36 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-soft-3.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-soft-3.c @@ -7,6 +7,6 @@ int test_soft_compare (_Float16 a, _Float16 b) /* { dg-final { scan-assembler-times "call\t__extendhfsf2" 2 } } */ return a > b; /* { dg-final { scan-assembler-not "call\t__gthf2" } } */ - /* { dg-final { scan-assembler-times "fgt.s" 1 } } */ + /* { dg-final { scan-assembler-times {\mfgt\.s\M} 1 } } */ } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zfh-1.c b/gcc/testsuite/gcc.target/riscv/_Float16-zfh-1.c index 98908dc..4339455 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-zfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zfh-1.c @@ -3,6 +3,6 @@ _Float16 foo1 (_Float16 a, _Float16 b) { - /* { dg-final { scan-assembler-times "fmv.h" 1 } } */ + /* { dg-final { scan-assembler-times {\mfmv\.h\M} 1 } } */ return b; } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zfh-2.c b/gcc/testsuite/gcc.target/riscv/_Float16-zfh-2.c index 58bfa6b..3f9eced 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-zfh-2.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zfh-2.c @@ -3,6 +3,6 @@ _Float16 foo1 (_Float16 a, _Float16 b) { - /* { dg-final { scan-assembler-times "fadd.h" 1 } } */ + /* { dg-final { scan-assembler-times {\mfadd\.h\M} 1 } } */ return a + b; } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zfh-3.c b/gcc/testsuite/gcc.target/riscv/_Float16-zfh-3.c index 128b4e5..b70b711 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-zfh-3.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zfh-3.c @@ -3,6 +3,6 @@ int foo1 (_Float16 a, _Float16 b) { - /* { dg-final { scan-assembler-times "fgt.h" 1 } } */ + /* { dg-final { scan-assembler-times {\mfgt\.h\M} 1 } } */ return a > b; } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-1.c b/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-1.c index 631a049..8fcc51b 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-1.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-1.c @@ -3,7 +3,7 @@ _Float16 foo1 (_Float16 a, _Float16 b) { - /* { dg-final { scan-assembler-not "fmv.h" } } */ - /* { dg-final { scan-assembler-times "fmv.s" 1 } } */ + /* { dg-final { scan-assembler-not {\mfmv\.h\M} } } */ + /* { dg-final { scan-assembler-times {\mfmv\.s\M} 1 } } */ return b; } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-2.c b/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-2.c index 06c85eb..f9b615c 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-2.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-2.c @@ -3,7 +3,7 @@ _Float16 foo1 (_Float16 a, _Float16 b) { - /* { dg-final { scan-assembler-not "fadd.h" } } */ - /* { dg-final { scan-assembler-times "fadd.s" 1 } } */ + /* { dg-final { scan-assembler-not {\mfadd\.h\M} } } */ + /* { dg-final { scan-assembler-times {\mfadd\.s\M} 1 } } */ return a + b; } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-3.c b/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-3.c index 28960d6..2a35006 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-3.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-3.c @@ -3,7 +3,7 @@ int foo1 (_Float16 a, _Float16 b) { - /* { dg-final { scan-assembler-not "fgt.h" } } */ - /* { dg-final { scan-assembler-times "fgt.s" 1 } } */ + /* { dg-final { scan-assembler-not {\mfgt\.h\M} } } */ + /* { dg-final { scan-assembler-times {\mfgt\.s\M} 1 } } */ return a > b; } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c index fa049db..4c57890 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c @@ -3,8 +3,8 @@ _Float16 foo1 (_Float16 a, _Float16 b) { - /* { dg-final { scan-assembler-not "fmv.h" } } */ - /* { dg-final { scan-assembler-not "fmv.s" } } */ + /* { dg-final { scan-assembler-not {\mfmv\.h\M} } } */ + /* { dg-final { scan-assembler-not {\mfmv\.s\M} } } */ /* { dg-final { scan-assembler-times "mv\ta0" 1 } } */ return b; } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c index 17f45a9..31aa40d 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c @@ -3,7 +3,7 @@ _Float16 foo1 (_Float16 a, _Float16 b) { - /* { dg-final { scan-assembler-not "fadd.h" } } */ + /* { dg-final { scan-assembler-not {\mfadd\.h\M} } } */ /* { dg-final { scan-assembler-not "fadd.s fa" } } */ /* { dg-final { scan-assembler-times "fadd.s a" 1 } } */ return a + b; diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c index 939b378..230c022 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c @@ -3,7 +3,7 @@ int foo1 (_Float16 a, _Float16 b) { - /* { dg-final { scan-assembler-not "fgt.h" } } */ + /* { dg-final { scan-assembler-not {\mfgt\.h\M} } } */ /* { dg-final { scan-assembler-not "fgt.s fa" } } */ /* { dg-final { scan-assembler-times "fgt.s a" 1 } } */ return a > b; diff --git a/gcc/testsuite/gcc.target/riscv/and-extend-1.c b/gcc/testsuite/gcc.target/riscv/and-extend-1.c index a270d28..2fe4da3 100644 --- a/gcc/testsuite/gcc.target/riscv/and-extend-1.c +++ b/gcc/testsuite/gcc.target/riscv/and-extend-1.c @@ -23,8 +23,8 @@ foo3(unsigned int a, unsigned int* ptr) ptr[1] &= 0xffff; } -/* { dg-final { scan-assembler-times "zext.w" 1 } } */ -/* { dg-final { scan-assembler-times "zext.h" 2 } } */ -/* { dg-final { scan-assembler-times "lwu" 1 } } */ -/* { dg-final { scan-assembler-times "lhu" 2 } } */ +/* { dg-final { scan-assembler-times {\mzext\.w\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mzext\.h\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mlwu} 1 } } */ +/* { dg-final { scan-assembler-times {\mlhu} 2 } } */ /* { dg-final { scan-assembler-not "and\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/and-extend-2.c b/gcc/testsuite/gcc.target/riscv/and-extend-2.c index fe639cd..e5a9cf6 100644 --- a/gcc/testsuite/gcc.target/riscv/and-extend-2.c +++ b/gcc/testsuite/gcc.target/riscv/and-extend-2.c @@ -23,6 +23,6 @@ foo3(unsigned int a, unsigned int* ptr) ptr[1] &= 0xffff; } -/* { dg-final { scan-assembler-times "zext.h" 2 } } */ -/* { dg-final { scan-assembler-times "lhu" 2 } } */ +/* { dg-final { scan-assembler-times {\mzext\.h\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mlhu} 2 } } */ /* { dg-final { scan-assembler-not "and\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/fle-ieee.c b/gcc/testsuite/gcc.target/riscv/fle-ieee.c index af9d503..e55331f 100644 --- a/gcc/testsuite/gcc.target/riscv/fle-ieee.c +++ b/gcc/testsuite/gcc.target/riscv/fle-ieee.c @@ -9,4 +9,4 @@ fle (double x, double y) } /* { dg-final { scan-assembler "\tfrflags\t(\[^\n\]*)\n\tfle\\.d\t\[^\n\]*\n\tfsflags\t\\1\n" } } */ -/* { dg-final { scan-assembler-not "snez" } } */ +/* { dg-final { scan-assembler-not {\msnez} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/fle-snan.c b/gcc/testsuite/gcc.target/riscv/fle-snan.c index 0579d93..f40bb2c 100644 --- a/gcc/testsuite/gcc.target/riscv/fle-snan.c +++ b/gcc/testsuite/gcc.target/riscv/fle-snan.c @@ -9,4 +9,4 @@ fle (double x, double y) } /* { dg-final { scan-assembler "\tfrflags\t(\[^\n\]*)\n\tfle\\.d\t\[^,\]*,(\[^,\]*),(\[^,\]*)\n\tfsflags\t\\1\n\tfeq\\.d\tzero,\\2,\\3\n" } } */ -/* { dg-final { scan-assembler-not "snez" } } */ +/* { dg-final { scan-assembler-not {\msnez} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/flef-ieee.c b/gcc/testsuite/gcc.target/riscv/flef-ieee.c index e2d6b0d..f3e7e7d 100644 --- a/gcc/testsuite/gcc.target/riscv/flef-ieee.c +++ b/gcc/testsuite/gcc.target/riscv/flef-ieee.c @@ -9,4 +9,4 @@ flef (float x, float y) } /* { dg-final { scan-assembler "\tfrflags\t(\[^\n\]*)\n\tfle\\.s\t\[^\n\]*\n\tfsflags\t\\1\n" } } */ -/* { dg-final { scan-assembler-not "snez" } } */ +/* { dg-final { scan-assembler-not {\msnez} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/flef-snan.c b/gcc/testsuite/gcc.target/riscv/flef-snan.c index 2d2c5b9..ef75b35 100644 --- a/gcc/testsuite/gcc.target/riscv/flef-snan.c +++ b/gcc/testsuite/gcc.target/riscv/flef-snan.c @@ -9,4 +9,4 @@ flef (float x, float y) } /* { dg-final { scan-assembler "\tfrflags\t(\[^\n\]*)\n\tfle\\.s\t\[^,\]*,(\[^,\]*),(\[^,\]*)\n\tfsflags\t\\1\n\tfeq\\.s\tzero,\\2,\\3\n" } } */ -/* { dg-final { scan-assembler-not "snez" } } */ +/* { dg-final { scan-assembler-not {\msnez} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/flt-ieee.c b/gcc/testsuite/gcc.target/riscv/flt-ieee.c index 7d7aae3..c40a0fc 100644 --- a/gcc/testsuite/gcc.target/riscv/flt-ieee.c +++ b/gcc/testsuite/gcc.target/riscv/flt-ieee.c @@ -9,4 +9,4 @@ flt (double x, double y) } /* { dg-final { scan-assembler "\tfrflags\t(\[^\n\]*)\n\tflt\\.d\t\[^\n\]*\n\tfsflags\t\\1\n" } } */ -/* { dg-final { scan-assembler-not "snez" } } */ +/* { dg-final { scan-assembler-not {\msnez} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/flt-snan.c b/gcc/testsuite/gcc.target/riscv/flt-snan.c index ff4c4e9..c958ec0 100644 --- a/gcc/testsuite/gcc.target/riscv/flt-snan.c +++ b/gcc/testsuite/gcc.target/riscv/flt-snan.c @@ -9,4 +9,4 @@ flt (double x, double y) } /* { dg-final { scan-assembler "\tfrflags\t(\[^\n\]*)\n\tflt\\.d\t\[^,\]*,(\[^,\]*),(\[^,\]*)\n\tfsflags\t\\1\n\tfeq\\.d\tzero,\\2,\\3\n" } } */ -/* { dg-final { scan-assembler-not "snez" } } */ +/* { dg-final { scan-assembler-not {\msnez} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/fltf-ieee.c b/gcc/testsuite/gcc.target/riscv/fltf-ieee.c index ede076e..a9c0805 100644 --- a/gcc/testsuite/gcc.target/riscv/fltf-ieee.c +++ b/gcc/testsuite/gcc.target/riscv/fltf-ieee.c @@ -9,4 +9,4 @@ fltf (float x, float y) } /* { dg-final { scan-assembler "\tfrflags\t(\[^\n\]*)\n\tflt\\.s\t\[^\n\]*\n\tfsflags\t\\1\n" } } */ -/* { dg-final { scan-assembler-not "snez" } } */ +/* { dg-final { scan-assembler-not {\msnez} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/fltf-snan.c b/gcc/testsuite/gcc.target/riscv/fltf-snan.c index d29d786..34a51e3 100644 --- a/gcc/testsuite/gcc.target/riscv/fltf-snan.c +++ b/gcc/testsuite/gcc.target/riscv/fltf-snan.c @@ -9,4 +9,4 @@ fltf (float x, float y) } /* { dg-final { scan-assembler "\tfrflags\t(\[^\n\]*)\n\tflt\\.s\t\[^,\]*,(\[^,\]*),(\[^,\]*)\n\tfsflags\t\\1\n\tfeq\\.s\tzero,\\2,\\3\n" } } */ -/* { dg-final { scan-assembler-not "snez" } } */ +/* { dg-final { scan-assembler-not {\msnez} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-1.c b/gcc/testsuite/gcc.target/riscv/interrupt-1.c index d85eb98..506aef4 100644 --- a/gcc/testsuite/gcc.target/riscv/interrupt-1.c +++ b/gcc/testsuite/gcc.target/riscv/interrupt-1.c @@ -5,4 +5,4 @@ void __attribute__ ((interrupt)) foo (void) { } -/* { dg-final { scan-assembler "mret" } } */ +/* { dg-final { scan-assembler {\mmret} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-mmode.c b/gcc/testsuite/gcc.target/riscv/interrupt-mmode.c index 50d54a0..7b7f0a7 100644 --- a/gcc/testsuite/gcc.target/riscv/interrupt-mmode.c +++ b/gcc/testsuite/gcc.target/riscv/interrupt-mmode.c @@ -5,4 +5,4 @@ void __attribute__ ((interrupt ("machine"))) foo (void) { } -/* { dg-final { scan-assembler "mret" } } */ +/* { dg-final { scan-assembler {\mmret} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-smode.c b/gcc/testsuite/gcc.target/riscv/interrupt-smode.c index 973a9b1..ef0e59b 100644 --- a/gcc/testsuite/gcc.target/riscv/interrupt-smode.c +++ b/gcc/testsuite/gcc.target/riscv/interrupt-smode.c @@ -5,4 +5,4 @@ void __attribute__ ((interrupt ("supervisor"))) foo (void) { } -/* { dg-final { scan-assembler "sret" } } */ +/* { dg-final { scan-assembler {\msret} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-umode.c b/gcc/testsuite/gcc.target/riscv/interrupt-umode.c index 7fcef755..042abf0 100644 --- a/gcc/testsuite/gcc.target/riscv/interrupt-umode.c +++ b/gcc/testsuite/gcc.target/riscv/interrupt-umode.c @@ -5,4 +5,4 @@ void __attribute__ ((interrupt ("user"))) foo (void) { } -/* { dg-final { scan-assembler "uret" } } */ +/* { dg-final { scan-assembler {\muret} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr106888.c b/gcc/testsuite/gcc.target/riscv/pr106888.c index 77fb8e5..739d5d7 100644 --- a/gcc/testsuite/gcc.target/riscv/pr106888.c +++ b/gcc/testsuite/gcc.target/riscv/pr106888.c @@ -8,5 +8,5 @@ ctz (int i) return res&0xffff; } -/* { dg-final { scan-assembler-times "ctzw" 1 } } */ -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-times {\mctzw} 1 } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr108987.c b/gcc/testsuite/gcc.target/riscv/pr108987.c index 6179c7e..be9cd92 100644 --- a/gcc/testsuite/gcc.target/riscv/pr108987.c +++ b/gcc/testsuite/gcc.target/riscv/pr108987.c @@ -6,4 +6,4 @@ unsigned long long f5(unsigned long long i) return i * 0x0202020202020202ULL; } -/* { dg-final { scan-assembler-times "mul" 1 } } */ +/* { dg-final { scan-assembler-times {\mmul} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr89835.c b/gcc/testsuite/gcc.target/riscv/pr89835.c index ab190e1..b7adc7c 100644 --- a/gcc/testsuite/gcc.target/riscv/pr89835.c +++ b/gcc/testsuite/gcc.target/riscv/pr89835.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that relaxed atomic stores use simple store instuctions. */ -/* { dg-final { scan-assembler-not "amoswap" } } */ +/* { dg-final { scan-assembler-not {\mamoswap} } } */ void foo(int bar, int baz) diff --git a/gcc/testsuite/gcc.target/riscv/ret-1.c b/gcc/testsuite/gcc.target/riscv/ret-1.c index 28133aa..9279595 100644 --- a/gcc/testsuite/gcc.target/riscv/ret-1.c +++ b/gcc/testsuite/gcc.target/riscv/ret-1.c @@ -37,5 +37,5 @@ core_list_find(list_head *list, list_data *info) /* There is only one legitimate unconditional jump, so test for that, which will catch the case where bb-reorder leaves a jump to a ret in the IL. */ -/* { dg-final { scan-assembler-times "jump" 1 } } */ +/* { dg-final { scan-assembler-times {\mjump} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c index 14201e1..64007ee 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c @@ -8,5 +8,5 @@ f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int count) dst[i] = op1[i] + op2[i]; } -/* { dg-final { scan-assembler-not "lw" } } */ -/* { dg-final { scan-assembler-not "sw" } } */ +/* { dg-final { scan-assembler-not {\mlw} } } */ +/* { dg-final { scan-assembler-not {\msw} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c index 812584e..a82f34e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c @@ -8,5 +8,5 @@ f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int count) dst[i] = op1[i] + op2[i]; } -/* { dg-final { scan-assembler-not "lw" } } */ -/* { dg-final { scan-assembler-not "sw" } } */ +/* { dg-final { scan-assembler-not {\mlw} } } */ +/* { dg-final { scan-assembler-not {\msw} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c index 7a6d429..d97555b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c index 7aaac97..3bf64ab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c index 7a47e11..6f7689d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "mulh-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c index 72c72b0..a0f744a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "mulh-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c index 2a89810..32a7200 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c index 1630ba1..5c414b1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c index 7638851..21f8e8f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c index d7052b2..d661c19 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "shift-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c index a8ecf97..4790688 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "shift-scalar-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c index 66ae116..b6328d0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vadd-run.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c index 12fb952..ba453d1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c index 30b467f..2a8618a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c index 3fa6cf3..848b6eb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vand-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c index ed340b8..8b26617 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vdiv-run.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c index 2cd841f..4ce2cee 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c index 7407a4f..1b8e692 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c index 20aceb3..9b03aa3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c index 60226b0..ea9455a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c index 2babc70..6fce322 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c index 2f74e80..7be92f5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c index 225030e..4f4566a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vmul-run.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c index 390e0b9..3704995 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c index aa056e7..a427181 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c index f6b3770..10b3499 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c index 58b69ec..a08038e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vrem-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c index 36a1706..318323e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vsub-run.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c index 28b2a0e..bd44f5a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c index 6ccec19..c996ce8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c index 7239733..9c03d8f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vxor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c index a84d22d..1055338 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "vcond-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c index 56fd39f..234535d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ /* { dg-require-effective-target fenv_exceptions } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c index e50d561..e547da6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-trapping-math" } */ /* { dg-require-effective-target fenv_exceptions } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c index 6c45c27..b72a44f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "vcond-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c index 9d0ba59..df22bd3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_arith-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c index 608354de..2832cc5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_arith_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c index 20e49e7..a73d9f7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_arith-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c index a47243c..e57f7db 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_arith_run-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c index e4cb7a6..03092f4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_arith-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c index 717790d..47055de 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_arith_run-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c index a49525f..8d679cd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_arith-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c index 3f06a21..1e317d9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_arith-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c index 280479d..c1a5f71 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -ffast-math" } */ #include "cond_arith-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c index 407bbc2..31509ec 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_float2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c index 05d217d..cb4fa18 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_float2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c index 65b54bb..ed039a3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_convert_float2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c index 030ea2c..70271fd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_convert_float2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c index 10bc067..acb6716 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_convert_int2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c index 08d27e6..a4cf1ac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_convert_int2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c index 04f2416..07b28dc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_convert_int2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c index 7a6897b..3bf63dc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_convert_int2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c index be37854..f223ba2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "cond_copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c index 6e337f9..bdf6eed 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "cond_copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c index 4ceedeb..daec93b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_fadd-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c index d10c42c..2908bea 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_fadd-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c index 7ee291b..e35419e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_fadd-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c index 2502b60..515afb2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_fadd-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c index 91578a4..e344485 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fma_fnma-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c index 61526b6..7517087 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fma_fnma-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c index af446d9..98b3c48 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fma_fnma-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c index 4880a46..e56eea7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fma_fnma-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c index 2aa2524..3b0582d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fma_fnma-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c index 36c3c64..ea0c105 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fma_fnma-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c index b74b4d2..d282772 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fma_fnma-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c index fb9b6f2..735b899 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fma_fnma-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c index bbf04f6..e136f98 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fmax-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c index ae2740f..291cfca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fmax-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c index d02eba1..34f011d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fmax-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c index 608a3dd..9986f8d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fmax-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c index 31fa50a..293e1d9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #define FN(X) __builtin_fmin##X diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c index 13b2189..3310bb7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #define FN(X) __builtin_fmin##X diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c index 61e347b..6bed341 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #define FN(X) __builtin_fmin##X diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c index 4921464..4af0322 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #define FN(X) __builtin_fmin##X diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c index 29cabc9..d86ceb8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fms_fnms-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c index ef69172..87c497a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fms_fnms-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c index fe8b5f2..08de30f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fms_fnms-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c index b68448d..46c2157 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fms_fnms-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c index 575494a..266bee7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fms_fnms-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c index e0e5bd9..e325f9b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fms_fnms-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c index 49290a8..29a75ce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_fmul-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c index f25a24c..744f48a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_fmul-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c index fc958e1..edd940c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_fmul-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c index 692f4cd..4dea086 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_fmul-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c index 439cc90..9ef36dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_logical_min_max-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c index e7cf6a8..0d1aec2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_logical_min_max-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c index 6005498..caf9c6a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_logical_min_max-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c index f8016a3..bea7c98 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_logical_min_max-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c index e265b6f..bacceb3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_logical_min_max-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c index 8260472..5dd0b34 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_mulh-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c index 24612ff..183542d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_mulh-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c index bf07468..ff3646a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_narrow_shift-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c index b0454bd..f3ae207 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_narrow_shift-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c index 1c025a9..27f9b68 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_narrow_shift-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_reduc-1.c new file mode 100644 index 0000000..db6f9d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_reduc-1.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-vect-cost-model -ffast-math -fdump-tree-optimized" } */ + +#include <stdint-gcc.h> + +#define COND_REDUCTION(TYPE) \ + TYPE foo##TYPE (TYPE *restrict a, TYPE *restrict b, int loop_size) \ + { \ + TYPE result = 0; \ + for (int i = 0; i < loop_size; i++) \ + if (b[i] <= a[i]) \ + result += a[i]; \ + return result; \ + } + +COND_REDUCTION (int8_t) +COND_REDUCTION (int16_t) +COND_REDUCTION (int32_t) +COND_REDUCTION (int64_t) +COND_REDUCTION (uint8_t) +COND_REDUCTION (uint16_t) +COND_REDUCTION (uint32_t) +COND_REDUCTION (uint64_t) +COND_REDUCTION (_Float16) +COND_REDUCTION (float) +COND_REDUCTION (double) + +/* { dg-final { scan-tree-dump-not "VCOND_MASK" "optimized" } } */ +/* { dg-final { scan-tree-dump-times "COND_LEN_ADD" 11 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c index d4ddc1c..00c309c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_shift-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c index a2eb673..ec6f0f8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_shift-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c index e1bb44e..8c62825 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_shift-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c index c1bbe6b..32a6f6c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_shift-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c index ff6b78c..0b0730e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_shift-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c index 1a3a6e9..31f44ec 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_shift-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c index 45823c8..fdd225e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_shift-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c index dd34df0..8ab8e84 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_shift-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c index d822796..fcaa1cd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_shift-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c index c6f9ba8..c3981c8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math " } */ #include "cond_sqrt-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c index 5cfcfed..a48e281 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_sqrt-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c index 3de65aa..71e5196 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_unary-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c index 799f1f7..c2d68fc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_unary-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c index 6ad7e61..e1e38d9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_unary-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c index cd7934b..2f5b967 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_unary-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c index 38e9fb8..d507a38 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_unary-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c index 71f8464..fc6cbd2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_unary-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c index 7a52b0c..1825372 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_unary-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c index ee5c2f3..157310e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "cond_unary-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c new file mode 100644 index 0000000..22a7104 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ +#include <stdint-gcc.h> + +#define TEST_TYPE(TYPE1, TYPE2, N) \ + __attribute__ ((noipa)) \ + TYPE1 reduc_##TYPE1##_##TYPE2 (TYPE2 *restrict a, TYPE2 *restrict pred) \ + { \ + TYPE1 sum = 0; \ + for (int i = 0; i < N; i += 1) \ + if (pred[i]) \ + sum += a[i]; \ + return sum; \ + } + +#define TEST_ALL(TEST) \ + TEST (int16_t, int8_t, 16) \ + TEST (int32_t, int16_t, 8) \ + TEST (int64_t, int32_t, 4) \ + TEST (uint16_t, uint8_t, 16) \ + TEST (uint32_t, uint16_t, 8) \ + TEST (uint64_t, uint32_t, 4) \ + TEST (float, _Float16, 8) \ + TEST (double, float, 4) + +TEST_ALL (TEST_TYPE) + +/* { dg-final { scan-assembler-times {\tvfwredusum\.vs\tv[0-9]+,v[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvwredsum\.vs\tv[0-9]+,v[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvwredsumu\.vs\tv[0-9]+,v[0-9]+,v[0-9]+,v0\.t} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c new file mode 100644 index 0000000..7c8fedd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ +#include <stdint-gcc.h> + +#define TEST_TYPE(TYPE1, TYPE2, N) \ + __attribute__ ((noipa)) \ + TYPE1 reduc_##TYPE1##_##TYPE2 (TYPE2 *restrict a, TYPE2 *restrict pred) \ + { \ + TYPE1 sum = 0; \ + for (int i = 0; i < N; i += 1) \ + if (pred[i]) \ + sum += a[i]; \ + return sum; \ + } + +#define TEST_ALL(TEST) \ + TEST (int16_t, int8_t, 16) \ + TEST (int32_t, int16_t, 8) \ + TEST (int64_t, int32_t, 4) \ + TEST (uint16_t, uint8_t, 16) \ + TEST (uint32_t, uint16_t, 8) \ + TEST (uint64_t, uint32_t, 4) \ + TEST (float, _Float16, 8) \ + TEST (double, float, 4) + +TEST_ALL (TEST_TYPE) + +/* { dg-final { scan-assembler-times {\tvfwredusum\.vs\tv[0-9]+,v[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvwredsum\.vs\tv[0-9]+,v[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvwredsumu\.vs\tv[0-9]+,v[0-9]+,v[0-9]+,v0\.t} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c new file mode 100644 index 0000000..e738ede --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ + +#include "cond_widen_reduc-1.c" + +#define RUN(TYPE1, TYPE2, N) \ + { \ + TYPE2 a[N]; \ + TYPE2 pred[N]; \ + TYPE1 r = 0; \ + for (int i = 0; i < N; i++) \ + { \ + a[i] = (i * 0.1) * (i & 1 ? 1 : -1); \ + pred[i] = i % 3; \ + if (pred[i]) \ + r += a[i]; \ + asm volatile ("" ::: "memory"); \ + } \ + if (r != reduc_##TYPE1##_##TYPE2 (a, pred)) \ + __builtin_abort (); \ + } + +int __attribute__ ((optimize (1))) +main () +{ + TEST_ALL (RUN) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c new file mode 100644 index 0000000..60f92ca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ + +#include "cond_widen_reduc-2.c" + +#define RUN(TYPE1, TYPE2, N) \ + { \ + TYPE2 a[N]; \ + TYPE2 pred[N]; \ + TYPE1 r = 0; \ + for (int i = 0; i < N; i++) \ + { \ + a[i] = (i * 0.1) * (i & 1 ? 1 : -1); \ + pred[i] = i % 3; \ + if (pred[i]) \ + r += a[i]; \ + asm volatile ("" ::: "memory"); \ + } \ + if (r != reduc_##TYPE1##_##TYPE2 (a, pred)) \ + __builtin_abort (); \ + } + +int __attribute__ ((optimize (1))) +main () +{ + TEST_ALL (RUN) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111594.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111594.c new file mode 100644 index 0000000..6d81b26 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111594.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -fno-vect-cost-model -ffast-math" } */ + +#include <stdint-gcc.h> + +void +pr11594 (uint64_t *restrict a, uint64_t *restrict b, int loop_size) +{ + uint64_t result = 0; + + for (int i = 0; i < loop_size; i++) + { + if (b[i] <= a[i]) + { + result += a[i]; + } + } + + a[0] = result; +} + +/* { dg-final { scan-assembler-not {vmerge} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c index dfe7328..3098ba6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vfcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c index e7a8f0a..f30e55b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vfcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c index e4dca60..2000cfd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c index e75aee7..637e51a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c index 73eda06..5bec699 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vfncvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c index 9771562..ddbbdf3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vfncvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c index 9f3db6c..f516677 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vfncvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c index 2fb9b0c..ea08429 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vfncvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c index 65d2826..41b8781 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vfncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c index 38e0d84..6b8f3b5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vfncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c index 928e0b3..333bd7a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vfwcvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c index 5bf4bc9..d13d4dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c index a90faef..adf67a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vfwcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c index 15e3320..8289e53 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vfwcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c index 9594909..bf369d6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vfwcvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c index 77d653e..10c8bdd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ #include "vfwcvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c index f55d2df..2dfd6eb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c index d5f0190..ed1fa35 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vsext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c index 9d1c259..3770f83 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vzext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-1.c index 0d3c5b7..232873c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "gather_load-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-10.c index 145df1e..9696a21 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-10.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "gather_load-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-11.c index d36b6f0..459a1a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-11.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "gather_load-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c index 2fb525d..1cbf507 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "gather_load-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-2.c index 76c6df3..93a07e0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "gather_load-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-3.c index 0fd6426..f318a43 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "gather_load-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-4.c index 069d232..a210cdf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "gather_load-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-5.c index 499e555..ade9175 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "gather_load-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-6.c index ec6587a..f5bdece 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "gather_load-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-7.c index 3f7ffbd..47a1783 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* For some reason we exceed the default code model's +-2 GiB limits. We should investigate why and add a proper description here. For now just make sure the test case diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-8.c index 1bcab84..1ce18040 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* For some reason we exceed the default code model's +-2 GiB limits. We should investigate why and add a proper description here. For now just make sure the test case diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-9.c index 3ad6d33..3c08c63 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-9.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "gather_load-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-1.c index 41f60bd..fb34285 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "mask_gather_load-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-10.c index 9840434..531f298 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-10.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "mask_gather_load-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-11.c index 105c706..0ce20a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-11.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-mcmodel=medany" } */ #include "mask_gather_load-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-2.c index 33ddb5d..8bb78aea 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "mask_gather_load-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-3.c index 9f06fbe..0472ed0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "mask_gather_load-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-4.c index ae578f0c..4fab81a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "mask_gather_load-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-5.c index 741abd1..8db1ea1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "mask_gather_load-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-6.c index a14a5c4..d58bc80 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "mask_gather_load-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-7.c index 5f6ec81..cc49571 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-mcmodel=medany" } */ #include "mask_gather_load-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-8.c index a34688f..4745985 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-mcmodel=medany" } */ #include "mask_gather_load-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-9.c index 1cfdede..32924f0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-9.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "mask_gather_load-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-1.c index e0d52bf62..cf89555 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "mask_scatter_store-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-10.c index c1af0d3..6e5dc5d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-10.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "mask_scatter_store-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-2.c index 6b1b02ea..197b443 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "mask_scatter_store-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-3.c index cef0bde..81059e4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "mask_scatter_store-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-4.c index 88a74d5..a50b6d2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "mask_scatter_store-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-5.c index 06804ab..645e3a5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "mask_scatter_store-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-6.c index c6c9a67..52032ba 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "mask_scatter_store-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-7.c index 06a37f9..38b0595 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-mcmodel=medany" } */ #include "mask_scatter_store-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-8.c index da688f3..fcb3110 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* For some reason we exceed the default code model's +-2 GiB limits. We should investigate why and add a proper description here. For now just make sure the test case diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-9.c index c27a673..c120e68 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-9.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "mask_scatter_store-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-1.c index cafa64f..91edba7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "scatter_store-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-10.c index 79f6885..40e34c6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-10.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "scatter_store-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-2.c index 376db08..721c6f6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-mcmodel=medany" } */ #include "scatter_store-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-3.c index 103b864..8d268a6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "scatter_store-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-4.c index f5f89c0..3931a81 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "scatter_store-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-5.c index 049251e..ff30630 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "scatter_store-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-6.c index 59c8e70..a30c47d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "scatter_store-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-7.c index 6f7316e..94ab404 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* For some reason we exceed the default code model's +-2 GiB limits. We should investigate why and add a proper description here. For now just make sure the test case diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-8.c index f74b96e..16c1e17 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* For some reason we exceed the default code model's +-2 GiB limits. We should investigate why and add a proper description here. For now just make sure the test case diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-9.c index cc9f20f..a91b500 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-9.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-mcmodel=medany" } */ #include "scatter_store-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c index 7eeb22a..efc6b70 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-mcmodel=medany" } */ #include "strided_load-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-2.c index 8499e4c..70cb4b0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "strided_load-2.c" #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store_run-1.c index e9dca46..b9f279f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "strided_store-1.c" #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store_run-2.c index 509def7..4c5edb7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ #include "strided_store-2.c" #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c index 42913a1..ecd3219 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "live-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c index 80d076b..3724dac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "live-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c index d3e187e..4352140 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */ #include "multiple_rgroup-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c index 5166c9e..13602c4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */ #include "multiple_rgroup-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c index b786738..292a9af 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */ #include "multiple_rgroup-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c index 7751384..a764161 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */ #include "multiple_rgroup-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c index 4af2f18..52d21b2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-fno-vect-cost-model -fno-tree-loop-distribute-patterns --param riscv-autovec-preference=scalable" } */ #include "single_rgroup-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c index 8767efe..d753d56 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */ #include "single_rgroup-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c index 9ff6e92..04edbc7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "single_rgroup-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c index 16f078a..cb07c96 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "slp-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c index be95309..b7ba21c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "slp-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c index a48b186..0f8bdad 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "slp-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c index af892ad..75ec419 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "slp-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c index 251054e..555a73f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "slp-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c index d0f7f0b..0219528 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "slp-14.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c index df14f11..6d3218fc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "slp-15.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c index 765ec51..490003e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "slp-16.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c index 224db4e..1ea6a27 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "slp-17.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c index 7d22e1f..6685e03 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "slp-18.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c index 5cd7156..58de15b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "slp-19.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c index 41f688f6..d3ee634 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "slp-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c index 30996cb..d4dc241 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "slp-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c index 3d43ef0..5a4b768 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "slp-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c index 814308b..8084657 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "slp-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c index e317eea..881dc79 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "slp-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c index a8e4781..886b9c4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ #include "slp-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c index 39ae513..7e41733 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "slp-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c index 791cfbc..c010564 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "slp-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111548.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111548.c new file mode 100644 index 0000000..9bdf42d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111548.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -Wno-implicit-int -Wno-implicit-function-declaration -Wno-int-conversion" } */ + +a, c, d; /* { dg-warning "data definition has no type or storage class" } */ +*b; /* { dg-warning "data definition has no type or storage class" } */ +h() { + int e; + i(); + for (;;) { + unsigned f; + char *g; + f = a; + for (; f; f--) { + if (*g == '"') + e = !e; + *b = g++; + } + if (c) + break; + f = d; + for (; d;) + if (e) + b++; + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c index c208345..7415310 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */ #include "extract_last-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c index 7ff435d..367fa23 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "extract_last_run-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c index 99af6b3..cff23b5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */ #include "extract_last-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c index 43d1c76..fa05d11 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "extract_last_run-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c index 1e41896..90a0ff5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */ #include "extract_last-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c index 535b68f..77ef983 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "extract_last_run-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c index ee53bf9..e969f10 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "extract_last_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c index ff2b025..6433f10 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */ #include "extract_last-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c index 4b5b633..ad620c2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "extract_last_run-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c index 7b66b24..1d984b1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */ #include "extract_last-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c index a52eac9..0339102 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "extract_last_run-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c index a1ac4a5..2f078e2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */ #include "extract_last-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c index 56858f9..eac1b531 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "extract_last_run-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c index 67672bf..d23fe74 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */ #include "extract_last-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c index b500f85..f52af7a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ #include "reduc-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c index 3c2f625..36ba4b1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "reduc-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c index d1b22c0..dceb88e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ #include "reduc-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c index c17e125..772003a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ #include "reduc-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c index c47463d..c47e3fc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -ffast-math -fno-vect-cost-model" } */ #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c index 540b2e7..ec526c0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c index cc141dc..c9ffd8c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c index 07fa76d..29200df 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-9.c index 47f8082..a0d5904 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-9.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c index 39c36ef..74b989d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "reduc_strict-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c index 0a4238d..340d56b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "reduc_strict-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c index 09a2080..2a9ffbc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4" } */ #include "series-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c index 232ebce..cf29d64 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "mask_struct_load-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c index 309baf3..c8c8742 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "mask_struct_load-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c index 2c818bb..5a6a4de 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "mask_struct_load-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c index c2135b8..c6c2b6b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "mask_struct_load-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c index 0297699..aa2642a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "mask_struct_load-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c index c24c641..eeecb03 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "mask_struct_load-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c index be65d94..1153362 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "mask_struct_load-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c index 1208ea7..d4e9895 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "mask_struct_store-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c index 199402f..02a28fa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "mask_struct_store-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c index 22fc0d5..c07df7e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "mask_struct_store-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c index 807e06e..4c1314b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "mask_struct_store-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c index 3ce3774..5152875 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "mask_struct_store-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c index 8a22844..3b04191 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "mask_struct_store-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c index af80f30..2ffe943 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "mask_struct_store-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c index 4807beb..a499c7c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ #include "struct_vect-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c index afebde1..7903704 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #define TYPE _Float16 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c index 8d311b4..387d697 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #define TYPE float diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c index 763aa9e..391caa4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #define TYPE double diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c index e1824e9..711ea44 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "struct_vect-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c index 6b23023..bb66c5f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "struct_vect-14.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c index 92eadd6..07d6c08 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "struct_vect-15.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c index f43e06c..d2a0046 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "struct_vect-16.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c index b0bafb1..c34a8ab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "struct_vect-17.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c index 169974c..5346c90 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "struct_vect-18.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c index ab26245..6ac6182 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ #define TYPE uint16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c index a2b2e81..f64174b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ #define TYPE uint32_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c index 4e4ddb3..610ee8e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ #define TYPE uint64_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c index 2fa48f1..5dfa0ba 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ #define TYPE float diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c index 7146042..c096888 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "struct_vect-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c index 73e7449..2023b33 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #define TYPE uint16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c index 383a6c6..476c54a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #define TYPE uint32_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c index 79b5df7..2cb2efa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #define TYPE uint64_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c index 446d216..af6d5c6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "ternop_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c index 2e11144..f4a2060 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "ternop_run-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c index bdbbb76..0060592 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "ternop_run-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c index 77d92dd..f295e87 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "ternop_run-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c index 55ee829..9dedaa9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "ternop_run-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c index 31aab4c..09e44bb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "ternop_run-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c index d595b60..3a2bdcc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "ternop_run-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c index a537337..e672fc1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "ternop_run-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c index 844b563..1a25928 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "ternop_run-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c index bd7fcfc..c6ebc12 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "ternop_run-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c index 90300cc..e764723 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "ternop_run-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c index 7e752af..05878d0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include "ternop_run-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c index e0ec9ed..56599d7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c index 854827f..d4492f9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c index b5a0845..dd6e6f7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c index c7c4b4b..8bdc4e9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c index ee7c725..7817134 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c index 6c4f28e..3e96688 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c index 44a4771..f6a07a9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c index efe2f36..4de0124 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c index f1ce6a7..9e79c03 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c index 1809b23..61b97f1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c index f048652..52ef262 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c index dcf87f6..2bc4d96 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c index 84fcb68..3ae6e59 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c index d669cd4..9b7e057 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c index fac17b6..7a35d85 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c index a51b926..51b77da 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c index 8fc6a1b..e069a8c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c index 3601307..8b3994d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c index a26bcaa..ef5bf49 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c index 6dee6ba..67fc570c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c index 3fdf2d3..d036184 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c index a25a6f7..7838406 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c index 1d90bee..ec2907b3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c index c633f54..a855e0c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include "ternop-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c index 5575ece..49cdffe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "abs-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-0.c new file mode 100644 index 0000000..1c53d9b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-0.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test__Float16___builtin_ceilf16: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+3 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_UNARY_CALL (_Float16, __builtin_ceilf16) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-1.c new file mode 100644 index 0000000..a6d0ac3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float___builtin_ceilf: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+3 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_UNARY_CALL (float, __builtin_ceilf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-2.c new file mode 100644 index 0000000..d196fc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_double___builtin_ceil: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+3 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_UNARY_CALL (double, __builtin_ceil) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-3.c new file mode 100644 index 0000000..cd3df49 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-3.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float___builtin_ceilf: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+3 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0 +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_COND_UNARY_CALL (float, __builtin_ceilf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-run-1.c new file mode 100644 index 0000000..88611e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-run-1.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include "test-math.h" + +#define ARRAY_SIZE 128 + +float in[ARRAY_SIZE]; +float out[ARRAY_SIZE]; +float ref[ARRAY_SIZE]; + +TEST_UNARY_CALL (float, __builtin_ceilf) +TEST_ASSERT (float) + +TEST_INIT (float, 1.2, 2.0, 1) +TEST_INIT (float, -1.2, -1.0, 2) +TEST_INIT (float, 3.0, 3.0, 3) +TEST_INIT (float, 8388607.5, 8388608.0, 4) +TEST_INIT (float, 8388609.0, 8388609.0, 5) +TEST_INIT (float, 0.0, 0.0, 6) +TEST_INIT (float, -0.0, -0.0, 7) +TEST_INIT (float, -8388607.5, -8388607.0, 8) +TEST_INIT (float, -8388608.0, -8388608.0, 9) + +int +main () +{ + RUN_TEST (float, 1, __builtin_ceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 2, __builtin_ceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 3, __builtin_ceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 4, __builtin_ceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 5, __builtin_ceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 6, __builtin_ceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 7, __builtin_ceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 8, __builtin_ceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 9, __builtin_ceilf, in, out, ref, ARRAY_SIZE); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-run-2.c new file mode 100644 index 0000000..bb4c86c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-run-2.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include "test-math.h" + +#define ARRAY_SIZE 128 + +double in[ARRAY_SIZE]; +double out[ARRAY_SIZE]; +double ref[ARRAY_SIZE]; + +TEST_UNARY_CALL (double, __builtin_ceil) +TEST_ASSERT (double) + +TEST_INIT (double, 1.2, 2.0, 1) +TEST_INIT (double, -1.2, -1.0, 2) +TEST_INIT (double, 3.0, 3.0, 3) +TEST_INIT (double, 4503599627370495.5, 4503599627370496.0, 4) +TEST_INIT (double, 4503599627370497.0, 4503599627370497.0, 5) +TEST_INIT (double, 0.0, 0.0, 6) +TEST_INIT (double, -0.0, -0.0, 7) +TEST_INIT (double, -4503599627370495.5, -4503599627370495.0, 8) +TEST_INIT (double, -4503599627370496.0, -4503599627370496.0, 9) + +int +main () +{ + RUN_TEST (double, 1, __builtin_ceil, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 2, __builtin_ceil, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 3, __builtin_ceil, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 4, __builtin_ceil, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 5, __builtin_ceil, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 6, __builtin_ceil, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 7, __builtin_ceil, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 8, __builtin_ceil, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 9, __builtin_ceil, in, out, ref, ARRAY_SIZE); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-0.c new file mode 100644 index 0000000..33b1693 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-0.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test__Float16___builtin_floorf16: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+2 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_UNARY_CALL (_Float16, __builtin_floorf16) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-1.c new file mode 100644 index 0000000..5c462c42 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float___builtin_floorf: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+2 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_UNARY_CALL (float, __builtin_floorf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-2.c new file mode 100644 index 0000000..6f07add --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_double___builtin_floor: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+2 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_UNARY_CALL (double, __builtin_floor) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-3.c new file mode 100644 index 0000000..a091ffd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-3.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float___builtin_floorf: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+2 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0 +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_COND_UNARY_CALL (float, __builtin_floorf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-run-1.c new file mode 100644 index 0000000..4af60c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-run-1.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include "test-math.h" + +#define ARRAY_SIZE 128 + +float in[ARRAY_SIZE]; +float out[ARRAY_SIZE]; +float ref[ARRAY_SIZE]; + +TEST_UNARY_CALL (float, __builtin_floorf) +TEST_ASSERT (float) + +TEST_INIT (float, 1.2, 1.0, 1) +TEST_INIT (float, -1.2, -2.0, 2) +TEST_INIT (float, 3.0, 3.0, 3) +TEST_INIT (float, 8388607.5, 8388607.0, 4) +TEST_INIT (float, 8388609.0, 8388609.0, 5) +TEST_INIT (float, 0.0, 0.0, 6) +TEST_INIT (float, -0.0, -0.0, 7) +TEST_INIT (float, -8388607.5, -8388608.0, 8) +TEST_INIT (float, -8388608.0, -8388608.0, 9) + +int +main () +{ + RUN_TEST (float, 1, __builtin_floorf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 2, __builtin_floorf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 3, __builtin_floorf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 4, __builtin_floorf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 5, __builtin_floorf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 6, __builtin_floorf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 7, __builtin_floorf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 8, __builtin_floorf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 9, __builtin_floorf, in, out, ref, ARRAY_SIZE); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-run-2.c new file mode 100644 index 0000000..ad3735c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-run-2.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include "test-math.h" + +#define ARRAY_SIZE 128 + +double in[ARRAY_SIZE]; +double out[ARRAY_SIZE]; +double ref[ARRAY_SIZE]; + +TEST_UNARY_CALL (double, __builtin_floor) +TEST_ASSERT (double) + +TEST_INIT (double, 1.2, 1.0, 1) +TEST_INIT (double, -1.2, -2.0, 2) +TEST_INIT (double, 3.0, 3.0, 3) +TEST_INIT (double, 4503599627370495.5, 4503599627370495.0, 4) +TEST_INIT (double, 4503599627370497.0, 4503599627370497.0, 5) +TEST_INIT (double, 0.0, 0.0, 6) +TEST_INIT (double, -0.0, -0.0, 7) +TEST_INIT (double, -4503599627370495.5, -4503599627370496.0, 8) +TEST_INIT (double, -4503599627370496.0, -4503599627370496.0, 9) + +int +main () +{ + RUN_TEST (double, 1, __builtin_floor, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 2, __builtin_floor, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 3, __builtin_floor, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 4, __builtin_floor, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 5, __builtin_floor, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 6, __builtin_floor, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 7, __builtin_floor, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 8, __builtin_floor, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 9, __builtin_floor, in, out, ref, ARRAY_SIZE); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-0.c new file mode 100644 index 0000000..f67b22a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-0.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test__Float16___builtin_nearbyintf16: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** frflags\s+[axt][0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** fsflags\s+[axt][0-9]+ +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +TEST_UNARY_CALL (_Float16, __builtin_nearbyintf16) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-1.c new file mode 100644 index 0000000..9363986 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float___builtin_nearbyintf: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** frflags\s+[axt][0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** fsflags\s+[axt][0-9]+ +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +TEST_UNARY_CALL (float, __builtin_nearbyintf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-2.c new file mode 100644 index 0000000..d31de73 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_double___builtin_nearbyint: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** frflags\s+[axt][0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** fsflags\s+[axt][0-9]+ +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +TEST_UNARY_CALL (double, __builtin_nearbyint) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-3.c new file mode 100644 index 0000000..4fd9950 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-3.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float___builtin_nearbyintf: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** frflags\s+[axt][0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** fsflags\s+[axt][0-9]+ +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0 +** ... +*/ +TEST_COND_UNARY_CALL (float, __builtin_nearbyintf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-run-1.c new file mode 100644 index 0000000..6786e54 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-run-1.c @@ -0,0 +1,48 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include "test-math.h" + +#define ARRAY_SIZE 128 + +float in[ARRAY_SIZE]; +float out[ARRAY_SIZE]; +float ref[ARRAY_SIZE]; + +TEST_UNARY_CALL (float, __builtin_nearbyintf) +TEST_ASSERT (float) + +TEST_INIT (float, 1.2, 1.0, 1) +TEST_INIT (float, -1.2, -1.0, 2) +TEST_INIT (float, 3.0, 3.0, 3) +TEST_INIT (float, 8388607.5, 8388607.0, 4) +TEST_INIT (float, 8388609.0, 8388609.0, 5) +TEST_INIT (float, 0.0, 0.0, 6) +TEST_INIT (float, -0.0, -0.0, 7) +TEST_INIT (float, -8388607.5, -8388607.0, 8) +TEST_INIT (float, -8388608.0, -8388608.0, 9) + +int +main () +{ + unsigned fflags_before = get_fflags (); + + set_rm (FRM_RTZ); + + RUN_TEST (float, 1, __builtin_nearbyintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 2, __builtin_nearbyintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 3, __builtin_nearbyintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 4, __builtin_nearbyintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 5, __builtin_nearbyintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 6, __builtin_nearbyintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 7, __builtin_nearbyintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 8, __builtin_nearbyintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 9, __builtin_nearbyintf, in, out, ref, ARRAY_SIZE); + + unsigned fflags_after = get_fflags (); + + if (fflags_before != fflags_after) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-run-2.c new file mode 100644 index 0000000..9d3a3a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-run-2.c @@ -0,0 +1,48 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include "test-math.h" + +#define ARRAY_SIZE 128 + +double in[ARRAY_SIZE]; +double out[ARRAY_SIZE]; +double ref[ARRAY_SIZE]; + +TEST_UNARY_CALL (double, __builtin_nearbyint) +TEST_ASSERT (double) + +TEST_INIT (double, 1.2, 1.0, 1) +TEST_INIT (double, -1.8, -2.0, 2) +TEST_INIT (double, 3.0, 3.0, 3) +TEST_INIT (double, 4503599627370495.5, 4503599627370496.0, 4) +TEST_INIT (double, 4503599627370497.0, 4503599627370497.0, 5) +TEST_INIT (double, 0.0, 0.0, 6) +TEST_INIT (double, -0.0, -0.0, 7) +TEST_INIT (double, -4503599627370495.5, -4503599627370496.0, 8) +TEST_INIT (double, -4503599627370496.0, -4503599627370496.0, 9) + +int +main () +{ + unsigned fflags_before = get_fflags (); + + set_rm (FRM_RNE); + + RUN_TEST (double, 1, __builtin_nearbyint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 2, __builtin_nearbyint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 3, __builtin_nearbyint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 4, __builtin_nearbyint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 5, __builtin_nearbyint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 6, __builtin_nearbyint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 7, __builtin_nearbyint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 8, __builtin_nearbyint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 9, __builtin_nearbyint, in, out, ref, ARRAY_SIZE); + + unsigned fflags_after = get_fflags (); + + if (fflags_before != fflags_after) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-0.c new file mode 100644 index 0000000..0d44b98 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-0.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test__Float16___builtin_rintf16: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +TEST_UNARY_CALL (_Float16, __builtin_rintf16) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-1.c new file mode 100644 index 0000000..2ce122a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float___builtin_rintf: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +TEST_UNARY_CALL (float, __builtin_rintf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-2.c new file mode 100644 index 0000000..e3b911b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_double___builtin_rint: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +TEST_UNARY_CALL (double, __builtin_rint) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-3.c new file mode 100644 index 0000000..541c42c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-3.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float___builtin_rintf: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0 +** ... +*/ +TEST_COND_UNARY_CALL (float, __builtin_rintf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-run-1.c new file mode 100644 index 0000000..080f1d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-run-1.c @@ -0,0 +1,48 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include "test-math.h" + +#define ARRAY_SIZE 128 + +float in[ARRAY_SIZE]; +float out[ARRAY_SIZE]; +float ref[ARRAY_SIZE]; + +TEST_UNARY_CALL (float, __builtin_rintf) +TEST_ASSERT (float) + +TEST_INIT (float, 1.2, 1.0, 1) +TEST_INIT (float, -1.2, -1.0, 2) +TEST_INIT (float, 3.0, 3.0, 3) +TEST_INIT (float, 8388607.5, 8388607.0, 4) +TEST_INIT (float, 8388609.0, 8388609.0, 5) +TEST_INIT (float, 0.0, 0.0, 6) +TEST_INIT (float, -0.0, -0.0, 7) +TEST_INIT (float, -8388607.5, -8388607.0, 8) +TEST_INIT (float, -8388608.0, -8388608.0, 9) + +int +main () +{ + unsigned fflags_before = get_fflags (); + + set_rm (FRM_RTZ); + + RUN_TEST (float, 1, __builtin_rintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 2, __builtin_rintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 3, __builtin_rintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 4, __builtin_rintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 5, __builtin_rintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 6, __builtin_rintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 7, __builtin_rintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 8, __builtin_rintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 9, __builtin_rintf, in, out, ref, ARRAY_SIZE); + + unsigned fflags_after = get_fflags (); + + if (fflags_before == fflags_after) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-run-2.c new file mode 100644 index 0000000..6d03118 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-run-2.c @@ -0,0 +1,48 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include "test-math.h" + +#define ARRAY_SIZE 128 + +double in[ARRAY_SIZE]; +double out[ARRAY_SIZE]; +double ref[ARRAY_SIZE]; + +TEST_UNARY_CALL (double, __builtin_rint) +TEST_ASSERT (double) + +TEST_INIT (double, 1.2, 1.0, 1) +TEST_INIT (double, -1.8, -2.0, 2) +TEST_INIT (double, 3.0, 3.0, 3) +TEST_INIT (double, 4503599627370495.5, 4503599627370496.0, 4) +TEST_INIT (double, 4503599627370497.0, 4503599627370497.0, 5) +TEST_INIT (double, 0.0, 0.0, 6) +TEST_INIT (double, -0.0, -0.0, 7) +TEST_INIT (double, -4503599627370495.5, -4503599627370496.0, 8) +TEST_INIT (double, -4503599627370496.0, -4503599627370496.0, 9) + +int +main () +{ + unsigned fflags_before = get_fflags (); + + set_rm (FRM_RNE); + + RUN_TEST (double, 1, __builtin_rint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 2, __builtin_rint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 3, __builtin_rint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 4, __builtin_rint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 5, __builtin_rint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 6, __builtin_rint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 7, __builtin_rint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 8, __builtin_rint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 9, __builtin_rint, in, out, ref, ARRAY_SIZE); + + unsigned fflags_after = get_fflags (); + + if (fflags_before == fflags_after) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-0.c new file mode 100644 index 0000000..06de57b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-0.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test__Float16___builtin_roundf16: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+4 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_UNARY_CALL (_Float16, __builtin_roundf16) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-1.c new file mode 100644 index 0000000..ee51bcd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float___builtin_roundf: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+4 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_UNARY_CALL (float, __builtin_roundf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-2.c new file mode 100644 index 0000000..d78f058 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_double___builtin_round: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+4 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_UNARY_CALL (double, __builtin_round) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-3.c new file mode 100644 index 0000000..98d1467 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-3.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float___builtin_roundf: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+4 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0 +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_COND_UNARY_CALL (float, __builtin_roundf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-run-1.c new file mode 100644 index 0000000..fc8686f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-run-1.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include "test-math.h" + +#define ARRAY_SIZE 128 + +float in[ARRAY_SIZE]; +float out[ARRAY_SIZE]; +float ref[ARRAY_SIZE]; + +TEST_UNARY_CALL (float, __builtin_roundf) +TEST_ASSERT (float) + +TEST_INIT (float, 1.2, 1.0, 1) +TEST_INIT (float, -1.6, -2.0, 2) +TEST_INIT (float, 3.0, 3.0, 3) +TEST_INIT (float, 8388607.5, 8388608.0, 4) +TEST_INIT (float, 8388609.0, 8388609.0, 5) +TEST_INIT (float, 0.0, 0.0, 6) +TEST_INIT (float, -0.0, -0.0, 7) +TEST_INIT (float, -8388607.5, -8388608.0, 8) +TEST_INIT (float, -8388608.0, -8388608.0, 9) + +int +main () +{ + RUN_TEST (float, 1, __builtin_roundf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 2, __builtin_roundf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 3, __builtin_roundf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 4, __builtin_roundf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 5, __builtin_roundf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 6, __builtin_roundf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 7, __builtin_roundf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 8, __builtin_roundf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 9, __builtin_roundf, in, out, ref, ARRAY_SIZE); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-run-2.c new file mode 100644 index 0000000..14ddf6c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-run-2.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include "test-math.h" + +#define ARRAY_SIZE 128 + +double in[ARRAY_SIZE]; +double out[ARRAY_SIZE]; +double ref[ARRAY_SIZE]; + +TEST_UNARY_CALL (double, __builtin_round) +TEST_ASSERT (double) + +TEST_INIT (double, 1.2, 1.0, 1) +TEST_INIT (double, -1.8, -2.0, 2) +TEST_INIT (double, 3.0, 3.0, 3) +TEST_INIT (double, 4503599627370495.5, 4503599627370496.0, 4) +TEST_INIT (double, 4503599627370497.0, 4503599627370497.0, 5) +TEST_INIT (double, 0.0, 0.0, 6) +TEST_INIT (double, -0.0, -0.0, 7) +TEST_INIT (double, -4503599627370495.5, -4503599627370496.0, 8) +TEST_INIT (double, -4503599627370496.0, -4503599627370496.0, 9) + +int +main () +{ + RUN_TEST (double, 1, __builtin_round, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 2, __builtin_round, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 3, __builtin_round, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 4, __builtin_round, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 5, __builtin_round, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 6, __builtin_round, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 7, __builtin_round, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 8, __builtin_round, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 9, __builtin_round, in, out, ref, ARRAY_SIZE); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-0.c new file mode 100644 index 0000000..ab65e37 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-0.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test__Float16___builtin_roundevenf16: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+0 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_UNARY_CALL (_Float16, __builtin_roundevenf16) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-1.c new file mode 100644 index 0000000..fac85ed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float___builtin_roundevenf: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+0 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_UNARY_CALL (float, __builtin_roundevenf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-2.c new file mode 100644 index 0000000..074f1b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_double___builtin_roundeven: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+0 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_UNARY_CALL (double, __builtin_roundeven) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-3.c new file mode 100644 index 0000000..c95e8ec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-3.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float___builtin_roundevenf: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+0 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0 +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_COND_UNARY_CALL (float, __builtin_roundevenf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-0.c new file mode 100644 index 0000000..e304634 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-0.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test__Float16___builtin_truncf16: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.rtz\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +TEST_UNARY_CALL (_Float16, __builtin_truncf16) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-1.c new file mode 100644 index 0000000..8100419 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float___builtin_truncf: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.rtz\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +TEST_UNARY_CALL (float, __builtin_truncf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-2.c new file mode 100644 index 0000000..40551f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_double___builtin_trunc: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.rtz\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +TEST_UNARY_CALL (double, __builtin_trunc) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-3.c new file mode 100644 index 0000000..bb113fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-3.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float___builtin_truncf: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.rtz\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0 +** ... +*/ +TEST_COND_UNARY_CALL (float, __builtin_truncf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-run-1.c new file mode 100644 index 0000000..8b9f6d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-run-1.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include "test-math.h" + +#define ARRAY_SIZE 128 + +float in[ARRAY_SIZE]; +float out[ARRAY_SIZE]; +float ref[ARRAY_SIZE]; + +TEST_UNARY_CALL (float, __builtin_truncf) +TEST_ASSERT (float) + +TEST_INIT (float, 1.2, 1.0, 1) +TEST_INIT (float, -1.2, -1.0, 2) +TEST_INIT (float, 3.0, 3.0, 3) +TEST_INIT (float, 8388607.5, 8388607.0, 4) +TEST_INIT (float, 8388609.0, 8388609.0, 5) +TEST_INIT (float, 0.0, 0.0, 6) +TEST_INIT (float, -0.0, -0.0, 7) +TEST_INIT (float, -8388607.5, -8388607.0, 8) +TEST_INIT (float, -8388608.0, -8388608.0, 9) + +int +main () +{ + RUN_TEST (float, 1, __builtin_truncf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 2, __builtin_truncf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 3, __builtin_truncf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 4, __builtin_truncf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 5, __builtin_truncf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 6, __builtin_truncf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 7, __builtin_truncf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 8, __builtin_truncf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 9, __builtin_truncf, in, out, ref, ARRAY_SIZE); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-run-2.c new file mode 100644 index 0000000..2ae354f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-run-2.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include "test-math.h" + +#define ARRAY_SIZE 128 + +double in[ARRAY_SIZE]; +double out[ARRAY_SIZE]; +double ref[ARRAY_SIZE]; + +TEST_UNARY_CALL (double, __builtin_trunc) +TEST_ASSERT (double) + +TEST_INIT (double, 1.2, 1.0, 1) +TEST_INIT (double, -1.2, -1.0, 2) +TEST_INIT (double, 3.0, 3.0, 3) +TEST_INIT (double, 4503599627370495.5, 4503599627370495.0, 4) +TEST_INIT (double, 4503599627370497.0, 4503599627370497.0, 5) +TEST_INIT (double, 0.0, 0.0, 6) +TEST_INIT (double, -0.0, -0.0, 7) +TEST_INIT (double, -4503599627370495.5, -4503599627370495.0, 8) +TEST_INIT (double, -4503599627370496.0, -4503599627370496.0, 9) + +int +main () +{ + RUN_TEST (double, 1, __builtin_trunc, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 2, __builtin_trunc, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 3, __builtin_trunc, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 4, __builtin_trunc, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 5, __builtin_trunc, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 6, __builtin_trunc, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 7, __builtin_trunc, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 8, __builtin_trunc, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 9, __builtin_trunc, in, out, ref, ARRAY_SIZE); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/test-math.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/test-math.h new file mode 100644 index 0000000..b63ca56 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/test-math.h @@ -0,0 +1,71 @@ +#define TEST_UNARY_CALL(TYPE, CALL) \ + void test_##TYPE##_##CALL (TYPE *out, TYPE *in, unsigned count) \ + { \ + for (unsigned i = 0; i < count; i++) \ + out[i] = CALL (in[i]); \ + } + +#define TEST_COND_UNARY_CALL(TYPE, CALL) \ + void test_##TYPE##_##CALL (TYPE *out, int *cond, TYPE *in, unsigned count) \ + { \ + for (unsigned i = 0; i < count; i++) \ + out[i] = cond[i] ? CALL (in[i]) : in[i]; \ + } + +#define TEST_INIT(TYPE, VAL_IN, VAL_REF, NUM) \ + void test_##TYPE##_init_##NUM (TYPE *in, TYPE *ref, unsigned size) \ + { \ + for (unsigned i = 0; i < size; i++) \ + { \ + in[i] = VAL_IN; \ + ref[i] = VAL_REF; \ + } \ + } + +#define TEST_ASSERT(TYPE) \ + void test_##TYPE##_assert (TYPE *out, TYPE *ref, unsigned size) \ + { \ + for (unsigned i = 0; i < size; i++) \ + { \ + if (out[i] != ref[i]) \ + __builtin_abort (); \ + } \ + } + +#define RUN_TEST(TYPE, NUM, CALL, IN, OUT, REF, SIZE) \ + test_##TYPE##_init_##NUM (IN, REF, SIZE); \ + test_##TYPE##_##CALL (OUT, IN, SIZE); \ + test_##TYPE##_assert (OUT, REF, SIZE); + +#define FRM_RNE 0 +#define FRM_RTZ 1 +#define FRM_RDN 2 +#define FRM_RUP 3 +#define FRM_RMM 4 +#define FRM_DYN 7 + +static inline void +set_rm (unsigned rm) +{ + __asm__ volatile ( + "fsrm %0" + : + :"r"(rm) + : + ); +} + +static inline unsigned +get_fflags () +{ + unsigned fflags = 0; + + __asm__ volatile ( + "frflags %0" + :"=r"(fflags) + : + : + ); + + return fflags; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c index 01a5184..427252c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vfsqrt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c index f9fb126..1429731 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vneg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c index 2870b21..6df15bc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vnot-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c index 81229fd..24daca5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c index d891f3c..264a096 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m2" } */ #include <stdint-gcc.h> #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c index 5356414..06521d1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c index a7c12c3..1690615 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m2" } */ #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c index 726238c..10b292b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m4" } */ #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c index c369cf0..f7e6765 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m8" } */ #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c index a23e471..1d0acf9c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c index 6ea8fdd..c6a65ac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c index 2d97c26..0cb39b7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c index b89b70e..ffc1f19 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3" } */ #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c index ac8d91e..eea1f97 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -O3" } */ #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c index f538db2..3f69cc7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */ #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c index 5abb34c..d9f65ab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */ #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c index 6fdaa51..7f9aa9f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */ #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c index a2c1312..349541b9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c index 9f9f152..c91de2e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c index 8a29a5b..55476e4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c index 42b3fa1..711b071 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c index 8f15f45..95e89e8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c index 5139ea2..e83ae74 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c index f7c2fdd..e3c62b7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "init-repeat-sequence-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c index 5564dd4..2395bd6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "init-repeat-sequence-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c index fec5adc..eb3f670 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "init-repeat-sequence-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c index 7eb129c..875efa3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "insert-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c index e3b97be..a3f4357b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "insert-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c index d6e8248b..934cdd9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ #include "merge-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c index 08506e3..9309e46 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ #include "merge-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c index ff92c39..e2dcc19 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ #include "merge-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c index 86a3f2d..df4fb96 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ #include "merge-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c index a64f82f..7c32bf0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ #include "merge-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c index 6193d2a..8a1ecd6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ #include "merge-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c index 267c1ac..90a1d58 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ #include "merge-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c index 9df69a0..7ab3104 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c @@ -55,6 +55,7 @@ TEST_ALL (PERMUTE) -/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */ +/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */ +/* { dg-final { scan-assembler-times {vrgatherei16\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 12 } } */ /* { dg-final { scan-assembler-times {vrsub\.vi} 24 } } */ /* { dg-final { scan-assembler-times {vrsub\.vx} 7 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c index 8fe80e6..55c5945 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */ #include "perm-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c index 04906d3..a17b61d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */ #include "perm-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c index f5e9f9e..1824564 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */ #include "perm-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c index 8460491..6951fd2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */ #include "perm-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c index 5394dec..dc22e72 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */ #include "perm-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c index cee7efc..24398f2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */ #include "perm-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c index 49b2583..71b1305 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O0 -Wno-psabi" } */ #include "perm-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c index 85ec963..d75d9c5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "repeat-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c index cb054b6c..98c04a5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "repeat-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c index 2cbe1c2..bd4ba41 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "repeat-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c index 9efb6b2..edcf4f9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "repeat-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c index efd7d29..bc26e6d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "repeat-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c index 53836956c..c8482876b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ #include "repeat-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c index c5ee270..5df7e08 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -Wno-pedantic -Wno-psabi" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-runu.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-runu.c index 924e40c..7c77ae8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-runu.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-runu.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -Wno-pedantic -Wno-psabi" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c index 44a0fd6..5dc095c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -Wno-pedantic -Wno-psabi" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-1.c new file mode 100644 index 0000000..7c7a5bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-1.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_V (fabs, 2, _Float16, __builtin_fabs) +DEF_OP_V (fabs, 4, _Float16, __builtin_fabs) +DEF_OP_V (fabs, 8, _Float16, __builtin_fabs) +DEF_OP_V (fabs, 16, _Float16, __builtin_fabs) +DEF_OP_V (fabs, 32, _Float16, __builtin_fabs) +DEF_OP_V (fabs, 64, _Float16, __builtin_fabs) +DEF_OP_V (fabs, 128, _Float16, __builtin_fabs) +DEF_OP_V (fabs, 256, _Float16, __builtin_fabs) +DEF_OP_V (fabs, 512, _Float16, __builtin_fabs) +DEF_OP_V (fabs, 1024, _Float16, __builtin_fabs) +DEF_OP_V (fabs, 2048, _Float16, __builtin_fabs) + +DEF_OP_V (fabs, 2, float, __builtin_fabs) +DEF_OP_V (fabs, 4, float, __builtin_fabs) +DEF_OP_V (fabs, 8, float, __builtin_fabs) +DEF_OP_V (fabs, 16, float, __builtin_fabs) +DEF_OP_V (fabs, 32, float, __builtin_fabs) +DEF_OP_V (fabs, 64, float, __builtin_fabs) +DEF_OP_V (fabs, 128, float, __builtin_fabs) +DEF_OP_V (fabs, 256, float, __builtin_fabs) +DEF_OP_V (fabs, 512, float, __builtin_fabs) +DEF_OP_V (fabs, 1024, float, __builtin_fabs) + +DEF_OP_V (fabs, 2, double, __builtin_fabs) +DEF_OP_V (fabs, 4, double, __builtin_fabs) +DEF_OP_V (fabs, 8, double, __builtin_fabs) +DEF_OP_V (fabs, 16, double, __builtin_fabs) +DEF_OP_V (fabs, 32, double, __builtin_fabs) +DEF_OP_V (fabs, 64, double, __builtin_fabs) +DEF_OP_V (fabs, 128, double, __builtin_fabs) +DEF_OP_V (fabs, 256, double, __builtin_fabs) +DEF_OP_V (fabs, 512, double, __builtin_fabs) + +/* { dg-final { scan-assembler-times {vfabs\.v\s+v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c new file mode 100644 index 0000000..e98f5c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_V (neg, 4, int8_t, __builtin_abs) +DEF_OP_V (neg, 8, int8_t, __builtin_abs) +DEF_OP_V (neg, 16, int8_t, __builtin_abs) +DEF_OP_V (neg, 32, int8_t, __builtin_abs) +DEF_OP_V (neg, 64, int8_t, __builtin_abs) +DEF_OP_V (neg, 128, int8_t, __builtin_abs) +DEF_OP_V (neg, 256, int8_t, __builtin_abs) +DEF_OP_V (neg, 512, int8_t, __builtin_abs) +DEF_OP_V (neg, 1024, int8_t, __builtin_abs) +DEF_OP_V (neg, 2048, int8_t, __builtin_abs) +DEF_OP_V (neg, 4096, int8_t, __builtin_abs) + +DEF_OP_V (neg, 4, int16_t, __builtin_abs) +DEF_OP_V (neg, 8, int16_t, __builtin_abs) +DEF_OP_V (neg, 16, int16_t, __builtin_abs) +DEF_OP_V (neg, 32, int16_t, __builtin_abs) +DEF_OP_V (neg, 64, int16_t, __builtin_abs) +DEF_OP_V (neg, 128, int16_t, __builtin_abs) +DEF_OP_V (neg, 256, int16_t, __builtin_abs) +DEF_OP_V (neg, 512, int16_t, __builtin_abs) +DEF_OP_V (neg, 1024, int16_t, __builtin_abs) +DEF_OP_V (neg, 2048, int16_t, __builtin_abs) + +DEF_OP_V (neg, 4, int32_t, __builtin_abs) +DEF_OP_V (neg, 8, int32_t, __builtin_abs) +DEF_OP_V (neg, 16, int32_t, __builtin_abs) +DEF_OP_V (neg, 32, int32_t, __builtin_abs) +DEF_OP_V (neg, 64, int32_t, __builtin_abs) +DEF_OP_V (neg, 128, int32_t, __builtin_abs) +DEF_OP_V (neg, 256, int32_t, __builtin_abs) +DEF_OP_V (neg, 512, int32_t, __builtin_abs) +DEF_OP_V (neg, 1024, int32_t, __builtin_abs) + +DEF_OP_V (neg, 4, int64_t, __builtin_abs) +DEF_OP_V (neg, 8, int64_t, __builtin_abs) +DEF_OP_V (neg, 16, int64_t, __builtin_abs) +DEF_OP_V (neg, 32, int64_t, __builtin_abs) +DEF_OP_V (neg, 64, int64_t, __builtin_abs) +DEF_OP_V (neg, 128, int64_t, __builtin_abs) +DEF_OP_V (neg, 256, int64_t, __builtin_abs) +DEF_OP_V (neg, 512, int64_t, __builtin_abs) + +/* { dg-final { scan-assembler-times {vneg\.v} 38 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vi} 38 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c new file mode 100644 index 0000000..3eaabce --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_UNOP (cond_abs, 4, v4hf, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 8, v8hf, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 16, v16hf, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 32, v32hf, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 64, v64hf, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 128, v128hf, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 256, v256hf, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 512, v512hf, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 1024, v1024hf, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 2048, v2048hf, __builtin_fabs) + +DEF_COND_UNOP (cond_abs, 4, v4sf, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 8, v8sf, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 16, v16sf, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 32, v32sf, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 64, v64sf, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 128, v128sf, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 256, v256sf, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 512, v512sf, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 1024, v1024sf, __builtin_fabs) + +DEF_COND_UNOP (cond_abs, 4, v4df, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 8, v8df, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 16, v16df, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 32, v32df, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 64, v64df, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 128, v128df, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 256, v256df, __builtin_fabs) +DEF_COND_UNOP (cond_abs, 512, v512df, __builtin_fabs) + +/* { dg-final { scan-assembler-times {vfabs\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c new file mode 100644 index 0000000..61da94c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_add, 4, v4qi, +) +DEF_COND_BINOP (cond_add, 8, v8qi, +) +DEF_COND_BINOP (cond_add, 16, v16qi, +) +DEF_COND_BINOP (cond_add, 32, v32qi, +) +DEF_COND_BINOP (cond_add, 64, v64qi, +) +DEF_COND_BINOP (cond_add, 128, v128qi, +) +DEF_COND_BINOP (cond_add, 256, v256qi, +) +DEF_COND_BINOP (cond_add, 512, v512qi, +) +DEF_COND_BINOP (cond_add, 1024, v1024qi, +) +DEF_COND_BINOP (cond_add, 2048, v2048qi, +) +DEF_COND_BINOP (cond_add, 4096, v4096qi, +) + +DEF_COND_BINOP (cond_add, 4, v4hi, +) +DEF_COND_BINOP (cond_add, 8, v8hi, +) +DEF_COND_BINOP (cond_add, 16, v16hi, +) +DEF_COND_BINOP (cond_add, 32, v32hi, +) +DEF_COND_BINOP (cond_add, 64, v64hi, +) +DEF_COND_BINOP (cond_add, 128, v128hi, +) +DEF_COND_BINOP (cond_add, 256, v256hi, +) +DEF_COND_BINOP (cond_add, 512, v512hi, +) +DEF_COND_BINOP (cond_add, 1024, v1024hi, +) +DEF_COND_BINOP (cond_add, 2048, v2048hi, +) + +DEF_COND_BINOP (cond_add, 4, v4si, +) +DEF_COND_BINOP (cond_add, 8, v8si, +) +DEF_COND_BINOP (cond_add, 16, v16si, +) +DEF_COND_BINOP (cond_add, 32, v32si, +) +DEF_COND_BINOP (cond_add, 64, v64si, +) +DEF_COND_BINOP (cond_add, 128, v128si, +) +DEF_COND_BINOP (cond_add, 256, v256si, +) +DEF_COND_BINOP (cond_add, 512, v512si, +) +DEF_COND_BINOP (cond_add, 1024, v1024si, +) + +DEF_COND_BINOP (cond_add, 4, v4di, +) +DEF_COND_BINOP (cond_add, 8, v8di, +) +DEF_COND_BINOP (cond_add, 16, v16di, +) +DEF_COND_BINOP (cond_add, 32, v32di, +) +DEF_COND_BINOP (cond_add, 64, v64di, +) +DEF_COND_BINOP (cond_add, 128, v128di, +) +DEF_COND_BINOP (cond_add, 256, v256di, +) +DEF_COND_BINOP (cond_add, 512, v512di, +) + +DEF_COND_BINOP (cond_add, 4, v4uqi, +) +DEF_COND_BINOP (cond_add, 8, v8uqi, +) +DEF_COND_BINOP (cond_add, 16, v16uqi, +) +DEF_COND_BINOP (cond_add, 32, v32uqi, +) +DEF_COND_BINOP (cond_add, 64, v64uqi, +) +DEF_COND_BINOP (cond_add, 128, v128uqi, +) +DEF_COND_BINOP (cond_add, 256, v256uqi, +) +DEF_COND_BINOP (cond_add, 512, v512uqi, +) +DEF_COND_BINOP (cond_add, 1024, v1024uqi, +) +DEF_COND_BINOP (cond_add, 2048, v2048uqi, +) +DEF_COND_BINOP (cond_add, 4096, v4096uqi, +) + +DEF_COND_BINOP (cond_add, 4, v4uhi, +) +DEF_COND_BINOP (cond_add, 8, v8uhi, +) +DEF_COND_BINOP (cond_add, 16, v16uhi, +) +DEF_COND_BINOP (cond_add, 32, v32uhi, +) +DEF_COND_BINOP (cond_add, 64, v64uhi, +) +DEF_COND_BINOP (cond_add, 128, v128uhi, +) +DEF_COND_BINOP (cond_add, 256, v256uhi, +) +DEF_COND_BINOP (cond_add, 512, v512uhi, +) +DEF_COND_BINOP (cond_add, 1024, v1024uhi, +) +DEF_COND_BINOP (cond_add, 2048, v2048uhi, +) + +DEF_COND_BINOP (cond_add, 4, v4usi, +) +DEF_COND_BINOP (cond_add, 8, v8usi, +) +DEF_COND_BINOP (cond_add, 16, v16usi, +) +DEF_COND_BINOP (cond_add, 32, v32usi, +) +DEF_COND_BINOP (cond_add, 64, v64usi, +) +DEF_COND_BINOP (cond_add, 128, v128usi, +) +DEF_COND_BINOP (cond_add, 256, v256usi, +) +DEF_COND_BINOP (cond_add, 512, v512usi, +) +DEF_COND_BINOP (cond_add, 1024, v1024usi, +) + +DEF_COND_BINOP (cond_add, 4, v4udi, +) +DEF_COND_BINOP (cond_add, 8, v8udi, +) +DEF_COND_BINOP (cond_add, 16, v16udi, +) +DEF_COND_BINOP (cond_add, 32, v32udi, +) +DEF_COND_BINOP (cond_add, 64, v64udi, +) +DEF_COND_BINOP (cond_add, 128, v128udi, +) +DEF_COND_BINOP (cond_add, 256, v256udi, +) +DEF_COND_BINOP (cond_add, 512, v512udi, +) + +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c new file mode 100644 index 0000000..cb73087 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_add, 4, v4hf, +) +DEF_COND_BINOP (cond_add, 8, v8hf, +) +DEF_COND_BINOP (cond_add, 16, v16hf, +) +DEF_COND_BINOP (cond_add, 32, v32hf, +) +DEF_COND_BINOP (cond_add, 64, v64hf, +) +DEF_COND_BINOP (cond_add, 128, v128hf, +) +DEF_COND_BINOP (cond_add, 256, v256hf, +) +DEF_COND_BINOP (cond_add, 512, v512hf, +) +DEF_COND_BINOP (cond_add, 1024, v1024hf, +) +DEF_COND_BINOP (cond_add, 2048, v2048hf, +) + +DEF_COND_BINOP (cond_add, 4, v4sf, +) +DEF_COND_BINOP (cond_add, 8, v8sf, +) +DEF_COND_BINOP (cond_add, 16, v16sf, +) +DEF_COND_BINOP (cond_add, 32, v32sf, +) +DEF_COND_BINOP (cond_add, 64, v64sf, +) +DEF_COND_BINOP (cond_add, 128, v128sf, +) +DEF_COND_BINOP (cond_add, 256, v256sf, +) +DEF_COND_BINOP (cond_add, 512, v512sf, +) +DEF_COND_BINOP (cond_add, 1024, v1024sf, +) + +DEF_COND_BINOP (cond_add, 4, v4df, +) +DEF_COND_BINOP (cond_add, 8, v8df, +) +DEF_COND_BINOP (cond_add, 16, v16df, +) +DEF_COND_BINOP (cond_add, 32, v32df, +) +DEF_COND_BINOP (cond_add, 64, v64df, +) +DEF_COND_BINOP (cond_add, 128, v128df, +) +DEF_COND_BINOP (cond_add, 256, v256df, +) +DEF_COND_BINOP (cond_add, 512, v512df, +) + +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c new file mode 100644 index 0000000..eb8d56a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_and, 4, v4qi, &) +DEF_COND_BINOP (cond_and, 8, v8qi, &) +DEF_COND_BINOP (cond_and, 16, v16qi, &) +DEF_COND_BINOP (cond_and, 32, v32qi, &) +DEF_COND_BINOP (cond_and, 64, v64qi, &) +DEF_COND_BINOP (cond_and, 128, v128qi, &) +DEF_COND_BINOP (cond_and, 256, v256qi, &) +DEF_COND_BINOP (cond_and, 512, v512qi, &) +DEF_COND_BINOP (cond_and, 1024, v1024qi, &) +DEF_COND_BINOP (cond_and, 2048, v2048qi, &) +DEF_COND_BINOP (cond_and, 4096, v4096qi, &) + +DEF_COND_BINOP (cond_and, 4, v4hi, &) +DEF_COND_BINOP (cond_and, 8, v8hi, &) +DEF_COND_BINOP (cond_and, 16, v16hi, &) +DEF_COND_BINOP (cond_and, 32, v32hi, &) +DEF_COND_BINOP (cond_and, 64, v64hi, &) +DEF_COND_BINOP (cond_and, 128, v128hi, &) +DEF_COND_BINOP (cond_and, 256, v256hi, &) +DEF_COND_BINOP (cond_and, 512, v512hi, &) +DEF_COND_BINOP (cond_and, 1024, v1024hi, &) +DEF_COND_BINOP (cond_and, 2048, v2048hi, &) + +DEF_COND_BINOP (cond_and, 4, v4si, &) +DEF_COND_BINOP (cond_and, 8, v8si, &) +DEF_COND_BINOP (cond_and, 16, v16si, &) +DEF_COND_BINOP (cond_and, 32, v32si, &) +DEF_COND_BINOP (cond_and, 64, v64si, &) +DEF_COND_BINOP (cond_and, 128, v128si, &) +DEF_COND_BINOP (cond_and, 256, v256si, &) +DEF_COND_BINOP (cond_and, 512, v512si, &) +DEF_COND_BINOP (cond_and, 1024, v1024si, &) + +DEF_COND_BINOP (cond_and, 4, v4di, &) +DEF_COND_BINOP (cond_and, 8, v8di, &) +DEF_COND_BINOP (cond_and, 16, v16di, &) +DEF_COND_BINOP (cond_and, 32, v32di, &) +DEF_COND_BINOP (cond_and, 64, v64di, &) +DEF_COND_BINOP (cond_and, 128, v128di, &) +DEF_COND_BINOP (cond_and, 256, v256di, &) +DEF_COND_BINOP (cond_and, 512, v512di, &) + +DEF_COND_BINOP (cond_and, 4, v4uqi, &) +DEF_COND_BINOP (cond_and, 8, v8uqi, &) +DEF_COND_BINOP (cond_and, 16, v16uqi, &) +DEF_COND_BINOP (cond_and, 32, v32uqi, &) +DEF_COND_BINOP (cond_and, 64, v64uqi, &) +DEF_COND_BINOP (cond_and, 128, v128uqi, &) +DEF_COND_BINOP (cond_and, 256, v256uqi, &) +DEF_COND_BINOP (cond_and, 512, v512uqi, &) +DEF_COND_BINOP (cond_and, 1024, v1024uqi, &) +DEF_COND_BINOP (cond_and, 2048, v2048uqi, &) +DEF_COND_BINOP (cond_and, 4096, v4096uqi, &) + +DEF_COND_BINOP (cond_and, 4, v4uhi, &) +DEF_COND_BINOP (cond_and, 8, v8uhi, &) +DEF_COND_BINOP (cond_and, 16, v16uhi, &) +DEF_COND_BINOP (cond_and, 32, v32uhi, &) +DEF_COND_BINOP (cond_and, 64, v64uhi, &) +DEF_COND_BINOP (cond_and, 128, v128uhi, &) +DEF_COND_BINOP (cond_and, 256, v256uhi, &) +DEF_COND_BINOP (cond_and, 512, v512uhi, &) +DEF_COND_BINOP (cond_and, 1024, v1024uhi, &) +DEF_COND_BINOP (cond_and, 2048, v2048uhi, &) + +DEF_COND_BINOP (cond_and, 4, v4usi, &) +DEF_COND_BINOP (cond_and, 8, v8usi, &) +DEF_COND_BINOP (cond_and, 16, v16usi, &) +DEF_COND_BINOP (cond_and, 32, v32usi, &) +DEF_COND_BINOP (cond_and, 64, v64usi, &) +DEF_COND_BINOP (cond_and, 128, v128usi, &) +DEF_COND_BINOP (cond_and, 256, v256usi, &) +DEF_COND_BINOP (cond_and, 512, v512usi, &) +DEF_COND_BINOP (cond_and, 1024, v1024usi, &) + +DEF_COND_BINOP (cond_and, 4, v4udi, &) +DEF_COND_BINOP (cond_and, 8, v8udi, &) +DEF_COND_BINOP (cond_and, 16, v16udi, &) +DEF_COND_BINOP (cond_and, 32, v32udi, &) +DEF_COND_BINOP (cond_and, 64, v64udi, &) +DEF_COND_BINOP (cond_and, 128, v128udi, &) +DEF_COND_BINOP (cond_and, 256, v256udi, &) +DEF_COND_BINOP (cond_and, 512, v512udi, &) + +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-1.c new file mode 100644 index 0000000..3baf5cf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-1.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FP_CONVERT (fcvt, hf, hi, int16_t, 4) +DEF_COND_FP_CONVERT (fcvt, hf, hi, int16_t, 16) +DEF_COND_FP_CONVERT (fcvt, hf, hi, int16_t, 32) +DEF_COND_FP_CONVERT (fcvt, hf, hi, int16_t, 64) +DEF_COND_FP_CONVERT (fcvt, hf, hi, int16_t, 128) +DEF_COND_FP_CONVERT (fcvt, hf, hi, int16_t, 256) +DEF_COND_FP_CONVERT (fcvt, hf, hi, int16_t, 512) +DEF_COND_FP_CONVERT (fcvt, hf, hi, int16_t, 1024) + +DEF_COND_FP_CONVERT (fcvt, sf, si, int32_t, 4) +DEF_COND_FP_CONVERT (fcvt, sf, si, int32_t, 16) +DEF_COND_FP_CONVERT (fcvt, sf, si, int32_t, 32) +DEF_COND_FP_CONVERT (fcvt, sf, si, int32_t, 64) +DEF_COND_FP_CONVERT (fcvt, sf, si, int32_t, 128) +DEF_COND_FP_CONVERT (fcvt, sf, si, int32_t, 256) +DEF_COND_FP_CONVERT (fcvt, sf, si, int32_t, 512) +DEF_COND_FP_CONVERT (fcvt, sf, si, int32_t, 1024) + +DEF_COND_FP_CONVERT (fcvt, df, di, int64_t, 4) +DEF_COND_FP_CONVERT (fcvt, df, di, int64_t, 16) +DEF_COND_FP_CONVERT (fcvt, df, di, int64_t, 32) +DEF_COND_FP_CONVERT (fcvt, df, di, int64_t, 64) +DEF_COND_FP_CONVERT (fcvt, df, di, int64_t, 128) +DEF_COND_FP_CONVERT (fcvt, df, di, int64_t, 256) +DEF_COND_FP_CONVERT (fcvt, df, di, int64_t, 512) + +DEF_COND_FP_CONVERT (fcvt, hf, uhi, uint16_t, 4) +DEF_COND_FP_CONVERT (fcvt, hf, uhi, uint16_t, 16) +DEF_COND_FP_CONVERT (fcvt, hf, uhi, uint16_t, 32) +DEF_COND_FP_CONVERT (fcvt, hf, uhi, uint16_t, 64) +DEF_COND_FP_CONVERT (fcvt, hf, uhi, uint16_t, 128) +DEF_COND_FP_CONVERT (fcvt, hf, uhi, uint16_t, 256) +DEF_COND_FP_CONVERT (fcvt, hf, uhi, uint16_t, 512) +DEF_COND_FP_CONVERT (fcvt, hf, uhi, uint16_t, 1024) + +DEF_COND_FP_CONVERT (fcvt, sf, usi, uint32_t, 4) +DEF_COND_FP_CONVERT (fcvt, sf, usi, uint32_t, 16) +DEF_COND_FP_CONVERT (fcvt, sf, usi, uint32_t, 32) +DEF_COND_FP_CONVERT (fcvt, sf, usi, uint32_t, 64) +DEF_COND_FP_CONVERT (fcvt, sf, usi, uint32_t, 128) +DEF_COND_FP_CONVERT (fcvt, sf, usi, uint32_t, 256) +DEF_COND_FP_CONVERT (fcvt, sf, usi, uint32_t, 512) +DEF_COND_FP_CONVERT (fcvt, sf, usi, uint32_t, 1024) + +DEF_COND_FP_CONVERT (fcvt, df, udi, uint64_t, 4) +DEF_COND_FP_CONVERT (fcvt, df, udi, uint64_t, 16) +DEF_COND_FP_CONVERT (fcvt, df, udi, uint64_t, 32) +DEF_COND_FP_CONVERT (fcvt, df, udi, uint64_t, 64) +DEF_COND_FP_CONVERT (fcvt, df, udi, uint64_t, 128) +DEF_COND_FP_CONVERT (fcvt, df, udi, uint64_t, 256) +DEF_COND_FP_CONVERT (fcvt, df, udi, uint64_t, 512) + +/* { dg-final { scan-assembler-times {vfcvt\.rtz\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 23 } } */ +/* { dg-final { scan-assembler-times {vfcvt\.rtz\.xu\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 23 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-10.c new file mode 100644 index 0000000..e56dc33 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-10.c @@ -0,0 +1,72 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FP_CONVERT (fncvt, hf, qi, int8_t, 4) +DEF_COND_FP_CONVERT (fncvt, hf, qi, int8_t, 16) +DEF_COND_FP_CONVERT (fncvt, hf, qi, int8_t, 32) +DEF_COND_FP_CONVERT (fncvt, hf, qi, int8_t, 64) +DEF_COND_FP_CONVERT (fncvt, hf, qi, int8_t, 128) +DEF_COND_FP_CONVERT (fncvt, hf, qi, int8_t, 256) +DEF_COND_FP_CONVERT (fncvt, hf, qi, int8_t, 512) +DEF_COND_FP_CONVERT (fncvt, hf, qi, int8_t, 1024) + +DEF_COND_FP_CONVERT (fncvt, hf, uqi, uint8_t, 4) +DEF_COND_FP_CONVERT (fncvt, hf, uqi, uint8_t, 16) +DEF_COND_FP_CONVERT (fncvt, hf, uqi, uint8_t, 32) +DEF_COND_FP_CONVERT (fncvt, hf, uqi, uint8_t, 64) +DEF_COND_FP_CONVERT (fncvt, hf, uqi, uint8_t, 128) +DEF_COND_FP_CONVERT (fncvt, hf, uqi, uint8_t, 256) +DEF_COND_FP_CONVERT (fncvt, hf, uqi, uint8_t, 512) +DEF_COND_FP_CONVERT (fncvt, hf, uqi, uint8_t, 1024) + +DEF_COND_FP_CONVERT (fncvt, sf, hi, int16_t, 4) +DEF_COND_FP_CONVERT (fncvt, sf, hi, int16_t, 16) +DEF_COND_FP_CONVERT (fncvt, sf, hi, int16_t, 32) +DEF_COND_FP_CONVERT (fncvt, sf, hi, int16_t, 64) +DEF_COND_FP_CONVERT (fncvt, sf, hi, int16_t, 128) +DEF_COND_FP_CONVERT (fncvt, sf, hi, int16_t, 256) +DEF_COND_FP_CONVERT (fncvt, sf, hi, int16_t, 512) +DEF_COND_FP_CONVERT (fncvt, sf, hi, int16_t, 1024) + +DEF_COND_FP_CONVERT (fncvt, sf, uhi, uint16_t, 4) +DEF_COND_FP_CONVERT (fncvt, sf, uhi, uint16_t, 16) +DEF_COND_FP_CONVERT (fncvt, sf, uhi, uint16_t, 32) +DEF_COND_FP_CONVERT (fncvt, sf, uhi, uint16_t, 64) +DEF_COND_FP_CONVERT (fncvt, sf, uhi, uint16_t, 128) +DEF_COND_FP_CONVERT (fncvt, sf, uhi, uint16_t, 256) +DEF_COND_FP_CONVERT (fncvt, sf, uhi, uint16_t, 512) +DEF_COND_FP_CONVERT (fncvt, sf, uhi, uint16_t, 1024) + +DEF_COND_FP_CONVERT (fncvt, df, si, int32_t, 4) +DEF_COND_FP_CONVERT (fncvt, df, si, int32_t, 16) +DEF_COND_FP_CONVERT (fncvt, df, si, int32_t, 32) +DEF_COND_FP_CONVERT (fncvt, df, si, int32_t, 64) +DEF_COND_FP_CONVERT (fncvt, df, si, int32_t, 128) +DEF_COND_FP_CONVERT (fncvt, df, si, int32_t, 256) +DEF_COND_FP_CONVERT (fncvt, df, si, int32_t, 512) + +DEF_COND_FP_CONVERT (fncvt, df, usi, uint32_t, 4) +DEF_COND_FP_CONVERT (fncvt, df, usi, uint32_t, 16) +DEF_COND_FP_CONVERT (fncvt, df, usi, uint32_t, 32) +DEF_COND_FP_CONVERT (fncvt, df, usi, uint32_t, 64) +DEF_COND_FP_CONVERT (fncvt, df, usi, uint32_t, 128) +DEF_COND_FP_CONVERT (fncvt, df, usi, uint32_t, 256) +DEF_COND_FP_CONVERT (fncvt, df, usi, uint32_t, 512) + +/* { dg-final { scan-assembler-times {vfncvt\.rtz\.xu?\.f\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 46 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c new file mode 100644 index 0000000..41ec468 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c @@ -0,0 +1,54 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FP_CONVERT (fncvt, sf, qi, int8_t, 4) +DEF_COND_FP_CONVERT (fncvt, sf, qi, int8_t, 16) +DEF_COND_FP_CONVERT (fncvt, sf, qi, int8_t, 32) +DEF_COND_FP_CONVERT (fncvt, sf, qi, int8_t, 64) +DEF_COND_FP_CONVERT (fncvt, sf, qi, int8_t, 128) +DEF_COND_FP_CONVERT (fncvt, sf, qi, int8_t, 256) +DEF_COND_FP_CONVERT (fncvt, sf, qi, int8_t, 512) +DEF_COND_FP_CONVERT (fncvt, sf, qi, int8_t, 1024) + +DEF_COND_FP_CONVERT (fncvt, sf, uqi, uint8_t, 4) +DEF_COND_FP_CONVERT (fncvt, sf, uqi, uint8_t, 16) +DEF_COND_FP_CONVERT (fncvt, sf, uqi, uint8_t, 32) +DEF_COND_FP_CONVERT (fncvt, sf, uqi, uint8_t, 64) +DEF_COND_FP_CONVERT (fncvt, sf, uqi, uint8_t, 128) +DEF_COND_FP_CONVERT (fncvt, sf, uqi, uint8_t, 256) +DEF_COND_FP_CONVERT (fncvt, sf, uqi, uint8_t, 512) +DEF_COND_FP_CONVERT (fncvt, sf, uqi, uint8_t, 1024) + +DEF_COND_FP_CONVERT (fncvt, df, hi, int16_t, 4) +DEF_COND_FP_CONVERT (fncvt, df, hi, int16_t, 16) +DEF_COND_FP_CONVERT (fncvt, df, hi, int16_t, 32) +DEF_COND_FP_CONVERT (fncvt, df, hi, int16_t, 64) +DEF_COND_FP_CONVERT (fncvt, df, hi, int16_t, 128) +DEF_COND_FP_CONVERT (fncvt, df, hi, int16_t, 256) +DEF_COND_FP_CONVERT (fncvt, df, hi, int16_t, 512) + +DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 4) +DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 16) +DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 32) +DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 64) +DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 128) +DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 256) +DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 512) + +/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c new file mode 100644 index 0000000..c2cb8bfd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FP_CONVERT (fncvt, df, qi, int8_t, 4) +DEF_COND_FP_CONVERT (fncvt, df, qi, int8_t, 16) +DEF_COND_FP_CONVERT (fncvt, df, qi, int8_t, 32) +DEF_COND_FP_CONVERT (fncvt, df, qi, int8_t, 64) +DEF_COND_FP_CONVERT (fncvt, df, qi, int8_t, 128) +DEF_COND_FP_CONVERT (fncvt, df, qi, int8_t, 256) +DEF_COND_FP_CONVERT (fncvt, df, qi, int8_t, 512) + +DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 4) +DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 16) +DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 32) +DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 64) +DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 128) +DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 256) +DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 512) + +/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 14 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-2.c new file mode 100644 index 0000000..beecdf4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-2.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FP_CONVERT (fcvt, si, sf, float, 16) +DEF_COND_FP_CONVERT (fcvt, si, sf, float, 32) +DEF_COND_FP_CONVERT (fcvt, si, sf, float, 64) +DEF_COND_FP_CONVERT (fcvt, si, sf, float, 128) +DEF_COND_FP_CONVERT (fcvt, si, sf, float, 256) +DEF_COND_FP_CONVERT (fcvt, si, sf, float, 512) +DEF_COND_FP_CONVERT (fcvt, si, sf, float, 1024) + +DEF_COND_FP_CONVERT (fcvt, di, df, double, 4) +DEF_COND_FP_CONVERT (fcvt, di, df, double, 16) +DEF_COND_FP_CONVERT (fcvt, di, df, double, 32) +DEF_COND_FP_CONVERT (fcvt, di, df, double, 64) +DEF_COND_FP_CONVERT (fcvt, di, df, double, 128) +DEF_COND_FP_CONVERT (fcvt, di, df, double, 256) +DEF_COND_FP_CONVERT (fcvt, di, df, double, 512) + +DEF_COND_FP_CONVERT (fcvt, uhi, hf, _Float16, 4) +DEF_COND_FP_CONVERT (fcvt, uhi, hf, _Float16, 16) +DEF_COND_FP_CONVERT (fcvt, uhi, hf, _Float16, 32) +DEF_COND_FP_CONVERT (fcvt, uhi, hf, _Float16, 64) +DEF_COND_FP_CONVERT (fcvt, uhi, hf, _Float16, 128) +DEF_COND_FP_CONVERT (fcvt, uhi, hf, _Float16, 256) +DEF_COND_FP_CONVERT (fcvt, uhi, hf, _Float16, 512) +DEF_COND_FP_CONVERT (fcvt, uhi, hf, _Float16, 1024) + +DEF_COND_FP_CONVERT (fcvt, usi, sf, float, 4) +DEF_COND_FP_CONVERT (fcvt, usi, sf, float, 16) +DEF_COND_FP_CONVERT (fcvt, usi, sf, float, 32) +DEF_COND_FP_CONVERT (fcvt, usi, sf, float, 64) +DEF_COND_FP_CONVERT (fcvt, usi, sf, float, 128) +DEF_COND_FP_CONVERT (fcvt, usi, sf, float, 256) +DEF_COND_FP_CONVERT (fcvt, usi, sf, float, 512) +DEF_COND_FP_CONVERT (fcvt, usi, sf, float, 1024) + +DEF_COND_FP_CONVERT (fcvt, udi, df, double, 4) +DEF_COND_FP_CONVERT (fcvt, udi, df, double, 16) +DEF_COND_FP_CONVERT (fcvt, udi, df, double, 32) +DEF_COND_FP_CONVERT (fcvt, udi, df, double, 64) +DEF_COND_FP_CONVERT (fcvt, udi, df, double, 128) +DEF_COND_FP_CONVERT (fcvt, udi, df, double, 256) +DEF_COND_FP_CONVERT (fcvt, udi, df, double, 512) + +/* { dg-final { scan-assembler-times {vfcvt\.f\.xu?\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 37 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-3.c new file mode 100644 index 0000000..f71236b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-3.c @@ -0,0 +1,54 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FP_CONVERT (fwcvt, hf, si, int32_t, 4) +DEF_COND_FP_CONVERT (fwcvt, hf, si, int32_t, 16) +DEF_COND_FP_CONVERT (fwcvt, hf, si, int32_t, 32) +DEF_COND_FP_CONVERT (fwcvt, hf, si, int32_t, 64) +DEF_COND_FP_CONVERT (fwcvt, hf, si, int32_t, 128) +DEF_COND_FP_CONVERT (fwcvt, hf, si, int32_t, 256) +DEF_COND_FP_CONVERT (fwcvt, hf, si, int32_t, 512) +DEF_COND_FP_CONVERT (fwcvt, hf, si, int32_t, 1024) + +DEF_COND_FP_CONVERT (fwcvt, hf, usi, uint32_t, 4) +DEF_COND_FP_CONVERT (fwcvt, hf, usi, uint32_t, 16) +DEF_COND_FP_CONVERT (fwcvt, hf, usi, uint32_t, 32) +DEF_COND_FP_CONVERT (fwcvt, hf, usi, uint32_t, 64) +DEF_COND_FP_CONVERT (fwcvt, hf, usi, uint32_t, 128) +DEF_COND_FP_CONVERT (fwcvt, hf, usi, uint32_t, 256) +DEF_COND_FP_CONVERT (fwcvt, hf, usi, uint32_t, 512) +DEF_COND_FP_CONVERT (fwcvt, hf, usi, uint32_t, 1024) + +DEF_COND_FP_CONVERT (fwcvt, sf, di, int64_t, 4) +DEF_COND_FP_CONVERT (fwcvt, sf, di, int64_t, 16) +DEF_COND_FP_CONVERT (fwcvt, sf, di, int64_t, 32) +DEF_COND_FP_CONVERT (fwcvt, sf, di, int64_t, 64) +DEF_COND_FP_CONVERT (fwcvt, sf, di, int64_t, 128) +DEF_COND_FP_CONVERT (fwcvt, sf, di, int64_t, 256) +DEF_COND_FP_CONVERT (fwcvt, sf, di, int64_t, 512) + +DEF_COND_FP_CONVERT (fwcvt, sf, udi, uint64_t, 4) +DEF_COND_FP_CONVERT (fwcvt, sf, udi, uint64_t, 16) +DEF_COND_FP_CONVERT (fwcvt, sf, udi, uint64_t, 32) +DEF_COND_FP_CONVERT (fwcvt, sf, udi, uint64_t, 64) +DEF_COND_FP_CONVERT (fwcvt, sf, udi, uint64_t, 128) +DEF_COND_FP_CONVERT (fwcvt, sf, udi, uint64_t, 256) +DEF_COND_FP_CONVERT (fwcvt, sf, udi, uint64_t, 512) + +/* { dg-final { scan-assembler-times {vfwcvt\.rtz\.xu?\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-4.c new file mode 100644 index 0000000..fa5780c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-4.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FP_CONVERT (fwcvt, hf, di, int64_t, 4) +DEF_COND_FP_CONVERT (fwcvt, hf, di, int64_t, 16) +DEF_COND_FP_CONVERT (fwcvt, hf, di, int64_t, 32) +DEF_COND_FP_CONVERT (fwcvt, hf, di, int64_t, 64) +DEF_COND_FP_CONVERT (fwcvt, hf, di, int64_t, 128) +DEF_COND_FP_CONVERT (fwcvt, hf, di, int64_t, 256) +DEF_COND_FP_CONVERT (fwcvt, hf, di, int64_t, 512) + +DEF_COND_FP_CONVERT (fwcvt, hf, udi, uint64_t, 4) +DEF_COND_FP_CONVERT (fwcvt, hf, udi, uint64_t, 16) +DEF_COND_FP_CONVERT (fwcvt, hf, udi, uint64_t, 32) +DEF_COND_FP_CONVERT (fwcvt, hf, udi, uint64_t, 64) +DEF_COND_FP_CONVERT (fwcvt, hf, udi, uint64_t, 128) +DEF_COND_FP_CONVERT (fwcvt, hf, udi, uint64_t, 256) +DEF_COND_FP_CONVERT (fwcvt, hf, udi, uint64_t, 512) + +/* { dg-final { scan-assembler-times {vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 14 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-5.c new file mode 100644 index 0000000..696e17c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-5.c @@ -0,0 +1,72 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FP_CONVERT (fwcvt, qi, hf, _Float16, 4) +DEF_COND_FP_CONVERT (fwcvt, qi, hf, _Float16, 16) +DEF_COND_FP_CONVERT (fwcvt, qi, hf, _Float16, 32) +DEF_COND_FP_CONVERT (fwcvt, qi, hf, _Float16, 64) +DEF_COND_FP_CONVERT (fwcvt, qi, hf, _Float16, 128) +DEF_COND_FP_CONVERT (fwcvt, qi, hf, _Float16, 256) +DEF_COND_FP_CONVERT (fwcvt, qi, hf, _Float16, 512) +DEF_COND_FP_CONVERT (fwcvt, qi, hf, _Float16, 1024) + +DEF_COND_FP_CONVERT (fwcvt, uqi, hf, _Float16, 4) +DEF_COND_FP_CONVERT (fwcvt, uqi, hf, _Float16, 16) +DEF_COND_FP_CONVERT (fwcvt, uqi, hf, _Float16, 32) +DEF_COND_FP_CONVERT (fwcvt, uqi, hf, _Float16, 64) +DEF_COND_FP_CONVERT (fwcvt, uqi, hf, _Float16, 128) +DEF_COND_FP_CONVERT (fwcvt, uqi, hf, _Float16, 256) +DEF_COND_FP_CONVERT (fwcvt, uqi, hf, _Float16, 512) +DEF_COND_FP_CONVERT (fwcvt, uqi, hf, _Float16, 1024) + +DEF_COND_FP_CONVERT (fwcvt, hi, sf, float, 4) +DEF_COND_FP_CONVERT (fwcvt, hi, sf, float, 16) +DEF_COND_FP_CONVERT (fwcvt, hi, sf, float, 32) +DEF_COND_FP_CONVERT (fwcvt, hi, sf, float, 64) +DEF_COND_FP_CONVERT (fwcvt, hi, sf, float, 128) +DEF_COND_FP_CONVERT (fwcvt, hi, sf, float, 256) +DEF_COND_FP_CONVERT (fwcvt, hi, sf, float, 512) +DEF_COND_FP_CONVERT (fwcvt, hi, sf, float, 1024) + +DEF_COND_FP_CONVERT (fwcvt, uhi, sf, float, 4) +DEF_COND_FP_CONVERT (fwcvt, uhi, sf, float, 16) +DEF_COND_FP_CONVERT (fwcvt, uhi, sf, float, 32) +DEF_COND_FP_CONVERT (fwcvt, uhi, sf, float, 64) +DEF_COND_FP_CONVERT (fwcvt, uhi, sf, float, 128) +DEF_COND_FP_CONVERT (fwcvt, uhi, sf, float, 256) +DEF_COND_FP_CONVERT (fwcvt, uhi, sf, float, 512) +DEF_COND_FP_CONVERT (fwcvt, uhi, sf, float, 1024) + +DEF_COND_FP_CONVERT (fwcvt, si, df, double, 4) +DEF_COND_FP_CONVERT (fwcvt, si, df, double, 16) +DEF_COND_FP_CONVERT (fwcvt, si, df, double, 32) +DEF_COND_FP_CONVERT (fwcvt, si, df, double, 64) +DEF_COND_FP_CONVERT (fwcvt, si, df, double, 128) +DEF_COND_FP_CONVERT (fwcvt, si, df, double, 256) +DEF_COND_FP_CONVERT (fwcvt, si, df, double, 512) + +DEF_COND_FP_CONVERT (fwcvt, usi, df, double, 4) +DEF_COND_FP_CONVERT (fwcvt, usi, df, double, 16) +DEF_COND_FP_CONVERT (fwcvt, usi, df, double, 32) +DEF_COND_FP_CONVERT (fwcvt, usi, df, double, 64) +DEF_COND_FP_CONVERT (fwcvt, usi, df, double, 128) +DEF_COND_FP_CONVERT (fwcvt, usi, df, double, 256) +DEF_COND_FP_CONVERT (fwcvt, usi, df, double, 512) + +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu?\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 46 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-6.c new file mode 100644 index 0000000..a830777 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-6.c @@ -0,0 +1,54 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FP_CONVERT (fwcvt, qi, sf, float, 4) +DEF_COND_FP_CONVERT (fwcvt, qi, sf, float, 16) +DEF_COND_FP_CONVERT (fwcvt, qi, sf, float, 32) +DEF_COND_FP_CONVERT (fwcvt, qi, sf, float, 64) +DEF_COND_FP_CONVERT (fwcvt, qi, sf, float, 128) +DEF_COND_FP_CONVERT (fwcvt, qi, sf, float, 256) +DEF_COND_FP_CONVERT (fwcvt, qi, sf, float, 512) +DEF_COND_FP_CONVERT (fwcvt, qi, sf, float, 1024) + +DEF_COND_FP_CONVERT (fwcvt, uqi, sf, float, 4) +DEF_COND_FP_CONVERT (fwcvt, uqi, sf, float, 16) +DEF_COND_FP_CONVERT (fwcvt, uqi, sf, float, 32) +DEF_COND_FP_CONVERT (fwcvt, uqi, sf, float, 64) +DEF_COND_FP_CONVERT (fwcvt, uqi, sf, float, 128) +DEF_COND_FP_CONVERT (fwcvt, uqi, sf, float, 256) +DEF_COND_FP_CONVERT (fwcvt, uqi, sf, float, 512) +DEF_COND_FP_CONVERT (fwcvt, uqi, sf, float, 1024) + +DEF_COND_FP_CONVERT (fwcvt, hi, df, double, 4) +DEF_COND_FP_CONVERT (fwcvt, hi, df, double, 16) +DEF_COND_FP_CONVERT (fwcvt, hi, df, double, 32) +DEF_COND_FP_CONVERT (fwcvt, hi, df, double, 64) +DEF_COND_FP_CONVERT (fwcvt, hi, df, double, 128) +DEF_COND_FP_CONVERT (fwcvt, hi, df, double, 256) +DEF_COND_FP_CONVERT (fwcvt, hi, df, double, 512) + +DEF_COND_FP_CONVERT (fwcvt, uhi, df, double, 4) +DEF_COND_FP_CONVERT (fwcvt, uhi, df, double, 16) +DEF_COND_FP_CONVERT (fwcvt, uhi, df, double, 32) +DEF_COND_FP_CONVERT (fwcvt, uhi, df, double, 64) +DEF_COND_FP_CONVERT (fwcvt, uhi, df, double, 128) +DEF_COND_FP_CONVERT (fwcvt, uhi, df, double, 256) +DEF_COND_FP_CONVERT (fwcvt, uhi, df, double, 512) + +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu?\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-7.c new file mode 100644 index 0000000..6f56cb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-7.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FP_CONVERT (fwcvt, qi, df, double, 4) +DEF_COND_FP_CONVERT (fwcvt, qi, df, double, 16) +DEF_COND_FP_CONVERT (fwcvt, qi, df, double, 32) +DEF_COND_FP_CONVERT (fwcvt, qi, df, double, 64) +DEF_COND_FP_CONVERT (fwcvt, qi, df, double, 128) +DEF_COND_FP_CONVERT (fwcvt, qi, df, double, 256) +DEF_COND_FP_CONVERT (fwcvt, qi, df, double, 512) + +DEF_COND_FP_CONVERT (fwcvt, uqi, df, double, 4) +DEF_COND_FP_CONVERT (fwcvt, uqi, df, double, 16) +DEF_COND_FP_CONVERT (fwcvt, uqi, df, double, 32) +DEF_COND_FP_CONVERT (fwcvt, uqi, df, double, 64) +DEF_COND_FP_CONVERT (fwcvt, uqi, df, double, 128) +DEF_COND_FP_CONVERT (fwcvt, uqi, df, double, 256) +DEF_COND_FP_CONVERT (fwcvt, uqi, df, double, 512) + +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu?\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 14 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-8.c new file mode 100644 index 0000000..62cc7a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-8.c @@ -0,0 +1,54 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FP_CONVERT (fncvt, si, hf, _Float16, 4) +DEF_COND_FP_CONVERT (fncvt, si, hf, _Float16, 16) +DEF_COND_FP_CONVERT (fncvt, si, hf, _Float16, 32) +DEF_COND_FP_CONVERT (fncvt, si, hf, _Float16, 64) +DEF_COND_FP_CONVERT (fncvt, si, hf, _Float16, 128) +DEF_COND_FP_CONVERT (fncvt, si, hf, _Float16, 256) +DEF_COND_FP_CONVERT (fncvt, si, hf, _Float16, 512) +DEF_COND_FP_CONVERT (fncvt, si, hf, _Float16, 1024) + +DEF_COND_FP_CONVERT (fncvt, usi, hf, _Float16, 4) +DEF_COND_FP_CONVERT (fncvt, usi, hf, _Float16, 16) +DEF_COND_FP_CONVERT (fncvt, usi, hf, _Float16, 32) +DEF_COND_FP_CONVERT (fncvt, usi, hf, _Float16, 64) +DEF_COND_FP_CONVERT (fncvt, usi, hf, _Float16, 128) +DEF_COND_FP_CONVERT (fncvt, usi, hf, _Float16, 256) +DEF_COND_FP_CONVERT (fncvt, usi, hf, _Float16, 512) +DEF_COND_FP_CONVERT (fncvt, usi, hf, _Float16, 1024) + +DEF_COND_FP_CONVERT (fncvt, di, sf, float, 4) +DEF_COND_FP_CONVERT (fncvt, di, sf, float, 16) +DEF_COND_FP_CONVERT (fncvt, di, sf, float, 32) +DEF_COND_FP_CONVERT (fncvt, di, sf, float, 64) +DEF_COND_FP_CONVERT (fncvt, di, sf, float, 128) +DEF_COND_FP_CONVERT (fncvt, di, sf, float, 256) +DEF_COND_FP_CONVERT (fncvt, di, sf, float, 512) + +DEF_COND_FP_CONVERT (fncvt, udi, sf, float, 4) +DEF_COND_FP_CONVERT (fncvt, udi, sf, float, 16) +DEF_COND_FP_CONVERT (fncvt, udi, sf, float, 32) +DEF_COND_FP_CONVERT (fncvt, udi, sf, float, 64) +DEF_COND_FP_CONVERT (fncvt, udi, sf, float, 128) +DEF_COND_FP_CONVERT (fncvt, udi, sf, float, 256) +DEF_COND_FP_CONVERT (fncvt, udi, sf, float, 512) + +/* { dg-final { scan-assembler-times {vfncvt\.f\.xu?\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-9.c new file mode 100644 index 0000000..14ae1a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-9.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FP_CONVERT (fncvt, di, hf, _Float16, 4) +DEF_COND_FP_CONVERT (fncvt, di, hf, _Float16, 16) +DEF_COND_FP_CONVERT (fncvt, di, hf, _Float16, 32) +DEF_COND_FP_CONVERT (fncvt, di, hf, _Float16, 64) +DEF_COND_FP_CONVERT (fncvt, di, hf, _Float16, 128) +DEF_COND_FP_CONVERT (fncvt, di, hf, _Float16, 256) +DEF_COND_FP_CONVERT (fncvt, di, hf, _Float16, 512) + +DEF_COND_FP_CONVERT (fncvt, udi, hf, _Float16, 4) +DEF_COND_FP_CONVERT (fncvt, udi, hf, _Float16, 16) +DEF_COND_FP_CONVERT (fncvt, udi, hf, _Float16, 32) +DEF_COND_FP_CONVERT (fncvt, udi, hf, _Float16, 64) +DEF_COND_FP_CONVERT (fncvt, udi, hf, _Float16, 128) +DEF_COND_FP_CONVERT (fncvt, udi, hf, _Float16, 256) +DEF_COND_FP_CONVERT (fncvt, udi, hf, _Float16, 512) + +/* TODO: Currently, we can't vectorize DI -> HF. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_copysign-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_copysign-1.c new file mode 100644 index 0000000..5519158 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_copysign-1.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_CALL (cond_copysign, 4, v4hf, __builtin_copysignf16) +DEF_COND_CALL (cond_copysign, 8, v8hf, __builtin_copysignf16) +DEF_COND_CALL (cond_copysign, 16, v16hf, __builtin_copysignf16) +DEF_COND_CALL (cond_copysign, 32, v32hf, __builtin_copysignf16) +DEF_COND_CALL (cond_copysign, 64, v64hf, __builtin_copysignf16) +DEF_COND_CALL (cond_copysign, 128, v128hf, __builtin_copysignf16) +DEF_COND_CALL (cond_copysign, 256, v256hf, __builtin_copysignf16) +DEF_COND_CALL (cond_copysign, 512, v512hf, __builtin_copysignf16) +DEF_COND_CALL (cond_copysign, 1024, v1024hf, __builtin_copysignf16) +DEF_COND_CALL (cond_copysign, 2048, v2048hf, __builtin_copysignf16) + +DEF_COND_CALL (cond_copysign, 4, v4sf, __builtin_copysignf) +DEF_COND_CALL (cond_copysign, 8, v8sf, __builtin_copysignf) +DEF_COND_CALL (cond_copysign, 16, v16sf, __builtin_copysignf) +DEF_COND_CALL (cond_copysign, 32, v32sf, __builtin_copysignf) +DEF_COND_CALL (cond_copysign, 64, v64sf, __builtin_copysignf) +DEF_COND_CALL (cond_copysign, 128, v128sf, __builtin_copysignf) +DEF_COND_CALL (cond_copysign, 256, v256sf, __builtin_copysignf) +DEF_COND_CALL (cond_copysign, 512, v512sf, __builtin_copysignf) +DEF_COND_CALL (cond_copysign, 1024, v1024sf, __builtin_copysignf) + +DEF_COND_CALL (cond_copysign, 4, v4df, __builtin_copysign) +DEF_COND_CALL (cond_copysign, 8, v8df, __builtin_copysign) +DEF_COND_CALL (cond_copysign, 16, v16df, __builtin_copysign) +DEF_COND_CALL (cond_copysign, 32, v32df, __builtin_copysign) +DEF_COND_CALL (cond_copysign, 64, v64df, __builtin_copysign) +DEF_COND_CALL (cond_copysign, 128, v128df, __builtin_copysign) +DEF_COND_CALL (cond_copysign, 256, v256df, __builtin_copysign) +DEF_COND_CALL (cond_copysign, 512, v512df, __builtin_copysign) + +/* { dg-final { scan-assembler-times {vfsgnj\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c new file mode 100644 index 0000000..373ff00 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_div, 4, v4si, /) +DEF_COND_BINOP (cond_div, 8, v8si, /) +DEF_COND_BINOP (cond_div, 16, v16si, /) +DEF_COND_BINOP (cond_div, 32, v32si, /) +DEF_COND_BINOP (cond_div, 64, v64si, /) +DEF_COND_BINOP (cond_div, 128, v128si, /) +DEF_COND_BINOP (cond_div, 256, v256si, /) +DEF_COND_BINOP (cond_div, 512, v512si, /) +DEF_COND_BINOP (cond_div, 1024, v1024si, /) + +DEF_COND_BINOP (cond_div, 4, v4di, /) +DEF_COND_BINOP (cond_div, 8, v8di, /) +DEF_COND_BINOP (cond_div, 16, v16di, /) +DEF_COND_BINOP (cond_div, 32, v32di, /) +DEF_COND_BINOP (cond_div, 64, v64di, /) +DEF_COND_BINOP (cond_div, 128, v128di, /) +DEF_COND_BINOP (cond_div, 256, v256di, /) +DEF_COND_BINOP (cond_div, 512, v512di, /) + +DEF_COND_BINOP (cond_div, 4, v4usi, /) +DEF_COND_BINOP (cond_div, 8, v8usi, /) +DEF_COND_BINOP (cond_div, 16, v16usi, /) +DEF_COND_BINOP (cond_div, 32, v32usi, /) +DEF_COND_BINOP (cond_div, 64, v64usi, /) +DEF_COND_BINOP (cond_div, 128, v128usi, /) +DEF_COND_BINOP (cond_div, 256, v256usi, /) +DEF_COND_BINOP (cond_div, 512, v512usi, /) +DEF_COND_BINOP (cond_div, 1024, v1024usi, /) + +DEF_COND_BINOP (cond_div, 4, v4udi, /) +DEF_COND_BINOP (cond_div, 8, v8udi, /) +DEF_COND_BINOP (cond_div, 16, v16udi, /) +DEF_COND_BINOP (cond_div, 32, v32udi, /) +DEF_COND_BINOP (cond_div, 64, v64udi, /) +DEF_COND_BINOP (cond_div, 128, v128udi, /) +DEF_COND_BINOP (cond_div, 256, v256udi, /) +DEF_COND_BINOP (cond_div, 512, v512udi, /) + +/* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 34 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c new file mode 100644 index 0000000..fac75ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_div, 4, v4hf, /) +DEF_COND_BINOP (cond_div, 8, v8hf, /) +DEF_COND_BINOP (cond_div, 16, v16hf, /) +DEF_COND_BINOP (cond_div, 32, v32hf, /) +DEF_COND_BINOP (cond_div, 64, v64hf, /) +DEF_COND_BINOP (cond_div, 128, v128hf, /) +DEF_COND_BINOP (cond_div, 256, v256hf, /) +DEF_COND_BINOP (cond_div, 512, v512hf, /) +DEF_COND_BINOP (cond_div, 1024, v1024hf, /) +DEF_COND_BINOP (cond_div, 2048, v2048hf, /) + +DEF_COND_BINOP (cond_div, 4, v4sf, /) +DEF_COND_BINOP (cond_div, 8, v8sf, /) +DEF_COND_BINOP (cond_div, 16, v16sf, /) +DEF_COND_BINOP (cond_div, 32, v32sf, /) +DEF_COND_BINOP (cond_div, 64, v64sf, /) +DEF_COND_BINOP (cond_div, 128, v128sf, /) +DEF_COND_BINOP (cond_div, 256, v256sf, /) +DEF_COND_BINOP (cond_div, 512, v512sf, /) +DEF_COND_BINOP (cond_div, 1024, v1024sf, /) + +DEF_COND_BINOP (cond_div, 4, v4df, /) +DEF_COND_BINOP (cond_div, 8, v8df, /) +DEF_COND_BINOP (cond_div, 16, v16df, /) +DEF_COND_BINOP (cond_div, 32, v32df, /) +DEF_COND_BINOP (cond_div, 64, v64df, /) +DEF_COND_BINOP (cond_div, 128, v128df, /) +DEF_COND_BINOP (cond_div, 256, v256df, /) +DEF_COND_BINOP (cond_div, 512, v512df, /) + +/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c new file mode 100644 index 0000000..c356cf5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_CONVERT (sext, v4qi, v4hi, 4) +DEF_COND_CONVERT (sext, v16qi, v16hi, 16) +DEF_COND_CONVERT (sext, v32qi, v32hi, 32) +DEF_COND_CONVERT (sext, v64qi, v64hi, 64) +DEF_COND_CONVERT (sext, v128qi, v128hi, 128) +DEF_COND_CONVERT (sext, v256qi, v256hi, 256) +DEF_COND_CONVERT (sext, v512qi, v512hi, 512) +DEF_COND_CONVERT (sext, v1024qi, v1024hi, 1024) + +DEF_COND_CONVERT (sext, v4hi, v4si, 4) +DEF_COND_CONVERT (sext, v16hi, v16si, 16) +DEF_COND_CONVERT (sext, v32hi, v32si, 32) +DEF_COND_CONVERT (sext, v64hi, v64si, 64) +DEF_COND_CONVERT (sext, v128hi, v128si, 128) +DEF_COND_CONVERT (sext, v256hi, v256si, 256) +DEF_COND_CONVERT (sext, v512hi, v512si, 512) +DEF_COND_CONVERT (sext, v1024hi, v1024si, 1024) + +DEF_COND_CONVERT (sext, v4si, v4di, 4) +DEF_COND_CONVERT (sext, v16si, v16di, 16) +DEF_COND_CONVERT (sext, v32si, v32di, 32) +DEF_COND_CONVERT (sext, v64si, v64di, 64) +DEF_COND_CONVERT (sext, v128si, v128di, 128) +DEF_COND_CONVERT (sext, v256si, v256di, 256) +DEF_COND_CONVERT (sext, v512si, v512di, 512) + +DEF_COND_CONVERT (zext, v4uqi, v4uhi, 4) +DEF_COND_CONVERT (zext, v16uqi, v16uhi, 16) +DEF_COND_CONVERT (zext, v32uqi, v32uhi, 32) +DEF_COND_CONVERT (zext, v64uqi, v64uhi, 64) +DEF_COND_CONVERT (zext, v128uqi, v128uhi, 128) +DEF_COND_CONVERT (zext, v256uqi, v256uhi, 256) +DEF_COND_CONVERT (zext, v512uqi, v512uhi, 512) +DEF_COND_CONVERT (zext, v1024uqi, v1024uhi, 1024) + +DEF_COND_CONVERT (zext, v4uhi, v4usi, 4) +DEF_COND_CONVERT (zext, v16uhi, v16usi, 16) +DEF_COND_CONVERT (zext, v32uhi, v32usi, 32) +DEF_COND_CONVERT (zext, v64uhi, v64usi, 64) +DEF_COND_CONVERT (zext, v128uhi, v128usi, 128) +DEF_COND_CONVERT (zext, v256uhi, v256usi, 256) +DEF_COND_CONVERT (zext, v512uhi, v512usi, 512) +DEF_COND_CONVERT (zext, v1024uhi, v1024usi, 1024) + +DEF_COND_CONVERT (zext, v4usi, v4udi, 4) +DEF_COND_CONVERT (zext, v16usi, v16udi, 16) +DEF_COND_CONVERT (zext, v32usi, v32udi, 32) +DEF_COND_CONVERT (zext, v64usi, v64udi, 64) +DEF_COND_CONVERT (zext, v128usi, v128udi, 128) +DEF_COND_CONVERT (zext, v256usi, v256udi, 256) +DEF_COND_CONVERT (zext, v512usi, v512udi, 512) + +/* { dg-final { scan-assembler-times {vsext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 23 } } */ +/* { dg-final { scan-assembler-times {vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 23 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c new file mode 100644 index 0000000..02bdf65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_CONVERT (sext, v4qi, v4si, 4) +DEF_COND_CONVERT (sext, v16qi, v16si, 16) +DEF_COND_CONVERT (sext, v32qi, v32si, 32) +DEF_COND_CONVERT (sext, v64qi, v64si, 64) +DEF_COND_CONVERT (sext, v128qi, v128si, 128) +DEF_COND_CONVERT (sext, v256qi, v256si, 256) +DEF_COND_CONVERT (sext, v512qi, v512si, 512) +DEF_COND_CONVERT (sext, v1024qi, v1024si, 1024) + +DEF_COND_CONVERT (sext, v4hi, v4di, 4) +DEF_COND_CONVERT (sext, v16hi, v16di, 16) +DEF_COND_CONVERT (sext, v32hi, v32di, 32) +DEF_COND_CONVERT (sext, v64hi, v64di, 64) +DEF_COND_CONVERT (sext, v128hi, v128di, 128) +DEF_COND_CONVERT (sext, v256hi, v256di, 256) +DEF_COND_CONVERT (sext, v512hi, v512di, 512) + +DEF_COND_CONVERT (zext, v4uqi, v4usi, 4) +DEF_COND_CONVERT (zext, v16uqi, v16usi, 16) +DEF_COND_CONVERT (zext, v32uqi, v32usi, 32) +DEF_COND_CONVERT (zext, v64uqi, v64usi, 64) +DEF_COND_CONVERT (zext, v128uqi, v128usi, 128) +DEF_COND_CONVERT (zext, v256uqi, v256usi, 256) +DEF_COND_CONVERT (zext, v512uqi, v512usi, 512) +DEF_COND_CONVERT (zext, v1024uqi, v1024usi, 1024) + +DEF_COND_CONVERT (zext, v4uhi, v4udi, 4) +DEF_COND_CONVERT (zext, v16uhi, v16udi, 16) +DEF_COND_CONVERT (zext, v32uhi, v32udi, 32) +DEF_COND_CONVERT (zext, v64uhi, v64udi, 64) +DEF_COND_CONVERT (zext, v128uhi, v128udi, 128) +DEF_COND_CONVERT (zext, v256uhi, v256udi, 256) +DEF_COND_CONVERT (zext, v512uhi, v512udi, 512) + +/* { dg-final { scan-assembler-times {vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 15 } } */ +/* { dg-final { scan-assembler-times {vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 15 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c new file mode 100644 index 0000000..2db3ea2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_CONVERT (sext, v4qi, v4di, 4) +DEF_COND_CONVERT (sext, v16qi, v16di, 16) +DEF_COND_CONVERT (sext, v32qi, v32di, 32) +DEF_COND_CONVERT (sext, v64qi, v64di, 64) +DEF_COND_CONVERT (sext, v128qi, v128di, 128) +DEF_COND_CONVERT (sext, v256qi, v256di, 256) +DEF_COND_CONVERT (sext, v512qi, v512di, 512) + +DEF_COND_CONVERT (zext, v4uqi, v4udi, 4) +DEF_COND_CONVERT (zext, v16uqi, v16udi, 16) +DEF_COND_CONVERT (zext, v32uqi, v32udi, 32) +DEF_COND_CONVERT (zext, v64uqi, v64udi, 64) +DEF_COND_CONVERT (zext, v128uqi, v128udi, 128) +DEF_COND_CONVERT (zext, v256uqi, v256udi, 256) +DEF_COND_CONVERT (zext, v512uqi, v512udi, 512) + +/* { dg-final { scan-assembler-times {vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 7 } } */ +/* { dg-final { scan-assembler-times {vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 7 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c new file mode 100644 index 0000000..192722c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_CONVERT (fwcvt, v4hf, v4sf, 4) +DEF_COND_CONVERT (fwcvt, v16hf, v16sf, 16) +DEF_COND_CONVERT (fwcvt, v32hf, v32sf, 32) +DEF_COND_CONVERT (fwcvt, v64hf, v64sf, 64) +DEF_COND_CONVERT (fwcvt, v128hf, v128sf, 128) +DEF_COND_CONVERT (fwcvt, v256hf, v256sf, 256) +DEF_COND_CONVERT (fwcvt, v512hf, v512sf, 512) +DEF_COND_CONVERT (fwcvt, v1024hf, v1024sf, 1024) + +DEF_COND_CONVERT (fwcvt, v4sf, v4df, 4) +DEF_COND_CONVERT (fwcvt, v16sf, v16df, 16) +DEF_COND_CONVERT (fwcvt, v32sf, v32df, 32) +DEF_COND_CONVERT (fwcvt, v64sf, v64df, 64) +DEF_COND_CONVERT (fwcvt, v128sf, v128df, 128) +DEF_COND_CONVERT (fwcvt, v256sf, v256df, 256) +DEF_COND_CONVERT (fwcvt, v512sf, v512df, 512) + +/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 15 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c new file mode 100644 index 0000000..96ba993 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_CONVERT (fwcvt, v4hf, v4df, 4) +DEF_COND_CONVERT (fwcvt, v16hf, v16df, 16) +DEF_COND_CONVERT (fwcvt, v32hf, v32df, 32) +DEF_COND_CONVERT (fwcvt, v64hf, v64df, 64) +DEF_COND_CONVERT (fwcvt, v128hf, v128df, 128) +DEF_COND_CONVERT (fwcvt, v256hf, v256df, 256) +DEF_COND_CONVERT (fwcvt, v512hf, v512df, 512) + +/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 7 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c new file mode 100644 index 0000000..54d2f07 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FMA_VV (cond_fma, 4, v4qi) +DEF_COND_FMA_VV (cond_fma, 8, v8qi) +DEF_COND_FMA_VV (cond_fma, 16, v16qi) +DEF_COND_FMA_VV (cond_fma, 32, v32qi) +DEF_COND_FMA_VV (cond_fma, 64, v64qi) +DEF_COND_FMA_VV (cond_fma, 128, v128qi) +DEF_COND_FMA_VV (cond_fma, 256, v256qi) +DEF_COND_FMA_VV (cond_fma, 512, v512qi) +DEF_COND_FMA_VV (cond_fma, 1024, v1024qi) +DEF_COND_FMA_VV (cond_fma, 2048, v2048qi) +DEF_COND_FMA_VV (cond_fma, 4096, v4096qi) + +DEF_COND_FMA_VV (cond_fma, 4, v4hi) +DEF_COND_FMA_VV (cond_fma, 8, v8hi) +DEF_COND_FMA_VV (cond_fma, 16, v16hi) +DEF_COND_FMA_VV (cond_fma, 32, v32hi) +DEF_COND_FMA_VV (cond_fma, 64, v64hi) +DEF_COND_FMA_VV (cond_fma, 128, v128hi) +DEF_COND_FMA_VV (cond_fma, 256, v256hi) +DEF_COND_FMA_VV (cond_fma, 512, v512hi) +DEF_COND_FMA_VV (cond_fma, 1024, v1024hi) +DEF_COND_FMA_VV (cond_fma, 2048, v2048hi) + +DEF_COND_FMA_VV (cond_fma, 4, v4si) +DEF_COND_FMA_VV (cond_fma, 8, v8si) +DEF_COND_FMA_VV (cond_fma, 16, v16si) +DEF_COND_FMA_VV (cond_fma, 32, v32si) +DEF_COND_FMA_VV (cond_fma, 64, v64si) +DEF_COND_FMA_VV (cond_fma, 128, v128si) +DEF_COND_FMA_VV (cond_fma, 256, v256si) +DEF_COND_FMA_VV (cond_fma, 512, v512si) +DEF_COND_FMA_VV (cond_fma, 1024, v1024si) + +DEF_COND_FMA_VV (cond_fma, 4, v4di) +DEF_COND_FMA_VV (cond_fma, 8, v8di) +DEF_COND_FMA_VV (cond_fma, 16, v16di) +DEF_COND_FMA_VV (cond_fma, 32, v32di) +DEF_COND_FMA_VV (cond_fma, 64, v64di) +DEF_COND_FMA_VV (cond_fma, 128, v128di) +DEF_COND_FMA_VV (cond_fma, 256, v256di) +DEF_COND_FMA_VV (cond_fma, 512, v512di) + +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 38 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c new file mode 100644 index 0000000..145f81f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FMA_VV (cond_fma, 4, v4hf) +DEF_COND_FMA_VV (cond_fma, 8, v8hf) +DEF_COND_FMA_VV (cond_fma, 16, v16hf) +DEF_COND_FMA_VV (cond_fma, 32, v32hf) +DEF_COND_FMA_VV (cond_fma, 64, v64hf) +DEF_COND_FMA_VV (cond_fma, 128, v128hf) +DEF_COND_FMA_VV (cond_fma, 256, v256hf) +DEF_COND_FMA_VV (cond_fma, 512, v512hf) +DEF_COND_FMA_VV (cond_fma, 1024, v1024hf) +DEF_COND_FMA_VV (cond_fma, 2048, v2048hf) + +DEF_COND_FMA_VV (cond_fma, 4, v4sf) +DEF_COND_FMA_VV (cond_fma, 8, v8sf) +DEF_COND_FMA_VV (cond_fma, 16, v16sf) +DEF_COND_FMA_VV (cond_fma, 32, v32sf) +DEF_COND_FMA_VV (cond_fma, 64, v64sf) +DEF_COND_FMA_VV (cond_fma, 128, v128sf) +DEF_COND_FMA_VV (cond_fma, 256, v256sf) +DEF_COND_FMA_VV (cond_fma, 512, v512sf) +DEF_COND_FMA_VV (cond_fma, 1024, v1024sf) + +DEF_COND_FMA_VV (cond_fma, 4, v4df) +DEF_COND_FMA_VV (cond_fma, 8, v8df) +DEF_COND_FMA_VV (cond_fma, 16, v16df) +DEF_COND_FMA_VV (cond_fma, 32, v32df) +DEF_COND_FMA_VV (cond_fma, 64, v64df) +DEF_COND_FMA_VV (cond_fma, 128, v128df) +DEF_COND_FMA_VV (cond_fma, 256, v256df) +DEF_COND_FMA_VV (cond_fma, 512, v512df) + +/* { dg-final { scan-assembler-times {vfma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c new file mode 100644 index 0000000..bfed1db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FMS_VV (cond_fms, 4, v4hf) +DEF_COND_FMS_VV (cond_fms, 8, v8hf) +DEF_COND_FMS_VV (cond_fms, 16, v16hf) +DEF_COND_FMS_VV (cond_fms, 32, v32hf) +DEF_COND_FMS_VV (cond_fms, 64, v64hf) +DEF_COND_FMS_VV (cond_fms, 128, v128hf) +DEF_COND_FMS_VV (cond_fms, 256, v256hf) +DEF_COND_FMS_VV (cond_fms, 512, v512hf) +DEF_COND_FMS_VV (cond_fms, 1024, v1024hf) +DEF_COND_FMS_VV (cond_fms, 2048, v2048hf) + +DEF_COND_FMS_VV (cond_fms, 4, v4sf) +DEF_COND_FMS_VV (cond_fms, 8, v8sf) +DEF_COND_FMS_VV (cond_fms, 16, v16sf) +DEF_COND_FMS_VV (cond_fms, 32, v32sf) +DEF_COND_FMS_VV (cond_fms, 64, v64sf) +DEF_COND_FMS_VV (cond_fms, 128, v128sf) +DEF_COND_FMS_VV (cond_fms, 256, v256sf) +DEF_COND_FMS_VV (cond_fms, 512, v512sf) +DEF_COND_FMS_VV (cond_fms, 1024, v1024sf) + +DEF_COND_FMS_VV (cond_fms, 4, v4df) +DEF_COND_FMS_VV (cond_fms, 8, v8df) +DEF_COND_FMS_VV (cond_fms, 16, v16df) +DEF_COND_FMS_VV (cond_fms, 32, v32df) +DEF_COND_FMS_VV (cond_fms, 64, v64df) +DEF_COND_FMS_VV (cond_fms, 128, v128df) +DEF_COND_FMS_VV (cond_fms, 256, v256df) +DEF_COND_FMS_VV (cond_fms, 512, v512df) + +/* { dg-final { scan-assembler-times {vfms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c new file mode 100644 index 0000000..5871c71 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FNMA_VV (cond_fnma, 4, v4qi) +DEF_COND_FNMA_VV (cond_fnma, 8, v8qi) +DEF_COND_FNMA_VV (cond_fnma, 16, v16qi) +DEF_COND_FNMA_VV (cond_fnma, 32, v32qi) +DEF_COND_FNMA_VV (cond_fnma, 64, v64qi) +DEF_COND_FNMA_VV (cond_fnma, 128, v128qi) +DEF_COND_FNMA_VV (cond_fnma, 256, v256qi) +DEF_COND_FNMA_VV (cond_fnma, 512, v512qi) +DEF_COND_FNMA_VV (cond_fnma, 1024, v1024qi) +DEF_COND_FNMA_VV (cond_fnma, 2048, v2048qi) +DEF_COND_FNMA_VV (cond_fnma, 4096, v4096qi) + +DEF_COND_FNMA_VV (cond_fnma, 4, v4hi) +DEF_COND_FNMA_VV (cond_fnma, 8, v8hi) +DEF_COND_FNMA_VV (cond_fnma, 16, v16hi) +DEF_COND_FNMA_VV (cond_fnma, 32, v32hi) +DEF_COND_FNMA_VV (cond_fnma, 64, v64hi) +DEF_COND_FNMA_VV (cond_fnma, 128, v128hi) +DEF_COND_FNMA_VV (cond_fnma, 256, v256hi) +DEF_COND_FNMA_VV (cond_fnma, 512, v512hi) +DEF_COND_FNMA_VV (cond_fnma, 1024, v1024hi) +DEF_COND_FNMA_VV (cond_fnma, 2048, v2048hi) + +DEF_COND_FNMA_VV (cond_fnma, 4, v4si) +DEF_COND_FNMA_VV (cond_fnma, 8, v8si) +DEF_COND_FNMA_VV (cond_fnma, 16, v16si) +DEF_COND_FNMA_VV (cond_fnma, 32, v32si) +DEF_COND_FNMA_VV (cond_fnma, 64, v64si) +DEF_COND_FNMA_VV (cond_fnma, 128, v128si) +DEF_COND_FNMA_VV (cond_fnma, 256, v256si) +DEF_COND_FNMA_VV (cond_fnma, 512, v512si) +DEF_COND_FNMA_VV (cond_fnma, 1024, v1024si) + +DEF_COND_FNMA_VV (cond_fnma, 4, v4di) +DEF_COND_FNMA_VV (cond_fnma, 8, v8di) +DEF_COND_FNMA_VV (cond_fnma, 16, v16di) +DEF_COND_FNMA_VV (cond_fnma, 32, v32di) +DEF_COND_FNMA_VV (cond_fnma, 64, v64di) +DEF_COND_FNMA_VV (cond_fnma, 128, v128di) +DEF_COND_FNMA_VV (cond_fnma, 256, v256di) +DEF_COND_FNMA_VV (cond_fnma, 512, v512di) + +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 38 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c new file mode 100644 index 0000000..f91039a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FNMA_VV (cond_fnma, 4, v4hf) +DEF_COND_FNMA_VV (cond_fnma, 8, v8hf) +DEF_COND_FNMA_VV (cond_fnma, 16, v16hf) +DEF_COND_FNMA_VV (cond_fnma, 32, v32hf) +DEF_COND_FNMA_VV (cond_fnma, 64, v64hf) +DEF_COND_FNMA_VV (cond_fnma, 128, v128hf) +DEF_COND_FNMA_VV (cond_fnma, 256, v256hf) +DEF_COND_FNMA_VV (cond_fnma, 512, v512hf) +DEF_COND_FNMA_VV (cond_fnma, 1024, v1024hf) +DEF_COND_FNMA_VV (cond_fnma, 2048, v2048hf) + +DEF_COND_FNMA_VV (cond_fnma, 4, v4sf) +DEF_COND_FNMA_VV (cond_fnma, 8, v8sf) +DEF_COND_FNMA_VV (cond_fnma, 16, v16sf) +DEF_COND_FNMA_VV (cond_fnma, 32, v32sf) +DEF_COND_FNMA_VV (cond_fnma, 64, v64sf) +DEF_COND_FNMA_VV (cond_fnma, 128, v128sf) +DEF_COND_FNMA_VV (cond_fnma, 256, v256sf) +DEF_COND_FNMA_VV (cond_fnma, 512, v512sf) +DEF_COND_FNMA_VV (cond_fnma, 1024, v1024sf) + +DEF_COND_FNMA_VV (cond_fnma, 4, v4df) +DEF_COND_FNMA_VV (cond_fnma, 8, v8df) +DEF_COND_FNMA_VV (cond_fnma, 16, v16df) +DEF_COND_FNMA_VV (cond_fnma, 32, v32df) +DEF_COND_FNMA_VV (cond_fnma, 64, v64df) +DEF_COND_FNMA_VV (cond_fnma, 128, v128df) +DEF_COND_FNMA_VV (cond_fnma, 256, v256df) +DEF_COND_FNMA_VV (cond_fnma, 512, v512df) + +/* { dg-final { scan-assembler-times {vfnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c new file mode 100644 index 0000000..59fae9b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_FNMS_VV (cond_fnms, 4, v4hf) +DEF_COND_FNMS_VV (cond_fnms, 8, v8hf) +DEF_COND_FNMS_VV (cond_fnms, 16, v16hf) +DEF_COND_FNMS_VV (cond_fnms, 32, v32hf) +DEF_COND_FNMS_VV (cond_fnms, 64, v64hf) +DEF_COND_FNMS_VV (cond_fnms, 128, v128hf) +DEF_COND_FNMS_VV (cond_fnms, 256, v256hf) +DEF_COND_FNMS_VV (cond_fnms, 512, v512hf) +DEF_COND_FNMS_VV (cond_fnms, 1024, v1024hf) +DEF_COND_FNMS_VV (cond_fnms, 2048, v2048hf) + +DEF_COND_FNMS_VV (cond_fnms, 4, v4sf) +DEF_COND_FNMS_VV (cond_fnms, 8, v8sf) +DEF_COND_FNMS_VV (cond_fnms, 16, v16sf) +DEF_COND_FNMS_VV (cond_fnms, 32, v32sf) +DEF_COND_FNMS_VV (cond_fnms, 64, v64sf) +DEF_COND_FNMS_VV (cond_fnms, 128, v128sf) +DEF_COND_FNMS_VV (cond_fnms, 256, v256sf) +DEF_COND_FNMS_VV (cond_fnms, 512, v512sf) +DEF_COND_FNMS_VV (cond_fnms, 1024, v1024sf) + +DEF_COND_FNMS_VV (cond_fnms, 4, v4df) +DEF_COND_FNMS_VV (cond_fnms, 8, v8df) +DEF_COND_FNMS_VV (cond_fnms, 16, v16df) +DEF_COND_FNMS_VV (cond_fnms, 32, v32df) +DEF_COND_FNMS_VV (cond_fnms, 64, v64df) +DEF_COND_FNMS_VV (cond_fnms, 128, v128df) +DEF_COND_FNMS_VV (cond_fnms, 256, v256df) +DEF_COND_FNMS_VV (cond_fnms, 512, v512df) + +/* { dg-final { scan-assembler-times {vfnma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c new file mode 100644 index 0000000..2c30854 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_ior, 4, v4qi, |) +DEF_COND_BINOP (cond_ior, 8, v8qi, |) +DEF_COND_BINOP (cond_ior, 16, v16qi, |) +DEF_COND_BINOP (cond_ior, 32, v32qi, |) +DEF_COND_BINOP (cond_ior, 64, v64qi, |) +DEF_COND_BINOP (cond_ior, 128, v128qi, |) +DEF_COND_BINOP (cond_ior, 256, v256qi, |) +DEF_COND_BINOP (cond_ior, 512, v512qi, |) +DEF_COND_BINOP (cond_ior, 1024, v1024qi, |) +DEF_COND_BINOP (cond_ior, 2048, v2048qi, |) +DEF_COND_BINOP (cond_ior, 4096, v4096qi, |) + +DEF_COND_BINOP (cond_ior, 4, v4hi, |) +DEF_COND_BINOP (cond_ior, 8, v8hi, |) +DEF_COND_BINOP (cond_ior, 16, v16hi, |) +DEF_COND_BINOP (cond_ior, 32, v32hi, |) +DEF_COND_BINOP (cond_ior, 64, v64hi, |) +DEF_COND_BINOP (cond_ior, 128, v128hi, |) +DEF_COND_BINOP (cond_ior, 256, v256hi, |) +DEF_COND_BINOP (cond_ior, 512, v512hi, |) +DEF_COND_BINOP (cond_ior, 1024, v1024hi, |) +DEF_COND_BINOP (cond_ior, 2048, v2048hi, |) + +DEF_COND_BINOP (cond_ior, 4, v4si, |) +DEF_COND_BINOP (cond_ior, 8, v8si, |) +DEF_COND_BINOP (cond_ior, 16, v16si, |) +DEF_COND_BINOP (cond_ior, 32, v32si, |) +DEF_COND_BINOP (cond_ior, 64, v64si, |) +DEF_COND_BINOP (cond_ior, 128, v128si, |) +DEF_COND_BINOP (cond_ior, 256, v256si, |) +DEF_COND_BINOP (cond_ior, 512, v512si, |) +DEF_COND_BINOP (cond_ior, 1024, v1024si, |) + +DEF_COND_BINOP (cond_ior, 4, v4di, |) +DEF_COND_BINOP (cond_ior, 8, v8di, |) +DEF_COND_BINOP (cond_ior, 16, v16di, |) +DEF_COND_BINOP (cond_ior, 32, v32di, |) +DEF_COND_BINOP (cond_ior, 64, v64di, |) +DEF_COND_BINOP (cond_ior, 128, v128di, |) +DEF_COND_BINOP (cond_ior, 256, v256di, |) +DEF_COND_BINOP (cond_ior, 512, v512di, |) + +DEF_COND_BINOP (cond_ior, 4, v4uqi, |) +DEF_COND_BINOP (cond_ior, 8, v8uqi, |) +DEF_COND_BINOP (cond_ior, 16, v16uqi, |) +DEF_COND_BINOP (cond_ior, 32, v32uqi, |) +DEF_COND_BINOP (cond_ior, 64, v64uqi, |) +DEF_COND_BINOP (cond_ior, 128, v128uqi, |) +DEF_COND_BINOP (cond_ior, 256, v256uqi, |) +DEF_COND_BINOP (cond_ior, 512, v512uqi, |) +DEF_COND_BINOP (cond_ior, 1024, v1024uqi, |) +DEF_COND_BINOP (cond_ior, 2048, v2048uqi, |) +DEF_COND_BINOP (cond_ior, 4096, v4096uqi, |) + +DEF_COND_BINOP (cond_ior, 4, v4uhi, |) +DEF_COND_BINOP (cond_ior, 8, v8uhi, |) +DEF_COND_BINOP (cond_ior, 16, v16uhi, |) +DEF_COND_BINOP (cond_ior, 32, v32uhi, |) +DEF_COND_BINOP (cond_ior, 64, v64uhi, |) +DEF_COND_BINOP (cond_ior, 128, v128uhi, |) +DEF_COND_BINOP (cond_ior, 256, v256uhi, |) +DEF_COND_BINOP (cond_ior, 512, v512uhi, |) +DEF_COND_BINOP (cond_ior, 1024, v1024uhi, |) +DEF_COND_BINOP (cond_ior, 2048, v2048uhi, |) + +DEF_COND_BINOP (cond_ior, 4, v4usi, |) +DEF_COND_BINOP (cond_ior, 8, v8usi, |) +DEF_COND_BINOP (cond_ior, 16, v16usi, |) +DEF_COND_BINOP (cond_ior, 32, v32usi, |) +DEF_COND_BINOP (cond_ior, 64, v64usi, |) +DEF_COND_BINOP (cond_ior, 128, v128usi, |) +DEF_COND_BINOP (cond_ior, 256, v256usi, |) +DEF_COND_BINOP (cond_ior, 512, v512usi, |) +DEF_COND_BINOP (cond_ior, 1024, v1024usi, |) + +DEF_COND_BINOP (cond_ior, 4, v4udi, |) +DEF_COND_BINOP (cond_ior, 8, v8udi, |) +DEF_COND_BINOP (cond_ior, 16, v16udi, |) +DEF_COND_BINOP (cond_ior, 32, v32udi, |) +DEF_COND_BINOP (cond_ior, 64, v64udi, |) +DEF_COND_BINOP (cond_ior, 128, v128udi, |) +DEF_COND_BINOP (cond_ior, 256, v256udi, |) +DEF_COND_BINOP (cond_ior, 512, v512udi, |) + +/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c new file mode 100644 index 0000000..60e0f93 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_MINMAX (cond_max, 4, v4qi, >=) +DEF_COND_MINMAX (cond_max, 8, v8qi, >=) +DEF_COND_MINMAX (cond_max, 16, v16qi, >=) +DEF_COND_MINMAX (cond_max, 32, v32qi, >=) +DEF_COND_MINMAX (cond_max, 64, v64qi, >=) +DEF_COND_MINMAX (cond_max, 128, v128qi, >=) +DEF_COND_MINMAX (cond_max, 256, v256qi, >=) +DEF_COND_MINMAX (cond_max, 512, v512qi, >=) +DEF_COND_MINMAX (cond_max, 1024, v1024qi, >=) +DEF_COND_MINMAX (cond_max, 2048, v2048qi, >=) +DEF_COND_MINMAX (cond_max, 4096, v4096qi, >=) + +DEF_COND_MINMAX (cond_max, 4, v4hi, >=) +DEF_COND_MINMAX (cond_max, 8, v8hi, >=) +DEF_COND_MINMAX (cond_max, 16, v16hi, >=) +DEF_COND_MINMAX (cond_max, 32, v32hi, >=) +DEF_COND_MINMAX (cond_max, 64, v64hi, >=) +DEF_COND_MINMAX (cond_max, 128, v128hi, >=) +DEF_COND_MINMAX (cond_max, 256, v256hi, >=) +DEF_COND_MINMAX (cond_max, 512, v512hi, >=) +DEF_COND_MINMAX (cond_max, 1024, v1024hi, >=) +DEF_COND_MINMAX (cond_max, 2048, v2048hi, >=) + +DEF_COND_MINMAX (cond_max, 4, v4si, >=) +DEF_COND_MINMAX (cond_max, 8, v8si, >=) +DEF_COND_MINMAX (cond_max, 16, v16si, >=) +DEF_COND_MINMAX (cond_max, 32, v32si, >=) +DEF_COND_MINMAX (cond_max, 64, v64si, >=) +DEF_COND_MINMAX (cond_max, 128, v128si, >=) +DEF_COND_MINMAX (cond_max, 256, v256si, >=) +DEF_COND_MINMAX (cond_max, 512, v512si, >=) +DEF_COND_MINMAX (cond_max, 1024, v1024si, >=) + +DEF_COND_MINMAX (cond_max, 4, v4di, >=) +DEF_COND_MINMAX (cond_max, 8, v8di, >=) +DEF_COND_MINMAX (cond_max, 16, v16di, >=) +DEF_COND_MINMAX (cond_max, 32, v32di, >=) +DEF_COND_MINMAX (cond_max, 64, v64di, >=) +DEF_COND_MINMAX (cond_max, 128, v128di, >=) +DEF_COND_MINMAX (cond_max, 256, v256di, >=) +DEF_COND_MINMAX (cond_max, 512, v512di, >=) + +DEF_COND_MINMAX (cond_max, 4, v4uqi, >=) +DEF_COND_MINMAX (cond_max, 8, v8uqi, >=) +DEF_COND_MINMAX (cond_max, 16, v16uqi, >=) +DEF_COND_MINMAX (cond_max, 32, v32uqi, >=) +DEF_COND_MINMAX (cond_max, 64, v64uqi, >=) +DEF_COND_MINMAX (cond_max, 128, v128uqi, >=) +DEF_COND_MINMAX (cond_max, 256, v256uqi, >=) +DEF_COND_MINMAX (cond_max, 512, v512uqi, >=) +DEF_COND_MINMAX (cond_max, 1024, v1024uqi, >=) +DEF_COND_MINMAX (cond_max, 2048, v2048uqi, >=) +DEF_COND_MINMAX (cond_max, 4096, v4096uqi, >=) + +DEF_COND_MINMAX (cond_max, 4, v4uhi, >=) +DEF_COND_MINMAX (cond_max, 8, v8uhi, >=) +DEF_COND_MINMAX (cond_max, 16, v16uhi, >=) +DEF_COND_MINMAX (cond_max, 32, v32uhi, >=) +DEF_COND_MINMAX (cond_max, 64, v64uhi, >=) +DEF_COND_MINMAX (cond_max, 128, v128uhi, >=) +DEF_COND_MINMAX (cond_max, 256, v256uhi, >=) +DEF_COND_MINMAX (cond_max, 512, v512uhi, >=) +DEF_COND_MINMAX (cond_max, 1024, v1024uhi, >=) +DEF_COND_MINMAX (cond_max, 2048, v2048uhi, >=) + +DEF_COND_MINMAX (cond_max, 4, v4usi, >=) +DEF_COND_MINMAX (cond_max, 8, v8usi, >=) +DEF_COND_MINMAX (cond_max, 16, v16usi, >=) +DEF_COND_MINMAX (cond_max, 32, v32usi, >=) +DEF_COND_MINMAX (cond_max, 64, v64usi, >=) +DEF_COND_MINMAX (cond_max, 128, v128usi, >=) +DEF_COND_MINMAX (cond_max, 256, v256usi, >=) +DEF_COND_MINMAX (cond_max, 512, v512usi, >=) +DEF_COND_MINMAX (cond_max, 1024, v1024usi, >=) + +DEF_COND_MINMAX (cond_max, 4, v4udi, >=) +DEF_COND_MINMAX (cond_max, 8, v8udi, >=) +DEF_COND_MINMAX (cond_max, 16, v16udi, >=) +DEF_COND_MINMAX (cond_max, 32, v32udi, >=) +DEF_COND_MINMAX (cond_max, 64, v64udi, >=) +DEF_COND_MINMAX (cond_max, 128, v128udi, >=) +DEF_COND_MINMAX (cond_max, 256, v256udi, >=) +DEF_COND_MINMAX (cond_max, 512, v512udi, >=) + +/* { dg-final { scan-assembler-times {vmaxu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c new file mode 100644 index 0000000..f8db292 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_MINMAX (cond_max, 4, v4hf, >=) +DEF_COND_MINMAX (cond_max, 8, v8hf, >=) +DEF_COND_MINMAX (cond_max, 16, v16hf, >=) +DEF_COND_MINMAX (cond_max, 32, v32hf, >=) +DEF_COND_MINMAX (cond_max, 64, v64hf, >=) +DEF_COND_MINMAX (cond_max, 128, v128hf, >=) +DEF_COND_MINMAX (cond_max, 256, v256hf, >=) +DEF_COND_MINMAX (cond_max, 512, v512hf, >=) +DEF_COND_MINMAX (cond_max, 1024, v1024hf, >=) +DEF_COND_MINMAX (cond_max, 2048, v2048hf, >=) + +DEF_COND_MINMAX (cond_max, 4, v4sf, >=) +DEF_COND_MINMAX (cond_max, 8, v8sf, >=) +DEF_COND_MINMAX (cond_max, 16, v16sf, >=) +DEF_COND_MINMAX (cond_max, 32, v32sf, >=) +DEF_COND_MINMAX (cond_max, 64, v64sf, >=) +DEF_COND_MINMAX (cond_max, 128, v128sf, >=) +DEF_COND_MINMAX (cond_max, 256, v256sf, >=) +DEF_COND_MINMAX (cond_max, 512, v512sf, >=) +DEF_COND_MINMAX (cond_max, 1024, v1024sf, >=) + +DEF_COND_MINMAX (cond_max, 4, v4df, >=) +DEF_COND_MINMAX (cond_max, 8, v8df, >=) +DEF_COND_MINMAX (cond_max, 16, v16df, >=) +DEF_COND_MINMAX (cond_max, 32, v32df, >=) +DEF_COND_MINMAX (cond_max, 64, v64df, >=) +DEF_COND_MINMAX (cond_max, 128, v128df, >=) +DEF_COND_MINMAX (cond_max, 256, v256df, >=) +DEF_COND_MINMAX (cond_max, 512, v512df, >=) + +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c new file mode 100644 index 0000000..2a13c25 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_MINMAX (cond_min, 4, v4qi, <=) +DEF_COND_MINMAX (cond_min, 8, v8qi, <=) +DEF_COND_MINMAX (cond_min, 16, v16qi, <=) +DEF_COND_MINMAX (cond_min, 32, v32qi, <=) +DEF_COND_MINMAX (cond_min, 64, v64qi, <=) +DEF_COND_MINMAX (cond_min, 128, v128qi, <=) +DEF_COND_MINMAX (cond_min, 256, v256qi, <=) +DEF_COND_MINMAX (cond_min, 512, v512qi, <=) +DEF_COND_MINMAX (cond_min, 1024, v1024qi, <=) +DEF_COND_MINMAX (cond_min, 2048, v2048qi, <=) +DEF_COND_MINMAX (cond_min, 4096, v4096qi, <=) + +DEF_COND_MINMAX (cond_min, 4, v4hi, <=) +DEF_COND_MINMAX (cond_min, 8, v8hi, <=) +DEF_COND_MINMAX (cond_min, 16, v16hi, <=) +DEF_COND_MINMAX (cond_min, 32, v32hi, <=) +DEF_COND_MINMAX (cond_min, 64, v64hi, <=) +DEF_COND_MINMAX (cond_min, 128, v128hi, <=) +DEF_COND_MINMAX (cond_min, 256, v256hi, <=) +DEF_COND_MINMAX (cond_min, 512, v512hi, <=) +DEF_COND_MINMAX (cond_min, 1024, v1024hi, <=) +DEF_COND_MINMAX (cond_min, 2048, v2048hi, <=) + +DEF_COND_MINMAX (cond_min, 4, v4si, <=) +DEF_COND_MINMAX (cond_min, 8, v8si, <=) +DEF_COND_MINMAX (cond_min, 16, v16si, <=) +DEF_COND_MINMAX (cond_min, 32, v32si, <=) +DEF_COND_MINMAX (cond_min, 64, v64si, <=) +DEF_COND_MINMAX (cond_min, 128, v128si, <=) +DEF_COND_MINMAX (cond_min, 256, v256si, <=) +DEF_COND_MINMAX (cond_min, 512, v512si, <=) +DEF_COND_MINMAX (cond_min, 1024, v1024si, <=) + +DEF_COND_MINMAX (cond_min, 4, v4di, <=) +DEF_COND_MINMAX (cond_min, 8, v8di, <=) +DEF_COND_MINMAX (cond_min, 16, v16di, <=) +DEF_COND_MINMAX (cond_min, 32, v32di, <=) +DEF_COND_MINMAX (cond_min, 64, v64di, <=) +DEF_COND_MINMAX (cond_min, 128, v128di, <=) +DEF_COND_MINMAX (cond_min, 256, v256di, <=) +DEF_COND_MINMAX (cond_min, 512, v512di, <=) + +DEF_COND_MINMAX (cond_min, 4, v4uqi, <=) +DEF_COND_MINMAX (cond_min, 8, v8uqi, <=) +DEF_COND_MINMAX (cond_min, 16, v16uqi, <=) +DEF_COND_MINMAX (cond_min, 32, v32uqi, <=) +DEF_COND_MINMAX (cond_min, 64, v64uqi, <=) +DEF_COND_MINMAX (cond_min, 128, v128uqi, <=) +DEF_COND_MINMAX (cond_min, 256, v256uqi, <=) +DEF_COND_MINMAX (cond_min, 512, v512uqi, <=) +DEF_COND_MINMAX (cond_min, 1024, v1024uqi, <=) +DEF_COND_MINMAX (cond_min, 2048, v2048uqi, <=) +DEF_COND_MINMAX (cond_min, 4096, v4096uqi, <=) + +DEF_COND_MINMAX (cond_min, 4, v4uhi, <=) +DEF_COND_MINMAX (cond_min, 8, v8uhi, <=) +DEF_COND_MINMAX (cond_min, 16, v16uhi, <=) +DEF_COND_MINMAX (cond_min, 32, v32uhi, <=) +DEF_COND_MINMAX (cond_min, 64, v64uhi, <=) +DEF_COND_MINMAX (cond_min, 128, v128uhi, <=) +DEF_COND_MINMAX (cond_min, 256, v256uhi, <=) +DEF_COND_MINMAX (cond_min, 512, v512uhi, <=) +DEF_COND_MINMAX (cond_min, 1024, v1024uhi, <=) +DEF_COND_MINMAX (cond_min, 2048, v2048uhi, <=) + +DEF_COND_MINMAX (cond_min, 4, v4usi, <=) +DEF_COND_MINMAX (cond_min, 8, v8usi, <=) +DEF_COND_MINMAX (cond_min, 16, v16usi, <=) +DEF_COND_MINMAX (cond_min, 32, v32usi, <=) +DEF_COND_MINMAX (cond_min, 64, v64usi, <=) +DEF_COND_MINMAX (cond_min, 128, v128usi, <=) +DEF_COND_MINMAX (cond_min, 256, v256usi, <=) +DEF_COND_MINMAX (cond_min, 512, v512usi, <=) +DEF_COND_MINMAX (cond_min, 1024, v1024usi, <=) + +DEF_COND_MINMAX (cond_min, 4, v4udi, <=) +DEF_COND_MINMAX (cond_min, 8, v8udi, <=) +DEF_COND_MINMAX (cond_min, 16, v16udi, <=) +DEF_COND_MINMAX (cond_min, 32, v32udi, <=) +DEF_COND_MINMAX (cond_min, 64, v64udi, <=) +DEF_COND_MINMAX (cond_min, 128, v128udi, <=) +DEF_COND_MINMAX (cond_min, 256, v256udi, <=) +DEF_COND_MINMAX (cond_min, 512, v512udi, <=) + +/* { dg-final { scan-assembler-times {vminu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c new file mode 100644 index 0000000..0ae8208 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_MINMAX (cond_min, 4, v4hf, <=) +DEF_COND_MINMAX (cond_min, 8, v8hf, <=) +DEF_COND_MINMAX (cond_min, 16, v16hf, <=) +DEF_COND_MINMAX (cond_min, 32, v32hf, <=) +DEF_COND_MINMAX (cond_min, 64, v64hf, <=) +DEF_COND_MINMAX (cond_min, 128, v128hf, <=) +DEF_COND_MINMAX (cond_min, 256, v256hf, <=) +DEF_COND_MINMAX (cond_min, 512, v512hf, <=) +DEF_COND_MINMAX (cond_min, 1024, v1024hf, <=) +DEF_COND_MINMAX (cond_min, 2048, v2048hf, <=) + +DEF_COND_MINMAX (cond_min, 4, v4sf, <=) +DEF_COND_MINMAX (cond_min, 8, v8sf, <=) +DEF_COND_MINMAX (cond_min, 16, v16sf, <=) +DEF_COND_MINMAX (cond_min, 32, v32sf, <=) +DEF_COND_MINMAX (cond_min, 64, v64sf, <=) +DEF_COND_MINMAX (cond_min, 128, v128sf, <=) +DEF_COND_MINMAX (cond_min, 256, v256sf, <=) +DEF_COND_MINMAX (cond_min, 512, v512sf, <=) +DEF_COND_MINMAX (cond_min, 1024, v1024sf, <=) + +DEF_COND_MINMAX (cond_min, 4, v4df, <=) +DEF_COND_MINMAX (cond_min, 8, v8df, <=) +DEF_COND_MINMAX (cond_min, 16, v16df, <=) +DEF_COND_MINMAX (cond_min, 32, v32df, <=) +DEF_COND_MINMAX (cond_min, 64, v64df, <=) +DEF_COND_MINMAX (cond_min, 128, v128df, <=) +DEF_COND_MINMAX (cond_min, 256, v256df, <=) +DEF_COND_MINMAX (cond_min, 512, v512df, <=) + +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c new file mode 100644 index 0000000..060c58b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_rem, 4, v4si, %) +DEF_COND_BINOP (cond_rem, 8, v8si, %) +DEF_COND_BINOP (cond_rem, 16, v16si, %) +DEF_COND_BINOP (cond_rem, 32, v32si, %) +DEF_COND_BINOP (cond_rem, 64, v64si, %) +DEF_COND_BINOP (cond_rem, 128, v128si, %) +DEF_COND_BINOP (cond_rem, 256, v256si, %) +DEF_COND_BINOP (cond_rem, 512, v512si, %) +DEF_COND_BINOP (cond_rem, 1024, v1024si, %) + +DEF_COND_BINOP (cond_rem, 4, v4di, %) +DEF_COND_BINOP (cond_rem, 8, v8di, %) +DEF_COND_BINOP (cond_rem, 16, v16di, %) +DEF_COND_BINOP (cond_rem, 32, v32di, %) +DEF_COND_BINOP (cond_rem, 64, v64di, %) +DEF_COND_BINOP (cond_rem, 128, v128di, %) +DEF_COND_BINOP (cond_rem, 256, v256di, %) +DEF_COND_BINOP (cond_rem, 512, v512di, %) + +DEF_COND_BINOP (cond_rem, 4, v4usi, %) +DEF_COND_BINOP (cond_rem, 8, v8usi, %) +DEF_COND_BINOP (cond_rem, 16, v16usi, %) +DEF_COND_BINOP (cond_rem, 32, v32usi, %) +DEF_COND_BINOP (cond_rem, 64, v64usi, %) +DEF_COND_BINOP (cond_rem, 128, v128usi, %) +DEF_COND_BINOP (cond_rem, 256, v256usi, %) +DEF_COND_BINOP (cond_rem, 512, v512usi, %) +DEF_COND_BINOP (cond_rem, 1024, v1024usi, %) + +DEF_COND_BINOP (cond_rem, 4, v4udi, %) +DEF_COND_BINOP (cond_rem, 8, v8udi, %) +DEF_COND_BINOP (cond_rem, 16, v16udi, %) +DEF_COND_BINOP (cond_rem, 32, v32udi, %) +DEF_COND_BINOP (cond_rem, 64, v64udi, %) +DEF_COND_BINOP (cond_rem, 128, v128udi, %) +DEF_COND_BINOP (cond_rem, 256, v256udi, %) +DEF_COND_BINOP (cond_rem, 512, v512udi, %) + +/* { dg-final { scan-assembler-times {vremu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 34 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c new file mode 100644 index 0000000..f6b58c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_mul, 4, v4qi, *) +DEF_COND_BINOP (cond_mul, 8, v8qi, *) +DEF_COND_BINOP (cond_mul, 16, v16qi, *) +DEF_COND_BINOP (cond_mul, 32, v32qi, *) +DEF_COND_BINOP (cond_mul, 64, v64qi, *) +DEF_COND_BINOP (cond_mul, 128, v128qi, *) +DEF_COND_BINOP (cond_mul, 256, v256qi, *) +DEF_COND_BINOP (cond_mul, 512, v512qi, *) +DEF_COND_BINOP (cond_mul, 1024, v1024qi, *) +DEF_COND_BINOP (cond_mul, 2048, v2048qi, *) +DEF_COND_BINOP (cond_mul, 4096, v4096qi, *) + +DEF_COND_BINOP (cond_mul, 4, v4hi, *) +DEF_COND_BINOP (cond_mul, 8, v8hi, *) +DEF_COND_BINOP (cond_mul, 16, v16hi, *) +DEF_COND_BINOP (cond_mul, 32, v32hi, *) +DEF_COND_BINOP (cond_mul, 64, v64hi, *) +DEF_COND_BINOP (cond_mul, 128, v128hi, *) +DEF_COND_BINOP (cond_mul, 256, v256hi, *) +DEF_COND_BINOP (cond_mul, 512, v512hi, *) +DEF_COND_BINOP (cond_mul, 1024, v1024hi, *) +DEF_COND_BINOP (cond_mul, 2048, v2048hi, *) + +DEF_COND_BINOP (cond_mul, 4, v4si, *) +DEF_COND_BINOP (cond_mul, 8, v8si, *) +DEF_COND_BINOP (cond_mul, 16, v16si, *) +DEF_COND_BINOP (cond_mul, 32, v32si, *) +DEF_COND_BINOP (cond_mul, 64, v64si, *) +DEF_COND_BINOP (cond_mul, 128, v128si, *) +DEF_COND_BINOP (cond_mul, 256, v256si, *) +DEF_COND_BINOP (cond_mul, 512, v512si, *) +DEF_COND_BINOP (cond_mul, 1024, v1024si, *) + +DEF_COND_BINOP (cond_mul, 4, v4di, *) +DEF_COND_BINOP (cond_mul, 8, v8di, *) +DEF_COND_BINOP (cond_mul, 16, v16di, *) +DEF_COND_BINOP (cond_mul, 32, v32di, *) +DEF_COND_BINOP (cond_mul, 64, v64di, *) +DEF_COND_BINOP (cond_mul, 128, v128di, *) +DEF_COND_BINOP (cond_mul, 256, v256di, *) +DEF_COND_BINOP (cond_mul, 512, v512di, *) + +DEF_COND_BINOP (cond_mul, 4, v4uqi, *) +DEF_COND_BINOP (cond_mul, 8, v8uqi, *) +DEF_COND_BINOP (cond_mul, 16, v16uqi, *) +DEF_COND_BINOP (cond_mul, 32, v32uqi, *) +DEF_COND_BINOP (cond_mul, 64, v64uqi, *) +DEF_COND_BINOP (cond_mul, 128, v128uqi, *) +DEF_COND_BINOP (cond_mul, 256, v256uqi, *) +DEF_COND_BINOP (cond_mul, 512, v512uqi, *) +DEF_COND_BINOP (cond_mul, 1024, v1024uqi, *) +DEF_COND_BINOP (cond_mul, 2048, v2048uqi, *) +DEF_COND_BINOP (cond_mul, 4096, v4096uqi, *) + +DEF_COND_BINOP (cond_mul, 4, v4uhi, *) +DEF_COND_BINOP (cond_mul, 8, v8uhi, *) +DEF_COND_BINOP (cond_mul, 16, v16uhi, *) +DEF_COND_BINOP (cond_mul, 32, v32uhi, *) +DEF_COND_BINOP (cond_mul, 64, v64uhi, *) +DEF_COND_BINOP (cond_mul, 128, v128uhi, *) +DEF_COND_BINOP (cond_mul, 256, v256uhi, *) +DEF_COND_BINOP (cond_mul, 512, v512uhi, *) +DEF_COND_BINOP (cond_mul, 1024, v1024uhi, *) +DEF_COND_BINOP (cond_mul, 2048, v2048uhi, *) + +DEF_COND_BINOP (cond_mul, 4, v4usi, *) +DEF_COND_BINOP (cond_mul, 8, v8usi, *) +DEF_COND_BINOP (cond_mul, 16, v16usi, *) +DEF_COND_BINOP (cond_mul, 32, v32usi, *) +DEF_COND_BINOP (cond_mul, 64, v64usi, *) +DEF_COND_BINOP (cond_mul, 128, v128usi, *) +DEF_COND_BINOP (cond_mul, 256, v256usi, *) +DEF_COND_BINOP (cond_mul, 512, v512usi, *) +DEF_COND_BINOP (cond_mul, 1024, v1024usi, *) + +DEF_COND_BINOP (cond_mul, 4, v4udi, *) +DEF_COND_BINOP (cond_mul, 8, v8udi, *) +DEF_COND_BINOP (cond_mul, 16, v16udi, *) +DEF_COND_BINOP (cond_mul, 32, v32udi, *) +DEF_COND_BINOP (cond_mul, 64, v64udi, *) +DEF_COND_BINOP (cond_mul, 128, v128udi, *) +DEF_COND_BINOP (cond_mul, 256, v256udi, *) +DEF_COND_BINOP (cond_mul, 512, v512udi, *) + +/* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c new file mode 100644 index 0000000..4df3d55 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_mul, 4, v4hf, *) +DEF_COND_BINOP (cond_mul, 8, v8hf, *) +DEF_COND_BINOP (cond_mul, 16, v16hf, *) +DEF_COND_BINOP (cond_mul, 32, v32hf, *) +DEF_COND_BINOP (cond_mul, 64, v64hf, *) +DEF_COND_BINOP (cond_mul, 128, v128hf, *) +DEF_COND_BINOP (cond_mul, 256, v256hf, *) +DEF_COND_BINOP (cond_mul, 512, v512hf, *) +DEF_COND_BINOP (cond_mul, 1024, v1024hf, *) +DEF_COND_BINOP (cond_mul, 2048, v2048hf, *) + +DEF_COND_BINOP (cond_mul, 4, v4sf, *) +DEF_COND_BINOP (cond_mul, 8, v8sf, *) +DEF_COND_BINOP (cond_mul, 16, v16sf, *) +DEF_COND_BINOP (cond_mul, 32, v32sf, *) +DEF_COND_BINOP (cond_mul, 64, v64sf, *) +DEF_COND_BINOP (cond_mul, 128, v128sf, *) +DEF_COND_BINOP (cond_mul, 256, v256sf, *) +DEF_COND_BINOP (cond_mul, 512, v512sf, *) +DEF_COND_BINOP (cond_mul, 1024, v1024sf, *) + +DEF_COND_BINOP (cond_mul, 4, v4df, *) +DEF_COND_BINOP (cond_mul, 8, v8df, *) +DEF_COND_BINOP (cond_mul, 16, v16df, *) +DEF_COND_BINOP (cond_mul, 32, v32df, *) +DEF_COND_BINOP (cond_mul, 64, v64df, *) +DEF_COND_BINOP (cond_mul, 128, v128df, *) +DEF_COND_BINOP (cond_mul, 256, v256df, *) +DEF_COND_BINOP (cond_mul, 512, v512df, *) + +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c new file mode 100644 index 0000000..ffa6458 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c @@ -0,0 +1,81 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_MULH (cond_mulh, 4, v4qi, int16_t, int8_t, 8) +DEF_COND_MULH (cond_mulh, 8, v8qi, int16_t, int8_t, 8) +DEF_COND_MULH (cond_mulh, 16, v16qi, int16_t, int8_t, 8) +DEF_COND_MULH (cond_mulh, 32, v32qi, int16_t, int8_t, 8) +DEF_COND_MULH (cond_mulh, 64, v64qi, int16_t, int8_t, 8) +DEF_COND_MULH (cond_mulh, 128, v128qi, int16_t, int8_t, 8) +DEF_COND_MULH (cond_mulh, 256, v256qi, int16_t, int8_t, 8) +DEF_COND_MULH (cond_mulh, 512, v512qi, int16_t, int8_t, 8) +DEF_COND_MULH (cond_mulh, 1024, v1024qi, int16_t, int8_t, 8) +DEF_COND_MULH (cond_mulh, 2048, v2048qi, int16_t, int8_t, 8) + +DEF_COND_MULH (cond_mulh, 4, v4hi, int32_t, int16_t, 16) +DEF_COND_MULH (cond_mulh, 8, v8hi, int32_t, int16_t, 16) +DEF_COND_MULH (cond_mulh, 16, v16hi, int32_t, int16_t, 16) +DEF_COND_MULH (cond_mulh, 32, v32hi, int32_t, int16_t, 16) +DEF_COND_MULH (cond_mulh, 64, v64hi, int32_t, int16_t, 16) +DEF_COND_MULH (cond_mulh, 128, v128hi, int32_t, int16_t, 16) +DEF_COND_MULH (cond_mulh, 256, v256hi, int32_t, int16_t, 16) +DEF_COND_MULH (cond_mulh, 512, v512hi, int32_t, int16_t, 16) +DEF_COND_MULH (cond_mulh, 1024, v1024hi, int32_t, int16_t, 16) + +DEF_COND_MULH (cond_mulh, 4, v4si, int64_t, int32_t, 32) +DEF_COND_MULH (cond_mulh, 8, v8si, int64_t, int32_t, 32) +DEF_COND_MULH (cond_mulh, 16, v16si, int64_t, int32_t, 32) +DEF_COND_MULH (cond_mulh, 32, v32si, int64_t, int32_t, 32) +DEF_COND_MULH (cond_mulh, 64, v64si, int64_t, int32_t, 32) +DEF_COND_MULH (cond_mulh, 128, v128si, int64_t, int32_t, 32) +DEF_COND_MULH (cond_mulh, 256, v256si, int64_t, int32_t, 32) +DEF_COND_MULH (cond_mulh, 512, v512si, int64_t, int32_t, 32) + +DEF_COND_MULH (cond_mulh, 4, v4uqi, uint16_t, uint8_t, 8) +DEF_COND_MULH (cond_mulh, 8, v8uqi, uint16_t, uint8_t, 8) +DEF_COND_MULH (cond_mulh, 16, v16uqi, uint16_t, uint8_t, 8) +DEF_COND_MULH (cond_mulh, 32, v32uqi, uint16_t, uint8_t, 8) +DEF_COND_MULH (cond_mulh, 64, v64uqi, uint16_t, uint8_t, 8) +DEF_COND_MULH (cond_mulh, 128, v128uqi, uint16_t, uint8_t, 8) +DEF_COND_MULH (cond_mulh, 256, v256uqi, uint16_t, uint8_t, 8) +DEF_COND_MULH (cond_mulh, 512, v512uqi, uint16_t, uint8_t, 8) +DEF_COND_MULH (cond_mulh, 1024, v1024uqi, uint16_t, uint8_t, 8) +DEF_COND_MULH (cond_mulh, 2048, v2048uqi, uint16_t, uint8_t, 8) + +DEF_COND_MULH (cond_mulh, 4, v4uhi, uint32_t, uint16_t, 16) +DEF_COND_MULH (cond_mulh, 8, v8uhi, uint32_t, uint16_t, 16) +DEF_COND_MULH (cond_mulh, 16, v16uhi, uint32_t, uint16_t, 16) +DEF_COND_MULH (cond_mulh, 32, v32uhi, uint32_t, uint16_t, 16) +DEF_COND_MULH (cond_mulh, 64, v64uhi, uint32_t, uint16_t, 16) +DEF_COND_MULH (cond_mulh, 128, v128uhi, uint32_t, uint16_t, 16) +DEF_COND_MULH (cond_mulh, 256, v256uhi, uint32_t, uint16_t, 16) +DEF_COND_MULH (cond_mulh, 512, v512uhi, uint32_t, uint16_t, 16) +DEF_COND_MULH (cond_mulh, 1024, v1024uhi, uint32_t, uint16_t, 16) + +DEF_COND_MULH (cond_mulh, 4, v4usi, uint64_t, uint32_t, 32) +DEF_COND_MULH (cond_mulh, 8, v8usi, uint64_t, uint32_t, 32) +DEF_COND_MULH (cond_mulh, 16, v16usi, uint64_t, uint32_t, 32) +DEF_COND_MULH (cond_mulh, 32, v32usi, uint64_t, uint32_t, 32) +DEF_COND_MULH (cond_mulh, 64, v64usi, uint64_t, uint32_t, 32) +DEF_COND_MULH (cond_mulh, 128, v128usi, uint64_t, uint32_t, 32) +DEF_COND_MULH (cond_mulh, 256, v256usi, uint64_t, uint32_t, 32) +DEF_COND_MULH (cond_mulh, 512, v512usi, uint64_t, uint32_t, 32) + +/* { dg-final { scan-assembler-times {vmulhu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-1.c new file mode 100644 index 0000000..08f2285 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-1.c @@ -0,0 +1,61 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_NARROW_TRUNC_IMM (qi, hi, int8_t, 4) +DEF_COND_NARROW_TRUNC_IMM (qi, hi, int8_t, 8) +DEF_COND_NARROW_TRUNC_IMM (qi, hi, int8_t, 16) +DEF_COND_NARROW_TRUNC_IMM (qi, hi, int8_t, 32) +DEF_COND_NARROW_TRUNC_IMM (qi, hi, int8_t, 64) +DEF_COND_NARROW_TRUNC_IMM (qi, hi, int8_t, 128) +DEF_COND_NARROW_TRUNC_IMM (qi, hi, int8_t, 256) +DEF_COND_NARROW_TRUNC_IMM (qi, hi, int8_t, 512) +DEF_COND_NARROW_TRUNC_IMM (qi, hi, int8_t, 1024) + +DEF_COND_NARROW_TRUNC_IMM (hi, si, int16_t, 4) +DEF_COND_NARROW_TRUNC_IMM (hi, si, int16_t, 8) +DEF_COND_NARROW_TRUNC_IMM (hi, si, int16_t, 16) +DEF_COND_NARROW_TRUNC_IMM (hi, si, int16_t, 32) +DEF_COND_NARROW_TRUNC_IMM (hi, si, int16_t, 64) +DEF_COND_NARROW_TRUNC_IMM (hi, si, int16_t, 128) +DEF_COND_NARROW_TRUNC_IMM (hi, si, int16_t, 256) +DEF_COND_NARROW_TRUNC_IMM (hi, si, int16_t, 512) +DEF_COND_NARROW_TRUNC_IMM (hi, si, int16_t, 1024) + +DEF_COND_NARROW_TRUNC_IMM (uqi, uhi, uint8_t, 4) +DEF_COND_NARROW_TRUNC_IMM (uqi, uhi, uint8_t, 8) +DEF_COND_NARROW_TRUNC_IMM (uqi, uhi, uint8_t, 16) +DEF_COND_NARROW_TRUNC_IMM (uqi, uhi, uint8_t, 32) +DEF_COND_NARROW_TRUNC_IMM (uqi, uhi, uint8_t, 64) +DEF_COND_NARROW_TRUNC_IMM (uqi, uhi, uint8_t, 128) +DEF_COND_NARROW_TRUNC_IMM (uqi, uhi, uint8_t, 256) +DEF_COND_NARROW_TRUNC_IMM (uqi, uhi, uint8_t, 512) +DEF_COND_NARROW_TRUNC_IMM (uqi, uhi, uint8_t, 1024) + +DEF_COND_NARROW_TRUNC_IMM (uhi, usi, uint16_t, 4) +DEF_COND_NARROW_TRUNC_IMM (uhi, usi, uint16_t, 8) +DEF_COND_NARROW_TRUNC_IMM (uhi, usi, uint16_t, 16) +DEF_COND_NARROW_TRUNC_IMM (uhi, usi, uint16_t, 32) +DEF_COND_NARROW_TRUNC_IMM (uhi, usi, uint16_t, 64) +DEF_COND_NARROW_TRUNC_IMM (uhi, usi, uint16_t, 128) +DEF_COND_NARROW_TRUNC_IMM (uhi, usi, uint16_t, 256) +DEF_COND_NARROW_TRUNC_IMM (uhi, usi, uint16_t, 512) +DEF_COND_NARROW_TRUNC_IMM (uhi, usi, uint16_t, 1024) + +/* { dg-final { scan-assembler-times {vnsra\.wi\s+v[0-9]+,\s*v[0-9]+,\s*7,\s*v0.t} 18 } } */ +/* { dg-final { scan-assembler-times {vnsrl\.wi\s+v[0-9]+,\s*v[0-9]+,\s*7,\s*v0.t} 18 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-2.c new file mode 100644 index 0000000..41452e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-2.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_NARROW_TRUNC_XREG (hi, si, int16_t, 4) +DEF_COND_NARROW_TRUNC_XREG (hi, si, int16_t, 8) +DEF_COND_NARROW_TRUNC_XREG (hi, si, int16_t, 16) +DEF_COND_NARROW_TRUNC_XREG (hi, si, int16_t, 32) +DEF_COND_NARROW_TRUNC_XREG (hi, si, int16_t, 64) +DEF_COND_NARROW_TRUNC_XREG (hi, si, int16_t, 128) +DEF_COND_NARROW_TRUNC_XREG (hi, si, int16_t, 256) +DEF_COND_NARROW_TRUNC_XREG (hi, si, int16_t, 512) +DEF_COND_NARROW_TRUNC_XREG (hi, si, int16_t, 1024) + +DEF_COND_NARROW_TRUNC_XREG (uhi, usi, uint16_t, 4) +DEF_COND_NARROW_TRUNC_XREG (uhi, usi, uint16_t, 8) +DEF_COND_NARROW_TRUNC_XREG (uhi, usi, uint16_t, 16) +DEF_COND_NARROW_TRUNC_XREG (uhi, usi, uint16_t, 32) +DEF_COND_NARROW_TRUNC_XREG (uhi, usi, uint16_t, 64) +DEF_COND_NARROW_TRUNC_XREG (uhi, usi, uint16_t, 128) +DEF_COND_NARROW_TRUNC_XREG (uhi, usi, uint16_t, 256) +DEF_COND_NARROW_TRUNC_XREG (uhi, usi, uint16_t, 512) +DEF_COND_NARROW_TRUNC_XREG (uhi, usi, uint16_t, 1024) + +/* { dg-final { scan-assembler-times {vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 9 } } */ +/* { dg-final { scan-assembler-times {vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 9 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c new file mode 100644 index 0000000..ca94446 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_UNOP (cond_neg, 4, v4qi, -) +DEF_COND_UNOP (cond_neg, 8, v8qi, -) +DEF_COND_UNOP (cond_neg, 16, v16qi, -) +DEF_COND_UNOP (cond_neg, 32, v32qi, -) +DEF_COND_UNOP (cond_neg, 64, v64qi, -) +DEF_COND_UNOP (cond_neg, 128, v128qi, -) +DEF_COND_UNOP (cond_neg, 256, v256qi, -) +DEF_COND_UNOP (cond_neg, 512, v512qi, -) +DEF_COND_UNOP (cond_neg, 1024, v1024qi, -) +DEF_COND_UNOP (cond_neg, 2048, v2048qi, -) +DEF_COND_UNOP (cond_neg, 4096, v4096qi, -) + +DEF_COND_UNOP (cond_neg, 4, v4hi, -) +DEF_COND_UNOP (cond_neg, 8, v8hi, -) +DEF_COND_UNOP (cond_neg, 16, v16hi, -) +DEF_COND_UNOP (cond_neg, 32, v32hi, -) +DEF_COND_UNOP (cond_neg, 64, v64hi, -) +DEF_COND_UNOP (cond_neg, 128, v128hi, -) +DEF_COND_UNOP (cond_neg, 256, v256hi, -) +DEF_COND_UNOP (cond_neg, 512, v512hi, -) +DEF_COND_UNOP (cond_neg, 1024, v1024hi, -) +DEF_COND_UNOP (cond_neg, 2048, v2048hi, -) + +DEF_COND_UNOP (cond_neg, 4, v4si, -) +DEF_COND_UNOP (cond_neg, 8, v8si, -) +DEF_COND_UNOP (cond_neg, 16, v16si, -) +DEF_COND_UNOP (cond_neg, 32, v32si, -) +DEF_COND_UNOP (cond_neg, 64, v64si, -) +DEF_COND_UNOP (cond_neg, 128, v128si, -) +DEF_COND_UNOP (cond_neg, 256, v256si, -) +DEF_COND_UNOP (cond_neg, 512, v512si, -) +DEF_COND_UNOP (cond_neg, 1024, v1024si, -) + +DEF_COND_UNOP (cond_neg, 4, v4di, -) +DEF_COND_UNOP (cond_neg, 8, v8di, -) +DEF_COND_UNOP (cond_neg, 16, v16di, -) +DEF_COND_UNOP (cond_neg, 32, v32di, -) +DEF_COND_UNOP (cond_neg, 64, v64di, -) +DEF_COND_UNOP (cond_neg, 128, v128di, -) +DEF_COND_UNOP (cond_neg, 256, v256di, -) +DEF_COND_UNOP (cond_neg, 512, v512di, -) + +/* { dg-final { scan-assembler-times {vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 38 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c new file mode 100644 index 0000000..cf44c18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_UNOP (cond_neg, 4, v4hf, -) +DEF_COND_UNOP (cond_neg, 8, v8hf, -) +DEF_COND_UNOP (cond_neg, 16, v16hf, -) +DEF_COND_UNOP (cond_neg, 32, v32hf, -) +DEF_COND_UNOP (cond_neg, 64, v64hf, -) +DEF_COND_UNOP (cond_neg, 128, v128hf, -) +DEF_COND_UNOP (cond_neg, 256, v256hf, -) +DEF_COND_UNOP (cond_neg, 512, v512hf, -) +DEF_COND_UNOP (cond_neg, 1024, v1024hf, -) +DEF_COND_UNOP (cond_neg, 2048, v2048hf, -) + +DEF_COND_UNOP (cond_neg, 4, v4sf, -) +DEF_COND_UNOP (cond_neg, 8, v8sf, -) +DEF_COND_UNOP (cond_neg, 16, v16sf, -) +DEF_COND_UNOP (cond_neg, 32, v32sf, -) +DEF_COND_UNOP (cond_neg, 64, v64sf, -) +DEF_COND_UNOP (cond_neg, 128, v128sf, -) +DEF_COND_UNOP (cond_neg, 256, v256sf, -) +DEF_COND_UNOP (cond_neg, 512, v512sf, -) +DEF_COND_UNOP (cond_neg, 1024, v1024sf, -) + +DEF_COND_UNOP (cond_neg, 4, v4df, -) +DEF_COND_UNOP (cond_neg, 8, v8df, -) +DEF_COND_UNOP (cond_neg, 16, v16df, -) +DEF_COND_UNOP (cond_neg, 32, v32df, -) +DEF_COND_UNOP (cond_neg, 64, v64df, -) +DEF_COND_UNOP (cond_neg, 128, v128df, -) +DEF_COND_UNOP (cond_neg, 256, v256df, -) +DEF_COND_UNOP (cond_neg, 512, v512df, -) + +/* { dg-final { scan-assembler-times {vfneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c new file mode 100644 index 0000000..1a2a8f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_UNOP (cond_not, 4, v4qi, ~) +DEF_COND_UNOP (cond_not, 8, v8qi, ~) +DEF_COND_UNOP (cond_not, 16, v16qi, ~) +DEF_COND_UNOP (cond_not, 32, v32qi, ~) +DEF_COND_UNOP (cond_not, 64, v64qi, ~) +DEF_COND_UNOP (cond_not, 128, v128qi, ~) +DEF_COND_UNOP (cond_not, 256, v256qi, ~) +DEF_COND_UNOP (cond_not, 512, v512qi, ~) +DEF_COND_UNOP (cond_not, 1024, v1024qi, ~) +DEF_COND_UNOP (cond_not, 2048, v2048qi, ~) +DEF_COND_UNOP (cond_not, 4096, v4096qi, ~) + +DEF_COND_UNOP (cond_not, 4, v4hi, ~) +DEF_COND_UNOP (cond_not, 8, v8hi, ~) +DEF_COND_UNOP (cond_not, 16, v16hi, ~) +DEF_COND_UNOP (cond_not, 32, v32hi, ~) +DEF_COND_UNOP (cond_not, 64, v64hi, ~) +DEF_COND_UNOP (cond_not, 128, v128hi, ~) +DEF_COND_UNOP (cond_not, 256, v256hi, ~) +DEF_COND_UNOP (cond_not, 512, v512hi, ~) +DEF_COND_UNOP (cond_not, 1024, v1024hi, ~) +DEF_COND_UNOP (cond_not, 2048, v2048hi, ~) + +DEF_COND_UNOP (cond_not, 4, v4si, ~) +DEF_COND_UNOP (cond_not, 8, v8si, ~) +DEF_COND_UNOP (cond_not, 16, v16si, ~) +DEF_COND_UNOP (cond_not, 32, v32si, ~) +DEF_COND_UNOP (cond_not, 64, v64si, ~) +DEF_COND_UNOP (cond_not, 128, v128si, ~) +DEF_COND_UNOP (cond_not, 256, v256si, ~) +DEF_COND_UNOP (cond_not, 512, v512si, ~) +DEF_COND_UNOP (cond_not, 1024, v1024si, ~) + +DEF_COND_UNOP (cond_not, 4, v4di, ~) +DEF_COND_UNOP (cond_not, 8, v8di, ~) +DEF_COND_UNOP (cond_not, 16, v16di, ~) +DEF_COND_UNOP (cond_not, 32, v32di, ~) +DEF_COND_UNOP (cond_not, 64, v64di, ~) +DEF_COND_UNOP (cond_not, 128, v128di, ~) +DEF_COND_UNOP (cond_not, 256, v256di, ~) +DEF_COND_UNOP (cond_not, 512, v512di, ~) + +/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 38 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c new file mode 100644 index 0000000..3ac6203 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c @@ -0,0 +1,57 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_shift, 4, v4si, >>) +DEF_COND_BINOP (cond_shift, 8, v8si, >>) +DEF_COND_BINOP (cond_shift, 16, v16si, >>) +DEF_COND_BINOP (cond_shift, 32, v32si, >>) +DEF_COND_BINOP (cond_shift, 64, v64si, >>) +DEF_COND_BINOP (cond_shift, 128, v128si, >>) +DEF_COND_BINOP (cond_shift, 256, v256si, >>) +DEF_COND_BINOP (cond_shift, 512, v512si, >>) +DEF_COND_BINOP (cond_shift, 1024, v1024si, >>) + +DEF_COND_BINOP (cond_shift, 4, v4di, >>) +DEF_COND_BINOP (cond_shift, 8, v8di, >>) +DEF_COND_BINOP (cond_shift, 16, v16di, >>) +DEF_COND_BINOP (cond_shift, 32, v32di, >>) +DEF_COND_BINOP (cond_shift, 64, v64di, >>) +DEF_COND_BINOP (cond_shift, 128, v128di, >>) +DEF_COND_BINOP (cond_shift, 256, v256di, >>) + +DEF_COND_BINOP (cond_shift, 4, v4usi, >>) +DEF_COND_BINOP (cond_shift, 8, v8usi, >>) +DEF_COND_BINOP (cond_shift, 16, v16usi, >>) +DEF_COND_BINOP (cond_shift, 32, v32usi, >>) +DEF_COND_BINOP (cond_shift, 64, v64usi, >>) +DEF_COND_BINOP (cond_shift, 128, v128usi, >>) +DEF_COND_BINOP (cond_shift, 256, v256usi, >>) +DEF_COND_BINOP (cond_shift, 512, v512usi, >>) +DEF_COND_BINOP (cond_shift, 1024, v1024usi, >>) + +DEF_COND_BINOP (cond_shift, 4, v4udi, >>) +DEF_COND_BINOP (cond_shift, 8, v8udi, >>) +DEF_COND_BINOP (cond_shift, 16, v16udi, >>) +DEF_COND_BINOP (cond_shift, 32, v32udi, >>) +DEF_COND_BINOP (cond_shift, 64, v64udi, >>) +DEF_COND_BINOP (cond_shift, 128, v128udi, >>) +DEF_COND_BINOP (cond_shift, 256, v256udi, >>) + +/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 16 } } */ +/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 16 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c new file mode 100644 index 0000000..8c2fa47 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_shift, 4, v4si, <<) +DEF_COND_BINOP (cond_shift, 8, v8si, <<) +DEF_COND_BINOP (cond_shift, 16, v16si, <<) +DEF_COND_BINOP (cond_shift, 32, v32si, <<) +DEF_COND_BINOP (cond_shift, 64, v64si, <<) +DEF_COND_BINOP (cond_shift, 128, v128si, <<) +DEF_COND_BINOP (cond_shift, 256, v256si, <<) +DEF_COND_BINOP (cond_shift, 512, v512si, <<) +DEF_COND_BINOP (cond_shift, 1024, v1024si, <<) + +DEF_COND_BINOP (cond_shift, 4, v4di, <<) +DEF_COND_BINOP (cond_shift, 8, v8di, <<) +DEF_COND_BINOP (cond_shift, 16, v16di, <<) +DEF_COND_BINOP (cond_shift, 32, v32di, <<) +DEF_COND_BINOP (cond_shift, 64, v64di, <<) +DEF_COND_BINOP (cond_shift, 128, v128di, <<) +DEF_COND_BINOP (cond_shift, 256, v256di, <<) + +DEF_COND_BINOP (cond_shift, 4, v4usi, <<) +DEF_COND_BINOP (cond_shift, 8, v8usi, <<) +DEF_COND_BINOP (cond_shift, 16, v16usi, <<) +DEF_COND_BINOP (cond_shift, 32, v32usi, <<) +DEF_COND_BINOP (cond_shift, 64, v64usi, <<) +DEF_COND_BINOP (cond_shift, 128, v128usi, <<) +DEF_COND_BINOP (cond_shift, 256, v256usi, <<) +DEF_COND_BINOP (cond_shift, 512, v512usi, <<) +DEF_COND_BINOP (cond_shift, 1024, v1024usi, <<) + +DEF_COND_BINOP (cond_shift, 4, v4udi, <<) +DEF_COND_BINOP (cond_shift, 8, v8udi, <<) +DEF_COND_BINOP (cond_shift, 16, v16udi, <<) +DEF_COND_BINOP (cond_shift, 32, v32udi, <<) +DEF_COND_BINOP (cond_shift, 64, v64udi, <<) +DEF_COND_BINOP (cond_shift, 128, v128udi, <<) +DEF_COND_BINOP (cond_shift, 256, v256udi, <<) + +/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 32 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c new file mode 100644 index 0000000..1c1c2ab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_UNOP (cond_abs, 4, v4hf, __builtin_sqrtf16) +DEF_COND_UNOP (cond_abs, 8, v8hf, __builtin_sqrtf16) +DEF_COND_UNOP (cond_abs, 16, v16hf, __builtin_sqrtf16) +DEF_COND_UNOP (cond_abs, 32, v32hf, __builtin_sqrtf16) +DEF_COND_UNOP (cond_abs, 64, v64hf, __builtin_sqrtf16) +DEF_COND_UNOP (cond_abs, 128, v128hf, __builtin_sqrtf16) +DEF_COND_UNOP (cond_abs, 256, v256hf, __builtin_sqrtf16) +DEF_COND_UNOP (cond_abs, 512, v512hf, __builtin_sqrtf16) +DEF_COND_UNOP (cond_abs, 1024, v1024hf, __builtin_sqrtf16) +DEF_COND_UNOP (cond_abs, 2048, v2048hf, __builtin_sqrtf16) + +DEF_COND_UNOP (cond_abs, 4, v4sf, __builtin_sqrtf) +DEF_COND_UNOP (cond_abs, 8, v8sf, __builtin_sqrtf) +DEF_COND_UNOP (cond_abs, 16, v16sf, __builtin_sqrtf) +DEF_COND_UNOP (cond_abs, 32, v32sf, __builtin_sqrtf) +DEF_COND_UNOP (cond_abs, 64, v64sf, __builtin_sqrtf) +DEF_COND_UNOP (cond_abs, 128, v128sf, __builtin_sqrtf) +DEF_COND_UNOP (cond_abs, 256, v256sf, __builtin_sqrtf) +DEF_COND_UNOP (cond_abs, 512, v512sf, __builtin_sqrtf) +DEF_COND_UNOP (cond_abs, 1024, v1024sf, __builtin_sqrtf) + +DEF_COND_UNOP (cond_abs, 4, v4df, __builtin_sqrt) +DEF_COND_UNOP (cond_abs, 8, v8df, __builtin_sqrt) +DEF_COND_UNOP (cond_abs, 16, v16df, __builtin_sqrt) +DEF_COND_UNOP (cond_abs, 32, v32df, __builtin_sqrt) +DEF_COND_UNOP (cond_abs, 64, v64df, __builtin_sqrt) +DEF_COND_UNOP (cond_abs, 128, v128df, __builtin_sqrt) +DEF_COND_UNOP (cond_abs, 256, v256df, __builtin_sqrt) +DEF_COND_UNOP (cond_abs, 512, v512df, __builtin_sqrt) + +/* { dg-final { scan-assembler-times {vfsqrt\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c new file mode 100644 index 0000000..629e66c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_sub, 4, v4qi, -) +DEF_COND_BINOP (cond_sub, 8, v8qi, -) +DEF_COND_BINOP (cond_sub, 16, v16qi, -) +DEF_COND_BINOP (cond_sub, 32, v32qi, -) +DEF_COND_BINOP (cond_sub, 64, v64qi, -) +DEF_COND_BINOP (cond_sub, 128, v128qi, -) +DEF_COND_BINOP (cond_sub, 256, v256qi, -) +DEF_COND_BINOP (cond_sub, 512, v512qi, -) +DEF_COND_BINOP (cond_sub, 1024, v1024qi, -) +DEF_COND_BINOP (cond_sub, 2048, v2048qi, -) +DEF_COND_BINOP (cond_sub, 4096, v4096qi, -) + +DEF_COND_BINOP (cond_sub, 4, v4hi, -) +DEF_COND_BINOP (cond_sub, 8, v8hi, -) +DEF_COND_BINOP (cond_sub, 16, v16hi, -) +DEF_COND_BINOP (cond_sub, 32, v32hi, -) +DEF_COND_BINOP (cond_sub, 64, v64hi, -) +DEF_COND_BINOP (cond_sub, 128, v128hi, -) +DEF_COND_BINOP (cond_sub, 256, v256hi, -) +DEF_COND_BINOP (cond_sub, 512, v512hi, -) +DEF_COND_BINOP (cond_sub, 1024, v1024hi, -) +DEF_COND_BINOP (cond_sub, 2048, v2048hi, -) + +DEF_COND_BINOP (cond_sub, 4, v4si, -) +DEF_COND_BINOP (cond_sub, 8, v8si, -) +DEF_COND_BINOP (cond_sub, 16, v16si, -) +DEF_COND_BINOP (cond_sub, 32, v32si, -) +DEF_COND_BINOP (cond_sub, 64, v64si, -) +DEF_COND_BINOP (cond_sub, 128, v128si, -) +DEF_COND_BINOP (cond_sub, 256, v256si, -) +DEF_COND_BINOP (cond_sub, 512, v512si, -) +DEF_COND_BINOP (cond_sub, 1024, v1024si, -) + +DEF_COND_BINOP (cond_sub, 4, v4di, -) +DEF_COND_BINOP (cond_sub, 8, v8di, -) +DEF_COND_BINOP (cond_sub, 16, v16di, -) +DEF_COND_BINOP (cond_sub, 32, v32di, -) +DEF_COND_BINOP (cond_sub, 64, v64di, -) +DEF_COND_BINOP (cond_sub, 128, v128di, -) +DEF_COND_BINOP (cond_sub, 256, v256di, -) +DEF_COND_BINOP (cond_sub, 512, v512di, -) + +DEF_COND_BINOP (cond_sub, 4, v4uqi, -) +DEF_COND_BINOP (cond_sub, 8, v8uqi, -) +DEF_COND_BINOP (cond_sub, 16, v16uqi, -) +DEF_COND_BINOP (cond_sub, 32, v32uqi, -) +DEF_COND_BINOP (cond_sub, 64, v64uqi, -) +DEF_COND_BINOP (cond_sub, 128, v128uqi, -) +DEF_COND_BINOP (cond_sub, 256, v256uqi, -) +DEF_COND_BINOP (cond_sub, 512, v512uqi, -) +DEF_COND_BINOP (cond_sub, 1024, v1024uqi, -) +DEF_COND_BINOP (cond_sub, 2048, v2048uqi, -) +DEF_COND_BINOP (cond_sub, 4096, v4096uqi, -) + +DEF_COND_BINOP (cond_sub, 4, v4uhi, -) +DEF_COND_BINOP (cond_sub, 8, v8uhi, -) +DEF_COND_BINOP (cond_sub, 16, v16uhi, -) +DEF_COND_BINOP (cond_sub, 32, v32uhi, -) +DEF_COND_BINOP (cond_sub, 64, v64uhi, -) +DEF_COND_BINOP (cond_sub, 128, v128uhi, -) +DEF_COND_BINOP (cond_sub, 256, v256uhi, -) +DEF_COND_BINOP (cond_sub, 512, v512uhi, -) +DEF_COND_BINOP (cond_sub, 1024, v1024uhi, -) +DEF_COND_BINOP (cond_sub, 2048, v2048uhi, -) + +DEF_COND_BINOP (cond_sub, 4, v4usi, -) +DEF_COND_BINOP (cond_sub, 8, v8usi, -) +DEF_COND_BINOP (cond_sub, 16, v16usi, -) +DEF_COND_BINOP (cond_sub, 32, v32usi, -) +DEF_COND_BINOP (cond_sub, 64, v64usi, -) +DEF_COND_BINOP (cond_sub, 128, v128usi, -) +DEF_COND_BINOP (cond_sub, 256, v256usi, -) +DEF_COND_BINOP (cond_sub, 512, v512usi, -) +DEF_COND_BINOP (cond_sub, 1024, v1024usi, -) + +DEF_COND_BINOP (cond_sub, 4, v4udi, -) +DEF_COND_BINOP (cond_sub, 8, v8udi, -) +DEF_COND_BINOP (cond_sub, 16, v16udi, -) +DEF_COND_BINOP (cond_sub, 32, v32udi, -) +DEF_COND_BINOP (cond_sub, 64, v64udi, -) +DEF_COND_BINOP (cond_sub, 128, v128udi, -) +DEF_COND_BINOP (cond_sub, 256, v256udi, -) +DEF_COND_BINOP (cond_sub, 512, v512udi, -) + +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c new file mode 100644 index 0000000..385ab41 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_sub, 4, v4hf, -) +DEF_COND_BINOP (cond_sub, 8, v8hf, -) +DEF_COND_BINOP (cond_sub, 16, v16hf, -) +DEF_COND_BINOP (cond_sub, 32, v32hf, -) +DEF_COND_BINOP (cond_sub, 64, v64hf, -) +DEF_COND_BINOP (cond_sub, 128, v128hf, -) +DEF_COND_BINOP (cond_sub, 256, v256hf, -) +DEF_COND_BINOP (cond_sub, 512, v512hf, -) +DEF_COND_BINOP (cond_sub, 1024, v1024hf, -) +DEF_COND_BINOP (cond_sub, 2048, v2048hf, -) + +DEF_COND_BINOP (cond_sub, 4, v4sf, -) +DEF_COND_BINOP (cond_sub, 8, v8sf, -) +DEF_COND_BINOP (cond_sub, 16, v16sf, -) +DEF_COND_BINOP (cond_sub, 32, v32sf, -) +DEF_COND_BINOP (cond_sub, 64, v64sf, -) +DEF_COND_BINOP (cond_sub, 128, v128sf, -) +DEF_COND_BINOP (cond_sub, 256, v256sf, -) +DEF_COND_BINOP (cond_sub, 512, v512sf, -) +DEF_COND_BINOP (cond_sub, 1024, v1024sf, -) + +DEF_COND_BINOP (cond_sub, 4, v4df, -) +DEF_COND_BINOP (cond_sub, 8, v8df, -) +DEF_COND_BINOP (cond_sub, 16, v16df, -) +DEF_COND_BINOP (cond_sub, 32, v32df, -) +DEF_COND_BINOP (cond_sub, 64, v64df, -) +DEF_COND_BINOP (cond_sub, 128, v128df, -) +DEF_COND_BINOP (cond_sub, 256, v256df, -) +DEF_COND_BINOP (cond_sub, 512, v512df, -) + +/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c new file mode 100644 index 0000000..f548856a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c @@ -0,0 +1,72 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_CONVERT (trunc, v4hi, v4qi, 4) +DEF_COND_CONVERT (trunc, v16hi, v16qi, 16) +DEF_COND_CONVERT (trunc, v32hi, v32qi, 32) +DEF_COND_CONVERT (trunc, v64hi, v64qi, 64) +DEF_COND_CONVERT (trunc, v128hi, v128qi, 128) +DEF_COND_CONVERT (trunc, v256hi, v256qi, 256) +DEF_COND_CONVERT (trunc, v512hi, v512qi, 512) +DEF_COND_CONVERT (trunc, v1024hi, v1024qi, 1024) + +DEF_COND_CONVERT (trunc, v4si, v4hi, 4) +DEF_COND_CONVERT (trunc, v16si, v16hi, 16) +DEF_COND_CONVERT (trunc, v32si, v32hi, 32) +DEF_COND_CONVERT (trunc, v64si, v64hi, 64) +DEF_COND_CONVERT (trunc, v128si, v128hi, 128) +DEF_COND_CONVERT (trunc, v256si, v256hi, 256) +DEF_COND_CONVERT (trunc, v512si, v512hi, 512) +DEF_COND_CONVERT (trunc, v1024si, v1024hi, 1024) + +DEF_COND_CONVERT (trunc, v4di, v4si, 4) +DEF_COND_CONVERT (trunc, v16di, v16si, 16) +DEF_COND_CONVERT (trunc, v32di, v32si, 32) +DEF_COND_CONVERT (trunc, v64di, v64si, 64) +DEF_COND_CONVERT (trunc, v128di, v128si, 128) +DEF_COND_CONVERT (trunc, v256di, v256si, 256) +DEF_COND_CONVERT (trunc, v512di, v512si, 512) + +DEF_COND_CONVERT (trunc, v4uhi, v4uqi, 4) +DEF_COND_CONVERT (trunc, v16uhi, v16uqi, 16) +DEF_COND_CONVERT (trunc, v32uhi, v32uqi, 32) +DEF_COND_CONVERT (trunc, v64uhi, v64uqi, 64) +DEF_COND_CONVERT (trunc, v128uhi, v128uqi,128) +DEF_COND_CONVERT (trunc, v256uhi, v256uqi,256) +DEF_COND_CONVERT (trunc, v512uhi, v512uqi,512) +DEF_COND_CONVERT (trunc, v1024uhi, v1024uqi, 1024) + +DEF_COND_CONVERT (trunc, v4usi, v4uhi, 4) +DEF_COND_CONVERT (trunc, v16usi, v16uhi, 16) +DEF_COND_CONVERT (trunc, v32usi, v32uhi, 32) +DEF_COND_CONVERT (trunc, v64usi, v64uhi, 64) +DEF_COND_CONVERT (trunc, v128usi, v128uhi, 128) +DEF_COND_CONVERT (trunc, v256usi, v256uhi, 256) +DEF_COND_CONVERT (trunc, v512usi, v512uhi, 512) +DEF_COND_CONVERT (trunc, v1024usi, v1024uhi, 1024) + +DEF_COND_CONVERT (trunc, v4udi, v4usi, 4) +DEF_COND_CONVERT (trunc, v16udi, v16usi, 16) +DEF_COND_CONVERT (trunc, v32udi, v32usi, 32) +DEF_COND_CONVERT (trunc, v64udi, v64usi, 64) +DEF_COND_CONVERT (trunc, v128udi, v128usi, 128) +DEF_COND_CONVERT (trunc, v256udi, v256usi, 256) +DEF_COND_CONVERT (trunc, v512udi, v512usi, 512) + +/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 46 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c new file mode 100644 index 0000000..5d38c77 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c @@ -0,0 +1,54 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_CONVERT (trunc, v4si, v4qi, 4) +DEF_COND_CONVERT (trunc, v16si, v16qi, 16) +DEF_COND_CONVERT (trunc, v32si, v32qi, 32) +DEF_COND_CONVERT (trunc, v64si, v64qi, 64) +DEF_COND_CONVERT (trunc, v128si, v128qi, 128) +DEF_COND_CONVERT (trunc, v256si, v256qi, 256) +DEF_COND_CONVERT (trunc, v512si, v512qi, 512) +DEF_COND_CONVERT (trunc, v1024si, v1024qi, 1024) + +DEF_COND_CONVERT (trunc, v4di, v4hi, 4) +DEF_COND_CONVERT (trunc, v16di, v16hi, 16) +DEF_COND_CONVERT (trunc, v32di, v32hi, 32) +DEF_COND_CONVERT (trunc, v64di, v64hi, 64) +DEF_COND_CONVERT (trunc, v128di, v128hi, 128) +DEF_COND_CONVERT (trunc, v256di, v256hi, 256) +DEF_COND_CONVERT (trunc, v512di, v512hi, 512) + +DEF_COND_CONVERT (trunc, v4usi, v4uqi, 4) +DEF_COND_CONVERT (trunc, v16usi, v16uqi, 16) +DEF_COND_CONVERT (trunc, v32usi, v32uqi, 32) +DEF_COND_CONVERT (trunc, v64usi, v64uqi, 64) +DEF_COND_CONVERT (trunc, v128usi, v128uqi, 128) +DEF_COND_CONVERT (trunc, v256usi, v256uqi, 256) +DEF_COND_CONVERT (trunc, v512usi, v512uqi, 512) +DEF_COND_CONVERT (trunc, v1024usi, v1024uqi, 1024) + +DEF_COND_CONVERT (trunc, v4udi, v4uhi, 4) +DEF_COND_CONVERT (trunc, v16udi, v16uhi, 16) +DEF_COND_CONVERT (trunc, v32udi, v32uhi, 32) +DEF_COND_CONVERT (trunc, v64udi, v64uhi, 64) +DEF_COND_CONVERT (trunc, v128udi, v128uhi, 128) +DEF_COND_CONVERT (trunc, v256udi, v256uhi, 256) +DEF_COND_CONVERT (trunc, v512udi, v512uhi, 512) + +/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c new file mode 100644 index 0000000..7596733 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_CONVERT (trunc, v4di, v4qi, 4) +DEF_COND_CONVERT (trunc, v16di, v16qi, 16) +DEF_COND_CONVERT (trunc, v32di, v32qi, 32) +DEF_COND_CONVERT (trunc, v64di, v64qi, 64) +DEF_COND_CONVERT (trunc, v128di, v128qi, 128) +DEF_COND_CONVERT (trunc, v256di, v256qi, 256) +DEF_COND_CONVERT (trunc, v512di, v512qi, 512) + +DEF_COND_CONVERT (trunc, v4udi, v4uqi, 4) +DEF_COND_CONVERT (trunc, v16udi, v16uqi, 16) +DEF_COND_CONVERT (trunc, v32udi, v32uqi, 32) +DEF_COND_CONVERT (trunc, v64udi, v64uqi, 64) +DEF_COND_CONVERT (trunc, v128udi, v128uqi, 128) +DEF_COND_CONVERT (trunc, v256udi, v256uqi, 256) +DEF_COND_CONVERT (trunc, v512udi, v512uqi, 512) + +/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 14 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-4.c new file mode 100644 index 0000000..867de13 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-4.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_CONVERT (trunc, v4sf, v4hf, 4) +DEF_COND_CONVERT (trunc, v16sf, v16hf, 16) +DEF_COND_CONVERT (trunc, v32sf, v32hf, 32) +DEF_COND_CONVERT (trunc, v64sf, v64hf, 64) +DEF_COND_CONVERT (trunc, v128sf, v128hf, 128) +DEF_COND_CONVERT (trunc, v256sf, v256hf, 256) +DEF_COND_CONVERT (trunc, v512sf, v512hf, 512) +DEF_COND_CONVERT (trunc, v1024sf, v1024hf, 1024) + +DEF_COND_CONVERT (trunc, v4df, v4sf, 4) +DEF_COND_CONVERT (trunc, v16df, v16sf, 16) +DEF_COND_CONVERT (trunc, v32df, v32sf, 32) +DEF_COND_CONVERT (trunc, v64df, v64sf, 64) +DEF_COND_CONVERT (trunc, v128df, v128sf, 128) +DEF_COND_CONVERT (trunc, v256df, v256sf, 256) +DEF_COND_CONVERT (trunc, v512df, v512sf, 512) + +/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 15 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-5.c new file mode 100644 index 0000000..12ca119 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-5.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_CONVERT (trunc, v4df, v4hf, 4) +DEF_COND_CONVERT (trunc, v16df, v16hf, 16) +DEF_COND_CONVERT (trunc, v32df, v32hf, 32) +DEF_COND_CONVERT (trunc, v64df, v64hf, 64) +DEF_COND_CONVERT (trunc, v128df, v128hf, 128) +DEF_COND_CONVERT (trunc, v256df, v256hf, 256) +DEF_COND_CONVERT (trunc, v512df, v512hf, 512) + +/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 7 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c new file mode 100644 index 0000000..ccaaf31 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c @@ -0,0 +1,79 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_OP_WVV (cond_wadd, 4, qi, hi, int16_t, +) +DEF_COND_OP_WVV (cond_wadd, 8, qi, hi, int16_t, +) +DEF_COND_OP_WVV (cond_wadd, 16, qi, hi, int16_t, +) +DEF_COND_OP_WVV (cond_wadd, 32, qi, hi, int16_t, +) +DEF_COND_OP_WVV (cond_wadd, 64, qi, hi, int16_t, +) +DEF_COND_OP_WVV (cond_wadd, 128, qi, hi, int16_t, +) +DEF_COND_OP_WVV (cond_wadd, 256, qi, hi, int16_t, +) +DEF_COND_OP_WVV (cond_wadd, 512, qi, hi, int16_t, +) +DEF_COND_OP_WVV (cond_wadd, 1024, qi, hi, int16_t, +) + +DEF_COND_OP_WVV (cond_wadd, 4, hi, si, int32_t, +) +DEF_COND_OP_WVV (cond_wadd, 8, hi, si, int32_t, +) +DEF_COND_OP_WVV (cond_wadd, 16, hi, si, int32_t, +) +DEF_COND_OP_WVV (cond_wadd, 32, hi, si, int32_t, +) +DEF_COND_OP_WVV (cond_wadd, 64, hi, si, int32_t, +) +DEF_COND_OP_WVV (cond_wadd, 128, hi, si, int32_t, +) +DEF_COND_OP_WVV (cond_wadd, 256, hi, si, int32_t, +) +DEF_COND_OP_WVV (cond_wadd, 512, hi, si, int32_t, +) +DEF_COND_OP_WVV (cond_wadd, 1024, hi, si, int32_t, +) + +DEF_COND_OP_WVV (cond_wadd, 4, si, di, int64_t, +) +DEF_COND_OP_WVV (cond_wadd, 8, si, di, int64_t, +) +DEF_COND_OP_WVV (cond_wadd, 16, si, di, int64_t, +) +DEF_COND_OP_WVV (cond_wadd, 32, si, di, int64_t, +) +DEF_COND_OP_WVV (cond_wadd, 64, si, di, int64_t, +) +DEF_COND_OP_WVV (cond_wadd, 128, si, di, int64_t, +) +DEF_COND_OP_WVV (cond_wadd, 256, si, di, int64_t, +) +DEF_COND_OP_WVV (cond_wadd, 512, si, di, int64_t, +) + +DEF_COND_OP_WVV (cond_wadd, 4, uqi, uhi, uint16_t, +) +DEF_COND_OP_WVV (cond_wadd, 8, uqi, uhi, uint16_t, +) +DEF_COND_OP_WVV (cond_wadd, 16, uqi, uhi, uint16_t, +) +DEF_COND_OP_WVV (cond_wadd, 32, uqi, uhi, uint16_t, +) +DEF_COND_OP_WVV (cond_wadd, 64, uqi, uhi, uint16_t, +) +DEF_COND_OP_WVV (cond_wadd, 128, uqi, uhi, uint16_t, +) +DEF_COND_OP_WVV (cond_wadd, 256, uqi, uhi, uint16_t, +) +DEF_COND_OP_WVV (cond_wadd, 512, uqi, uhi, uint16_t, +) +DEF_COND_OP_WVV (cond_wadd, 1024, uqi, uhi, uint16_t, +) + +DEF_COND_OP_WVV (cond_wadd, 4, uhi, usi, uint32_t, +) +DEF_COND_OP_WVV (cond_wadd, 8, uhi, usi, uint32_t, +) +DEF_COND_OP_WVV (cond_wadd, 16, uhi, usi, uint32_t, +) +DEF_COND_OP_WVV (cond_wadd, 32, uhi, usi, uint32_t, +) +DEF_COND_OP_WVV (cond_wadd, 64, uhi, usi, uint32_t, +) +DEF_COND_OP_WVV (cond_wadd, 128, uhi, usi, uint32_t, +) +DEF_COND_OP_WVV (cond_wadd, 256, uhi, usi, uint32_t, +) +DEF_COND_OP_WVV (cond_wadd, 512, uhi, usi, uint32_t, +) +DEF_COND_OP_WVV (cond_wadd, 1024, uhi, usi, uint32_t, +) + +DEF_COND_OP_WVV (cond_wadd, 4, usi, udi, uint64_t, +) +DEF_COND_OP_WVV (cond_wadd, 8, usi, udi, uint64_t, +) +DEF_COND_OP_WVV (cond_wadd, 16, usi, udi, uint64_t, +) +DEF_COND_OP_WVV (cond_wadd, 32, usi, udi, uint64_t, +) +DEF_COND_OP_WVV (cond_wadd, 64, usi, udi, uint64_t, +) +DEF_COND_OP_WVV (cond_wadd, 128, usi, udi, uint64_t, +) +DEF_COND_OP_WVV (cond_wadd, 256, usi, udi, uint64_t, +) +DEF_COND_OP_WVV (cond_wadd, 512, usi, udi, uint64_t, +) + +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */ +/* { dg-final { scan-assembler-times {vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c new file mode 100644 index 0000000..d2a67c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_OP_WVV (cond_wadd, 4, hf, sf, float, +) +DEF_COND_OP_WVV (cond_wadd, 8, hf, sf, float, +) +DEF_COND_OP_WVV (cond_wadd, 16, hf, sf, float, +) +DEF_COND_OP_WVV (cond_wadd, 32, hf, sf, float, +) +DEF_COND_OP_WVV (cond_wadd, 64, hf, sf, float, +) +DEF_COND_OP_WVV (cond_wadd, 128, hf, sf, float, +) +DEF_COND_OP_WVV (cond_wadd, 256, hf, sf, float, +) +DEF_COND_OP_WVV (cond_wadd, 512, hf, sf, float, +) +DEF_COND_OP_WVV (cond_wadd, 1024, hf, sf, float, +) + +DEF_COND_OP_WVV (cond_wadd, 4, sf, df, double, +) +DEF_COND_OP_WVV (cond_wadd, 8, sf, df, double, +) +DEF_COND_OP_WVV (cond_wadd, 16, sf, df, double, +) +DEF_COND_OP_WVV (cond_wadd, 32, sf, df, double, +) +DEF_COND_OP_WVV (cond_wadd, 64, sf, df, double, +) +DEF_COND_OP_WVV (cond_wadd, 128, sf, df, double, +) +DEF_COND_OP_WVV (cond_wadd, 256, sf, df, double, +) +DEF_COND_OP_WVV (cond_wadd, 512, sf, df, double, +) + +/* { dg-final { scan-assembler-times {vfwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c new file mode 100644 index 0000000..6ae95f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c @@ -0,0 +1,79 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_OP_WWV (cond_wadd, 4, qi, hi, int16_t, +) +DEF_COND_OP_WWV (cond_wadd, 8, qi, hi, int16_t, +) +DEF_COND_OP_WWV (cond_wadd, 16, qi, hi, int16_t, +) +DEF_COND_OP_WWV (cond_wadd, 32, qi, hi, int16_t, +) +DEF_COND_OP_WWV (cond_wadd, 64, qi, hi, int16_t, +) +DEF_COND_OP_WWV (cond_wadd, 128, qi, hi, int16_t, +) +DEF_COND_OP_WWV (cond_wadd, 256, qi, hi, int16_t, +) +DEF_COND_OP_WWV (cond_wadd, 512, qi, hi, int16_t, +) +DEF_COND_OP_WWV (cond_wadd, 1024, qi, hi, int16_t, +) + +DEF_COND_OP_WWV (cond_wadd, 4, hi, si, int32_t, +) +DEF_COND_OP_WWV (cond_wadd, 8, hi, si, int32_t, +) +DEF_COND_OP_WWV (cond_wadd, 16, hi, si, int32_t, +) +DEF_COND_OP_WWV (cond_wadd, 32, hi, si, int32_t, +) +DEF_COND_OP_WWV (cond_wadd, 64, hi, si, int32_t, +) +DEF_COND_OP_WWV (cond_wadd, 128, hi, si, int32_t, +) +DEF_COND_OP_WWV (cond_wadd, 256, hi, si, int32_t, +) +DEF_COND_OP_WWV (cond_wadd, 512, hi, si, int32_t, +) +DEF_COND_OP_WWV (cond_wadd, 1024, hi, si, int32_t, +) + +DEF_COND_OP_WWV (cond_wadd, 4, si, di, int64_t, +) +DEF_COND_OP_WWV (cond_wadd, 8, si, di, int64_t, +) +DEF_COND_OP_WWV (cond_wadd, 16, si, di, int64_t, +) +DEF_COND_OP_WWV (cond_wadd, 32, si, di, int64_t, +) +DEF_COND_OP_WWV (cond_wadd, 64, si, di, int64_t, +) +DEF_COND_OP_WWV (cond_wadd, 128, si, di, int64_t, +) +DEF_COND_OP_WWV (cond_wadd, 256, si, di, int64_t, +) +DEF_COND_OP_WWV (cond_wadd, 512, si, di, int64_t, +) + +DEF_COND_OP_WWV (cond_wadd, 4, uqi, uhi, uint16_t, +) +DEF_COND_OP_WWV (cond_wadd, 8, uqi, uhi, uint16_t, +) +DEF_COND_OP_WWV (cond_wadd, 16, uqi, uhi, uint16_t, +) +DEF_COND_OP_WWV (cond_wadd, 32, uqi, uhi, uint16_t, +) +DEF_COND_OP_WWV (cond_wadd, 64, uqi, uhi, uint16_t, +) +DEF_COND_OP_WWV (cond_wadd, 128, uqi, uhi, uint16_t, +) +DEF_COND_OP_WWV (cond_wadd, 256, uqi, uhi, uint16_t, +) +DEF_COND_OP_WWV (cond_wadd, 512, uqi, uhi, uint16_t, +) +DEF_COND_OP_WWV (cond_wadd, 1024, uqi, uhi, uint16_t, +) + +DEF_COND_OP_WWV (cond_wadd, 4, uhi, usi, uint32_t, +) +DEF_COND_OP_WWV (cond_wadd, 8, uhi, usi, uint32_t, +) +DEF_COND_OP_WWV (cond_wadd, 16, uhi, usi, uint32_t, +) +DEF_COND_OP_WWV (cond_wadd, 32, uhi, usi, uint32_t, +) +DEF_COND_OP_WWV (cond_wadd, 64, uhi, usi, uint32_t, +) +DEF_COND_OP_WWV (cond_wadd, 128, uhi, usi, uint32_t, +) +DEF_COND_OP_WWV (cond_wadd, 256, uhi, usi, uint32_t, +) +DEF_COND_OP_WWV (cond_wadd, 512, uhi, usi, uint32_t, +) +DEF_COND_OP_WWV (cond_wadd, 1024, uhi, usi, uint32_t, +) + +DEF_COND_OP_WWV (cond_wadd, 4, usi, udi, uint64_t, +) +DEF_COND_OP_WWV (cond_wadd, 8, usi, udi, uint64_t, +) +DEF_COND_OP_WWV (cond_wadd, 16, usi, udi, uint64_t, +) +DEF_COND_OP_WWV (cond_wadd, 32, usi, udi, uint64_t, +) +DEF_COND_OP_WWV (cond_wadd, 64, usi, udi, uint64_t, +) +DEF_COND_OP_WWV (cond_wadd, 128, usi, udi, uint64_t, +) +DEF_COND_OP_WWV (cond_wadd, 256, usi, udi, uint64_t, +) +DEF_COND_OP_WWV (cond_wadd, 512, usi, udi, uint64_t, +) + +/* { dg-final { scan-assembler-times {vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */ +/* { dg-final { scan-assembler-times {vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c new file mode 100644 index 0000000..d9056e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_OP_WWV (cond_wadd, 4, hf, sf, float, +) +DEF_COND_OP_WWV (cond_wadd, 8, hf, sf, float, +) +DEF_COND_OP_WWV (cond_wadd, 16, hf, sf, float, +) +DEF_COND_OP_WWV (cond_wadd, 32, hf, sf, float, +) +DEF_COND_OP_WWV (cond_wadd, 64, hf, sf, float, +) +DEF_COND_OP_WWV (cond_wadd, 128, hf, sf, float, +) +DEF_COND_OP_WWV (cond_wadd, 256, hf, sf, float, +) +DEF_COND_OP_WWV (cond_wadd, 512, hf, sf, float, +) +DEF_COND_OP_WWV (cond_wadd, 1024, hf, sf, float, +) + +DEF_COND_OP_WWV (cond_wadd, 4, sf, df, double, +) +DEF_COND_OP_WWV (cond_wadd, 8, sf, df, double, +) +DEF_COND_OP_WWV (cond_wadd, 16, sf, df, double, +) +DEF_COND_OP_WWV (cond_wadd, 32, sf, df, double, +) +DEF_COND_OP_WWV (cond_wadd, 64, sf, df, double, +) +DEF_COND_OP_WWV (cond_wadd, 128, sf, df, double, +) +DEF_COND_OP_WWV (cond_wadd, 256, sf, df, double, +) +DEF_COND_OP_WWV (cond_wadd, 512, sf, df, double, +) + +/* { dg-final { scan-assembler-times {vfwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c new file mode 100644 index 0000000..fa4022b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c @@ -0,0 +1,79 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_WFMA_VV (cond_wfma, 4, qi, hi, int16_t) +DEF_WFMA_VV (cond_wfma, 8, qi, hi, int16_t) +DEF_WFMA_VV (cond_wfma, 16, qi, hi, int16_t) +DEF_WFMA_VV (cond_wfma, 32, qi, hi, int16_t) +DEF_WFMA_VV (cond_wfma, 64, qi, hi, int16_t) +DEF_WFMA_VV (cond_wfma, 128, qi, hi, int16_t) +DEF_WFMA_VV (cond_wfma, 256, qi, hi, int16_t) +DEF_WFMA_VV (cond_wfma, 512, qi, hi, int16_t) +DEF_WFMA_VV (cond_wfma, 1024, qi, hi, int16_t) + +DEF_WFMA_VV (cond_wfma, 4, hi, si, int32_t) +DEF_WFMA_VV (cond_wfma, 8, hi, si, int32_t) +DEF_WFMA_VV (cond_wfma, 16, hi, si, int32_t) +DEF_WFMA_VV (cond_wfma, 32, hi, si, int32_t) +DEF_WFMA_VV (cond_wfma, 64, hi, si, int32_t) +DEF_WFMA_VV (cond_wfma, 128, hi, si, int32_t) +DEF_WFMA_VV (cond_wfma, 256, hi, si, int32_t) +DEF_WFMA_VV (cond_wfma, 512, hi, si, int32_t) +DEF_WFMA_VV (cond_wfma, 1024, hi, si, int32_t) + +DEF_WFMA_VV (cond_wfma, 4, si, di, int64_t) +DEF_WFMA_VV (cond_wfma, 8, si, di, int64_t) +DEF_WFMA_VV (cond_wfma, 16, si, di, int64_t) +DEF_WFMA_VV (cond_wfma, 32, si, di, int64_t) +DEF_WFMA_VV (cond_wfma, 64, si, di, int64_t) +DEF_WFMA_VV (cond_wfma, 128, si, di, int64_t) +DEF_WFMA_VV (cond_wfma, 256, si, di, int64_t) +DEF_WFMA_VV (cond_wfma, 512, si, di, int64_t) + +DEF_WFMA_VV (cond_wfma, 4, uqi, uhi, uint16_t) +DEF_WFMA_VV (cond_wfma, 8, uqi, uhi, uint16_t) +DEF_WFMA_VV (cond_wfma, 16, uqi, uhi, uint16_t) +DEF_WFMA_VV (cond_wfma, 32, uqi, uhi, uint16_t) +DEF_WFMA_VV (cond_wfma, 64, uqi, uhi, uint16_t) +DEF_WFMA_VV (cond_wfma, 128, uqi, uhi, uint16_t) +DEF_WFMA_VV (cond_wfma, 256, uqi, uhi, uint16_t) +DEF_WFMA_VV (cond_wfma, 512, uqi, uhi, uint16_t) +DEF_WFMA_VV (cond_wfma, 1024, uqi, uhi, uint16_t) + +DEF_WFMA_VV (cond_wfma, 4, uhi, usi, uint32_t) +DEF_WFMA_VV (cond_wfma, 8, uhi, usi, uint32_t) +DEF_WFMA_VV (cond_wfma, 16, uhi, usi, uint32_t) +DEF_WFMA_VV (cond_wfma, 32, uhi, usi, uint32_t) +DEF_WFMA_VV (cond_wfma, 64, uhi, usi, uint32_t) +DEF_WFMA_VV (cond_wfma, 128, uhi, usi, uint32_t) +DEF_WFMA_VV (cond_wfma, 256, uhi, usi, uint32_t) +DEF_WFMA_VV (cond_wfma, 512, uhi, usi, uint32_t) +DEF_WFMA_VV (cond_wfma, 1024, uhi, usi, uint32_t) + +DEF_WFMA_VV (cond_wfma, 4, usi, udi, uint64_t) +DEF_WFMA_VV (cond_wfma, 8, usi, udi, uint64_t) +DEF_WFMA_VV (cond_wfma, 16, usi, udi, uint64_t) +DEF_WFMA_VV (cond_wfma, 32, usi, udi, uint64_t) +DEF_WFMA_VV (cond_wfma, 64, usi, udi, uint64_t) +DEF_WFMA_VV (cond_wfma, 128, usi, udi, uint64_t) +DEF_WFMA_VV (cond_wfma, 256, usi, udi, uint64_t) +DEF_WFMA_VV (cond_wfma, 512, usi, udi, uint64_t) + +/* { dg-final { scan-assembler-times {vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */ +/* { dg-final { scan-assembler-times {vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c new file mode 100644 index 0000000..5a2bfed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_WFMA_VV (cond_wfma, 4, hf, sf, float) +DEF_WFMA_VV (cond_wfma, 8, hf, sf, float) +DEF_WFMA_VV (cond_wfma, 16, hf, sf, float) +DEF_WFMA_VV (cond_wfma, 32, hf, sf, float) +DEF_WFMA_VV (cond_wfma, 64, hf, sf, float) +DEF_WFMA_VV (cond_wfma, 128, hf, sf, float) +DEF_WFMA_VV (cond_wfma, 256, hf, sf, float) +DEF_WFMA_VV (cond_wfma, 512, hf, sf, float) +DEF_WFMA_VV (cond_wfma, 1024, hf, sf, float) + +DEF_WFMA_VV (cond_wfma, 4, sf, df, double) +DEF_WFMA_VV (cond_wfma, 8, sf, df, double) +DEF_WFMA_VV (cond_wfma, 16, sf, df, double) +DEF_WFMA_VV (cond_wfma, 32, sf, df, double) +DEF_WFMA_VV (cond_wfma, 64, sf, df, double) +DEF_WFMA_VV (cond_wfma, 128, sf, df, double) +DEF_WFMA_VV (cond_wfma, 256, sf, df, double) +DEF_WFMA_VV (cond_wfma, 512, sf, df, double) + +/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c new file mode 100644 index 0000000..86fbe0b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_WFMS_VV (cond_wfms, 4, hf, sf, float) +DEF_WFMS_VV (cond_wfms, 8, hf, sf, float) +DEF_WFMS_VV (cond_wfms, 16, hf, sf, float) +DEF_WFMS_VV (cond_wfms, 32, hf, sf, float) +DEF_WFMS_VV (cond_wfms, 64, hf, sf, float) +DEF_WFMS_VV (cond_wfms, 128, hf, sf, float) +DEF_WFMS_VV (cond_wfms, 256, hf, sf, float) +DEF_WFMS_VV (cond_wfms, 512, hf, sf, float) +DEF_WFMS_VV (cond_wfms, 1024, hf, sf, float) + +DEF_WFMS_VV (cond_wfms, 4, sf, df, double) +DEF_WFMS_VV (cond_wfms, 8, sf, df, double) +DEF_WFMS_VV (cond_wfms, 16, sf, df, double) +DEF_WFMS_VV (cond_wfms, 32, sf, df, double) +DEF_WFMS_VV (cond_wfms, 64, sf, df, double) +DEF_WFMS_VV (cond_wfms, 128, sf, df, double) +DEF_WFMS_VV (cond_wfms, 256, sf, df, double) +DEF_WFMS_VV (cond_wfms, 512, sf, df, double) + +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfnma-1.c new file mode 100644 index 0000000..fa0fc64 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfnma-1.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_WFNMA_VV (cond_wfnma, 4, hf, sf, float) +DEF_WFNMA_VV (cond_wfnma, 8, hf, sf, float) +DEF_WFNMA_VV (cond_wfnma, 16, hf, sf, float) +DEF_WFNMA_VV (cond_wfnma, 32, hf, sf, float) +DEF_WFNMA_VV (cond_wfnma, 64, hf, sf, float) +DEF_WFNMA_VV (cond_wfnma, 128, hf, sf, float) +DEF_WFNMA_VV (cond_wfnma, 256, hf, sf, float) +DEF_WFNMA_VV (cond_wfnma, 512, hf, sf, float) +DEF_WFNMA_VV (cond_wfnma, 1024, hf, sf, float) + +DEF_WFNMA_VV (cond_wfnma, 4, sf, df, double) +DEF_WFNMA_VV (cond_wfnma, 8, sf, df, double) +DEF_WFNMA_VV (cond_wfnma, 16, sf, df, double) +DEF_WFNMA_VV (cond_wfnma, 32, sf, df, double) +DEF_WFNMA_VV (cond_wfnma, 64, sf, df, double) +DEF_WFNMA_VV (cond_wfnma, 128, sf, df, double) +DEF_WFNMA_VV (cond_wfnma, 256, sf, df, double) +DEF_WFNMA_VV (cond_wfnma, 512, sf, df, double) + +/* { dg-final { scan-assembler-times {vfnmsac\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c new file mode 100644 index 0000000..f18cd66 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c @@ -0,0 +1,79 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_OP_WVV (cond_wmul, 4, qi, hi, int16_t, *) +DEF_COND_OP_WVV (cond_wmul, 8, qi, hi, int16_t, *) +DEF_COND_OP_WVV (cond_wmul, 16, qi, hi, int16_t, *) +DEF_COND_OP_WVV (cond_wmul, 32, qi, hi, int16_t, *) +DEF_COND_OP_WVV (cond_wmul, 64, qi, hi, int16_t, *) +DEF_COND_OP_WVV (cond_wmul, 128, qi, hi, int16_t, *) +DEF_COND_OP_WVV (cond_wmul, 256, qi, hi, int16_t, *) +DEF_COND_OP_WVV (cond_wmul, 512, qi, hi, int16_t, *) +DEF_COND_OP_WVV (cond_wmul, 1024, qi, hi, int16_t, *) + +DEF_COND_OP_WVV (cond_wmul, 4, hi, si, int32_t, *) +DEF_COND_OP_WVV (cond_wmul, 8, hi, si, int32_t, *) +DEF_COND_OP_WVV (cond_wmul, 16, hi, si, int32_t, *) +DEF_COND_OP_WVV (cond_wmul, 32, hi, si, int32_t, *) +DEF_COND_OP_WVV (cond_wmul, 64, hi, si, int32_t, *) +DEF_COND_OP_WVV (cond_wmul, 128, hi, si, int32_t, *) +DEF_COND_OP_WVV (cond_wmul, 256, hi, si, int32_t, *) +DEF_COND_OP_WVV (cond_wmul, 512, hi, si, int32_t, *) +DEF_COND_OP_WVV (cond_wmul, 1024, hi, si, int32_t, *) + +DEF_COND_OP_WVV (cond_wmul, 4, si, di, int64_t, *) +DEF_COND_OP_WVV (cond_wmul, 8, si, di, int64_t, *) +DEF_COND_OP_WVV (cond_wmul, 16, si, di, int64_t, *) +DEF_COND_OP_WVV (cond_wmul, 32, si, di, int64_t, *) +DEF_COND_OP_WVV (cond_wmul, 64, si, di, int64_t, *) +DEF_COND_OP_WVV (cond_wmul, 128, si, di, int64_t, *) +DEF_COND_OP_WVV (cond_wmul, 256, si, di, int64_t, *) +DEF_COND_OP_WVV (cond_wmul, 512, si, di, int64_t, *) + +DEF_COND_OP_WVV (cond_wmul, 4, uqi, uhi, uint16_t, *) +DEF_COND_OP_WVV (cond_wmul, 8, uqi, uhi, uint16_t, *) +DEF_COND_OP_WVV (cond_wmul, 16, uqi, uhi, uint16_t, *) +DEF_COND_OP_WVV (cond_wmul, 32, uqi, uhi, uint16_t, *) +DEF_COND_OP_WVV (cond_wmul, 64, uqi, uhi, uint16_t, *) +DEF_COND_OP_WVV (cond_wmul, 128, uqi, uhi, uint16_t, *) +DEF_COND_OP_WVV (cond_wmul, 256, uqi, uhi, uint16_t, *) +DEF_COND_OP_WVV (cond_wmul, 512, uqi, uhi, uint16_t, *) +DEF_COND_OP_WVV (cond_wmul, 1024, uqi, uhi, uint16_t, *) + +DEF_COND_OP_WVV (cond_wmul, 4, uhi, usi, uint32_t, *) +DEF_COND_OP_WVV (cond_wmul, 8, uhi, usi, uint32_t, *) +DEF_COND_OP_WVV (cond_wmul, 16, uhi, usi, uint32_t, *) +DEF_COND_OP_WVV (cond_wmul, 32, uhi, usi, uint32_t, *) +DEF_COND_OP_WVV (cond_wmul, 64, uhi, usi, uint32_t, *) +DEF_COND_OP_WVV (cond_wmul, 128, uhi, usi, uint32_t, *) +DEF_COND_OP_WVV (cond_wmul, 256, uhi, usi, uint32_t, *) +DEF_COND_OP_WVV (cond_wmul, 512, uhi, usi, uint32_t, *) +DEF_COND_OP_WVV (cond_wmul, 1024, uhi, usi, uint32_t, *) + +DEF_COND_OP_WVV (cond_wmul, 4, usi, udi, uint64_t, *) +DEF_COND_OP_WVV (cond_wmul, 8, usi, udi, uint64_t, *) +DEF_COND_OP_WVV (cond_wmul, 16, usi, udi, uint64_t, *) +DEF_COND_OP_WVV (cond_wmul, 32, usi, udi, uint64_t, *) +DEF_COND_OP_WVV (cond_wmul, 64, usi, udi, uint64_t, *) +DEF_COND_OP_WVV (cond_wmul, 128, usi, udi, uint64_t, *) +DEF_COND_OP_WVV (cond_wmul, 256, usi, udi, uint64_t, *) +DEF_COND_OP_WVV (cond_wmul, 512, usi, udi, uint64_t, *) + +/* { dg-final { scan-assembler-times {vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */ +/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c new file mode 100644 index 0000000..b7a6d52 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_OP_WVV (cond_wmul, 4, hf, sf, float, *) +DEF_COND_OP_WVV (cond_wmul, 8, hf, sf, float, *) +DEF_COND_OP_WVV (cond_wmul, 16, hf, sf, float, *) +DEF_COND_OP_WVV (cond_wmul, 32, hf, sf, float, *) +DEF_COND_OP_WVV (cond_wmul, 64, hf, sf, float, *) +DEF_COND_OP_WVV (cond_wmul, 128, hf, sf, float, *) +DEF_COND_OP_WVV (cond_wmul, 256, hf, sf, float, *) +DEF_COND_OP_WVV (cond_wmul, 512, hf, sf, float, *) +DEF_COND_OP_WVV (cond_wmul, 1024, hf, sf, float, *) + +DEF_COND_OP_WVV (cond_wmul, 4, sf, df, double, *) +DEF_COND_OP_WVV (cond_wmul, 8, sf, df, double, *) +DEF_COND_OP_WVV (cond_wmul, 16, sf, df, double, *) +DEF_COND_OP_WVV (cond_wmul, 32, sf, df, double, *) +DEF_COND_OP_WVV (cond_wmul, 64, sf, df, double, *) +DEF_COND_OP_WVV (cond_wmul, 128, sf, df, double, *) +DEF_COND_OP_WVV (cond_wmul, 256, sf, df, double, *) +DEF_COND_OP_WVV (cond_wmul, 512, sf, df, double, *) + +/* { dg-final { scan-assembler-times {vfwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c new file mode 100644 index 0000000..64ca747 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_OP_WVV_SU (cond_wmul, 4, qi, hi, int16_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 8, qi, hi, int16_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 16, qi, hi, int16_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 32, qi, hi, int16_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 64, qi, hi, int16_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 128, qi, hi, int16_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 256, qi, hi, int16_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 512, qi, hi, int16_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 1024, qi, hi, int16_t, *) + +DEF_COND_OP_WVV_SU (cond_wmul, 4, hi, si, int32_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 8, hi, si, int32_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 16, hi, si, int32_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 32, hi, si, int32_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 64, hi, si, int32_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 128, hi, si, int32_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 256, hi, si, int32_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 512, hi, si, int32_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 1024, hi, si, int32_t, *) + +DEF_COND_OP_WVV_SU (cond_wmul, 4, si, di, int64_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 8, si, di, int64_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 16, si, di, int64_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 32, si, di, int64_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 64, si, di, int64_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 128, si, di, int64_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 256, si, di, int64_t, *) +DEF_COND_OP_WVV_SU (cond_wmul, 512, si, di, int64_t, *) + +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c new file mode 100644 index 0000000..887aabd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c @@ -0,0 +1,79 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_OP_WVV (cond_wsub, 4, qi, hi, int16_t, -) +DEF_COND_OP_WVV (cond_wsub, 8, qi, hi, int16_t, -) +DEF_COND_OP_WVV (cond_wsub, 16, qi, hi, int16_t, -) +DEF_COND_OP_WVV (cond_wsub, 32, qi, hi, int16_t, -) +DEF_COND_OP_WVV (cond_wsub, 64, qi, hi, int16_t, -) +DEF_COND_OP_WVV (cond_wsub, 128, qi, hi, int16_t, -) +DEF_COND_OP_WVV (cond_wsub, 256, qi, hi, int16_t, -) +DEF_COND_OP_WVV (cond_wsub, 512, qi, hi, int16_t, -) +DEF_COND_OP_WVV (cond_wsub, 1024, qi, hi, int16_t, -) + +DEF_COND_OP_WVV (cond_wsub, 4, hi, si, int32_t, -) +DEF_COND_OP_WVV (cond_wsub, 8, hi, si, int32_t, -) +DEF_COND_OP_WVV (cond_wsub, 16, hi, si, int32_t, -) +DEF_COND_OP_WVV (cond_wsub, 32, hi, si, int32_t, -) +DEF_COND_OP_WVV (cond_wsub, 64, hi, si, int32_t, -) +DEF_COND_OP_WVV (cond_wsub, 128, hi, si, int32_t, -) +DEF_COND_OP_WVV (cond_wsub, 256, hi, si, int32_t, -) +DEF_COND_OP_WVV (cond_wsub, 512, hi, si, int32_t, -) +DEF_COND_OP_WVV (cond_wsub, 1024, hi, si, int32_t, -) + +DEF_COND_OP_WVV (cond_wsub, 4, si, di, int64_t, -) +DEF_COND_OP_WVV (cond_wsub, 8, si, di, int64_t, -) +DEF_COND_OP_WVV (cond_wsub, 16, si, di, int64_t, -) +DEF_COND_OP_WVV (cond_wsub, 32, si, di, int64_t, -) +DEF_COND_OP_WVV (cond_wsub, 64, si, di, int64_t, -) +DEF_COND_OP_WVV (cond_wsub, 128, si, di, int64_t, -) +DEF_COND_OP_WVV (cond_wsub, 256, si, di, int64_t, -) +DEF_COND_OP_WVV (cond_wsub, 512, si, di, int64_t, -) + +DEF_COND_OP_WVV (cond_wsub, 4, uqi, uhi, uint16_t, -) +DEF_COND_OP_WVV (cond_wsub, 8, uqi, uhi, uint16_t, -) +DEF_COND_OP_WVV (cond_wsub, 16, uqi, uhi, uint16_t, -) +DEF_COND_OP_WVV (cond_wsub, 32, uqi, uhi, uint16_t, -) +DEF_COND_OP_WVV (cond_wsub, 64, uqi, uhi, uint16_t, -) +DEF_COND_OP_WVV (cond_wsub, 128, uqi, uhi, uint16_t, -) +DEF_COND_OP_WVV (cond_wsub, 256, uqi, uhi, uint16_t, -) +DEF_COND_OP_WVV (cond_wsub, 512, uqi, uhi, uint16_t, -) +DEF_COND_OP_WVV (cond_wsub, 1024, uqi, uhi, uint16_t, -) + +DEF_COND_OP_WVV (cond_wsub, 4, uhi, usi, uint32_t, -) +DEF_COND_OP_WVV (cond_wsub, 8, uhi, usi, uint32_t, -) +DEF_COND_OP_WVV (cond_wsub, 16, uhi, usi, uint32_t, -) +DEF_COND_OP_WVV (cond_wsub, 32, uhi, usi, uint32_t, -) +DEF_COND_OP_WVV (cond_wsub, 64, uhi, usi, uint32_t, -) +DEF_COND_OP_WVV (cond_wsub, 128, uhi, usi, uint32_t, -) +DEF_COND_OP_WVV (cond_wsub, 256, uhi, usi, uint32_t, -) +DEF_COND_OP_WVV (cond_wsub, 512, uhi, usi, uint32_t, -) +DEF_COND_OP_WVV (cond_wsub, 1024, uhi, usi, uint32_t, -) + +DEF_COND_OP_WVV (cond_wsub, 4, usi, udi, uint64_t, -) +DEF_COND_OP_WVV (cond_wsub, 8, usi, udi, uint64_t, -) +DEF_COND_OP_WVV (cond_wsub, 16, usi, udi, uint64_t, -) +DEF_COND_OP_WVV (cond_wsub, 32, usi, udi, uint64_t, -) +DEF_COND_OP_WVV (cond_wsub, 64, usi, udi, uint64_t, -) +DEF_COND_OP_WVV (cond_wsub, 128, usi, udi, uint64_t, -) +DEF_COND_OP_WVV (cond_wsub, 256, usi, udi, uint64_t, -) +DEF_COND_OP_WVV (cond_wsub, 512, usi, udi, uint64_t, -) + +/* { dg-final { scan-assembler-times {vwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */ +/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c new file mode 100644 index 0000000..4093450 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_OP_WVV (cond_wsub, 4, hf, sf, float, -) +DEF_COND_OP_WVV (cond_wsub, 8, hf, sf, float, -) +DEF_COND_OP_WVV (cond_wsub, 16, hf, sf, float, -) +DEF_COND_OP_WVV (cond_wsub, 32, hf, sf, float, -) +DEF_COND_OP_WVV (cond_wsub, 64, hf, sf, float, -) +DEF_COND_OP_WVV (cond_wsub, 128, hf, sf, float, -) +DEF_COND_OP_WVV (cond_wsub, 256, hf, sf, float, -) +DEF_COND_OP_WVV (cond_wsub, 512, hf, sf, float, -) +DEF_COND_OP_WVV (cond_wsub, 1024, hf, sf, float, -) + +DEF_COND_OP_WVV (cond_wsub, 4, sf, df, double, -) +DEF_COND_OP_WVV (cond_wsub, 8, sf, df, double, -) +DEF_COND_OP_WVV (cond_wsub, 16, sf, df, double, -) +DEF_COND_OP_WVV (cond_wsub, 32, sf, df, double, -) +DEF_COND_OP_WVV (cond_wsub, 64, sf, df, double, -) +DEF_COND_OP_WVV (cond_wsub, 128, sf, df, double, -) +DEF_COND_OP_WVV (cond_wsub, 256, sf, df, double, -) +DEF_COND_OP_WVV (cond_wsub, 512, sf, df, double, -) + +/* { dg-final { scan-assembler-times {vfwsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c new file mode 100644 index 0000000..20e3a8f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c @@ -0,0 +1,79 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_OP_WWV (cond_wsub, 4, qi, hi, int16_t, -) +DEF_COND_OP_WWV (cond_wsub, 8, qi, hi, int16_t, -) +DEF_COND_OP_WWV (cond_wsub, 16, qi, hi, int16_t, -) +DEF_COND_OP_WWV (cond_wsub, 32, qi, hi, int16_t, -) +DEF_COND_OP_WWV (cond_wsub, 64, qi, hi, int16_t, -) +DEF_COND_OP_WWV (cond_wsub, 128, qi, hi, int16_t, -) +DEF_COND_OP_WWV (cond_wsub, 256, qi, hi, int16_t, -) +DEF_COND_OP_WWV (cond_wsub, 512, qi, hi, int16_t, -) +DEF_COND_OP_WWV (cond_wsub, 1024, qi, hi, int16_t, -) + +DEF_COND_OP_WWV (cond_wsub, 4, hi, si, int32_t, -) +DEF_COND_OP_WWV (cond_wsub, 8, hi, si, int32_t, -) +DEF_COND_OP_WWV (cond_wsub, 16, hi, si, int32_t, -) +DEF_COND_OP_WWV (cond_wsub, 32, hi, si, int32_t, -) +DEF_COND_OP_WWV (cond_wsub, 64, hi, si, int32_t, -) +DEF_COND_OP_WWV (cond_wsub, 128, hi, si, int32_t, -) +DEF_COND_OP_WWV (cond_wsub, 256, hi, si, int32_t, -) +DEF_COND_OP_WWV (cond_wsub, 512, hi, si, int32_t, -) +DEF_COND_OP_WWV (cond_wsub, 1024, hi, si, int32_t, -) + +DEF_COND_OP_WWV (cond_wsub, 4, si, di, int64_t, -) +DEF_COND_OP_WWV (cond_wsub, 8, si, di, int64_t, -) +DEF_COND_OP_WWV (cond_wsub, 16, si, di, int64_t, -) +DEF_COND_OP_WWV (cond_wsub, 32, si, di, int64_t, -) +DEF_COND_OP_WWV (cond_wsub, 64, si, di, int64_t, -) +DEF_COND_OP_WWV (cond_wsub, 128, si, di, int64_t, -) +DEF_COND_OP_WWV (cond_wsub, 256, si, di, int64_t, -) +DEF_COND_OP_WWV (cond_wsub, 512, si, di, int64_t, -) + +DEF_COND_OP_WWV (cond_wsub, 4, uqi, uhi, uint16_t, -) +DEF_COND_OP_WWV (cond_wsub, 8, uqi, uhi, uint16_t, -) +DEF_COND_OP_WWV (cond_wsub, 16, uqi, uhi, uint16_t, -) +DEF_COND_OP_WWV (cond_wsub, 32, uqi, uhi, uint16_t, -) +DEF_COND_OP_WWV (cond_wsub, 64, uqi, uhi, uint16_t, -) +DEF_COND_OP_WWV (cond_wsub, 128, uqi, uhi, uint16_t, -) +DEF_COND_OP_WWV (cond_wsub, 256, uqi, uhi, uint16_t, -) +DEF_COND_OP_WWV (cond_wsub, 512, uqi, uhi, uint16_t, -) +DEF_COND_OP_WWV (cond_wsub, 1024, uqi, uhi, uint16_t, -) + +DEF_COND_OP_WWV (cond_wsub, 4, uhi, usi, uint32_t, -) +DEF_COND_OP_WWV (cond_wsub, 8, uhi, usi, uint32_t, -) +DEF_COND_OP_WWV (cond_wsub, 16, uhi, usi, uint32_t, -) +DEF_COND_OP_WWV (cond_wsub, 32, uhi, usi, uint32_t, -) +DEF_COND_OP_WWV (cond_wsub, 64, uhi, usi, uint32_t, -) +DEF_COND_OP_WWV (cond_wsub, 128, uhi, usi, uint32_t, -) +DEF_COND_OP_WWV (cond_wsub, 256, uhi, usi, uint32_t, -) +DEF_COND_OP_WWV (cond_wsub, 512, uhi, usi, uint32_t, -) +DEF_COND_OP_WWV (cond_wsub, 1024, uhi, usi, uint32_t, -) + +DEF_COND_OP_WWV (cond_wsub, 4, usi, udi, uint64_t, -) +DEF_COND_OP_WWV (cond_wsub, 8, usi, udi, uint64_t, -) +DEF_COND_OP_WWV (cond_wsub, 16, usi, udi, uint64_t, -) +DEF_COND_OP_WWV (cond_wsub, 32, usi, udi, uint64_t, -) +DEF_COND_OP_WWV (cond_wsub, 64, usi, udi, uint64_t, -) +DEF_COND_OP_WWV (cond_wsub, 128, usi, udi, uint64_t, -) +DEF_COND_OP_WWV (cond_wsub, 256, usi, udi, uint64_t, -) +DEF_COND_OP_WWV (cond_wsub, 512, usi, udi, uint64_t, -) + +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */ +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 26 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c new file mode 100644 index 0000000..b97cd8a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_OP_WWV (cond_wsub, 4, hf, sf, float, -) +DEF_COND_OP_WWV (cond_wsub, 8, hf, sf, float, -) +DEF_COND_OP_WWV (cond_wsub, 16, hf, sf, float, -) +DEF_COND_OP_WWV (cond_wsub, 32, hf, sf, float, -) +DEF_COND_OP_WWV (cond_wsub, 64, hf, sf, float, -) +DEF_COND_OP_WWV (cond_wsub, 128, hf, sf, float, -) +DEF_COND_OP_WWV (cond_wsub, 256, hf, sf, float, -) +DEF_COND_OP_WWV (cond_wsub, 512, hf, sf, float, -) +DEF_COND_OP_WWV (cond_wsub, 1024, hf, sf, float, -) + +DEF_COND_OP_WWV (cond_wsub, 4, sf, df, double, -) +DEF_COND_OP_WWV (cond_wsub, 8, sf, df, double, -) +DEF_COND_OP_WWV (cond_wsub, 16, sf, df, double, -) +DEF_COND_OP_WWV (cond_wsub, 32, sf, df, double, -) +DEF_COND_OP_WWV (cond_wsub, 64, sf, df, double, -) +DEF_COND_OP_WWV (cond_wsub, 128, sf, df, double, -) +DEF_COND_OP_WWV (cond_wsub, 256, sf, df, double, -) +DEF_COND_OP_WWV (cond_wsub, 512, sf, df, double, -) + +/* { dg-final { scan-assembler-times {vfwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c new file mode 100644 index 0000000..1bb0570 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_COND_BINOP (cond_xor, 4, v4qi, ^) +DEF_COND_BINOP (cond_xor, 8, v8qi, ^) +DEF_COND_BINOP (cond_xor, 16, v16qi, ^) +DEF_COND_BINOP (cond_xor, 32, v32qi, ^) +DEF_COND_BINOP (cond_xor, 64, v64qi, ^) +DEF_COND_BINOP (cond_xor, 128, v128qi, ^) +DEF_COND_BINOP (cond_xor, 256, v256qi, ^) +DEF_COND_BINOP (cond_xor, 512, v512qi, ^) +DEF_COND_BINOP (cond_xor, 1024, v1024qi, ^) +DEF_COND_BINOP (cond_xor, 2048, v2048qi, ^) +DEF_COND_BINOP (cond_xor, 4096, v4096qi, ^) + +DEF_COND_BINOP (cond_xor, 4, v4hi, ^) +DEF_COND_BINOP (cond_xor, 8, v8hi, ^) +DEF_COND_BINOP (cond_xor, 16, v16hi, ^) +DEF_COND_BINOP (cond_xor, 32, v32hi, ^) +DEF_COND_BINOP (cond_xor, 64, v64hi, ^) +DEF_COND_BINOP (cond_xor, 128, v128hi, ^) +DEF_COND_BINOP (cond_xor, 256, v256hi, ^) +DEF_COND_BINOP (cond_xor, 512, v512hi, ^) +DEF_COND_BINOP (cond_xor, 1024, v1024hi, ^) +DEF_COND_BINOP (cond_xor, 2048, v2048hi, ^) + +DEF_COND_BINOP (cond_xor, 4, v4si, ^) +DEF_COND_BINOP (cond_xor, 8, v8si, ^) +DEF_COND_BINOP (cond_xor, 16, v16si, ^) +DEF_COND_BINOP (cond_xor, 32, v32si, ^) +DEF_COND_BINOP (cond_xor, 64, v64si, ^) +DEF_COND_BINOP (cond_xor, 128, v128si, ^) +DEF_COND_BINOP (cond_xor, 256, v256si, ^) +DEF_COND_BINOP (cond_xor, 512, v512si, ^) +DEF_COND_BINOP (cond_xor, 1024, v1024si, ^) + +DEF_COND_BINOP (cond_xor, 4, v4di, ^) +DEF_COND_BINOP (cond_xor, 8, v8di, ^) +DEF_COND_BINOP (cond_xor, 16, v16di, ^) +DEF_COND_BINOP (cond_xor, 32, v32di, ^) +DEF_COND_BINOP (cond_xor, 64, v64di, ^) +DEF_COND_BINOP (cond_xor, 128, v128di, ^) +DEF_COND_BINOP (cond_xor, 256, v256di, ^) +DEF_COND_BINOP (cond_xor, 512, v512di, ^) + +DEF_COND_BINOP (cond_xor, 4, v4uqi, ^) +DEF_COND_BINOP (cond_xor, 8, v8uqi, ^) +DEF_COND_BINOP (cond_xor, 16, v16uqi, ^) +DEF_COND_BINOP (cond_xor, 32, v32uqi, ^) +DEF_COND_BINOP (cond_xor, 64, v64uqi, ^) +DEF_COND_BINOP (cond_xor, 128, v128uqi, ^) +DEF_COND_BINOP (cond_xor, 256, v256uqi, ^) +DEF_COND_BINOP (cond_xor, 512, v512uqi, ^) +DEF_COND_BINOP (cond_xor, 1024, v1024uqi, ^) +DEF_COND_BINOP (cond_xor, 2048, v2048uqi, ^) +DEF_COND_BINOP (cond_xor, 4096, v4096uqi, ^) + +DEF_COND_BINOP (cond_xor, 4, v4uhi, ^) +DEF_COND_BINOP (cond_xor, 8, v8uhi, ^) +DEF_COND_BINOP (cond_xor, 16, v16uhi, ^) +DEF_COND_BINOP (cond_xor, 32, v32uhi, ^) +DEF_COND_BINOP (cond_xor, 64, v64uhi, ^) +DEF_COND_BINOP (cond_xor, 128, v128uhi, ^) +DEF_COND_BINOP (cond_xor, 256, v256uhi, ^) +DEF_COND_BINOP (cond_xor, 512, v512uhi, ^) +DEF_COND_BINOP (cond_xor, 1024, v1024uhi, ^) +DEF_COND_BINOP (cond_xor, 2048, v2048uhi, ^) + +DEF_COND_BINOP (cond_xor, 4, v4usi, ^) +DEF_COND_BINOP (cond_xor, 8, v8usi, ^) +DEF_COND_BINOP (cond_xor, 16, v16usi, ^) +DEF_COND_BINOP (cond_xor, 32, v32usi, ^) +DEF_COND_BINOP (cond_xor, 64, v64usi, ^) +DEF_COND_BINOP (cond_xor, 128, v128usi, ^) +DEF_COND_BINOP (cond_xor, 256, v256usi, ^) +DEF_COND_BINOP (cond_xor, 512, v512usi, ^) +DEF_COND_BINOP (cond_xor, 1024, v1024usi, ^) + +DEF_COND_BINOP (cond_xor, 4, v4udi, ^) +DEF_COND_BINOP (cond_xor, 8, v8udi, ^) +DEF_COND_BINOP (cond_xor, 16, v16udi, ^) +DEF_COND_BINOP (cond_xor, 32, v32udi, ^) +DEF_COND_BINOP (cond_xor, 64, v64udi, ^) +DEF_COND_BINOP (cond_xor, 128, v128udi, ^) +DEF_COND_BINOP (cond_xor, 256, v256udi, ^) +DEF_COND_BINOP (cond_xor, 512, v512udi, ^) + +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 76 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {vmerge} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h index 74685f8..fa124ff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h @@ -518,3 +518,309 @@ typedef double v512df __attribute__ ((vector_size (4096))); for (int i = 0; i < NUM; i++) \ dst[i] = ((TYPE2) a[i] + b[i] + 1) >> 1; \ } + +#define DEF_MULH(TYPE, NUM) \ + void __attribute__ ((noipa)) \ + mod_##TYPE##_##NUM (TYPE *__restrict dst, TYPE *__restrict src) \ + { \ + for (int i = 0; i < NUM; ++i) \ + dst[i] = src[i] % 19; \ + } + +#define DEF_COND_UNOP(PREFIX, NUM, TYPE, OP) \ + TYPE __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE cond) \ + { \ + TYPE v; \ + for (int i = 0; i < NUM; ++i) \ + v[i] = cond[i] ? OP (a[i]) : b[i]; \ + return v; \ + } + +#define DEF_COND_BINOP(PREFIX, NUM, TYPE, OP) \ + TYPE __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \ + { \ + TYPE v; \ + for (int i = 0; i < NUM; ++i) \ + v[i] = cond[i] ? a[i] OP b[i] : c[i]; \ + return v; \ + } + +#define DEF_COND_MINMAX(PREFIX, NUM, TYPE, OP) \ + TYPE __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \ + { \ + TYPE v; \ + for (int i = 0; i < NUM; ++i) \ + v[i] = cond[i] ? ((a[i]) OP (b[i]) ? (a[i]) : (b[i])) : c[i]; \ + return v; \ + } + +#define DEF_COND_FMA_VV(PREFIX, NUM, TYPE) \ + TYPE __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \ + { \ + TYPE v; \ + for (int i = 0; i < NUM; ++i) \ + v[i] = cond[i] ? a[i] * b[i] + c[i] : b[i]; \ + return v; \ + } + +#define DEF_COND_FNMA_VV(PREFIX, NUM, TYPE) \ + TYPE __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \ + { \ + TYPE v; \ + for (int i = 0; i < NUM; ++i) \ + v[i] = cond[i] ? a[i] - b[i] * c[i] : b[i]; \ + return v; \ + } + +#define DEF_COND_FMS_VV(PREFIX, NUM, TYPE) \ + TYPE __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \ + { \ + TYPE v; \ + for (int i = 0; i < NUM; ++i) \ + v[i] = cond[i] ? a[i] * b[i] - c[i] : b[i]; \ + return v; \ + } + +#define DEF_COND_FNMS_VV(PREFIX, NUM, TYPE) \ + TYPE __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \ + { \ + TYPE v; \ + for (int i = 0; i < NUM; ++i) \ + v[i] = cond[i] ? -(a[i] * b[i]) - c[i] : b[i]; \ + return v; \ + } + +#define DEF_OP_WVV(PREFIX, NUM, TYPE, TYPE2, OP) \ + void __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##_##TYPE2##NUM (TYPE2 *restrict a, TYPE *restrict b, \ + TYPE *restrict c) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = (TYPE2) b[i] OP (TYPE2) c[i]; \ + } + +#define DEF_OP_WWV(PREFIX, NUM, TYPE, TYPE2, OP) \ + void __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##_##TYPE2##NUM (TYPE2 *restrict a, TYPE2 *restrict b, \ + TYPE *restrict c) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = b[i] OP (TYPE2) c[i]; \ + } + +#define DEF_OP_WVV_SU(PREFIX, NUM, TYPE1, TYPE2, TYPE3, OP) \ + void __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##_##TYPE2##NUM (TYPE3 *restrict a, TYPE1 *restrict b, \ + TYPE2 *restrict c) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = (TYPE3) b[i] OP (TYPE3) c[i]; \ + } + +#define DEF_FMA_WVV(PREFIX, NUM, TYPE1, TYPE2) \ + void __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE1##_##TYPE2##NUM (TYPE2 *restrict a, TYPE1 *restrict b, \ + TYPE1 *restrict c, TYPE2 *restrict d) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = (TYPE2) b[i] * (TYPE2) c[i] + d[i]; \ + } + +#define DEF_FMA_WVV_SU(PREFIX, NUM, TYPE1, TYPE2, TYPE3) \ + void __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE1##_##TYPE2##_##TYPE3##NUM (TYPE3 *restrict a, \ + TYPE1 *restrict b, \ + TYPE2 *restrict c, \ + TYPE3 *restrict d) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = (TYPE3) b[i] * (TYPE3) c[i] + d[i]; \ + } + +#define DEF_FNMA_WVV(PREFIX, NUM, TYPE1, TYPE2) \ + void __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE1##_##TYPE2##NUM (TYPE2 *restrict a, TYPE1 *restrict b, \ + TYPE1 *restrict c, TYPE2 *restrict d) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = d[i] - (TYPE2) b[i] * (TYPE2) c[i]; \ + } + +#define DEF_FMS_WVV(PREFIX, NUM, TYPE1, TYPE2) \ + void __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE1##_##TYPE2##NUM (TYPE2 *restrict a, TYPE1 *restrict b, \ + TYPE1 *restrict c, TYPE2 *restrict d) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = (TYPE2) b[i] * (TYPE2) c[i] - d[i]; \ + } + +#define DEF_FNMS_WVV(PREFIX, NUM, TYPE1, TYPE2) \ + void __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE1##_##TYPE2##NUM (TYPE2 *restrict a, TYPE1 *restrict b, \ + TYPE1 *restrict c, TYPE2 *restrict d) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = -((TYPE2) b[i] * (TYPE2) c[i]) - d[i]; \ + } + +#define DEF_WIDEN_REDUC_PLUS(TYPE, TYPE2, NUM) \ + TYPE2 __attribute__ ((noinline, noclone)) \ + reduc_plus_##TYPE##_##TYPE2##NUM (TYPE *__restrict a) \ + { \ + TYPE2 r = 0; \ + for (int i = 0; i < NUM; ++i) \ + r += a[i]; \ + return r; \ + } + +#define DEF_NARROW_TRUNC_IMM(TYPE1, TYPE2, NUM) \ + void narrow_##TYPE1##_##TYPE2##_##NUM (TYPE1 *restrict a, TYPE2 *restrict b) \ + { \ + for (int i = 0; i < NUM; i += 1) \ + a[i] = (TYPE1) (b[i] >> 7); \ + } + +#define DEF_NARROW_TRUNC_XREG(TYPE1, TYPE2, NUM) \ + void narrow_##TYPE1##_##TYPE2##_##NUM (TYPE1 *restrict a, TYPE2 *restrict b, \ + int shift) \ + { \ + for (int i = 0; i < NUM; i += 1) \ + a[i] = (TYPE1) (b[i] >> shift); \ + } + +#define DEF_NARROW_TRUNC_VREG(TYPE1, TYPE2, NUM) \ + void narrow_##TYPE1##_##TYPE2##_##NUM (TYPE1 *restrict a, TYPE2 *restrict b, \ + int *restrict shift) \ + { \ + for (int i = 0; i < NUM; i += 1) \ + a[i] = (TYPE1) (b[i] >> shift[i]); \ + } + +#define DEF_COND_CONVERT(PREFIX, TYPE1, TYPE2, NUM) \ + __attribute__ ((noipa)) \ + TYPE2 PREFIX##_##TYPE1##TYPE2##_##NUM (TYPE2 dst, TYPE1 a, int *cond) \ + { \ + for (int i = 0; i < NUM; i++) \ + dst[i] = cond[i] ? a[i] : dst[i]; \ + return dst; \ + } + +#define DEF_COND_FP_CONVERT(PREFIX, TYPE1, TYPE2, TYPE3, NUM) \ + __attribute__ ((noipa)) \ + v##NUM##TYPE2 PREFIX##_##TYPE1##TYPE2##TYPE3##_##NUM (v##NUM##TYPE2 dst, \ + v##NUM##TYPE1 a, \ + int *cond) \ + { \ + for (int i = 0; i < NUM; i++) \ + dst[i] = cond[i] ? (TYPE3) a[i] : dst[i]; \ + return dst; \ + } + +#define DEF_COND_CALL(PREFIX, NUM, TYPE, CALL) \ + TYPE __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \ + { \ + TYPE v; \ + for (int i = 0; i < NUM; ++i) \ + v[i] = cond[i] ? CALL (a[i], b[i]) : c[i]; \ + return v; \ + } + +#define DEF_COND_MULH(PREFIX, NUM, TYPE, TYPE2, TYPE3, SHIFT) \ + TYPE __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE a, TYPE b, TYPE c, TYPE cond) \ + { \ + TYPE v; \ + for (int i = 0; i < NUM; ++i) \ + v[i] \ + = cond[i] ? (TYPE3) (((TYPE2) a[i] * (TYPE2) b[i]) >> SHIFT) : c[i]; \ + return v; \ + } + +#define DEF_COND_OP_WVV(PREFIX, NUM, TYPE, TYPE2, TYPE3, OP) \ + v##NUM##TYPE2 __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##_##TYPE2##NUM (v##NUM##TYPE2 a, v##NUM##TYPE b, \ + v##NUM##TYPE c, int *restrict cond) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = cond[i] ? (TYPE3) b[i] OP (TYPE3) c[i] : a[i]; \ + return a; \ + } + +#define DEF_COND_OP_WVV_SU(PREFIX, NUM, TYPE, TYPE2, TYPE3, OP) \ + v##NUM##TYPE2 __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##_##TYPE2##NUM (v##NUM##TYPE2 a, v##NUM##u##TYPE b, \ + v##NUM##TYPE c, int *restrict cond) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = cond[i] ? (TYPE3) b[i] OP (TYPE3) c[i] : a[i]; \ + return a; \ + } + +#define DEF_COND_OP_WWV(PREFIX, NUM, TYPE, TYPE2, TYPE3, OP) \ + v##NUM##TYPE2 __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##_##TYPE2##NUM (v##NUM##TYPE2 a, v##NUM##TYPE2 b, \ + v##NUM##TYPE c, int *restrict cond) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = cond[i] ? (TYPE3) b[i] OP (TYPE3) c[i] : a[i]; \ + return a; \ + } + +#define DEF_WFMA_VV(PREFIX, NUM, TYPE, TYPE2, TYPE3) \ + v##NUM##TYPE2 __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##TYPE2##TYPE3##NUM (v##NUM##TYPE2 a, v##NUM##TYPE b, \ + v##NUM##TYPE c, int *restrict cond) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = cond[i] ? (TYPE3) b[i] * (TYPE3) c[i] + a[i] : a[i]; \ + return a; \ + } + +#define DEF_WFNMA_VV(PREFIX, NUM, TYPE, TYPE2, TYPE3) \ + v##NUM##TYPE2 __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##TYPE2##TYPE3##NUM (v##NUM##TYPE2 a, v##NUM##TYPE b, \ + v##NUM##TYPE c, int *restrict cond) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = cond[i] ? a[i] - (TYPE3) b[i] * (TYPE3) c[i] : a[i]; \ + return a; \ + } + +#define DEF_WFMS_VV(PREFIX, NUM, TYPE, TYPE2, TYPE3) \ + v##NUM##TYPE2 __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##TYPE2##TYPE3##NUM (v##NUM##TYPE2 a, v##NUM##TYPE b, \ + v##NUM##TYPE c, int *restrict cond) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = cond[i] ? (TYPE3) b[i] * (TYPE3) c[i] - a[i] : a[i]; \ + return a; \ + } + +#define DEF_COND_NARROW_TRUNC_IMM(TYPE1, TYPE2, TYPE3, NUM) \ + v##NUM##TYPE1 narrow_##TYPE1##_##TYPE2##_##NUM (v##NUM##TYPE1 a, \ + v##NUM##TYPE2 b, \ + int *__restrict cond) \ + { \ + for (int i = 0; i < NUM; i += 1) \ + a[i] = cond[i] ? (TYPE3) (b[i] >> 7) : a[i]; \ + return a; \ + } + +#define DEF_COND_NARROW_TRUNC_XREG(TYPE1, TYPE2, TYPE3, NUM) \ + v##NUM##TYPE1 narrow_##TYPE1##_##TYPE2##_##NUM (v##NUM##TYPE1 a, \ + v##NUM##TYPE2 b, int shift, \ + int *__restrict cond) \ + { \ + for (int i = 0; i < NUM; i += 1) \ + a[i] = cond[i] ? (TYPE3) (b[i] >> shift) : a[i]; \ + return a; \ + } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c index 775ddb1..dd16368 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c @@ -2,30 +2,29 @@ /* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */ #include "def.h" -#include "math.h" -DEF_CALL_VV (max, 1, float, fmaxf) -DEF_CALL_VV (max, 2, float, fmaxf) -DEF_CALL_VV (max, 4, float, fmaxf) -DEF_CALL_VV (max, 8, float, fmaxf) -DEF_CALL_VV (max, 16, float, fmaxf) -DEF_CALL_VV (max, 32, float, fmaxf) -DEF_CALL_VV (max, 64, float, fmaxf) -DEF_CALL_VV (max, 128, float, fmaxf) -DEF_CALL_VV (max, 256, float, fmaxf) -DEF_CALL_VV (max, 512, float, fmaxf) -DEF_CALL_VV (max, 1024, float, fmaxf) +DEF_CALL_VV (max, 1, float, __builtin_fmaxf) +DEF_CALL_VV (max, 2, float, __builtin_fmaxf) +DEF_CALL_VV (max, 4, float, __builtin_fmaxf) +DEF_CALL_VV (max, 8, float, __builtin_fmaxf) +DEF_CALL_VV (max, 16, float, __builtin_fmaxf) +DEF_CALL_VV (max, 32, float, __builtin_fmaxf) +DEF_CALL_VV (max, 64, float, __builtin_fmaxf) +DEF_CALL_VV (max, 128, float, __builtin_fmaxf) +DEF_CALL_VV (max, 256, float, __builtin_fmaxf) +DEF_CALL_VV (max, 512, float, __builtin_fmaxf) +DEF_CALL_VV (max, 1024, float, __builtin_fmaxf) -DEF_CALL_VV (max, 1, double, fmax) -DEF_CALL_VV (max, 2, double, fmax) -DEF_CALL_VV (max, 4, double, fmax) -DEF_CALL_VV (max, 8, double, fmax) -DEF_CALL_VV (max, 16, double, fmax) -DEF_CALL_VV (max, 32, double, fmax) -DEF_CALL_VV (max, 64, double, fmax) -DEF_CALL_VV (max, 128, double, fmax) -DEF_CALL_VV (max, 256, double, fmax) -DEF_CALL_VV (max, 512, double, fmax) +DEF_CALL_VV (max, 1, double, __builtin_fmax) +DEF_CALL_VV (max, 2, double, __builtin_fmax) +DEF_CALL_VV (max, 4, double, __builtin_fmax) +DEF_CALL_VV (max, 8, double, __builtin_fmax) +DEF_CALL_VV (max, 16, double, __builtin_fmax) +DEF_CALL_VV (max, 32, double, __builtin_fmax) +DEF_CALL_VV (max, 64, double, __builtin_fmax) +DEF_CALL_VV (max, 128, double, __builtin_fmax) +DEF_CALL_VV (max, 256, double, __builtin_fmax) +DEF_CALL_VV (max, 512, double, __builtin_fmax) /* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c index 1e9ff7d..0e3cbf2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c @@ -2,30 +2,29 @@ /* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */ #include "def.h" -#include "math.h" -DEF_CALL_VV (min, 1, float, fminf) -DEF_CALL_VV (min, 2, float, fminf) -DEF_CALL_VV (min, 4, float, fminf) -DEF_CALL_VV (min, 8, float, fminf) -DEF_CALL_VV (min, 16, float, fminf) -DEF_CALL_VV (min, 32, float, fminf) -DEF_CALL_VV (min, 64, float, fminf) -DEF_CALL_VV (min, 128, float, fminf) -DEF_CALL_VV (min, 256, float, fminf) -DEF_CALL_VV (min, 512, float, fminf) -DEF_CALL_VV (min, 1024, float, fminf) +DEF_CALL_VV (min, 1, float, __builtin_fminf) +DEF_CALL_VV (min, 2, float, __builtin_fminf) +DEF_CALL_VV (min, 4, float, __builtin_fminf) +DEF_CALL_VV (min, 8, float, __builtin_fminf) +DEF_CALL_VV (min, 16, float, __builtin_fminf) +DEF_CALL_VV (min, 32, float, __builtin_fminf) +DEF_CALL_VV (min, 64, float, __builtin_fminf) +DEF_CALL_VV (min, 128, float, __builtin_fminf) +DEF_CALL_VV (min, 256, float, __builtin_fminf) +DEF_CALL_VV (min, 512, float, __builtin_fminf) +DEF_CALL_VV (min, 1024, float, __builtin_fminf) -DEF_CALL_VV (min, 1, double, fmin) -DEF_CALL_VV (min, 2, double, fmin) -DEF_CALL_VV (min, 4, double, fmin) -DEF_CALL_VV (min, 8, double, fmin) -DEF_CALL_VV (min, 16, double, fmin) -DEF_CALL_VV (min, 32, double, fmin) -DEF_CALL_VV (min, 64, double, fmin) -DEF_CALL_VV (min, 128, double, fmin) -DEF_CALL_VV (min, 256, double, fmin) -DEF_CALL_VV (min, 512, double, fmin) +DEF_CALL_VV (min, 1, double, __builtin_fmin) +DEF_CALL_VV (min, 2, double, __builtin_fmin) +DEF_CALL_VV (min, 4, double, __builtin_fmin) +DEF_CALL_VV (min, 8, double, __builtin_fmin) +DEF_CALL_VV (min, 16, double, __builtin_fmin) +DEF_CALL_VV (min, 32, double, __builtin_fmin) +DEF_CALL_VV (min, 64, double, __builtin_fmin) +DEF_CALL_VV (min, 128, double, __builtin_fmin) +DEF_CALL_VV (min, 256, double, __builtin_fmin) +DEF_CALL_VV (min, 512, double, __builtin_fmin) /* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c index 7e017de..ec9001f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c @@ -2,30 +2,29 @@ /* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */ #include "def.h" -#include <math.h> -DEF_SGNJX_VV (sgnj, 1, float, copysignf) -DEF_SGNJX_VV (sgnj, 2, float, copysignf) -DEF_SGNJX_VV (sgnj, 4, float, copysignf) -DEF_SGNJX_VV (sgnj, 8, float, copysignf) -DEF_SGNJX_VV (sgnj, 16, float, copysignf) -DEF_SGNJX_VV (sgnj, 32, float, copysignf) -DEF_SGNJX_VV (sgnj, 64, float, copysignf) -DEF_SGNJX_VV (sgnj, 128, float, copysignf) -DEF_SGNJX_VV (sgnj, 256, float, copysignf) -DEF_SGNJX_VV (sgnj, 512, float, copysignf) -DEF_SGNJX_VV (sgnj, 1024, float, copysignf) +DEF_SGNJX_VV (sgnj, 1, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 2, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 4, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 8, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 16, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 32, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 64, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 128, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 256, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 512, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 1024, float, __builtin_copysignf) -DEF_SGNJX_VV (sgnj, 1, double, copysign) -DEF_SGNJX_VV (sgnj, 2, double, copysign) -DEF_SGNJX_VV (sgnj, 4, double, copysign) -DEF_SGNJX_VV (sgnj, 8, double, copysign) -DEF_SGNJX_VV (sgnj, 16, double, copysign) -DEF_SGNJX_VV (sgnj, 32, double, copysign) -DEF_SGNJX_VV (sgnj, 64, double, copysign) -DEF_SGNJX_VV (sgnj, 128, double, copysign) -DEF_SGNJX_VV (sgnj, 256, double, copysign) -DEF_SGNJX_VV (sgnj, 512, double, copysign) +DEF_SGNJX_VV (sgnj, 1, double, __builtin_copysign) +DEF_SGNJX_VV (sgnj, 2, double, __builtin_copysign) +DEF_SGNJX_VV (sgnj, 4, double, __builtin_copysign) +DEF_SGNJX_VV (sgnj, 8, double, __builtin_copysign) +DEF_SGNJX_VV (sgnj, 16, double, __builtin_copysign) +DEF_SGNJX_VV (sgnj, 32, double, __builtin_copysign) +DEF_SGNJX_VV (sgnj, 64, double, __builtin_copysign) +DEF_SGNJX_VV (sgnj, 128, double, __builtin_copysign) +DEF_SGNJX_VV (sgnj, 256, double, __builtin_copysign) +DEF_SGNJX_VV (sgnj, 512, double, __builtin_copysign) /* { dg-final { scan-assembler-times {vfsgnjx\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ceil-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ceil-1.c new file mode 100644 index 0000000..b113df8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ceil-1.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_V (ceilf16, 1, _Float16, __builtin_ceilf16) +DEF_OP_V (ceilf16, 2, _Float16, __builtin_ceilf16) +DEF_OP_V (ceilf16, 4, _Float16, __builtin_ceilf16) +DEF_OP_V (ceilf16, 8, _Float16, __builtin_ceilf16) +DEF_OP_V (ceilf16, 16, _Float16, __builtin_ceilf16) +DEF_OP_V (ceilf16, 32, _Float16, __builtin_ceilf16) +DEF_OP_V (ceilf16, 64, _Float16, __builtin_ceilf16) +DEF_OP_V (ceilf16, 128, _Float16, __builtin_ceilf16) +DEF_OP_V (ceilf16, 256, _Float16, __builtin_ceilf16) +DEF_OP_V (ceilf16, 512, _Float16, __builtin_ceilf16) +DEF_OP_V (ceilf16, 1024, _Float16, __builtin_ceilf16) +DEF_OP_V (ceilf16, 2048, _Float16, __builtin_ceilf16) + +DEF_OP_V (ceilf, 1, float, __builtin_ceilf) +DEF_OP_V (ceilf, 2, float, __builtin_ceilf) +DEF_OP_V (ceilf, 4, float, __builtin_ceilf) +DEF_OP_V (ceilf, 8, float, __builtin_ceilf) +DEF_OP_V (ceilf, 16, float, __builtin_ceilf) +DEF_OP_V (ceilf, 32, float, __builtin_ceilf) +DEF_OP_V (ceilf, 64, float, __builtin_ceilf) +DEF_OP_V (ceilf, 128, float, __builtin_ceilf) +DEF_OP_V (ceilf, 256, float, __builtin_ceilf) +DEF_OP_V (ceilf, 512, float, __builtin_ceilf) +DEF_OP_V (ceilf, 1024, float, __builtin_ceilf) + +DEF_OP_V (ceil, 1, double, __builtin_ceil) +DEF_OP_V (ceil, 2, double, __builtin_ceil) +DEF_OP_V (ceil, 4, double, __builtin_ceil) +DEF_OP_V (ceil, 8, double, __builtin_ceil) +DEF_OP_V (ceil, 16, double, __builtin_ceil) +DEF_OP_V (ceil, 32, double, __builtin_ceil) +DEF_OP_V (ceil, 64, double, __builtin_ceil) +DEF_OP_V (ceil, 128, double, __builtin_ceil) +DEF_OP_V (ceil, 256, double, __builtin_ceil) +DEF_OP_V (ceil, 512, double, __builtin_ceil) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ +/* { dg-final { scan-assembler-times {vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ +/* { dg-final { scan-assembler-times {vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-floor-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-floor-1.c new file mode 100644 index 0000000..076580e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-floor-1.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_V (floorf16, 1, _Float16, __builtin_floorf16) +DEF_OP_V (floorf16, 2, _Float16, __builtin_floorf16) +DEF_OP_V (floorf16, 4, _Float16, __builtin_floorf16) +DEF_OP_V (floorf16, 8, _Float16, __builtin_floorf16) +DEF_OP_V (floorf16, 16, _Float16, __builtin_floorf16) +DEF_OP_V (floorf16, 32, _Float16, __builtin_floorf16) +DEF_OP_V (floorf16, 64, _Float16, __builtin_floorf16) +DEF_OP_V (floorf16, 128, _Float16, __builtin_floorf16) +DEF_OP_V (floorf16, 256, _Float16, __builtin_floorf16) +DEF_OP_V (floorf16, 512, _Float16, __builtin_floorf16) +DEF_OP_V (floorf16, 1024, _Float16, __builtin_floorf16) +DEF_OP_V (floorf16, 2048, _Float16, __builtin_floorf16) + +DEF_OP_V (floorf, 1, float, __builtin_floorf) +DEF_OP_V (floorf, 2, float, __builtin_floorf) +DEF_OP_V (floorf, 4, float, __builtin_floorf) +DEF_OP_V (floorf, 8, float, __builtin_floorf) +DEF_OP_V (floorf, 16, float, __builtin_floorf) +DEF_OP_V (floorf, 32, float, __builtin_floorf) +DEF_OP_V (floorf, 64, float, __builtin_floorf) +DEF_OP_V (floorf, 128, float, __builtin_floorf) +DEF_OP_V (floorf, 256, float, __builtin_floorf) +DEF_OP_V (floorf, 512, float, __builtin_floorf) +DEF_OP_V (floorf, 1024, float, __builtin_floorf) + +DEF_OP_V (floor, 1, double, __builtin_floor) +DEF_OP_V (floor, 2, double, __builtin_floor) +DEF_OP_V (floor, 4, double, __builtin_floor) +DEF_OP_V (floor, 8, double, __builtin_floor) +DEF_OP_V (floor, 16, double, __builtin_floor) +DEF_OP_V (floor, 32, double, __builtin_floor) +DEF_OP_V (floor, 64, double, __builtin_floor) +DEF_OP_V (floor, 128, double, __builtin_floor) +DEF_OP_V (floor, 256, double, __builtin_floor) +DEF_OP_V (floor, 512, double, __builtin_floor) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ +/* { dg-final { scan-assembler-times {vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ +/* { dg-final { scan-assembler-times {vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c new file mode 100644 index 0000000..8c8498c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_V (nearbyintf16, 1, _Float16, __builtin_nearbyintf16) +DEF_OP_V (nearbyintf16, 2, _Float16, __builtin_nearbyintf16) +DEF_OP_V (nearbyintf16, 4, _Float16, __builtin_nearbyintf16) +DEF_OP_V (nearbyintf16, 8, _Float16, __builtin_nearbyintf16) +DEF_OP_V (nearbyintf16, 16, _Float16, __builtin_nearbyintf16) +DEF_OP_V (nearbyintf16, 32, _Float16, __builtin_nearbyintf16) +DEF_OP_V (nearbyintf16, 64, _Float16, __builtin_nearbyintf16) +DEF_OP_V (nearbyintf16, 128, _Float16, __builtin_nearbyintf16) +DEF_OP_V (nearbyintf16, 256, _Float16, __builtin_nearbyintf16) +DEF_OP_V (nearbyintf16, 512, _Float16, __builtin_nearbyintf16) +DEF_OP_V (nearbyintf16, 1024, _Float16, __builtin_nearbyintf16) +DEF_OP_V (nearbyintf16, 2048, _Float16, __builtin_nearbyintf16) + +DEF_OP_V (nearbyintf, 1, float, __builtin_nearbyintf) +DEF_OP_V (nearbyintf, 2, float, __builtin_nearbyintf) +DEF_OP_V (nearbyintf, 4, float, __builtin_nearbyintf) +DEF_OP_V (nearbyintf, 8, float, __builtin_nearbyintf) +DEF_OP_V (nearbyintf, 16, float, __builtin_nearbyintf) +DEF_OP_V (nearbyintf, 32, float, __builtin_nearbyintf) +DEF_OP_V (nearbyintf, 64, float, __builtin_nearbyintf) +DEF_OP_V (nearbyintf, 128, float, __builtin_nearbyintf) +DEF_OP_V (nearbyintf, 256, float, __builtin_nearbyintf) +DEF_OP_V (nearbyintf, 512, float, __builtin_nearbyintf) +DEF_OP_V (nearbyintf, 1024, float, __builtin_nearbyintf) + +DEF_OP_V (nearbyint, 1, double, __builtin_nearbyint) +DEF_OP_V (nearbyint, 2, double, __builtin_nearbyint) +DEF_OP_V (nearbyint, 4, double, __builtin_nearbyint) +DEF_OP_V (nearbyint, 8, double, __builtin_nearbyint) +DEF_OP_V (nearbyint, 16, double, __builtin_nearbyint) +DEF_OP_V (nearbyint, 32, double, __builtin_nearbyint) +DEF_OP_V (nearbyint, 64, double, __builtin_nearbyint) +DEF_OP_V (nearbyint, 128, double, __builtin_nearbyint) +DEF_OP_V (nearbyint, 256, double, __builtin_nearbyint) +DEF_OP_V (nearbyint, 512, double, __builtin_nearbyint) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ +/* { dg-final { scan-assembler-times {vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ +/* { dg-final { scan-assembler-times {vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ +/* { dg-final { scan-assembler-times {frflags\s+[atx][0-9]+} 30 } } */ +/* { dg-final { scan-assembler-times {fsflags\s+[atx][0-9]+} 30 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-rint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-rint-1.c new file mode 100644 index 0000000..cf10d61 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-rint-1.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_V (rintf16, 1, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 2, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 4, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 8, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 16, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 32, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 64, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 128, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 256, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 512, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 1024, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 2048, _Float16, __builtin_rintf16) + +DEF_OP_V (rintf, 1, float, __builtin_rintf) +DEF_OP_V (rintf, 2, float, __builtin_rintf) +DEF_OP_V (rintf, 4, float, __builtin_rintf) +DEF_OP_V (rintf, 8, float, __builtin_rintf) +DEF_OP_V (rintf, 16, float, __builtin_rintf) +DEF_OP_V (rintf, 32, float, __builtin_rintf) +DEF_OP_V (rintf, 64, float, __builtin_rintf) +DEF_OP_V (rintf, 128, float, __builtin_rintf) +DEF_OP_V (rintf, 256, float, __builtin_rintf) +DEF_OP_V (rintf, 512, float, __builtin_rintf) +DEF_OP_V (rintf, 1024, float, __builtin_rintf) + +DEF_OP_V (rint, 1, double, __builtin_rint) +DEF_OP_V (rint, 2, double, __builtin_rint) +DEF_OP_V (rint, 4, double, __builtin_rint) +DEF_OP_V (rint, 8, double, __builtin_rint) +DEF_OP_V (rint, 16, double, __builtin_rint) +DEF_OP_V (rint, 32, double, __builtin_rint) +DEF_OP_V (rint, 64, double, __builtin_rint) +DEF_OP_V (rint, 128, double, __builtin_rint) +DEF_OP_V (rint, 256, double, __builtin_rint) +DEF_OP_V (rint, 512, double, __builtin_rint) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ +/* { dg-final { scan-assembler-not {frflags\s+[atx][0-9]+} } } */ +/* { dg-final { scan-assembler-not {fsflags\s+[atx][0-9]+} } } */ +/* { dg-final { scan-assembler-times {vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ +/* { dg-final { scan-assembler-times {vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-round-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-round-1.c new file mode 100644 index 0000000..97fd697 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-round-1.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_V (roundf16, 1, _Float16, __builtin_roundf16) +DEF_OP_V (roundf16, 2, _Float16, __builtin_roundf16) +DEF_OP_V (roundf16, 4, _Float16, __builtin_roundf16) +DEF_OP_V (roundf16, 8, _Float16, __builtin_roundf16) +DEF_OP_V (roundf16, 16, _Float16, __builtin_roundf16) +DEF_OP_V (roundf16, 32, _Float16, __builtin_roundf16) +DEF_OP_V (roundf16, 64, _Float16, __builtin_roundf16) +DEF_OP_V (roundf16, 128, _Float16, __builtin_roundf16) +DEF_OP_V (roundf16, 256, _Float16, __builtin_roundf16) +DEF_OP_V (roundf16, 512, _Float16, __builtin_roundf16) +DEF_OP_V (roundf16, 1024, _Float16, __builtin_roundf16) +DEF_OP_V (roundf16, 2048, _Float16, __builtin_roundf16) + +DEF_OP_V (roundf, 1, float, __builtin_roundf) +DEF_OP_V (roundf, 2, float, __builtin_roundf) +DEF_OP_V (roundf, 4, float, __builtin_roundf) +DEF_OP_V (roundf, 8, float, __builtin_roundf) +DEF_OP_V (roundf, 16, float, __builtin_roundf) +DEF_OP_V (roundf, 32, float, __builtin_roundf) +DEF_OP_V (roundf, 64, float, __builtin_roundf) +DEF_OP_V (roundf, 128, float, __builtin_roundf) +DEF_OP_V (roundf, 256, float, __builtin_roundf) +DEF_OP_V (roundf, 512, float, __builtin_roundf) +DEF_OP_V (roundf, 1024, float, __builtin_roundf) + +DEF_OP_V (round, 1, double, __builtin_round) +DEF_OP_V (round, 2, double, __builtin_round) +DEF_OP_V (round, 4, double, __builtin_round) +DEF_OP_V (round, 8, double, __builtin_round) +DEF_OP_V (round, 16, double, __builtin_round) +DEF_OP_V (round, 32, double, __builtin_round) +DEF_OP_V (round, 64, double, __builtin_round) +DEF_OP_V (round, 128, double, __builtin_round) +DEF_OP_V (round, 256, double, __builtin_round) +DEF_OP_V (round, 512, double, __builtin_round) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ +/* { dg-final { scan-assembler-times {vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ +/* { dg-final { scan-assembler-times {vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-roundeven-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-roundeven-1.c new file mode 100644 index 0000000..8489d39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-roundeven-1.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_V (roundevenf16, 1, _Float16, __builtin_roundevenf16) +DEF_OP_V (roundevenf16, 2, _Float16, __builtin_roundevenf16) +DEF_OP_V (roundevenf16, 4, _Float16, __builtin_roundevenf16) +DEF_OP_V (roundevenf16, 8, _Float16, __builtin_roundevenf16) +DEF_OP_V (roundevenf16, 16, _Float16, __builtin_roundevenf16) +DEF_OP_V (roundevenf16, 32, _Float16, __builtin_roundevenf16) +DEF_OP_V (roundevenf16, 64, _Float16, __builtin_roundevenf16) +DEF_OP_V (roundevenf16, 128, _Float16, __builtin_roundevenf16) +DEF_OP_V (roundevenf16, 256, _Float16, __builtin_roundevenf16) +DEF_OP_V (roundevenf16, 512, _Float16, __builtin_roundevenf16) +DEF_OP_V (roundevenf16, 1024, _Float16, __builtin_roundevenf16) +DEF_OP_V (roundevenf16, 2048, _Float16, __builtin_roundevenf16) + +DEF_OP_V (roundevenf, 1, float, __builtin_roundevenf) +DEF_OP_V (roundevenf, 2, float, __builtin_roundevenf) +DEF_OP_V (roundevenf, 4, float, __builtin_roundevenf) +DEF_OP_V (roundevenf, 8, float, __builtin_roundevenf) +DEF_OP_V (roundevenf, 16, float, __builtin_roundevenf) +DEF_OP_V (roundevenf, 32, float, __builtin_roundevenf) +DEF_OP_V (roundevenf, 64, float, __builtin_roundevenf) +DEF_OP_V (roundevenf, 128, float, __builtin_roundevenf) +DEF_OP_V (roundevenf, 256, float, __builtin_roundevenf) +DEF_OP_V (roundevenf, 512, float, __builtin_roundevenf) +DEF_OP_V (roundevenf, 1024, float, __builtin_roundevenf) + +DEF_OP_V (roundeven, 1, double, __builtin_roundeven) +DEF_OP_V (roundeven, 2, double, __builtin_roundeven) +DEF_OP_V (roundeven, 4, double, __builtin_roundeven) +DEF_OP_V (roundeven, 8, double, __builtin_roundeven) +DEF_OP_V (roundeven, 16, double, __builtin_roundeven) +DEF_OP_V (roundeven, 32, double, __builtin_roundeven) +DEF_OP_V (roundeven, 64, double, __builtin_roundeven) +DEF_OP_V (roundeven, 128, double, __builtin_roundeven) +DEF_OP_V (roundeven, 256, double, __builtin_roundeven) +DEF_OP_V (roundeven, 512, double, __builtin_roundeven) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ +/* { dg-final { scan-assembler-times {vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ +/* { dg-final { scan-assembler-times {vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c new file mode 100644 index 0000000..51211bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_V (truncf16, 1, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 2, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 4, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 8, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 16, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 32, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 64, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 128, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 256, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 512, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 1024, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 2048, _Float16, __builtin_truncf16) + +DEF_OP_V (truncf, 1, float, __builtin_truncf) +DEF_OP_V (truncf, 2, float, __builtin_truncf) +DEF_OP_V (truncf, 4, float, __builtin_truncf) +DEF_OP_V (truncf, 8, float, __builtin_truncf) +DEF_OP_V (truncf, 16, float, __builtin_truncf) +DEF_OP_V (truncf, 32, float, __builtin_truncf) +DEF_OP_V (truncf, 64, float, __builtin_truncf) +DEF_OP_V (truncf, 128, float, __builtin_truncf) +DEF_OP_V (truncf, 256, float, __builtin_truncf) +DEF_OP_V (truncf, 512, float, __builtin_truncf) +DEF_OP_V (truncf, 1024, float, __builtin_truncf) + +DEF_OP_V (trunc, 1, double, __builtin_trunc) +DEF_OP_V (trunc, 2, double, __builtin_trunc) +DEF_OP_V (trunc, 4, double, __builtin_trunc) +DEF_OP_V (trunc, 8, double, __builtin_trunc) +DEF_OP_V (trunc, 16, double, __builtin_trunc) +DEF_OP_V (trunc, 32, double, __builtin_trunc) +DEF_OP_V (trunc, 64, double, __builtin_trunc) +DEF_OP_V (trunc, 128, double, __builtin_trunc) +DEF_OP_V (trunc, 256, double, __builtin_trunc) +DEF_OP_V (trunc, 512, double, __builtin_trunc) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ +/* { dg-final { scan-assembler-times {vfcvt\.rtz\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ +/* { dg-final { scan-assembler-times {vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mulh-1.c new file mode 100644 index 0000000..47bb40f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mulh-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_MULH (int8_t, 4) +DEF_MULH (int8_t, 8) +DEF_MULH (int8_t, 16) +DEF_MULH (int8_t, 32) +DEF_MULH (int8_t, 64) +DEF_MULH (int8_t, 128) +DEF_MULH (int8_t, 256) +DEF_MULH (int8_t, 512) +DEF_MULH (int8_t, 1024) +DEF_MULH (int8_t, 2048) +DEF_MULH (int8_t, 4096) + +DEF_MULH (int16_t, 4) +DEF_MULH (int16_t, 8) +DEF_MULH (int16_t, 16) +DEF_MULH (int16_t, 32) +DEF_MULH (int16_t, 64) +DEF_MULH (int16_t, 128) +DEF_MULH (int16_t, 256) +DEF_MULH (int16_t, 512) +DEF_MULH (int16_t, 1024) +DEF_MULH (int16_t, 2048) + +DEF_MULH (int32_t, 4) +DEF_MULH (int32_t, 8) +DEF_MULH (int32_t, 16) +DEF_MULH (int32_t, 32) +DEF_MULH (int32_t, 64) +DEF_MULH (int32_t, 128) +DEF_MULH (int32_t, 256) +DEF_MULH (int32_t, 512) +DEF_MULH (int32_t, 1024) + +DEF_MULH (int64_t, 4) +DEF_MULH (int64_t, 8) +DEF_MULH (int64_t, 16) +DEF_MULH (int64_t, 32) +DEF_MULH (int64_t, 64) +DEF_MULH (int64_t, 128) +DEF_MULH (int64_t, 256) +DEF_MULH (int64_t, 512) + +DEF_MULH (uint8_t, 4) +DEF_MULH (uint8_t, 8) +DEF_MULH (uint8_t, 16) +DEF_MULH (uint8_t, 32) +DEF_MULH (uint8_t, 64) +DEF_MULH (uint8_t, 128) +DEF_MULH (uint8_t, 256) +DEF_MULH (uint8_t, 512) +DEF_MULH (uint8_t, 1024) +DEF_MULH (uint8_t, 2048) +DEF_MULH (uint8_t, 4096) + +DEF_MULH (uint16_t, 4) +DEF_MULH (uint16_t, 8) +DEF_MULH (uint16_t, 16) +DEF_MULH (uint16_t, 32) +DEF_MULH (uint16_t, 64) +DEF_MULH (uint16_t, 128) +DEF_MULH (uint16_t, 256) +DEF_MULH (uint16_t, 512) +DEF_MULH (uint16_t, 1024) +DEF_MULH (uint16_t, 2048) + +DEF_MULH (uint32_t, 4) +DEF_MULH (uint32_t, 8) +DEF_MULH (uint32_t, 16) +DEF_MULH (uint32_t, 32) +DEF_MULH (uint32_t, 64) +DEF_MULH (uint32_t, 128) +DEF_MULH (uint32_t, 256) +DEF_MULH (uint32_t, 512) +DEF_MULH (uint32_t, 1024) + +DEF_MULH (uint64_t, 4) +DEF_MULH (uint64_t, 8) +DEF_MULH (uint64_t, 16) +DEF_MULH (uint64_t, 32) +DEF_MULH (uint64_t, 64) +DEF_MULH (uint64_t, 128) +DEF_MULH (uint64_t, 256) +DEF_MULH (uint64_t, 512) + +/* { dg-final { scan-assembler-times {vmulh\.} 38 } } */ +/* { dg-final { scan-assembler-times {vmulhu\.} 38 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-1.c new file mode 100644 index 0000000..ca6b856 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-1.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 4) +DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 8) +DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 16) +DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 32) +DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 64) +DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 128) +DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 256) +DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 512) +DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 1024) +DEF_NARROW_TRUNC_IMM (int8_t, int16_t, 2048) + +DEF_NARROW_TRUNC_IMM (int16_t, int32_t, 4) +DEF_NARROW_TRUNC_IMM (int16_t, int32_t, 8) +DEF_NARROW_TRUNC_IMM (int16_t, int32_t, 16) +DEF_NARROW_TRUNC_IMM (int16_t, int32_t, 32) +DEF_NARROW_TRUNC_IMM (int16_t, int32_t, 64) +DEF_NARROW_TRUNC_IMM (int16_t, int32_t, 128) +DEF_NARROW_TRUNC_IMM (int16_t, int32_t, 256) +DEF_NARROW_TRUNC_IMM (int16_t, int32_t, 512) +DEF_NARROW_TRUNC_IMM (int16_t, int32_t, 1024) + +DEF_NARROW_TRUNC_IMM (int32_t, int64_t, 4) +DEF_NARROW_TRUNC_IMM (int32_t, int64_t, 8) +DEF_NARROW_TRUNC_IMM (int32_t, int64_t, 16) +DEF_NARROW_TRUNC_IMM (int32_t, int64_t, 32) +DEF_NARROW_TRUNC_IMM (int32_t, int64_t, 64) +DEF_NARROW_TRUNC_IMM (int32_t, int64_t, 128) +DEF_NARROW_TRUNC_IMM (int32_t, int64_t, 256) +DEF_NARROW_TRUNC_IMM (int32_t, int64_t, 512) + +/* { dg-final { scan-assembler-times {vnsra\.wi} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-2.c new file mode 100644 index 0000000..3838ee5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-2.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_NARROW_TRUNC_XREG (int32_t, int64_t, 4) +DEF_NARROW_TRUNC_XREG (int32_t, int64_t, 8) +DEF_NARROW_TRUNC_XREG (int32_t, int64_t, 16) +DEF_NARROW_TRUNC_XREG (int32_t, int64_t, 32) +DEF_NARROW_TRUNC_XREG (int32_t, int64_t, 64) +DEF_NARROW_TRUNC_XREG (int32_t, int64_t, 128) +DEF_NARROW_TRUNC_XREG (int32_t, int64_t, 256) +DEF_NARROW_TRUNC_XREG (int32_t, int64_t, 512) + +/* { dg-final { scan-assembler-times {vnsra\.wx} 8 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-3.c new file mode 100644 index 0000000..03d03dc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-3.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_NARROW_TRUNC_VREG (int32_t, int64_t, 4) +DEF_NARROW_TRUNC_VREG (int32_t, int64_t, 8) +DEF_NARROW_TRUNC_VREG (int32_t, int64_t, 16) +DEF_NARROW_TRUNC_VREG (int32_t, int64_t, 32) +DEF_NARROW_TRUNC_VREG (int32_t, int64_t, 64) +DEF_NARROW_TRUNC_VREG (int32_t, int64_t, 128) +DEF_NARROW_TRUNC_VREG (int32_t, int64_t, 256) +DEF_NARROW_TRUNC_VREG (int32_t, int64_t, 512) + +/* { dg-final { scan-assembler-times {vnsra\.wv} 8 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/not-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/not-1.c new file mode 100644 index 0000000..316bac8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/not-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_V (not, 1, int8_t, ~) +DEF_OP_V (not, 2, int8_t, ~) +DEF_OP_V (not, 4, int8_t, ~) +DEF_OP_V (not, 8, int8_t, ~) +DEF_OP_V (not, 16, int8_t, ~) +DEF_OP_V (not, 32, int8_t, ~) +DEF_OP_V (not, 64, int8_t, ~) +DEF_OP_V (not, 128, int8_t, ~) +DEF_OP_V (not, 256, int8_t, ~) +DEF_OP_V (not, 512, int8_t, ~) +DEF_OP_V (not, 1024, int8_t, ~) +DEF_OP_V (not, 2048, int8_t, ~) +DEF_OP_V (not, 4096, int8_t, ~) + +DEF_OP_V (not, 1, int16_t, ~) +DEF_OP_V (not, 2, int16_t, ~) +DEF_OP_V (not, 4, int16_t, ~) +DEF_OP_V (not, 8, int16_t, ~) +DEF_OP_V (not, 16, int16_t, ~) +DEF_OP_V (not, 32, int16_t, ~) +DEF_OP_V (not, 64, int16_t, ~) +DEF_OP_V (not, 128, int16_t, ~) +DEF_OP_V (not, 256, int16_t, ~) +DEF_OP_V (not, 512, int16_t, ~) +DEF_OP_V (not, 1024, int16_t, ~) +DEF_OP_V (not, 2048, int16_t, ~) + +DEF_OP_V (not, 1, int32_t, ~) +DEF_OP_V (not, 2, int32_t, ~) +DEF_OP_V (not, 4, int32_t, ~) +DEF_OP_V (not, 8, int32_t, ~) +DEF_OP_V (not, 16, int32_t, ~) +DEF_OP_V (not, 32, int32_t, ~) +DEF_OP_V (not, 64, int32_t, ~) +DEF_OP_V (not, 128, int32_t, ~) +DEF_OP_V (not, 256, int32_t, ~) +DEF_OP_V (not, 512, int32_t, ~) +DEF_OP_V (not, 1024, int32_t, ~) + +DEF_OP_V (not, 1, int64_t, ~) +DEF_OP_V (not, 2, int64_t, ~) +DEF_OP_V (not, 4, int64_t, ~) +DEF_OP_V (not, 8, int64_t, ~) +DEF_OP_V (not, 16, int64_t, ~) +DEF_OP_V (not, 32, int64_t, ~) +DEF_OP_V (not, 64, int64_t, ~) +DEF_OP_V (not, 128, int64_t, ~) +DEF_OP_V (not, 256, int64_t, ~) +DEF_OP_V (not, 512, int64_t, ~) + +/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,\s*v[0-9]+} 42 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c index 46cad8e..4d6862c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c @@ -3,6 +3,7 @@ #include "../vls-vlmax/perm-4.c" -/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */ +/* { dg-final { scan-assembler-times {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */ +/* { dg-final { scan-assembler-times {vrgatherei16\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 12 } } */ /* { dg-final { scan-assembler-times {vrsub\.vi} 24 } } */ /* { dg-final { scan-assembler-times {vrsub\.vx} 7 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/sqrt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/sqrt-1.c new file mode 100644 index 0000000..60dbfd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/sqrt-1.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_V (sqrt, 2, _Float16, __builtin_sqrtf16) +DEF_OP_V (sqrt, 4, _Float16, __builtin_sqrtf16) +DEF_OP_V (sqrt, 8, _Float16, __builtin_sqrtf16) +DEF_OP_V (sqrt, 16, _Float16, __builtin_sqrtf16) +DEF_OP_V (sqrt, 32, _Float16, __builtin_sqrtf16) +DEF_OP_V (sqrt, 64, _Float16, __builtin_sqrtf16) +DEF_OP_V (sqrt, 128, _Float16, __builtin_sqrtf16) +DEF_OP_V (sqrt, 256, _Float16, __builtin_sqrtf16) +DEF_OP_V (sqrt, 512, _Float16, __builtin_sqrtf16) +DEF_OP_V (sqrt, 1024, _Float16, __builtin_sqrtf16) +DEF_OP_V (sqrt, 2048, _Float16, __builtin_sqrtf16) + +DEF_OP_V (sqrt, 2, float, __builtin_sqrtf) +DEF_OP_V (sqrt, 4, float, __builtin_sqrtf) +DEF_OP_V (sqrt, 8, float, __builtin_sqrtf) +DEF_OP_V (sqrt, 16, float, __builtin_sqrtf) +DEF_OP_V (sqrt, 32, float, __builtin_sqrtf) +DEF_OP_V (sqrt, 64, float, __builtin_sqrtf) +DEF_OP_V (sqrt, 128, float, __builtin_sqrtf) +DEF_OP_V (sqrt, 256, float, __builtin_sqrtf) +DEF_OP_V (sqrt, 512, float, __builtin_sqrtf) +DEF_OP_V (sqrt, 1024, float, __builtin_sqrtf) + +DEF_OP_V (sqrt, 2, double, __builtin_sqrt) +DEF_OP_V (sqrt, 4, double, __builtin_sqrt) +DEF_OP_V (sqrt, 8, double, __builtin_sqrt) +DEF_OP_V (sqrt, 16, double, __builtin_sqrt) +DEF_OP_V (sqrt, 32, double, __builtin_sqrt) +DEF_OP_V (sqrt, 64, double, __builtin_sqrt) +DEF_OP_V (sqrt, 128, double, __builtin_sqrt) +DEF_OP_V (sqrt, 256, double, __builtin_sqrt) +DEF_OP_V (sqrt, 512, double, __builtin_sqrt) + +/* { dg-final { scan-assembler-times {vfsqrt\.v\s+v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-1.c new file mode 100644 index 0000000..bce56b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-1.c @@ -0,0 +1,80 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_WVV(wadd, 4, int8_t, int16_t, +) +DEF_OP_WVV(wadd, 8, int8_t, int16_t, +) +DEF_OP_WVV(wadd, 16, int8_t, int16_t, +) +DEF_OP_WVV(wadd, 32, int8_t, int16_t, +) +DEF_OP_WVV(wadd, 64, int8_t, int16_t, +) +DEF_OP_WVV(wadd, 128, int8_t, int16_t, +) +DEF_OP_WVV(wadd, 256, int8_t, int16_t, +) +DEF_OP_WVV(wadd, 512, int8_t, int16_t, +) +DEF_OP_WVV(wadd, 1024, int8_t, int16_t, +) +DEF_OP_WVV(wadd, 2048, int8_t, int16_t, +) + +DEF_OP_WVV(wadd, 4, int16_t, int32_t, +) +DEF_OP_WVV(wadd, 8, int16_t, int32_t, +) +DEF_OP_WVV(wadd, 16, int16_t, int32_t, +) +DEF_OP_WVV(wadd, 32, int16_t, int32_t, +) +DEF_OP_WVV(wadd, 64, int16_t, int32_t, +) +DEF_OP_WVV(wadd, 128, int16_t, int32_t, +) +DEF_OP_WVV(wadd, 256, int16_t, int32_t, +) +DEF_OP_WVV(wadd, 512, int16_t, int32_t, +) +DEF_OP_WVV(wadd, 1024, int16_t, int32_t, +) + +DEF_OP_WVV(wadd, 4, int32_t, int64_t, +) +DEF_OP_WVV(wadd, 8, int32_t, int64_t, +) +DEF_OP_WVV(wadd, 16, int32_t, int64_t, +) +DEF_OP_WVV(wadd, 32, int32_t, int64_t, +) +DEF_OP_WVV(wadd, 64, int32_t, int64_t, +) +DEF_OP_WVV(wadd, 128, int32_t, int64_t, +) +DEF_OP_WVV(wadd, 256, int32_t, int64_t, +) +DEF_OP_WVV(wadd, 512, int32_t, int64_t, +) + +DEF_OP_WVV(wadd, 4, uint8_t, uint16_t, +) +DEF_OP_WVV(wadd, 8, uint8_t, uint16_t, +) +DEF_OP_WVV(wadd, 16, uint8_t, uint16_t, +) +DEF_OP_WVV(wadd, 32, uint8_t, uint16_t, +) +DEF_OP_WVV(wadd, 64, uint8_t, uint16_t, +) +DEF_OP_WVV(wadd, 128, uint8_t, uint16_t, +) +DEF_OP_WVV(wadd, 256, uint8_t, uint16_t, +) +DEF_OP_WVV(wadd, 512, uint8_t, uint16_t, +) +DEF_OP_WVV(wadd, 1024, uint8_t, uint16_t, +) +DEF_OP_WVV(wadd, 2048, uint8_t, uint16_t, +) + +DEF_OP_WVV(wadd, 4, uint16_t, uint32_t, +) +DEF_OP_WVV(wadd, 8, uint16_t, uint32_t, +) +DEF_OP_WVV(wadd, 16, uint16_t, uint32_t, +) +DEF_OP_WVV(wadd, 32, uint16_t, uint32_t, +) +DEF_OP_WVV(wadd, 64, uint16_t, uint32_t, +) +DEF_OP_WVV(wadd, 128, uint16_t, uint32_t, +) +DEF_OP_WVV(wadd, 256, uint16_t, uint32_t, +) +DEF_OP_WVV(wadd, 512, uint16_t, uint32_t, +) +DEF_OP_WVV(wadd, 1024, uint16_t, uint32_t, +) + +DEF_OP_WVV(wadd, 4, uint32_t, uint64_t, +) +DEF_OP_WVV(wadd, 8, uint32_t, uint64_t, +) +DEF_OP_WVV(wadd, 16, uint32_t, uint64_t, +) +DEF_OP_WVV(wadd, 32, uint32_t, uint64_t, +) +DEF_OP_WVV(wadd, 64, uint32_t, uint64_t, +) +DEF_OP_WVV(wadd, 128, uint32_t, uint64_t, +) +DEF_OP_WVV(wadd, 256, uint32_t, uint64_t, +) +DEF_OP_WVV(wadd, 512, uint32_t, uint64_t, +) + +/* { dg-final { scan-assembler-times {vwadd\.vv} 27 } } */ +/* { dg-final { scan-assembler-times {vwaddu\.vv} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-2.c new file mode 100644 index 0000000..d0b55c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-2.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_WVV(wadd, 4, _Float16, float, +) +DEF_OP_WVV(wadd, 8, _Float16, float, +) +DEF_OP_WVV(wadd, 16, _Float16, float, +) +DEF_OP_WVV(wadd, 32, _Float16, float, +) +DEF_OP_WVV(wadd, 64, _Float16, float, +) +DEF_OP_WVV(wadd, 128, _Float16, float, +) +DEF_OP_WVV(wadd, 256, _Float16, float, +) +DEF_OP_WVV(wadd, 512, _Float16, float, +) +DEF_OP_WVV(wadd, 1024, _Float16, float, +) + +DEF_OP_WVV(wadd, 4, float, double, +) +DEF_OP_WVV(wadd, 8, float, double, +) +DEF_OP_WVV(wadd, 16, float, double, +) +DEF_OP_WVV(wadd, 32, float, double, +) +DEF_OP_WVV(wadd, 64, float, double, +) +DEF_OP_WVV(wadd, 128, float, double, +) +DEF_OP_WVV(wadd, 256, float, double, +) +DEF_OP_WVV(wadd, 512, float, double, +) + +/* { dg-final { scan-assembler-times {vfwadd\.vv} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-3.c new file mode 100644 index 0000000..b6067c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-3.c @@ -0,0 +1,80 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_WWV(wadd, 4, int8_t, int16_t, +) +DEF_OP_WWV(wadd, 8, int8_t, int16_t, +) +DEF_OP_WWV(wadd, 16, int8_t, int16_t, +) +DEF_OP_WWV(wadd, 32, int8_t, int16_t, +) +DEF_OP_WWV(wadd, 64, int8_t, int16_t, +) +DEF_OP_WWV(wadd, 128, int8_t, int16_t, +) +DEF_OP_WWV(wadd, 256, int8_t, int16_t, +) +DEF_OP_WWV(wadd, 512, int8_t, int16_t, +) +DEF_OP_WWV(wadd, 1024, int8_t, int16_t, +) +DEF_OP_WWV(wadd, 2048, int8_t, int16_t, +) + +DEF_OP_WWV(wadd, 4, int16_t, int32_t, +) +DEF_OP_WWV(wadd, 8, int16_t, int32_t, +) +DEF_OP_WWV(wadd, 16, int16_t, int32_t, +) +DEF_OP_WWV(wadd, 32, int16_t, int32_t, +) +DEF_OP_WWV(wadd, 64, int16_t, int32_t, +) +DEF_OP_WWV(wadd, 128, int16_t, int32_t, +) +DEF_OP_WWV(wadd, 256, int16_t, int32_t, +) +DEF_OP_WWV(wadd, 512, int16_t, int32_t, +) +DEF_OP_WWV(wadd, 1024, int16_t, int32_t, +) + +DEF_OP_WWV(wadd, 4, int32_t, int64_t, +) +DEF_OP_WWV(wadd, 8, int32_t, int64_t, +) +DEF_OP_WWV(wadd, 16, int32_t, int64_t, +) +DEF_OP_WWV(wadd, 32, int32_t, int64_t, +) +DEF_OP_WWV(wadd, 64, int32_t, int64_t, +) +DEF_OP_WWV(wadd, 128, int32_t, int64_t, +) +DEF_OP_WWV(wadd, 256, int32_t, int64_t, +) +DEF_OP_WWV(wadd, 512, int32_t, int64_t, +) + +DEF_OP_WWV(wadd, 4, uint8_t, uint16_t, +) +DEF_OP_WWV(wadd, 8, uint8_t, uint16_t, +) +DEF_OP_WWV(wadd, 16, uint8_t, uint16_t, +) +DEF_OP_WWV(wadd, 32, uint8_t, uint16_t, +) +DEF_OP_WWV(wadd, 64, uint8_t, uint16_t, +) +DEF_OP_WWV(wadd, 128, uint8_t, uint16_t, +) +DEF_OP_WWV(wadd, 256, uint8_t, uint16_t, +) +DEF_OP_WWV(wadd, 512, uint8_t, uint16_t, +) +DEF_OP_WWV(wadd, 1024, uint8_t, uint16_t, +) +DEF_OP_WWV(wadd, 2048, uint8_t, uint16_t, +) + +DEF_OP_WWV(wadd, 4, uint16_t, uint32_t, +) +DEF_OP_WWV(wadd, 8, uint16_t, uint32_t, +) +DEF_OP_WWV(wadd, 16, uint16_t, uint32_t, +) +DEF_OP_WWV(wadd, 32, uint16_t, uint32_t, +) +DEF_OP_WWV(wadd, 64, uint16_t, uint32_t, +) +DEF_OP_WWV(wadd, 128, uint16_t, uint32_t, +) +DEF_OP_WWV(wadd, 256, uint16_t, uint32_t, +) +DEF_OP_WWV(wadd, 512, uint16_t, uint32_t, +) +DEF_OP_WWV(wadd, 1024, uint16_t, uint32_t, +) + +DEF_OP_WWV(wadd, 4, uint32_t, uint64_t, +) +DEF_OP_WWV(wadd, 8, uint32_t, uint64_t, +) +DEF_OP_WWV(wadd, 16, uint32_t, uint64_t, +) +DEF_OP_WWV(wadd, 32, uint32_t, uint64_t, +) +DEF_OP_WWV(wadd, 64, uint32_t, uint64_t, +) +DEF_OP_WWV(wadd, 128, uint32_t, uint64_t, +) +DEF_OP_WWV(wadd, 256, uint32_t, uint64_t, +) +DEF_OP_WWV(wadd, 512, uint32_t, uint64_t, +) + +/* { dg-final { scan-assembler-times {vwadd\.wv} 27 } } */ +/* { dg-final { scan-assembler-times {vwaddu\.wv} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-4.c new file mode 100644 index 0000000..253750a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-4.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_WWV(wadd, 4, _Float16, float, +) +DEF_OP_WWV(wadd, 8, _Float16, float, +) +DEF_OP_WWV(wadd, 16, _Float16, float, +) +DEF_OP_WWV(wadd, 32, _Float16, float, +) +DEF_OP_WWV(wadd, 64, _Float16, float, +) +DEF_OP_WWV(wadd, 128, _Float16, float, +) +DEF_OP_WWV(wadd, 256, _Float16, float, +) +DEF_OP_WWV(wadd, 512, _Float16, float, +) +DEF_OP_WWV(wadd, 1024, _Float16, float, +) + +DEF_OP_WWV(wadd, 4, float, double, +) +DEF_OP_WWV(wadd, 8, float, double, +) +DEF_OP_WWV(wadd, 16, float, double, +) +DEF_OP_WWV(wadd, 32, float, double, +) +DEF_OP_WWV(wadd, 64, float, double, +) +DEF_OP_WWV(wadd, 128, float, double, +) +DEF_OP_WWV(wadd, 256, float, double, +) +DEF_OP_WWV(wadd, 512, float, double, +) + +/* { dg-final { scan-assembler-times {vfwadd\.wv} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-1.c new file mode 100644 index 0000000..a92b1c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-1.c @@ -0,0 +1,80 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_FMA_WVV (wfma, 4, int8_t, int16_t) +DEF_FMA_WVV (wfma, 8, int8_t, int16_t) +DEF_FMA_WVV (wfma, 16, int8_t, int16_t) +DEF_FMA_WVV (wfma, 32, int8_t, int16_t) +DEF_FMA_WVV (wfma, 64, int8_t, int16_t) +DEF_FMA_WVV (wfma, 128, int8_t, int16_t) +DEF_FMA_WVV (wfma, 256, int8_t, int16_t) +DEF_FMA_WVV (wfma, 512, int8_t, int16_t) +DEF_FMA_WVV (wfma, 1024, int8_t, int16_t) +DEF_FMA_WVV (wfma, 2048, int8_t, int16_t) + +DEF_FMA_WVV (wfma, 4, int16_t, int32_t) +DEF_FMA_WVV (wfma, 8, int16_t, int32_t) +DEF_FMA_WVV (wfma, 16, int16_t, int32_t) +DEF_FMA_WVV (wfma, 32, int16_t, int32_t) +DEF_FMA_WVV (wfma, 64, int16_t, int32_t) +DEF_FMA_WVV (wfma, 128, int16_t, int32_t) +DEF_FMA_WVV (wfma, 256, int16_t, int32_t) +DEF_FMA_WVV (wfma, 512, int16_t, int32_t) +DEF_FMA_WVV (wfma, 1024, int16_t, int32_t) + +DEF_FMA_WVV (wfma, 4, int32_t, int64_t) +DEF_FMA_WVV (wfma, 8, int32_t, int64_t) +DEF_FMA_WVV (wfma, 16, int32_t, int64_t) +DEF_FMA_WVV (wfma, 32, int32_t, int64_t) +DEF_FMA_WVV (wfma, 64, int32_t, int64_t) +DEF_FMA_WVV (wfma, 128, int32_t, int64_t) +DEF_FMA_WVV (wfma, 256, int32_t, int64_t) +DEF_FMA_WVV (wfma, 512, int32_t, int64_t) + +DEF_FMA_WVV (wfma, 4, uint8_t, uint16_t) +DEF_FMA_WVV (wfma, 8, uint8_t, uint16_t) +DEF_FMA_WVV (wfma, 16, uint8_t, uint16_t) +DEF_FMA_WVV (wfma, 32, uint8_t, uint16_t) +DEF_FMA_WVV (wfma, 64, uint8_t, uint16_t) +DEF_FMA_WVV (wfma, 128, uint8_t, uint16_t) +DEF_FMA_WVV (wfma, 256, uint8_t, uint16_t) +DEF_FMA_WVV (wfma, 512, uint8_t, uint16_t) +DEF_FMA_WVV (wfma, 1024, uint8_t, uint16_t) +DEF_FMA_WVV (wfma, 2048, uint8_t, uint16_t) + +DEF_FMA_WVV (wfma, 4, uint16_t, uint32_t) +DEF_FMA_WVV (wfma, 8, uint16_t, uint32_t) +DEF_FMA_WVV (wfma, 16, uint16_t, uint32_t) +DEF_FMA_WVV (wfma, 32, uint16_t, uint32_t) +DEF_FMA_WVV (wfma, 64, uint16_t, uint32_t) +DEF_FMA_WVV (wfma, 128, uint16_t, uint32_t) +DEF_FMA_WVV (wfma, 256, uint16_t, uint32_t) +DEF_FMA_WVV (wfma, 512, uint16_t, uint32_t) +DEF_FMA_WVV (wfma, 1024, uint16_t, uint32_t) + +DEF_FMA_WVV (wfma, 4, uint32_t, uint64_t) +DEF_FMA_WVV (wfma, 8, uint32_t, uint64_t) +DEF_FMA_WVV (wfma, 16, uint32_t, uint64_t) +DEF_FMA_WVV (wfma, 32, uint32_t, uint64_t) +DEF_FMA_WVV (wfma, 64, uint32_t, uint64_t) +DEF_FMA_WVV (wfma, 128, uint32_t, uint64_t) +DEF_FMA_WVV (wfma, 256, uint32_t, uint64_t) +DEF_FMA_WVV (wfma, 512, uint32_t, uint64_t) + +/* { dg-final { scan-assembler-times {vwmacc\.vv} 27 } } */ +/* { dg-final { scan-assembler-times {vwmaccu\.vv} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-2.c new file mode 100644 index 0000000..145ffd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-2.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_FMA_WVV(wfma, 4, _Float16, float) +DEF_FMA_WVV(wfma, 8, _Float16, float) +DEF_FMA_WVV(wfma, 16, _Float16, float) +DEF_FMA_WVV(wfma, 32, _Float16, float) +DEF_FMA_WVV(wfma, 64, _Float16, float) +DEF_FMA_WVV(wfma, 128, _Float16, float) +DEF_FMA_WVV(wfma, 256, _Float16, float) +DEF_FMA_WVV(wfma, 512, _Float16, float) +DEF_FMA_WVV(wfma, 1024, _Float16, float) + +DEF_FMA_WVV(wfma, 4, float, double) +DEF_FMA_WVV(wfma, 8, float, double) +DEF_FMA_WVV(wfma, 16, float, double) +DEF_FMA_WVV(wfma, 32, float, double) +DEF_FMA_WVV(wfma, 64, float, double) +DEF_FMA_WVV(wfma, 128, float, double) +DEF_FMA_WVV(wfma, 256, float, double) +DEF_FMA_WVV(wfma, 512, float, double) + +/* { dg-final { scan-assembler-times {vfwmacc\.vv} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-3.c new file mode 100644 index 0000000..4461a28 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-3.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_FMA_WVV_SU (wfma, 4, int8_t, uint8_t, int16_t) +DEF_FMA_WVV_SU (wfma, 8, int8_t, uint8_t, int16_t) +DEF_FMA_WVV_SU (wfma, 16, int8_t, uint8_t, int16_t) +DEF_FMA_WVV_SU (wfma, 32, int8_t, uint8_t, int16_t) +DEF_FMA_WVV_SU (wfma, 64, int8_t, uint8_t, int16_t) +DEF_FMA_WVV_SU (wfma, 128, int8_t, uint8_t, int16_t) +DEF_FMA_WVV_SU (wfma, 256, int8_t, uint8_t, int16_t) +DEF_FMA_WVV_SU (wfma, 512, int8_t, uint8_t, int16_t) +DEF_FMA_WVV_SU (wfma, 1024, int8_t, uint8_t, int16_t) +DEF_FMA_WVV_SU (wfma, 2048, int8_t, uint8_t, int16_t) + +DEF_FMA_WVV_SU (wfma, 4, int16_t, uint16_t, int32_t) +DEF_FMA_WVV_SU (wfma, 8, int16_t, uint16_t, int32_t) +DEF_FMA_WVV_SU (wfma, 16, int16_t, uint16_t, int32_t) +DEF_FMA_WVV_SU (wfma, 32, int16_t, uint16_t, int32_t) +DEF_FMA_WVV_SU (wfma, 64, int16_t, uint16_t, int32_t) +DEF_FMA_WVV_SU (wfma, 128, int16_t, uint16_t, int32_t) +DEF_FMA_WVV_SU (wfma, 256, int16_t, uint16_t, int32_t) +DEF_FMA_WVV_SU (wfma, 512, int16_t, uint16_t, int32_t) +DEF_FMA_WVV_SU (wfma, 1024, int16_t, uint16_t, int32_t) + +DEF_FMA_WVV_SU (wfma, 4, int32_t, uint32_t, int64_t) +DEF_FMA_WVV_SU (wfma, 8, int32_t, uint32_t, int64_t) +DEF_FMA_WVV_SU (wfma, 16, int32_t, uint32_t, int64_t) +DEF_FMA_WVV_SU (wfma, 32, int32_t, uint32_t, int64_t) +DEF_FMA_WVV_SU (wfma, 64, int32_t, uint32_t, int64_t) +DEF_FMA_WVV_SU (wfma, 128, int32_t, uint32_t, int64_t) +DEF_FMA_WVV_SU (wfma, 256, int32_t, uint32_t, int64_t) +DEF_FMA_WVV_SU (wfma, 512, int32_t, uint32_t, int64_t) + +/* { dg-final { scan-assembler-times {vwmaccsu\.vv} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfms-1.c new file mode 100644 index 0000000..804cfa0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfms-1.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_FMS_WVV(wfms, 4, _Float16, float) +DEF_FMS_WVV(wfms, 8, _Float16, float) +DEF_FMS_WVV(wfms, 16, _Float16, float) +DEF_FMS_WVV(wfms, 32, _Float16, float) +DEF_FMS_WVV(wfms, 64, _Float16, float) +DEF_FMS_WVV(wfms, 128, _Float16, float) +DEF_FMS_WVV(wfms, 256, _Float16, float) +DEF_FMS_WVV(wfms, 512, _Float16, float) +DEF_FMS_WVV(wfms, 1024, _Float16, float) + +DEF_FMS_WVV(wfms, 4, float, double) +DEF_FMS_WVV(wfms, 8, float, double) +DEF_FMS_WVV(wfms, 16, float, double) +DEF_FMS_WVV(wfms, 32, float, double) +DEF_FMS_WVV(wfms, 64, float, double) +DEF_FMS_WVV(wfms, 128, float, double) +DEF_FMS_WVV(wfms, 256, float, double) +DEF_FMS_WVV(wfms, 512, float, double) + +/* { dg-final { scan-assembler-times {vfwmsac\.vv} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnma-1.c new file mode 100644 index 0000000..7c55586 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnma-1.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_FNMA_WVV(wfnma, 4, _Float16, float) +DEF_FNMA_WVV(wfnma, 8, _Float16, float) +DEF_FNMA_WVV(wfnma, 16, _Float16, float) +DEF_FNMA_WVV(wfnma, 32, _Float16, float) +DEF_FNMA_WVV(wfnma, 64, _Float16, float) +DEF_FNMA_WVV(wfnma, 128, _Float16, float) +DEF_FNMA_WVV(wfnma, 256, _Float16, float) +DEF_FNMA_WVV(wfnma, 512, _Float16, float) +DEF_FNMA_WVV(wfnma, 1024, _Float16, float) + +DEF_FNMA_WVV(wfnma, 4, float, double) +DEF_FNMA_WVV(wfnma, 8, float, double) +DEF_FNMA_WVV(wfnma, 16, float, double) +DEF_FNMA_WVV(wfnma, 32, float, double) +DEF_FNMA_WVV(wfnma, 64, float, double) +DEF_FNMA_WVV(wfnma, 128, float, double) +DEF_FNMA_WVV(wfnma, 256, float, double) +DEF_FNMA_WVV(wfnma, 512, float, double) + +/* { dg-final { scan-assembler-times {vfwnmsac\.vv} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnms-1.c new file mode 100644 index 0000000..ce11509 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnms-1.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_FNMS_WVV(wfms, 4, _Float16, float) +DEF_FNMS_WVV(wfms, 8, _Float16, float) +DEF_FNMS_WVV(wfms, 16, _Float16, float) +DEF_FNMS_WVV(wfms, 32, _Float16, float) +DEF_FNMS_WVV(wfms, 64, _Float16, float) +DEF_FNMS_WVV(wfms, 128, _Float16, float) +DEF_FNMS_WVV(wfms, 256, _Float16, float) +DEF_FNMS_WVV(wfms, 512, _Float16, float) +DEF_FNMS_WVV(wfms, 1024, _Float16, float) + +DEF_FNMS_WVV(wfms, 4, float, double) +DEF_FNMS_WVV(wfms, 8, float, double) +DEF_FNMS_WVV(wfms, 16, float, double) +DEF_FNMS_WVV(wfms, 32, float, double) +DEF_FNMS_WVV(wfms, 64, float, double) +DEF_FNMS_WVV(wfms, 128, float, double) +DEF_FNMS_WVV(wfms, 256, float, double) +DEF_FNMS_WVV(wfms, 512, float, double) + +/* { dg-final { scan-assembler-times {vfwnmacc\.vv} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-1.c new file mode 100644 index 0000000..8269dfa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-1.c @@ -0,0 +1,80 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_WVV(wmul, 4, int8_t, int16_t, *) +DEF_OP_WVV(wmul, 8, int8_t, int16_t, *) +DEF_OP_WVV(wmul, 16, int8_t, int16_t, *) +DEF_OP_WVV(wmul, 32, int8_t, int16_t, *) +DEF_OP_WVV(wmul, 64, int8_t, int16_t, *) +DEF_OP_WVV(wmul, 128, int8_t, int16_t, *) +DEF_OP_WVV(wmul, 256, int8_t, int16_t, *) +DEF_OP_WVV(wmul, 512, int8_t, int16_t, *) +DEF_OP_WVV(wmul, 1024, int8_t, int16_t, *) +DEF_OP_WVV(wmul, 2048, int8_t, int16_t, *) + +DEF_OP_WVV(wmul, 4, int16_t, int32_t, *) +DEF_OP_WVV(wmul, 8, int16_t, int32_t, *) +DEF_OP_WVV(wmul, 16, int16_t, int32_t, *) +DEF_OP_WVV(wmul, 32, int16_t, int32_t, *) +DEF_OP_WVV(wmul, 64, int16_t, int32_t, *) +DEF_OP_WVV(wmul, 128, int16_t, int32_t, *) +DEF_OP_WVV(wmul, 256, int16_t, int32_t, *) +DEF_OP_WVV(wmul, 512, int16_t, int32_t, *) +DEF_OP_WVV(wmul, 1024, int16_t, int32_t, *) + +DEF_OP_WVV(wmul, 4, int32_t, int64_t, *) +DEF_OP_WVV(wmul, 8, int32_t, int64_t, *) +DEF_OP_WVV(wmul, 16, int32_t, int64_t, *) +DEF_OP_WVV(wmul, 32, int32_t, int64_t, *) +DEF_OP_WVV(wmul, 64, int32_t, int64_t, *) +DEF_OP_WVV(wmul, 128, int32_t, int64_t, *) +DEF_OP_WVV(wmul, 256, int32_t, int64_t, *) +DEF_OP_WVV(wmul, 512, int32_t, int64_t, *) + +DEF_OP_WVV(wmul, 4, uint8_t, uint16_t, *) +DEF_OP_WVV(wmul, 8, uint8_t, uint16_t, *) +DEF_OP_WVV(wmul, 16, uint8_t, uint16_t, *) +DEF_OP_WVV(wmul, 32, uint8_t, uint16_t, *) +DEF_OP_WVV(wmul, 64, uint8_t, uint16_t, *) +DEF_OP_WVV(wmul, 128, uint8_t, uint16_t, *) +DEF_OP_WVV(wmul, 256, uint8_t, uint16_t, *) +DEF_OP_WVV(wmul, 512, uint8_t, uint16_t, *) +DEF_OP_WVV(wmul, 1024, uint8_t, uint16_t, *) +DEF_OP_WVV(wmul, 2048, uint8_t, uint16_t, *) + +DEF_OP_WVV(wmul, 4, uint16_t, uint32_t, *) +DEF_OP_WVV(wmul, 8, uint16_t, uint32_t, *) +DEF_OP_WVV(wmul, 16, uint16_t, uint32_t, *) +DEF_OP_WVV(wmul, 32, uint16_t, uint32_t, *) +DEF_OP_WVV(wmul, 64, uint16_t, uint32_t, *) +DEF_OP_WVV(wmul, 128, uint16_t, uint32_t, *) +DEF_OP_WVV(wmul, 256, uint16_t, uint32_t, *) +DEF_OP_WVV(wmul, 512, uint16_t, uint32_t, *) +DEF_OP_WVV(wmul, 1024, uint16_t, uint32_t, *) + +DEF_OP_WVV(wmul, 4, uint32_t, uint64_t, *) +DEF_OP_WVV(wmul, 8, uint32_t, uint64_t, *) +DEF_OP_WVV(wmul, 16, uint32_t, uint64_t, *) +DEF_OP_WVV(wmul, 32, uint32_t, uint64_t, *) +DEF_OP_WVV(wmul, 64, uint32_t, uint64_t, *) +DEF_OP_WVV(wmul, 128, uint32_t, uint64_t, *) +DEF_OP_WVV(wmul, 256, uint32_t, uint64_t, *) +DEF_OP_WVV(wmul, 512, uint32_t, uint64_t, *) + +/* { dg-final { scan-assembler-times {vwmul\.vv} 27 } } */ +/* { dg-final { scan-assembler-times {vwmulu\.vv} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-2.c new file mode 100644 index 0000000..3675388 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-2.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_WVV(wmul, 4, _Float16, float, *) +DEF_OP_WVV(wmul, 8, _Float16, float, *) +DEF_OP_WVV(wmul, 16, _Float16, float, *) +DEF_OP_WVV(wmul, 32, _Float16, float, *) +DEF_OP_WVV(wmul, 64, _Float16, float, *) +DEF_OP_WVV(wmul, 128, _Float16, float, *) +DEF_OP_WVV(wmul, 256, _Float16, float, *) +DEF_OP_WVV(wmul, 512, _Float16, float, *) +DEF_OP_WVV(wmul, 1024, _Float16, float, *) + +DEF_OP_WVV(wmul, 4, float, double, *) +DEF_OP_WVV(wmul, 8, float, double, *) +DEF_OP_WVV(wmul, 16, float, double, *) +DEF_OP_WVV(wmul, 32, float, double, *) +DEF_OP_WVV(wmul, 64, float, double, *) +DEF_OP_WVV(wmul, 128, float, double, *) +DEF_OP_WVV(wmul, 256, float, double, *) +DEF_OP_WVV(wmul, 512, float, double, *) + +/* { dg-final { scan-assembler-times {vfwmul\.vv} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-3.c new file mode 100644 index 0000000..813a9a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-3.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_WVV_SU(wmul, 4, int8_t, uint8_t, int16_t, *) +DEF_OP_WVV_SU(wmul, 8, int8_t, uint8_t, int16_t, *) +DEF_OP_WVV_SU(wmul, 16, int8_t, uint8_t, int16_t, *) +DEF_OP_WVV_SU(wmul, 32, int8_t, uint8_t, int16_t, *) +DEF_OP_WVV_SU(wmul, 64, int8_t, uint8_t, int16_t, *) +DEF_OP_WVV_SU(wmul, 128, int8_t, uint8_t, int16_t, *) +DEF_OP_WVV_SU(wmul, 256, int8_t, uint8_t, int16_t, *) +DEF_OP_WVV_SU(wmul, 512, int8_t, uint8_t, int16_t, *) +DEF_OP_WVV_SU(wmul, 1024, int8_t, uint8_t, int16_t, *) +DEF_OP_WVV_SU(wmul, 2048, int8_t, uint8_t, int16_t, *) + +DEF_OP_WVV_SU(wmul, 4, int16_t, uint16_t, int32_t, *) +DEF_OP_WVV_SU(wmul, 8, int16_t, uint16_t, int32_t, *) +DEF_OP_WVV_SU(wmul, 16, int16_t, uint16_t, int32_t, *) +DEF_OP_WVV_SU(wmul, 32, int16_t, uint16_t, int32_t, *) +DEF_OP_WVV_SU(wmul, 64, int16_t, uint16_t, int32_t, *) +DEF_OP_WVV_SU(wmul, 128, int16_t, uint16_t, int32_t, *) +DEF_OP_WVV_SU(wmul, 256, int16_t, uint16_t, int32_t, *) +DEF_OP_WVV_SU(wmul, 512, int16_t, uint16_t, int32_t, *) +DEF_OP_WVV_SU(wmul, 1024, int16_t, uint16_t, int32_t, *) + +DEF_OP_WVV_SU(wmul, 4, int32_t, uint32_t, int64_t, *) +DEF_OP_WVV_SU(wmul, 8, int32_t, uint32_t, int64_t, *) +DEF_OP_WVV_SU(wmul, 16, int32_t, uint32_t, int64_t, *) +DEF_OP_WVV_SU(wmul, 32, int32_t, uint32_t, int64_t, *) +DEF_OP_WVV_SU(wmul, 64, int32_t, uint32_t, int64_t, *) +DEF_OP_WVV_SU(wmul, 128, int32_t, uint32_t, int64_t, *) +DEF_OP_WVV_SU(wmul, 256, int32_t, uint32_t, int64_t, *) +DEF_OP_WVV_SU(wmul, 512, int32_t, uint32_t, int64_t, *) + +/* { dg-final { scan-assembler-times {vwmulsu\.vv} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-1.c new file mode 100644 index 0000000..7ce910c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-1.c @@ -0,0 +1,80 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 4) +DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 8) +DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 16) +DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 32) +DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 64) +DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 128) +DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 256) +DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 512) +DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 1024) +DEF_WIDEN_REDUC_PLUS (int8_t, int16_t, 2048) + +DEF_WIDEN_REDUC_PLUS (int16_t, int32_t, 4) +DEF_WIDEN_REDUC_PLUS (int16_t, int32_t, 8) +DEF_WIDEN_REDUC_PLUS (int16_t, int32_t, 16) +DEF_WIDEN_REDUC_PLUS (int16_t, int32_t, 32) +DEF_WIDEN_REDUC_PLUS (int16_t, int32_t, 64) +DEF_WIDEN_REDUC_PLUS (int16_t, int32_t, 128) +DEF_WIDEN_REDUC_PLUS (int16_t, int32_t, 256) +DEF_WIDEN_REDUC_PLUS (int16_t, int32_t, 512) +DEF_WIDEN_REDUC_PLUS (int16_t, int32_t, 1024) + +DEF_WIDEN_REDUC_PLUS (int32_t, int64_t, 4) +DEF_WIDEN_REDUC_PLUS (int32_t, int64_t, 8) +DEF_WIDEN_REDUC_PLUS (int32_t, int64_t, 16) +DEF_WIDEN_REDUC_PLUS (int32_t, int64_t, 32) +DEF_WIDEN_REDUC_PLUS (int32_t, int64_t, 64) +DEF_WIDEN_REDUC_PLUS (int32_t, int64_t, 128) +DEF_WIDEN_REDUC_PLUS (int32_t, int64_t, 256) +DEF_WIDEN_REDUC_PLUS (int32_t, int64_t, 512) + +DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 4) +DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 8) +DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 16) +DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 32) +DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 64) +DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 128) +DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 256) +DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 512) +DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 1024) +DEF_WIDEN_REDUC_PLUS (uint8_t, uint16_t, 2048) + +DEF_WIDEN_REDUC_PLUS (uint16_t, uint32_t, 4) +DEF_WIDEN_REDUC_PLUS (uint16_t, uint32_t, 8) +DEF_WIDEN_REDUC_PLUS (uint16_t, uint32_t, 16) +DEF_WIDEN_REDUC_PLUS (uint16_t, uint32_t, 32) +DEF_WIDEN_REDUC_PLUS (uint16_t, uint32_t, 64) +DEF_WIDEN_REDUC_PLUS (uint16_t, uint32_t, 128) +DEF_WIDEN_REDUC_PLUS (uint16_t, uint32_t, 256) +DEF_WIDEN_REDUC_PLUS (uint16_t, uint32_t, 512) +DEF_WIDEN_REDUC_PLUS (uint16_t, uint32_t, 1024) + +DEF_WIDEN_REDUC_PLUS (uint32_t, uint64_t, 4) +DEF_WIDEN_REDUC_PLUS (uint32_t, uint64_t, 8) +DEF_WIDEN_REDUC_PLUS (uint32_t, uint64_t, 16) +DEF_WIDEN_REDUC_PLUS (uint32_t, uint64_t, 32) +DEF_WIDEN_REDUC_PLUS (uint32_t, uint64_t, 64) +DEF_WIDEN_REDUC_PLUS (uint32_t, uint64_t, 128) +DEF_WIDEN_REDUC_PLUS (uint32_t, uint64_t, 256) +DEF_WIDEN_REDUC_PLUS (uint32_t, uint64_t, 512) + +/* { dg-final { scan-assembler-times {vwredsum\.vs} 19 } } */ +/* { dg-final { scan-assembler-times {vwredsumu\.vs} 19 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-2.c new file mode 100644 index 0000000..75d49bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-2.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_WIDEN_REDUC_PLUS (_Float16, float, 4) +DEF_WIDEN_REDUC_PLUS (_Float16, float, 8) +DEF_WIDEN_REDUC_PLUS (_Float16, float, 16) +DEF_WIDEN_REDUC_PLUS (_Float16, float, 32) +DEF_WIDEN_REDUC_PLUS (_Float16, float, 64) +DEF_WIDEN_REDUC_PLUS (_Float16, float, 128) +DEF_WIDEN_REDUC_PLUS (_Float16, float, 256) +DEF_WIDEN_REDUC_PLUS (_Float16, float, 512) +DEF_WIDEN_REDUC_PLUS (_Float16, float, 1024) + +DEF_WIDEN_REDUC_PLUS (float, double, 4) +DEF_WIDEN_REDUC_PLUS (float, double, 8) +DEF_WIDEN_REDUC_PLUS (float, double, 16) +DEF_WIDEN_REDUC_PLUS (float, double, 32) +DEF_WIDEN_REDUC_PLUS (float, double, 64) +DEF_WIDEN_REDUC_PLUS (float, double, 128) +DEF_WIDEN_REDUC_PLUS (float, double, 256) +DEF_WIDEN_REDUC_PLUS (float, double, 512) + +/* { dg-final { scan-assembler-times {vfwredusum\.vs} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-3.c new file mode 100644 index 0000000..f49acc1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-3.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "wred-2.c" + +/* { dg-final { scan-assembler-times {vfwredosum\.vs} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-1.c new file mode 100644 index 0000000..eea9540 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-1.c @@ -0,0 +1,80 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_WVV(wsub, 4, int8_t, int16_t, -) +DEF_OP_WVV(wsub, 8, int8_t, int16_t, -) +DEF_OP_WVV(wsub, 16, int8_t, int16_t, -) +DEF_OP_WVV(wsub, 32, int8_t, int16_t, -) +DEF_OP_WVV(wsub, 64, int8_t, int16_t, -) +DEF_OP_WVV(wsub, 128, int8_t, int16_t, -) +DEF_OP_WVV(wsub, 256, int8_t, int16_t, -) +DEF_OP_WVV(wsub, 512, int8_t, int16_t, -) +DEF_OP_WVV(wsub, 1024, int8_t, int16_t, -) +DEF_OP_WVV(wsub, 2048, int8_t, int16_t, -) + +DEF_OP_WVV(wsub, 4, int16_t, int32_t, -) +DEF_OP_WVV(wsub, 8, int16_t, int32_t, -) +DEF_OP_WVV(wsub, 16, int16_t, int32_t, -) +DEF_OP_WVV(wsub, 32, int16_t, int32_t, -) +DEF_OP_WVV(wsub, 64, int16_t, int32_t, -) +DEF_OP_WVV(wsub, 128, int16_t, int32_t, -) +DEF_OP_WVV(wsub, 256, int16_t, int32_t, -) +DEF_OP_WVV(wsub, 512, int16_t, int32_t, -) +DEF_OP_WVV(wsub, 1024, int16_t, int32_t, -) + +DEF_OP_WVV(wsub, 4, int32_t, int64_t, -) +DEF_OP_WVV(wsub, 8, int32_t, int64_t, -) +DEF_OP_WVV(wsub, 16, int32_t, int64_t, -) +DEF_OP_WVV(wsub, 32, int32_t, int64_t, -) +DEF_OP_WVV(wsub, 64, int32_t, int64_t, -) +DEF_OP_WVV(wsub, 128, int32_t, int64_t, -) +DEF_OP_WVV(wsub, 256, int32_t, int64_t, -) +DEF_OP_WVV(wsub, 512, int32_t, int64_t, -) + +DEF_OP_WVV(wsub, 4, uint8_t, uint16_t, -) +DEF_OP_WVV(wsub, 8, uint8_t, uint16_t, -) +DEF_OP_WVV(wsub, 16, uint8_t, uint16_t, -) +DEF_OP_WVV(wsub, 32, uint8_t, uint16_t, -) +DEF_OP_WVV(wsub, 64, uint8_t, uint16_t, -) +DEF_OP_WVV(wsub, 128, uint8_t, uint16_t, -) +DEF_OP_WVV(wsub, 256, uint8_t, uint16_t, -) +DEF_OP_WVV(wsub, 512, uint8_t, uint16_t, -) +DEF_OP_WVV(wsub, 1024, uint8_t, uint16_t, -) +DEF_OP_WVV(wsub, 2048, uint8_t, uint16_t, -) + +DEF_OP_WVV(wsub, 4, uint16_t, uint32_t, -) +DEF_OP_WVV(wsub, 8, uint16_t, uint32_t, -) +DEF_OP_WVV(wsub, 16, uint16_t, uint32_t, -) +DEF_OP_WVV(wsub, 32, uint16_t, uint32_t, -) +DEF_OP_WVV(wsub, 64, uint16_t, uint32_t, -) +DEF_OP_WVV(wsub, 128, uint16_t, uint32_t, -) +DEF_OP_WVV(wsub, 256, uint16_t, uint32_t, -) +DEF_OP_WVV(wsub, 512, uint16_t, uint32_t, -) +DEF_OP_WVV(wsub, 1024, uint16_t, uint32_t, -) + +DEF_OP_WVV(wsub, 4, uint32_t, uint64_t, -) +DEF_OP_WVV(wsub, 8, uint32_t, uint64_t, -) +DEF_OP_WVV(wsub, 16, uint32_t, uint64_t, -) +DEF_OP_WVV(wsub, 32, uint32_t, uint64_t, -) +DEF_OP_WVV(wsub, 64, uint32_t, uint64_t, -) +DEF_OP_WVV(wsub, 128, uint32_t, uint64_t, -) +DEF_OP_WVV(wsub, 256, uint32_t, uint64_t, -) +DEF_OP_WVV(wsub, 512, uint32_t, uint64_t, -) + +/* { dg-final { scan-assembler-times {vwsub\.vv} 27 } } */ +/* { dg-final { scan-assembler-times {vwsubu\.vv} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-2.c new file mode 100644 index 0000000..1048d29 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-2.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_WVV(wsub, 4, _Float16, float, -) +DEF_OP_WVV(wsub, 8, _Float16, float, -) +DEF_OP_WVV(wsub, 16, _Float16, float, -) +DEF_OP_WVV(wsub, 32, _Float16, float, -) +DEF_OP_WVV(wsub, 64, _Float16, float, -) +DEF_OP_WVV(wsub, 128, _Float16, float, -) +DEF_OP_WVV(wsub, 256, _Float16, float, -) +DEF_OP_WVV(wsub, 512, _Float16, float, -) +DEF_OP_WVV(wsub, 1024, _Float16, float, -) + +DEF_OP_WVV(wsub, 4, float, double, -) +DEF_OP_WVV(wsub, 8, float, double, -) +DEF_OP_WVV(wsub, 16, float, double, -) +DEF_OP_WVV(wsub, 32, float, double, -) +DEF_OP_WVV(wsub, 64, float, double, -) +DEF_OP_WVV(wsub, 128, float, double, -) +DEF_OP_WVV(wsub, 256, float, double, -) +DEF_OP_WVV(wsub, 512, float, double, -) + +/* { dg-final { scan-assembler-times {vfwsub\.vv} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-3.c new file mode 100644 index 0000000..ac4bfe2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-3.c @@ -0,0 +1,80 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_WWV(wsub, 4, int8_t, int16_t, -) +DEF_OP_WWV(wsub, 8, int8_t, int16_t, -) +DEF_OP_WWV(wsub, 16, int8_t, int16_t, -) +DEF_OP_WWV(wsub, 32, int8_t, int16_t, -) +DEF_OP_WWV(wsub, 64, int8_t, int16_t, -) +DEF_OP_WWV(wsub, 128, int8_t, int16_t, -) +DEF_OP_WWV(wsub, 256, int8_t, int16_t, -) +DEF_OP_WWV(wsub, 512, int8_t, int16_t, -) +DEF_OP_WWV(wsub, 1024, int8_t, int16_t, -) +DEF_OP_WWV(wsub, 2048, int8_t, int16_t, -) + +DEF_OP_WWV(wsub, 4, int16_t, int32_t, -) +DEF_OP_WWV(wsub, 8, int16_t, int32_t, -) +DEF_OP_WWV(wsub, 16, int16_t, int32_t, -) +DEF_OP_WWV(wsub, 32, int16_t, int32_t, -) +DEF_OP_WWV(wsub, 64, int16_t, int32_t, -) +DEF_OP_WWV(wsub, 128, int16_t, int32_t, -) +DEF_OP_WWV(wsub, 256, int16_t, int32_t, -) +DEF_OP_WWV(wsub, 512, int16_t, int32_t, -) +DEF_OP_WWV(wsub, 1024, int16_t, int32_t, -) + +DEF_OP_WWV(wsub, 4, int32_t, int64_t, -) +DEF_OP_WWV(wsub, 8, int32_t, int64_t, -) +DEF_OP_WWV(wsub, 16, int32_t, int64_t, -) +DEF_OP_WWV(wsub, 32, int32_t, int64_t, -) +DEF_OP_WWV(wsub, 64, int32_t, int64_t, -) +DEF_OP_WWV(wsub, 128, int32_t, int64_t, -) +DEF_OP_WWV(wsub, 256, int32_t, int64_t, -) +DEF_OP_WWV(wsub, 512, int32_t, int64_t, -) + +DEF_OP_WWV(wsub, 4, uint8_t, uint16_t, -) +DEF_OP_WWV(wsub, 8, uint8_t, uint16_t, -) +DEF_OP_WWV(wsub, 16, uint8_t, uint16_t, -) +DEF_OP_WWV(wsub, 32, uint8_t, uint16_t, -) +DEF_OP_WWV(wsub, 64, uint8_t, uint16_t, -) +DEF_OP_WWV(wsub, 128, uint8_t, uint16_t, -) +DEF_OP_WWV(wsub, 256, uint8_t, uint16_t, -) +DEF_OP_WWV(wsub, 512, uint8_t, uint16_t, -) +DEF_OP_WWV(wsub, 1024, uint8_t, uint16_t, -) +DEF_OP_WWV(wsub, 2048, uint8_t, uint16_t, -) + +DEF_OP_WWV(wsub, 4, uint16_t, uint32_t, -) +DEF_OP_WWV(wsub, 8, uint16_t, uint32_t, -) +DEF_OP_WWV(wsub, 16, uint16_t, uint32_t, -) +DEF_OP_WWV(wsub, 32, uint16_t, uint32_t, -) +DEF_OP_WWV(wsub, 64, uint16_t, uint32_t, -) +DEF_OP_WWV(wsub, 128, uint16_t, uint32_t, -) +DEF_OP_WWV(wsub, 256, uint16_t, uint32_t, -) +DEF_OP_WWV(wsub, 512, uint16_t, uint32_t, -) +DEF_OP_WWV(wsub, 1024, uint16_t, uint32_t, -) + +DEF_OP_WWV(wsub, 4, uint32_t, uint64_t, -) +DEF_OP_WWV(wsub, 8, uint32_t, uint64_t, -) +DEF_OP_WWV(wsub, 16, uint32_t, uint64_t, -) +DEF_OP_WWV(wsub, 32, uint32_t, uint64_t, -) +DEF_OP_WWV(wsub, 64, uint32_t, uint64_t, -) +DEF_OP_WWV(wsub, 128, uint32_t, uint64_t, -) +DEF_OP_WWV(wsub, 256, uint32_t, uint64_t, -) +DEF_OP_WWV(wsub, 512, uint32_t, uint64_t, -) + +/* { dg-final { scan-assembler-times {vwsub\.wv} 27 } } */ +/* { dg-final { scan-assembler-times {vwsubu\.wv} 27 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-4.c new file mode 100644 index 0000000..619c0c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-4.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_WWV(wsub, 4, _Float16, float, -) +DEF_OP_WWV(wsub, 8, _Float16, float, -) +DEF_OP_WWV(wsub, 16, _Float16, float, -) +DEF_OP_WWV(wsub, 32, _Float16, float, -) +DEF_OP_WWV(wsub, 64, _Float16, float, -) +DEF_OP_WWV(wsub, 128, _Float16, float, -) +DEF_OP_WWV(wsub, 256, _Float16, float, -) +DEF_OP_WWV(wsub, 512, _Float16, float, -) +DEF_OP_WWV(wsub, 1024, _Float16, float, -) + +DEF_OP_WWV(wsub, 4, float, double, -) +DEF_OP_WWV(wsub, 8, float, double, -) +DEF_OP_WWV(wsub, 16, float, double, -) +DEF_OP_WWV(wsub, 32, float, double, -) +DEF_OP_WWV(wsub, 64, float, double, -) +DEF_OP_WWV(wsub, 128, float, double, -) +DEF_OP_WWV(wsub, 256, float, double, -) +DEF_OP_WWV(wsub, 512, float, double, -) + +/* { dg-final { scan-assembler-times {vfwsub\.wv} 17 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c index faa6c90..7a50b70 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin" } */ #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h index 84b26e0..35e60c0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h @@ -1,5 +1,4 @@ #include <stdint-gcc.h> -#include <assert.h> #define VMV_POS(TYPE,VAL) \ __attribute__ ((noipa)) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c index 7ca193e..537f135 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -lm" } */ #include <limits.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c index d4ba4f5..40352a5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "widen_reduc_order-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c index 6ac6762..3552f2f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "widen_reduc_order-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c index d70a652..f003420 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ #include "widen_reduc-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c index 21d0934..f20a892 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c index 262660c..cabb011 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c index 246999c..fc9c69c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c index 2a6a03b..324a39b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c index e5805a9..cb755c1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c index b7dd60f..a0887fc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c index a14539f..3c21b24 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c index d94f704..52bd00c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c index 6c4ccec..566341e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c index ab29f4a..c6bbf4f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c index 1509500..f7dbc06 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c index 2caa09a..042bc5b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c index e70f06f..5661252 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c index f678c35..1fcd836 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c index 294f77d..8e73095 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c index 013291c..6f04595 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c index e07a828..a3ddeb0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c index c3efd0b..47a1803 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c index 144e3d2..a5eb476 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c index 006dade..046d471 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c index 60e2401c..d10017c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c index 63563b8..2b945f9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ /* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c index 060d09e..6355ecb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O1 --param=riscv-vector-abi -Wno-psabi" } */ /* { dg-additional-sources abi-call-args-1.c } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c index 9808e41..fe036ef 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O1 --param=riscv-vector-abi -Wno-psabi" } */ /* { dg-additional-sources abi-call-args-2.c } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c index 8eb1ea2..8c5a094 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O1 --param=riscv-vector-abi -Wno-psabi" } */ /* { dg-additional-sources abi-call-args-3.c } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c index 84ba9d4..01cd55f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O1 --param=riscv-vector-abi -Wno-psabi" } */ /* { dg-additional-sources abi-call-args-4.c } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return-run.c index 539cd02..054b6fa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return-run.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O1 --param=riscv-vector-abi -Wno-psabi" } */ /* { dg-additional-sources abi-call-return.c } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c index 2832c9c..3fdc498 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c index ab003fd..19a016d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c index 8230695..e3e4b44 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c index f3089d2..34b8c48 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 -Wno-psabi" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c index 8303b61..4c43983 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 -Wno-psabi" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c index 592ff6b..ff43422 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 -Wno-psabi" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-4.c index 56e4668..f2b1b1b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-4.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 -Wno-psabi" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-5.c index 8b338f2..4cb913a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-5.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 -Wno-psabi" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c new file mode 100644 index 0000000..aba26df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -ffast-math -ftree-vectorize" } */ + +#include <stddef.h> + +typedef _Complex float GFC_COMPLEX_4; + +void +test (GFC_COMPLEX_4 *a, GFC_COMPLEX_4 *b, GFC_COMPLEX_4 c, ptrdiff_t i, ptrdiff_t j) +{ + ptrdiff_t l; + for (l = 0; l <= i; ++l) + c += b[l] * a[j]; + b[j] = c; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c new file mode 100644 index 0000000..a4d2011 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ + +#include <string.h> + +/* Return the number of DNS hierarchy levels in the name. */ +int +test (const char *name) { + int i, len, count; + + len = strlen(name); + for (i = 0, count = 0; i < len; i++) { + /* XXX need to check for \. or use named's nlabels(). */ + if (name[i] == '.') + count++; + } + + /* don't count initial wildcard */ + if (name[0] == '*') + if (count) + count--; + + /* don't count the null label for root. */ + /* if terminating '.' not found, must adjust */ + /* count to include last label */ + if (len > 0 && name[len-1] != '.') + count++; + return (count); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c index 7aee75c..7207010 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do run { target { riscv_v } } } */ /* { dg-options "-O3 -Wno-psabi" } */ #define TEST_VAL 2 diff --git a/gcc/testsuite/gcc.target/riscv/shift-and-1.c b/gcc/testsuite/gcc.target/riscv/shift-and-1.c index 429ab84f..2d483d0 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-and-1.c +++ b/gcc/testsuite/gcc.target/riscv/shift-and-1.c @@ -8,4 +8,4 @@ sub1 (int i, int j) { return i << (j & 0x1f); } -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-and-2.c b/gcc/testsuite/gcc.target/riscv/shift-and-2.c index ee9925b..9b4ca11 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-and-2.c +++ b/gcc/testsuite/gcc.target/riscv/shift-and-2.c @@ -57,5 +57,5 @@ sub9 (unsigned i, unsigned j) { return (i >> 10) & j; } -/* { dg-final { scan-assembler-not "andi" } } */ -/* { dg-final { scan-assembler-not "sext.w" } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ +/* { dg-final { scan-assembler-not {\msext\.w\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-1.c b/gcc/testsuite/gcc.target/riscv/shift-shift-1.c index 462e532..bae6c8a 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-shift-1.c +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-1.c @@ -14,5 +14,5 @@ sub2 (unsigned int i) { return (i << 20) >> 20; } -/* { dg-final { scan-assembler-times "slli" 2 } } */ -/* { dg-final { scan-assembler-times "srli" 2 } } */ +/* { dg-final { scan-assembler-times {\mslli} 2 } } */ +/* { dg-final { scan-assembler-times {\msrli} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c index bc8c4ef..3b0c9d5 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c @@ -36,8 +36,8 @@ sub5 (unsigned int i) j = i - j; return j; } -/* { dg-final { scan-assembler-times "slli" 5 } } */ -/* { dg-final { scan-assembler-times "srli" 5 } } */ +/* { dg-final { scan-assembler-times {\mslli} 5 } } */ +/* { dg-final { scan-assembler-times {\msrli} 5 } } */ /* { dg-final { scan-assembler-times ",40" 2 } } */ /* For sub5 test */ -/* { dg-final { scan-assembler-not "slliw" } } */ -/* { dg-final { scan-assembler-not "srliw" } } */ +/* { dg-final { scan-assembler-not {\mslliw} } } */ +/* { dg-final { scan-assembler-not {\msrliw} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-3.c b/gcc/testsuite/gcc.target/riscv/shift-shift-3.c index 16999b0..d9154a1 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-shift-3.c +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-3.c @@ -15,5 +15,5 @@ sub2 (unsigned long i) { return (i >> 63) << 63; } -/* { dg-final { scan-assembler-times "slli" 2 } } */ -/* { dg-final { scan-assembler-times "srli" 2 } } */ +/* { dg-final { scan-assembler-times {\mslli} 2 } } */ +/* { dg-final { scan-assembler-times {\msrli} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-4.c b/gcc/testsuite/gcc.target/riscv/shift-shift-4.c index bc7bca1..c479649 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-shift-4.c +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-4.c @@ -11,4 +11,4 @@ sub (int i) i &= 0x7fffffff; return i > 0x7f800000; } -/* { dg-final { scan-assembler-not "srli" } } */ +/* { dg-final { scan-assembler-not {\msrli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-5.c b/gcc/testsuite/gcc.target/riscv/shift-shift-5.c index ed8e7b3..d012866 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-shift-5.c +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-5.c @@ -18,4 +18,4 @@ sub (long l) u.l = l; return u.s.b; } -/* { dg-final { scan-assembler "srliw" } } */ +/* { dg-final { scan-assembler {\msrliw} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-7.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-7.c index 476d079..ba7b783 100644 --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-7.c +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-7.c @@ -44,4 +44,4 @@ load2r (long long *array) return a; } -/* { dg-final { scan-assembler-not "addi" } } */ +/* { dg-final { scan-assembler-not {\maddi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sign-extend.c b/gcc/testsuite/gcc.target/riscv/sign-extend.c index 6f84019..47be57d 100644 --- a/gcc/testsuite/gcc.target/riscv/sign-extend.c +++ b/gcc/testsuite/gcc.target/riscv/sign-extend.c @@ -69,13 +69,13 @@ foo11 (unsigned x) return x & (15 + x); } -/* { dg-final { scan-assembler-times "subw" 2 } } */ -/* { dg-final { scan-assembler-times "addw" 1 } } */ -/* { dg-final { scan-assembler-times "addiw" 1 } } */ -/* { dg-final { scan-assembler-times "mulw" 2 } } */ -/* { dg-final { scan-assembler-times "divw" 1 } } */ -/* { dg-final { scan-assembler-times "divuw" 1 } } */ -/* { dg-final { scan-assembler-times "remw" 1 } } */ -/* { dg-final { scan-assembler-times "remuw" 1 } } */ -/* { dg-final { scan-assembler-times "negw" 1 } } */ -/* { dg-final { scan-assembler-not "sext.w" } } */ +/* { dg-final { scan-assembler-times {\msubw} 2 } } */ +/* { dg-final { scan-assembler-times {\maddw} 1 } } */ +/* { dg-final { scan-assembler-times {\maddiw} 1 } } */ +/* { dg-final { scan-assembler-times {\mmulw} 2 } } */ +/* { dg-final { scan-assembler-times {\mdivw} 1 } } */ +/* { dg-final { scan-assembler-times {\mdivuw} 1 } } */ +/* { dg-final { scan-assembler-times {\mremw} 1 } } */ +/* { dg-final { scan-assembler-times {\mremuw} 1 } } */ +/* { dg-final { scan-assembler-times {\mnegw} 1 } } */ +/* { dg-final { scan-assembler-not {\msext\.w\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/switch-qi.c b/gcc/testsuite/gcc.target/riscv/switch-qi.c index e39219b..9126e0a 100644 --- a/gcc/testsuite/gcc.target/riscv/switch-qi.c +++ b/gcc/testsuite/gcc.target/riscv/switch-qi.c @@ -12,4 +12,4 @@ void foo(signed char x) { case 4: asdf(14); break; } } -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/switch-si.c b/gcc/testsuite/gcc.target/riscv/switch-si.c index c68f98d..e76c2aa 100644 --- a/gcc/testsuite/gcc.target/riscv/switch-si.c +++ b/gcc/testsuite/gcc.target/riscv/switch-si.c @@ -12,4 +12,4 @@ void foo(int x) { case 4: asdf(14); break; } } -/* { dg-final { scan-assembler-not "srli" } } */ +/* { dg-final { scan-assembler-not {\msrli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c index 02f6ec1..04b8232 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c @@ -63,5 +63,5 @@ char sext8_16(short s16) return s16; } -/* { dg-final { scan-assembler-not "slli" } } */ -/* { dg-final { scan-assembler-not "srli" } } */ +/* { dg-final { scan-assembler-not {\mslli} } } */ +/* { dg-final { scan-assembler-not {\msrli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c index 60fb7d4..121d969 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c @@ -17,4 +17,4 @@ foo (struct bar *s) } /* { dg-final { scan-assembler "th.ext\t" } } */ -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c index 01e3eda..b92445c 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c @@ -63,5 +63,5 @@ unsigned char zext8_16(unsigned short u16) return u16; } -/* { dg-final { scan-assembler-not "slli" } } */ -/* { dg-final { scan-assembler-not "srli" } } */ +/* { dg-final { scan-assembler-not {\mslli} } } */ +/* { dg-final { scan-assembler-not {\msrli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c index e0492f1..fca9b7e 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c @@ -17,6 +17,6 @@ foo (struct bar *s) } /* { dg-final { scan-assembler "th.extu\t" } } */ -/* { dg-final { scan-assembler-not "andi" } } */ -/* { dg-final { scan-assembler-not "slli" } } */ -/* { dg-final { scan-assembler-not "srli" } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ +/* { dg-final { scan-assembler-not {\mslli} } } */ +/* { dg-final { scan-assembler-not {\msrli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-strlen.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-strlen.c index dbc8d1e..f243b6f 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadbb-strlen.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-strlen.c @@ -13,7 +13,7 @@ my_str_len (const char *s) } /* { dg-final { scan-assembler "th.tstnbz\t" } } */ -/* { dg-final { scan-assembler-not "jalr" } } */ -/* { dg-final { scan-assembler-not "call" } } */ -/* { dg-final { scan-assembler-not "jr" } } */ -/* { dg-final { scan-assembler-not "tail" } } */ +/* { dg-final { scan-assembler-not {\mjalr} } } */ +/* { dg-final { scan-assembler-not {\mcall} } } */ +/* { dg-final { scan-assembler-not {\mjr} } } */ +/* { dg-final { scan-assembler-not {\mtail} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c b/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c index 674cec0..f56d9ad 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c @@ -10,4 +10,4 @@ foo1 (long i) } /* { dg-final { scan-assembler-times "th.tst\t" 1 } } */ -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c index 89eb48b..9b4e237 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c @@ -14,9 +14,9 @@ d2ll (double d) return *(long long*)&d; } -/* { dg-final { scan-assembler "fmv.w.x" } } */ +/* { dg-final { scan-assembler {\mfmv\.w.x\M} } } */ /* { dg-final { scan-assembler "th.fmv.hw.x" } } */ -/* { dg-final { scan-assembler "fmv.x.w" } } */ +/* { dg-final { scan-assembler {\mfmv\.x.w\M} } } */ /* { dg-final { scan-assembler "th.fmv.x.hw" } } */ /* { dg-final { scan-assembler-not "\tsw\t" } } */ /* { dg-final { scan-assembler-not "\tfld\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c index 644ca12..19bbcb6 100644 --- a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c @@ -6,5 +6,5 @@ /* { dg-final { scan-assembler-times "vt\\.maskc\t" 6 } } */ /* { dg-final { scan-assembler-times "vt\\.maskcn\t" 6 } } */ -/* { dg-final { scan-assembler-not "beq" } } */ -/* { dg-final { scan-assembler-not "bne" } } */ +/* { dg-final { scan-assembler-not {\mbeq} } } */ +/* { dg-final { scan-assembler-not {\mbne} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-adduw.c b/gcc/testsuite/gcc.target/riscv/zba-adduw.c index 2ae03ae..a15ad7f 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-adduw.c +++ b/gcc/testsuite/gcc.target/riscv/zba-adduw.c @@ -10,4 +10,4 @@ int foo(int n, unsigned char *arr, unsigned y){ return s; } -/* { dg-final { scan-assembler "add.uw" } } */ +/* { dg-final { scan-assembler {\madd\.uw\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c index bc97bc7..34dfd0c 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c @@ -15,6 +15,6 @@ long test_3(long a, long b) return a + (b << 3); } -/* { dg-final { scan-assembler-times "sh1add" 1 } } */ -/* { dg-final { scan-assembler-times "sh2add" 1 } } */ -/* { dg-final { scan-assembler-times "sh3add" 1 } } */ +/* { dg-final { scan-assembler-times {\msh1add} 1 } } */ +/* { dg-final { scan-assembler-times {\msh2add} 1 } } */ +/* { dg-final { scan-assembler-times {\msh3add} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c index 5f4b65f..c40f2cb 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c @@ -15,6 +15,6 @@ long test_3(long a, long b) return a + (b << 3); } -/* { dg-final { scan-assembler-times "sh1add" 1 } } */ -/* { dg-final { scan-assembler-times "sh2add" 1 } } */ -/* { dg-final { scan-assembler-times "sh3add" 1 } } */ +/* { dg-final { scan-assembler-times {\msh1add} 1 } } */ +/* { dg-final { scan-assembler-times {\msh2add} 1 } } */ +/* { dg-final { scan-assembler-times {\msh3add} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-04.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-04.c index abed149..48e225d 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-shNadd-04.c +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-04.c @@ -19,5 +19,5 @@ long long sub3(unsigned long long a, unsigned long long b) return (a + (b << 1)) & ~0u; } -/* { dg-final { scan-assembler-times "sh1add" 3 } } */ +/* { dg-final { scan-assembler-times {\msh1add} 3 } } */ /* { dg-final { scan-assembler-times "zext.w\t" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-07.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-07.c index 93da241..cd48664 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-shNadd-07.c +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-07.c @@ -25,7 +25,7 @@ f4 (unsigned long i) return i * 1574; } -/* { dg-final { scan-assembler-times "sh2add" 2 } } */ -/* { dg-final { scan-assembler-times "sh1add" 1 } } */ -/* { dg-final { scan-assembler-times "slli" 3 } } */ -/* { dg-final { scan-assembler-times "mul" 2 } } */ +/* { dg-final { scan-assembler-times {\msh2add} 2 } } */ +/* { dg-final { scan-assembler-times {\msh1add} 1 } } */ +/* { dg-final { scan-assembler-times {\mslli} 3 } } */ +/* { dg-final { scan-assembler-times {\mmul} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shadd.c b/gcc/testsuite/gcc.target/riscv/zba-shadd.c index 33da253..61305d3 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-shadd.c +++ b/gcc/testsuite/gcc.target/riscv/zba-shadd.c @@ -10,4 +10,4 @@ unsigned long foo(unsigned int a, unsigned long b) } /* { dg-final { scan-assembler "sh2add.uw" } } */ -/* { dg-final { scan-assembler-not "zext" } } */
\ No newline at end of file +/* { dg-final { scan-assembler-not {\mzext} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c index cd3cf0e..c123bb5 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c +++ b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c @@ -9,4 +9,4 @@ foo (long i) } /* XXX: This pattern need combine improvement or intermediate instruction * from zbs. */ -/* { dg-final { scan-assembler "slli.uw" } } */ +/* { dg-final { scan-assembler {\mslli\.uw\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-zextw.c b/gcc/testsuite/gcc.target/riscv/zba-zextw.c index 271c186..7da2a94 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-zextw.c +++ b/gcc/testsuite/gcc.target/riscv/zba-zextw.c @@ -8,4 +8,4 @@ foo (long i) return (long)(unsigned int)i; } /* XXX: This pattern require combine improvement. */ -/* { dg-final { scan-assembler-not "slli.uw" } } */ +/* { dg-final { scan-assembler-not {\mslli\.uw\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c index 89a3043..a1f5f03 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c @@ -17,6 +17,6 @@ unsigned long long foo3(unsigned long long rs1, unsigned long long rs2) return rs1 ^ ~rs2; } -/* { dg-final { scan-assembler-times "andn" 2 } } */ -/* { dg-final { scan-assembler-times "orn" 2 } } */ -/* { dg-final { scan-assembler-times "xnor" 2 } } */
\ No newline at end of file +/* { dg-final { scan-assembler-times {\mandn} 2 } } */ +/* { dg-final { scan-assembler-times {\morn} 2 } } */ +/* { dg-final { scan-assembler-times {\mxnor} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c index ef0dade..331bd33 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c @@ -17,6 +17,6 @@ unsigned int foo3(unsigned int rs1, unsigned int rs2) return rs1 ^ ~rs2; } -/* { dg-final { scan-assembler-times "andn" 2 } } */ -/* { dg-final { scan-assembler-times "orn" 2 } } */ -/* { dg-final { scan-assembler-times "xnor" 2 } } */
\ No newline at end of file +/* { dg-final { scan-assembler-times {\mandn} 2 } } */ +/* { dg-final { scan-assembler-times {\morn} 2 } } */ +/* { dg-final { scan-assembler-times {\mxnor} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c index edfbf80..22bfb93 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c @@ -8,7 +8,7 @@ int f(unsigned int* a) return *a * 3 > C ? C : *a * 3; } -/* { dg-final { scan-assembler-times "minu" 1 } } */ -/* { dg-final { scan-assembler-not "sext.w" } } */ -/* { dg-final { scan-assembler-not "zext.w" } } */ +/* { dg-final { scan-assembler-times {\mminu} 1 } } */ +/* { dg-final { scan-assembler-not {\msext\.w\M} } } */ +/* { dg-final { scan-assembler-not {\mzext\.w\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max-03.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max-03.c index 38c932b..769e876 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-min-max-03.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max-03.c @@ -18,6 +18,6 @@ unsigned f3(unsigned x, unsigned y) { /* { dg-final { scan-assembler-not "li\t" } } */ /* { dg-final { scan-assembler-times "maxu\t" 1 } } */ /* { dg-final { scan-assembler-times "minu\t" 1 } } */ -/* { dg-final { scan-assembler-not "zext.w" } } */ -/* { dg-final { scan-assembler-not "sext.w" } } */ +/* { dg-final { scan-assembler-not {\mzext\.w\M} } } */ +/* { dg-final { scan-assembler-not {\msext\.w\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max.c index ce054dd..2a5d934 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-min-max.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max.c @@ -26,7 +26,7 @@ foo4 (unsigned long i, unsigned long j) return i > j ? i : j; } -/* { dg-final { scan-assembler-times "min" 3 } } */ -/* { dg-final { scan-assembler-times "max" 3 } } */ -/* { dg-final { scan-assembler-times "minu" 1 } } */ -/* { dg-final { scan-assembler-times "maxu" 1 } } */ +/* { dg-final { scan-assembler-times {\mmin} 3 } } */ +/* { dg-final { scan-assembler-times {\mmax} 3 } } */ +/* { dg-final { scan-assembler-times {\mminu} 1 } } */ +/* { dg-final { scan-assembler-times {\mmaxu} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c index 0a5b5e1..4f2ff7f 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c @@ -13,6 +13,6 @@ unsigned long foo2(unsigned long rs1, unsigned long rs2) return (rs1 >> shamt) | (rs1 << ((64 - shamt) & (64 - 1))); } -/* { dg-final { scan-assembler-times "rol" 2 } } */ -/* { dg-final { scan-assembler-times "ror" 2 } } */ -/* { dg-final { scan-assembler-not "and" } } */
\ No newline at end of file +/* { dg-final { scan-assembler-times {\mrol} 2 } } */ +/* { dg-final { scan-assembler-times {\mror} 2 } } */ +/* { dg-final { scan-assembler-not {\mand} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c index d0d5813..c248092 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c @@ -13,6 +13,6 @@ unsigned int foo2(unsigned int rs1, unsigned int rs2) return (rs1 >> shamt) | (rs1 << ((32 - shamt) & (32 - 1))); } -/* { dg-final { scan-assembler-times "rol" 2 } } */ -/* { dg-final { scan-assembler-times "ror" 2 } } */ -/* { dg-final { scan-assembler-not {and} { target { no-opts "-O0" } } } } */
\ No newline at end of file +/* { dg-final { scan-assembler-times {\mrol} 2 } } */ +/* { dg-final { scan-assembler-times {\mror} 2 } } */ +/* { dg-final { scan-assembler-not {and} { target { no-opts "-O0" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c index e7e5cbb..f85c20e 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c @@ -14,7 +14,7 @@ unsigned int ror(unsigned int rs1, unsigned int rs2) return (rs1 >> shamt) | (rs1 << ((32 - shamt) & (32 - 1))); } -/* { dg-final { scan-assembler-times "rolw" 1 } } */ -/* { dg-final { scan-assembler-times "rorw" 1 } } */ -/* { dg-final { scan-assembler-not "and" } } */ -/* { dg-final { scan-assembler-not "sext.w" } } */ +/* { dg-final { scan-assembler-times {\mrolw} 1 } } */ +/* { dg-final { scan-assembler-times {\mrorw} 1 } } */ +/* { dg-final { scan-assembler-not {\mand} } } */ +/* { dg-final { scan-assembler-not {\msext\.w\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c index 7ef4c29..28350e5 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */ /* { dg-skip-if "" { *-*-* } { "-g" } } */ /* { dg-final { check-function-bodies "**" "" } } */ -/* { dg-final { scan-assembler-not "and" } } */ +/* { dg-final { scan-assembler-not {\mand} } } */ /* **foo1: diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c index 2108ccc..cc44653 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -fno-lto -O2" } */ /* { dg-skip-if "" { *-*-* } { "-g" } } */ /* { dg-final { check-function-bodies "**" "" } } */ -/* { dg-final { scan-assembler-not "and" } } */ +/* { dg-final { scan-assembler-not {\mand} } } */ /* **foo1: diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c index 8c0711d..7a98a57 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */ /* { dg-skip-if "" { *-*-* } { "-g" } } */ /* { dg-final { check-function-bodies "**" "" } } */ -/* { dg-final { scan-assembler-not "and" } } */ +/* { dg-final { scan-assembler-not {\mand} } } */ /* **foo1: @@ -34,4 +34,4 @@ unsigned int foo3 (unsigned int rs1) ** ret */ unsigned int foo4 (unsigned int rs1) -{ return ((rs1 << 18) | (rs1 >> 14)); }
\ No newline at end of file +{ return ((rs1 << 18) | (rs1 >> 14)); } diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c index bda3f0e..a08a9eb 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */ /* { dg-skip-if "" { *-*-* } { "-g" } } */ /* { dg-final { check-function-bodies "**" "" } } */ -/* { dg-final { scan-assembler-not "and" } } */ +/* { dg-final { scan-assembler-not {\mand} } } */ /* **foo1: @@ -62,4 +62,4 @@ unsigned long foo4 (unsigned long rs1) tempt = tempt << 6; rs1 = tempt | (rs1 >> 20); return rs1 ; -}
\ No newline at end of file +} diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c index 30696f3..bf19b76 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */ /* { dg-skip-if "" { *-*-* } { "-g" } } */ /* { dg-final { check-function-bodies "**" "" } } */ -/* { dg-final { scan-assembler-not "and" } } */ +/* { dg-final { scan-assembler-not {\mand} } } */ /* **foo1: diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c index a305455..5c4b9f5 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -fno-lto -O2" } */ /* { dg-skip-if "" { *-*-* } { "-g" } } */ /* { dg-final { check-function-bodies "**" "" } } */ -/* { dg-final { scan-assembler-not "and" } } */ +/* { dg-final { scan-assembler-not {\mand} } } */ /* **foo1: diff --git a/gcc/testsuite/gcc.target/riscv/zbb-strlen.c b/gcc/testsuite/gcc.target/riscv/zbb-strlen.c index 19ebfae..267ee41 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-strlen.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-strlen.c @@ -13,7 +13,7 @@ my_str_len (const char *s) } /* { dg-final { scan-assembler "orc.b\t" } } */ -/* { dg-final { scan-assembler-not "jalr" } } */ -/* { dg-final { scan-assembler-not "call" } } */ -/* { dg-final { scan-assembler-not "jr" } } */ -/* { dg-final { scan-assembler-not "tail" } } */ +/* { dg-final { scan-assembler-not {\mjalr} } } */ +/* { dg-final { scan-assembler-not {\mcall} } } */ +/* { dg-final { scan-assembler-not {\mjr} } } */ +/* { dg-final { scan-assembler-not {\mtail} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c index 3ff7d9d..789dda1 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c +++ b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c @@ -7,5 +7,5 @@ int foo(int n) return __builtin_bswap32(n); } -/* { dg-final { scan-assembler "rev8" } } */ +/* { dg-final { scan-assembler {\mrev8} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c index 679b34c..3b8462d 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c +++ b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c @@ -7,6 +7,6 @@ int foo(int n) return __builtin_bswap16(n); } -/* { dg-final { scan-assembler "rev8" } } */ -/* { dg-final { scan-assembler "srli" } } */ +/* { dg-final { scan-assembler {\mrev8} } } */ +/* { dg-final { scan-assembler {\msrli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c b/gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c index 20feded..158d97b 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c +++ b/gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c @@ -7,5 +7,5 @@ int foo(int n) return __builtin_bswap32(n); } -/* { dg-final { scan-assembler "rev8" } } */ +/* { dg-final { scan-assembler {\mrev8} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c b/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c index c358f66..cb81f98 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c +++ b/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c @@ -7,6 +7,6 @@ int foo(int n) return __builtin_bswap16(n); } -/* { dg-final { scan-assembler "rev8" } } */ -/* { dg-final { scan-assembler "srli" } } */ +/* { dg-final { scan-assembler {\mrev8} } } */ +/* { dg-final { scan-assembler {\msrli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbbw.c b/gcc/testsuite/gcc.target/riscv/zbbw.c index f7b2b63..bdf6b0c 100644 --- a/gcc/testsuite/gcc.target/riscv/zbbw.c +++ b/gcc/testsuite/gcc.target/riscv/zbbw.c @@ -20,7 +20,7 @@ popcount (int i) } -/* { dg-final { scan-assembler-times "clzw" 1 } } */ -/* { dg-final { scan-assembler-times "ctzw" 1 } } */ -/* { dg-final { scan-assembler-times "cpopw" 1 } } */ +/* { dg-final { scan-assembler-times {\mclzw} 1 } } */ +/* { dg-final { scan-assembler-times {\mctzw} 1 } } */ +/* { dg-final { scan-assembler-times {\mcpopw} 1 } } */ /* { dg-final { scan-assembler-not "andi\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbc32.c b/gcc/testsuite/gcc.target/riscv/zbc32.c index f3fb223..049ea95 100644 --- a/gcc/testsuite/gcc.target/riscv/zbc32.c +++ b/gcc/testsuite/gcc.target/riscv/zbc32.c @@ -19,5 +19,5 @@ uint32_t foo3(uint32_t rs1, uint32_t rs2) } /* { dg-final { scan-assembler-times "clmul\t" 1 } } */ -/* { dg-final { scan-assembler-times "clmulh" 1 } } */ -/* { dg-final { scan-assembler-times "clmulr" 1 } } */ +/* { dg-final { scan-assembler-times {\mclmulh} 1 } } */ +/* { dg-final { scan-assembler-times {\mclmulr} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbc64.c b/gcc/testsuite/gcc.target/riscv/zbc64.c index 841a0aa..69dadd1 100644 --- a/gcc/testsuite/gcc.target/riscv/zbc64.c +++ b/gcc/testsuite/gcc.target/riscv/zbc64.c @@ -19,5 +19,5 @@ uint64_t foo3(uint64_t rs1, uint64_t rs2) } /* { dg-final { scan-assembler-times "clmul\t" 1 } } */ -/* { dg-final { scan-assembler-times "clmulh" 1 } } */ -/* { dg-final { scan-assembler-times "clmulr" 1 } } */ +/* { dg-final { scan-assembler-times {\mclmulh} 1 } } */ +/* { dg-final { scan-assembler-times {\mclmulr} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkb32.c b/gcc/testsuite/gcc.target/riscv/zbkb32.c index b2e442d..841f5e0 100644 --- a/gcc/testsuite/gcc.target/riscv/zbkb32.c +++ b/gcc/testsuite/gcc.target/riscv/zbkb32.c @@ -30,7 +30,7 @@ uint32_t foo5(uint32_t rs1) } /* { dg-final { scan-assembler-times "pack\t" 1 } } */ -/* { dg-final { scan-assembler-times "packh" 1 } } */ -/* { dg-final { scan-assembler-times "brev8" 1 } } */ +/* { dg-final { scan-assembler-times {\mpackh} 1 } } */ +/* { dg-final { scan-assembler-times {\mbrev8} 1 } } */ /* { dg-final { scan-assembler-times "\tzip\t" 1 } } */ -/* { dg-final { scan-assembler-times "unzip" 1 } } */ +/* { dg-final { scan-assembler-times {\munzip} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkb64.c b/gcc/testsuite/gcc.target/riscv/zbkb64.c index 08ac9c2..8b6a0bf 100644 --- a/gcc/testsuite/gcc.target/riscv/zbkb64.c +++ b/gcc/testsuite/gcc.target/riscv/zbkb64.c @@ -23,6 +23,6 @@ uint64_t foo4(uint64_t rs1, uint64_t rs2) return __builtin_riscv_brev8(rs1); } /* { dg-final { scan-assembler-times "pack\t" 1 } } */ -/* { dg-final { scan-assembler-times "packh" 1 } } */ -/* { dg-final { scan-assembler-times "packw" 1 } } */ -/* { dg-final { scan-assembler-times "brev8" 1 } } */ +/* { dg-final { scan-assembler-times {\mpackh} 1 } } */ +/* { dg-final { scan-assembler-times {\mpackw} 1 } } */ +/* { dg-final { scan-assembler-times {\mbrev8} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkc32.c b/gcc/testsuite/gcc.target/riscv/zbkc32.c index 29f0d62..6d2a8ff 100644 --- a/gcc/testsuite/gcc.target/riscv/zbkc32.c +++ b/gcc/testsuite/gcc.target/riscv/zbkc32.c @@ -14,4 +14,4 @@ uint32_t foo2(uint32_t rs1, uint32_t rs2) } /* { dg-final { scan-assembler-times "clmul\t" 1 } } */ -/* { dg-final { scan-assembler-times "clmulh" 1 } } */ +/* { dg-final { scan-assembler-times {\mclmulh} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkc64.c b/gcc/testsuite/gcc.target/riscv/zbkc64.c index 53e6ac2..3708fb5 100644 --- a/gcc/testsuite/gcc.target/riscv/zbkc64.c +++ b/gcc/testsuite/gcc.target/riscv/zbkc64.c @@ -14,4 +14,4 @@ uint64_t foo2(uint64_t rs1, uint64_t rs2) } /* { dg-final { scan-assembler-times "clmul\t" 1 } } */ -/* { dg-final { scan-assembler-times "clmulh" 1 } } */ +/* { dg-final { scan-assembler-times {\mclmulh} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkx32.c b/gcc/testsuite/gcc.target/riscv/zbkx32.c index b8b822a..b41fd90 100644 --- a/gcc/testsuite/gcc.target/riscv/zbkx32.c +++ b/gcc/testsuite/gcc.target/riscv/zbkx32.c @@ -14,5 +14,5 @@ uint32_t foo4(uint32_t rs1, uint32_t rs2) return __builtin_riscv_xperm4(rs1, rs2); } -/* { dg-final { scan-assembler-times "xperm8" 1 } } */ -/* { dg-final { scan-assembler-times "xperm4" 1 } } */ +/* { dg-final { scan-assembler-times {\mxperm8} 1 } } */ +/* { dg-final { scan-assembler-times {\mxperm4} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkx64.c b/gcc/testsuite/gcc.target/riscv/zbkx64.c index 7324367..9ed42b4 100644 --- a/gcc/testsuite/gcc.target/riscv/zbkx64.c +++ b/gcc/testsuite/gcc.target/riscv/zbkx64.c @@ -14,5 +14,5 @@ uint64_t foo2(uint64_t rs1, uint64_t rs2) return __builtin_riscv_xperm4(rs1, rs2); } -/* { dg-final { scan-assembler-times "xperm8" 1 } } */ -/* { dg-final { scan-assembler-times "xperm4" 1 } } */ +/* { dg-final { scan-assembler-times {\mxperm8} 1 } } */ +/* { dg-final { scan-assembler-times {\mxperm4} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bclr.c b/gcc/testsuite/gcc.target/riscv/zbs-bclr.c index 5d7daa3..e37580d 100644 --- a/gcc/testsuite/gcc.target/riscv/zbs-bclr.c +++ b/gcc/testsuite/gcc.target/riscv/zbs-bclr.c @@ -18,4 +18,4 @@ foo1 (long i) /* { dg-final { scan-assembler-times "bclr\t" 1 } } */ /* { dg-final { scan-assembler-times "bclri\t" 1 } } */ -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bext-02.c b/gcc/testsuite/gcc.target/riscv/zbs-bext-02.c index 3f3b840..8c5d8c7 100644 --- a/gcc/testsuite/gcc.target/riscv/zbs-bext-02.c +++ b/gcc/testsuite/gcc.target/riscv/zbs-bext-02.c @@ -14,5 +14,5 @@ foo(const long long B, int a) } /* { dg-final { scan-assembler-times "bext\t" 1 } } */ -/* { dg-final { scan-assembler-not "bset" } } */ -/* { dg-final { scan-assembler-not "and" } } */ +/* { dg-final { scan-assembler-not {\mbset} } } */ +/* { dg-final { scan-assembler-not {\mand} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bext.c b/gcc/testsuite/gcc.target/riscv/zbs-bext.c index a8aadb6..ff75dad 100644 --- a/gcc/testsuite/gcc.target/riscv/zbs-bext.c +++ b/gcc/testsuite/gcc.target/riscv/zbs-bext.c @@ -41,4 +41,4 @@ long bext64_4(long a, char bitno) /* { dg-final { scan-assembler-times "xori\t|snez\t" 1 } } */ /* { dg-final { scan-assembler-times "addi\t" 1 } } */ /* { dg-final { scan-assembler-times "neg\t" 1 } } */ -/* { dg-final { scan-assembler-not "andi" } } */
\ No newline at end of file +/* { dg-final { scan-assembler-not {\mandi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbs-binv.c b/gcc/testsuite/gcc.target/riscv/zbs-binv.c index d8d6e47..f4bf27e 100644 --- a/gcc/testsuite/gcc.target/riscv/zbs-binv.c +++ b/gcc/testsuite/gcc.target/riscv/zbs-binv.c @@ -18,4 +18,4 @@ foo1 (long i) /* { dg-final { scan-assembler-times "binv\t" 1 } } */ /* { dg-final { scan-assembler-times "binvi\t" 1 } } */ -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bset.c b/gcc/testsuite/gcc.target/riscv/zbs-bset.c index cea2b64..4a5b6f5 100644 --- a/gcc/testsuite/gcc.target/riscv/zbs-bset.c +++ b/gcc/testsuite/gcc.target/riscv/zbs-bset.c @@ -39,4 +39,4 @@ sub4 (long i) /* { dg-final { scan-assembler-times "bset\t" 4 } } */ /* { dg-final { scan-assembler-times "bseti\t" 1 } } */ -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-1.c b/gcc/testsuite/gcc.target/riscv/zero-extend-1.c index b61ea8e..754842f 100644 --- a/gcc/testsuite/gcc.target/riscv/zero-extend-1.c +++ b/gcc/testsuite/gcc.target/riscv/zero-extend-1.c @@ -5,4 +5,4 @@ sub1 (unsigned int i) { return i >> 1; } -/* { dg-final { scan-assembler-times "srliw" 1 } } */ +/* { dg-final { scan-assembler-times {\msrliw} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-2.c b/gcc/testsuite/gcc.target/riscv/zero-extend-2.c index c3d6eeb..da48fe5 100644 --- a/gcc/testsuite/gcc.target/riscv/zero-extend-2.c +++ b/gcc/testsuite/gcc.target/riscv/zero-extend-2.c @@ -10,4 +10,4 @@ sub (unsigned int wc, unsigned long step, unsigned char *start) } while (step > 1); } -/* { dg-final { scan-assembler-times "sext.w" 0 } } */ +/* { dg-final { scan-assembler-times {\msext\.w\M} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-3.c b/gcc/testsuite/gcc.target/riscv/zero-extend-3.c index 6485ebd..c567300 100644 --- a/gcc/testsuite/gcc.target/riscv/zero-extend-3.c +++ b/gcc/testsuite/gcc.target/riscv/zero-extend-3.c @@ -9,4 +9,4 @@ c (void) d = b; return d; } -/* { dg-final { scan-assembler-times "sext.w" 0 } } */ +/* { dg-final { scan-assembler-times {\msext\.w\M} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-4.c b/gcc/testsuite/gcc.target/riscv/zero-extend-4.c index e1a8922..3c776b0 100644 --- a/gcc/testsuite/gcc.target/riscv/zero-extend-4.c +++ b/gcc/testsuite/gcc.target/riscv/zero-extend-4.c @@ -18,4 +18,4 @@ f(void) d->binmap[0] = e; } } -/* { dg-final { scan-assembler-times "sext.w" 0 } } */ +/* { dg-final { scan-assembler-times {\msext\.w\M} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-5.c b/gcc/testsuite/gcc.target/riscv/zero-extend-5.c index 4e58a15..2f68961 100644 --- a/gcc/testsuite/gcc.target/riscv/zero-extend-5.c +++ b/gcc/testsuite/gcc.target/riscv/zero-extend-5.c @@ -5,4 +5,4 @@ sub (unsigned int i, unsigned int j, unsigned int k, int *array) { return array[i] + array[j] + array[k]; } -/* { dg-final { scan-assembler-times "slli" 3 } } */ +/* { dg-final { scan-assembler-times {\mslli} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c index 9161dd3..cf3dfac 100644 --- a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c +++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c @@ -6,7 +6,7 @@ foo (void) { } -/* { dg-final { scan-assembler-not "vsetvli" } } */ +/* { dg-final { scan-assembler-not {\mvsetvli} } } */ /* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */ /* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */ /* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq.c b/gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq.c index 7c28b0b..7477738 100644 --- a/gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq.c +++ b/gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq.c @@ -14,7 +14,7 @@ foo() abort(); } -/* { dg-final { scan-assembler-times "fleq.s" 1 } } */ -/* { dg-final { scan-assembler-times "fltq.s" 1 } } */ -/* { dg-final { scan-assembler-times "fleq.d" 1 } } */ -/* { dg-final { scan-assembler-times "fltq.d" 1 } } */ +/* { dg-final { scan-assembler-times {\mfleq\.s\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mfltq\.s\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mfleq\.d\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mfltq\.d\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c b/gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c index 05e2dcb..a97c7bd2 100644 --- a/gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c +++ b/gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c @@ -39,4 +39,4 @@ void foo_float16 () a = __builtin_nanf16 (""); } -/* { dg-final { scan-assembler-times "fli.h" 32 } } */ +/* { dg-final { scan-assembler-times {\mfli\.h\M} 32 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fli.c b/gcc/testsuite/gcc.target/riscv/zfa-fli.c index e5c1e59..d7269c5 100644 --- a/gcc/testsuite/gcc.target/riscv/zfa-fli.c +++ b/gcc/testsuite/gcc.target/riscv/zfa-fli.c @@ -76,5 +76,5 @@ void foo_double64 () a = __builtin_nan (""); } -/* { dg-final { scan-assembler-times "fli.s" 32 } } */ -/* { dg-final { scan-assembler-times "fli.d" 32 } } */ +/* { dg-final { scan-assembler-times {\mfli\.s\M} 32 } } */ +/* { dg-final { scan-assembler-times {\mfli\.d\M} 32 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics.c index 47d4e4c..bcfa04b 100644 --- a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics.c +++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics.c @@ -43,7 +43,7 @@ int primitiveSemantics_11(int a, int b) { return b; } -/* { dg-final { scan-assembler-times "czero.eqz" 6 } } */ -/* { dg-final { scan-assembler-times "czero.nez" 6 } } */ -/* { dg-final { scan-assembler-not "beq" } } */ -/* { dg-final { scan-assembler-not "bne" } } */ +/* { dg-final { scan-assembler-times {\mczero\.eqz\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mczero\.nez\M} 6 } } */ +/* { dg-final { scan-assembler-not {\mbeq} } } */ +/* { dg-final { scan-assembler-not {\mbne} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c new file mode 100644 index 0000000..0764d29 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c @@ -0,0 +1,65 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz"} } */ + +long primitiveSemantics_return_0_imm_00(long a, long b) { + return a == 0 ? 0 : 3; +} + +long primitiveSemantics_return_0_imm_01(long a, long b) { + return a != 0 ? 0 : 3; +} + +long primitiveSemantics_return_0_imm_02(long a, long b) { + return a == 0 ? 3 : 0; +} + +long primitiveSemantics_return_0_imm_03(long a, long b) { + return a != 0 ? 3 : 0; +} + +long primitiveSemantics_return_0_imm_04(long a, long b) { + if (a) + b = 0; + else + b = 3; + return b; +} + +long primitiveSemantics_return_0_imm_05(long a, long b) { + if (!a) + b = 0; + else + b = 3; + return b; +} + +int primitiveSemantics_return_0_imm_06(int a, int b) { return a == 0 ? 0 : 3; } + +int primitiveSemantics_return_0_imm_07(int a, int b) { return a != 0 ? 0 : 3; } + +int primitiveSemantics_return_0_imm_08(int a, int b) { return a == 0 ? 3 : 0; } + +int primitiveSemantics_return_0_imm_09(int a, int b) { return a != 0 ? 3 : 0; } + +int primitiveSemantics_return_0_imm_10(int a, int b) { + if (a) + b = 0; + else + b = 3; + return b; +} + +int primitiveSemantics_return_0_imm_11(int a, int b) { + if (!a) + b = 0; + else + b = 3; + return b; +} + +/* { dg-final { scan-assembler-times {\mczero\.eqz\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mczero\.nez\M} 6 } } */ +/* { dg-final { scan-assembler-not {\mbeq} } } */ +/* { dg-final { scan-assembler-not {\mbne} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c new file mode 100644 index 0000000..2ff5033 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz"} } */ + +long primitiveSemantics_return_imm_imm_00(long a, long b) { + return a == 0 ? 4 : 6; +} + +long primitiveSemantics_return_imm_imm_01(long a, long b) { + return a != 0 ? 4 : 6; +} + +long primitiveSemantics_return_imm_imm_02(long a, long b) { + return a == 0 ? 6 : 4; +} + +long primitiveSemantics_return_imm_imm_03(long a, long b) { + return a != 0 ? 6 : 4; +} + +long primitiveSemantics_return_imm_imm_04(long a, long b) { + if (a) + b = 4; + else + b = 6; + return b; +} + +long primitiveSemantics_return_imm_imm_05(long a, long b) { + if (!a) + b = 4; + else + b = 6; + return b; +} + +int primitiveSemantics_return_imm_imm_06(int a, int b) { + return a == 0 ? 4 : 6; +} + +int primitiveSemantics_return_imm_imm_07(int a, int b) { + return a != 0 ? 4 : 6; +} + +int primitiveSemantics_return_imm_imm_08(int a, int b) { + return a == 0 ? 6 : 4; +} + +int primitiveSemantics_return_imm_imm_09(int a, int b) { + return a != 0 ? 6 : 4; +} + +int primitiveSemantics_return_imm_imm_10(int a, int b) { + if (a) + b = 4; + else + b = 6; + return b; +} + +int primitiveSemantics_return_imm_imm_11(int a, int b) { + if (!a) + b = 4; + else + b = 6; + return b; +} + +/* { dg-final { scan-assembler-times {\mczero\.eqz\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mczero\.nez\M} 6 } } */ +/* { dg-final { scan-assembler-not {\mbeq} } } */ +/* { dg-final { scan-assembler-not {\mbne} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c new file mode 100644 index 0000000..93844d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c @@ -0,0 +1,65 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz"} } */ + +long primitiveSemantics_return_imm_reg_00(long a, long b) { + return a == 0 ? 1 : b; +} + +long primitiveSemantics_return_imm_reg_01(long a, long b) { + return a != 0 ? 1 : b; +} + +long primitiveSemantics_return_imm_reg_02(long a, long b) { + return a == 0 ? b : 1; +} + +long primitiveSemantics_return_imm_reg_03(long a, long b) { + return a != 0 ? b : 1; +} + +long primitiveSemantics_return_imm_reg_04(long a, long b) { + if (a) + b = 1; + return b; +} + +long primitiveSemantics_return_imm_reg_05(long a, long b) { + if (!a) + b = 1; + return b; +} + +int primitiveSemantics_return_imm_reg_06(int a, int b) { + return a == 0 ? 1 : b; +} + +int primitiveSemantics_return_imm_reg_07(int a, int b) { + return a != 0 ? 1 : b; +} + +int primitiveSemantics_return_imm_reg_08(int a, int b) { + return a == 0 ? b : 1; +} + +int primitiveSemantics_return_imm_reg_09(int a, int b) { + return a != 0 ? b : 1; +} + +int primitiveSemantics_return_imm_reg_10(int a, int b) { + if (a) + b = 1; + return b; +} + +int primitiveSemantics_return_imm_reg_11(int a, int b) { + if (!a) + b = 1; + return b; +} + +/* { dg-final { scan-assembler-times {\mczero\.eqz\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mczero\.nez\M} 6 } } */ +/* { dg-final { scan-assembler-not {\mbeq} } } */ +/* { dg-final { scan-assembler-not {\mbne} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c new file mode 100644 index 0000000..619ad8e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c @@ -0,0 +1,65 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz"} } */ + +long primitiveSemantics_return_reg_reg_00(long a, long b, long c) { + return a == 0 ? c : b; +} + +long primitiveSemantics_return_reg_reg_01(long a, long b, long c) { + return a != 0 ? c : b; +} + +long primitiveSemantics_return_reg_reg_02(long a, long b, long c) { + return a == 0 ? b : c; +} + +long primitiveSemantics_return_reg_reg_03(long a, long b, long c) { + return a != 0 ? b : c; +} + +long primitiveSemantics_return_reg_reg_04(long a, long b, long c) { + if (a) + b = c; + return b; +} + +long primitiveSemantics_return_reg_reg_05(long a, long b, long c) { + if (!a) + b = c; + return b; +} + +int primitiveSemantics_return_reg_reg_06(int a, int b, int c) { + return a == 0 ? c : b; +} + +int primitiveSemantics_return_reg_reg_07(int a, int b, int c) { + return a != 0 ? c : b; +} + +int primitiveSemantics_return_reg_reg_08(int a, int b, int c) { + return a == 0 ? b : c; +} + +int primitiveSemantics_return_reg_reg_09(int a, int b, int c) { + return a != 0 ? b : c; +} + +int primitiveSemantics_return_reg_reg_10(int a, int b, int c) { + if (a) + b = c; + return b; +} + +int primitiveSemantics_return_reg_reg_11(int a, int b, int c) { + if (!a) + b = c; + return b; +} + +/* { dg-final { scan-assembler-times {\mczero\.eqz\M} 12 } } */ +/* { dg-final { scan-assembler-times {\mczero\.nez\M} 12 } } */ +/* { dg-final { scan-assembler-not {\mbeq} } } */ +/* { dg-final { scan-assembler-not {\mbne} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zknd64.c b/gcc/testsuite/gcc.target/riscv/zknd64.c index 910b91c..707418c 100644 --- a/gcc/testsuite/gcc.target/riscv/zknd64.c +++ b/gcc/testsuite/gcc.target/riscv/zknd64.c @@ -33,4 +33,4 @@ uint64_t foo5(uint64_t rs1) /* { dg-final { scan-assembler-times "aes64dsm" 1 } } */ /* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */ /* { dg-final { scan-assembler-times "aes64ks2" 1 } } */ -/* { dg-final { scan-assembler-times "aes64im" 1 } } */ +/* { dg-final { scan-assembler-times {\maes64im} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zksed32.c b/gcc/testsuite/gcc.target/riscv/zksed32.c index 7df0414..0e8f01c 100644 --- a/gcc/testsuite/gcc.target/riscv/zksed32.c +++ b/gcc/testsuite/gcc.target/riscv/zksed32.c @@ -15,5 +15,5 @@ uint32_t foo2(uint32_t rs1, uint32_t rs2, unsigned bs) } -/* { dg-final { scan-assembler-times "sm4ks" 1 } } */ -/* { dg-final { scan-assembler-times "sm4ed" 1 } } */ +/* { dg-final { scan-assembler-times {\msm4ks} 1 } } */ +/* { dg-final { scan-assembler-times {\msm4ed} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zksed64.c b/gcc/testsuite/gcc.target/riscv/zksed64.c index 913e7be..9e4d196 100644 --- a/gcc/testsuite/gcc.target/riscv/zksed64.c +++ b/gcc/testsuite/gcc.target/riscv/zksed64.c @@ -15,5 +15,5 @@ uint32_t foo2(uint32_t rs1, uint32_t rs2, unsigned bs) } -/* { dg-final { scan-assembler-times "sm4ks" 1 } } */ -/* { dg-final { scan-assembler-times "sm4ed" 1 } } */ +/* { dg-final { scan-assembler-times {\msm4ks} 1 } } */ +/* { dg-final { scan-assembler-times {\msm4ed} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zksh32.c b/gcc/testsuite/gcc.target/riscv/zksh32.c index 20513f9..c182e55 100644 --- a/gcc/testsuite/gcc.target/riscv/zksh32.c +++ b/gcc/testsuite/gcc.target/riscv/zksh32.c @@ -15,5 +15,5 @@ uint32_t foo2(uint32_t rs1) } -/* { dg-final { scan-assembler-times "sm3p0" 1 } } */ -/* { dg-final { scan-assembler-times "sm3p1" 1 } } */ +/* { dg-final { scan-assembler-times {\msm3p0} 1 } } */ +/* { dg-final { scan-assembler-times {\msm3p1} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zksh64.c b/gcc/testsuite/gcc.target/riscv/zksh64.c index 30bb1bd..d794b39 100644 --- a/gcc/testsuite/gcc.target/riscv/zksh64.c +++ b/gcc/testsuite/gcc.target/riscv/zksh64.c @@ -15,5 +15,5 @@ uint32_t foo2(uint32_t rs1) } -/* { dg-final { scan-assembler-times "sm3p0" 1 } } */ -/* { dg-final { scan-assembler-times "sm3p1" 1 } } */ +/* { dg-final { scan-assembler-times {\msm3p0} 1 } } */ +/* { dg-final { scan-assembler-times {\msm3p1} 1 } } */ diff --git a/gcc/testsuite/gdc.test/compilable/test23145.d b/gcc/testsuite/gdc.test/compilable/test23145.d index 45235dc..18eabfb 100644 --- a/gcc/testsuite/gdc.test/compilable/test23145.d +++ b/gcc/testsuite/gdc.test/compilable/test23145.d @@ -1,8 +1,9 @@ -/* TEST_OUTPUT: +/* REQUIRED_ARGS: -wo -wi +TEST_OUTPUT: --- -compilable/test23145.d(117): Deprecation: `scope` allocation of `c` requires that constructor be annotated with `scope` +compilable/test23145.d(117): Warning: `scope` allocation of `c` requires that constructor be annotated with `scope` compilable/test23145.d(111): is the location of the constructor -compilable/test23145.d(124): Deprecation: `scope` allocation of `c` requires that constructor be annotated with `scope` +compilable/test23145.d(124): Warning: `scope` allocation of `c` requires that constructor be annotated with `scope` compilable/test23145.d(111): is the location of the constructor --- */ @@ -24,7 +25,7 @@ class C this(D d) @safe @nogc; } -C foo(D d)@nogc @safe +C foo(D d) @nogc @safe { scope e = new C(1); // ok scope c = new C(d); // deprecation @@ -37,3 +38,8 @@ C bax(D d) @safe scope c = new C(d); // deprecation return c.d.c; } + +void inferred(D d) +{ + scope c = new C(d); // ok +} diff --git a/gcc/testsuite/gdc.test/fail_compilation/biterrors3.d b/gcc/testsuite/gdc.test/fail_compilation/biterrors3.d index c5031a4..09d7be6 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/biterrors3.d +++ b/gcc/testsuite/gdc.test/fail_compilation/biterrors3.d @@ -3,8 +3,8 @@ --- fail_compilation/biterrors3.d(103): Error: storage class not allowed for bit-field declaration fail_compilation/biterrors3.d(106): Error: expected `,` or `=` after identifier, not `:` -fail_compilation/biterrors3.d(106): Error: `:` is not a valid attribute for enum members -fail_compilation/biterrors3.d(106): Error: `3` is not a valid attribute for enum members +fail_compilation/biterrors3.d(106): Error: found `:` when expecting `,` +fail_compilation/biterrors3.d(106): Error: found `3` when expecting `identifier` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/bug8891.d b/gcc/testsuite/gdc.test/fail_compilation/bug8891.d index e7316c3..7b927f9 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/bug8891.d +++ b/gcc/testsuite/gdc.test/fail_compilation/bug8891.d @@ -1,7 +1,7 @@ /* TEST_OUTPUT: --- -fail_compilation/bug8891.d(21): Error: need `this` for `opCall` of type `S(int n)` +fail_compilation/bug8891.d(21): Error: calling non-static function `opCall` requires an instance of type `S` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/deprecatedinref.d b/gcc/testsuite/gdc.test/fail_compilation/deprecatedinref.d deleted file mode 100644 index 20c3666..0000000 --- a/gcc/testsuite/gdc.test/fail_compilation/deprecatedinref.d +++ /dev/null @@ -1,10 +0,0 @@ -/* -REQUIRED_ARGS: -de -TEST_OUTPUT: ---- -fail_compilation/deprecatedinref.d(9): Deprecation: using `in ref` is deprecated, use `-preview=in` and `in` instead -fail_compilation/deprecatedinref.d(10): Deprecation: using `ref in` is deprecated, use `-preview=in` and `in` instead ---- -*/ -void foo(in ref int); -void foor(ref in int); diff --git a/gcc/testsuite/gdc.test/fail_compilation/diag15209.d b/gcc/testsuite/gdc.test/fail_compilation/diag15209.d index 9a4f396..bd6d723 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/diag15209.d +++ b/gcc/testsuite/gdc.test/fail_compilation/diag15209.d @@ -1,8 +1,8 @@ /* TEST_OUTPUT: --- -fail_compilation/diag15209.d(18): Error: need `this` for `x` of type `int` -fail_compilation/diag15209.d(21): Error: need `this` for `x` of type `int` +fail_compilation/diag15209.d(18): Error: accessing non-static variable `x` requires an instance of `C1` +fail_compilation/diag15209.d(21): Error: accessing non-static variable `x` requires an instance of `S2` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/diag9451.d b/gcc/testsuite/gdc.test/fail_compilation/diag9451.d index ffec627..980c689 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/diag9451.d +++ b/gcc/testsuite/gdc.test/fail_compilation/diag9451.d @@ -1,11 +1,12 @@ /* TEST_OUTPUT: --- -fail_compilation/diag9451.d(26): Error: cannot create instance of abstract class `C2` -fail_compilation/diag9451.d(26): function `void f1()` is not implemented -fail_compilation/diag9451.d(26): function `void f2(int)` is not implemented -fail_compilation/diag9451.d(26): function `void f2(float) const` is not implemented -fail_compilation/diag9451.d(26): function `int f2(float) pure` is not implemented +fail_compilation/diag9451.d(27): Error: cannot create instance of abstract class `C2` +fail_compilation/diag9451.d(21): class `C2` is declared here +fail_compilation/diag9451.d(15): function `void f1()` is not implemented +fail_compilation/diag9451.d(16): function `void f2(int)` is not implemented +fail_compilation/diag9451.d(17): function `void f2(float) const` is not implemented +fail_compilation/diag9451.d(18): function `int f2(float) pure` is not implemented --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/diag9635.d b/gcc/testsuite/gdc.test/fail_compilation/diag9635.d index fe142ad..9794c8f 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/diag9635.d +++ b/gcc/testsuite/gdc.test/fail_compilation/diag9635.d @@ -2,8 +2,8 @@ /* TEST_OUTPUT: --- -fail_compilation/diag9635.d(17): Error: need `this` for `i` of type `int` -fail_compilation/diag9635.d(18): Error: need `this` for `foo` of type `pure nothrow @nogc @safe void()` +fail_compilation/diag9635.d(17): Error: accessing non-static variable `i` requires an instance of `Foo` +fail_compilation/diag9635.d(18): Error: calling non-static function `foo` requires an instance of type `Foo` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/dip1000_deprecation.d b/gcc/testsuite/gdc.test/fail_compilation/dip1000_deprecation.d index 6117439..e591a14 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/dip1000_deprecation.d +++ b/gcc/testsuite/gdc.test/fail_compilation/dip1000_deprecation.d @@ -1,5 +1,5 @@ /* -REQUIRED_ARGS: -de +REQUIRED_ARGS: -de -wo TEST_OUTPUT: --- fail_compilation/dip1000_deprecation.d(20): Deprecation: `@safe` function `main` calling `inferred` @@ -9,17 +9,17 @@ fail_compilation/dip1000_deprecation.d(22): Deprecation: `@safe` function `main` fail_compilation/dip1000_deprecation.d(39): which calls `dip1000_deprecation.inferred` fail_compilation/dip1000_deprecation.d(28): which wouldn't be `@safe` because of: fail_compilation/dip1000_deprecation.d(28): scope variable `x0` may not be returned -fail_compilation/dip1000_deprecation.d(54): Deprecation: escaping reference to stack allocated value returned by `S(null)` -fail_compilation/dip1000_deprecation.d(55): Deprecation: escaping reference to stack allocated value returned by `createS()` -fail_compilation/dip1000_deprecation.d(58): Deprecation: returning `s.incorrectReturnRef()` escapes a reference to local variable `s` +fail_compilation/dip1000_deprecation.d(54): Warning: escaping reference to stack allocated value returned by `S(null)` +fail_compilation/dip1000_deprecation.d(55): Warning: escaping reference to stack allocated value returned by `createS()` +fail_compilation/dip1000_deprecation.d(58): Warning: returning `s.incorrectReturnRef()` escapes a reference to local variable `s` --- */ void main() @safe { - inferred(); - inferredB(); // no deprecation, trusted - inferredC(); // nested deprecation + cast(void)inferred(); + cast(void)inferredB(); // no deprecation, trusted + cast(void)inferredC(); // nested deprecation } auto inferred() @@ -49,10 +49,10 @@ struct S S createS() { return S.init; } -int* escape() +int* escape(int i) { - return S().incorrectReturnRef(); - return createS().incorrectReturnRef(); + if (i) return S().incorrectReturnRef(); + if (i) return createS().incorrectReturnRef(); S s; return s.incorrectReturnRef(); diff --git a/gcc/testsuite/gdc.test/fail_compilation/e15876_6.d b/gcc/testsuite/gdc.test/fail_compilation/e15876_6.d index 7547b38..6b060fd 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/e15876_6.d +++ b/gcc/testsuite/gdc.test/fail_compilation/e15876_6.d @@ -1,7 +1,7 @@ /* TEST_OUTPUT: --- -fail_compilation/e15876_6.d(7): Error: identifier expected following `(type)`. +fail_compilation/e15876_6.d(7): Error: identifier expected following `immutable(int).`, not `;` --- */ auto unaryExParseError = immutable(int).; diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail10285.d b/gcc/testsuite/gdc.test/fail_compilation/fail10285.d index c88e306..1087125 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail10285.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail10285.d @@ -1,11 +1,14 @@ /* TEST_OUTPUT: --- -fail_compilation/fail10285.d(13): Error: no identifier for declarator `int` -fail_compilation/fail10285.d(14): Error: expected `,` or `=` after identifier, not `y` -fail_compilation/fail10285.d(15): Error: expected identifier after type, not `bool` -fail_compilation/fail10285.d(16): Error: expected identifier after type, not `int` -fail_compilation/fail10285.d(18): Error: initializer required after `z` when type is specified +fail_compilation/fail10285.d(16): Error: no identifier for declarator `int` +fail_compilation/fail10285.d(17): Error: expected `,` or `=` after identifier, not `y` +fail_compilation/fail10285.d(17): Error: initializer required after `x` when type is specified +fail_compilation/fail10285.d(18): Error: no identifier for declarator `int` +fail_compilation/fail10285.d(18): Error: found `bool` when expecting `,` +fail_compilation/fail10285.d(19): Error: no identifier for declarator `j` +fail_compilation/fail10285.d(19): Error: found `int` when expecting `,` +fail_compilation/fail10285.d(21): Error: initializer required after `z` when type is specified --- */ enum diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail11545.d b/gcc/testsuite/gdc.test/fail_compilation/fail11545.d index a576817..01d8e93 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail11545.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail11545.d @@ -1,8 +1,8 @@ /* TEST_OUTPUT: --- -fail_compilation/fail11545.d(14): Error: need `this` for `x` of type `int` -fail_compilation/fail11545.d(18): Error: need `this` for `x` of type `int` +fail_compilation/fail11545.d(14): Error: accessing non-static variable `x` requires an instance of `C` +fail_compilation/fail11545.d(18): Error: accessing non-static variable `x` requires an instance of `C` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail120.d b/gcc/testsuite/gdc.test/fail_compilation/fail120.d index c9d67a4..f9ede04 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail120.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail120.d @@ -1,8 +1,8 @@ /* TEST_OUTPUT: --- -fail_compilation/fail120.d(12): Error: need `this` for `nodes` of type `int[2]` -fail_compilation/fail120.d(13): Error: need `this` for `nodes` of type `int[2]` +fail_compilation/fail120.d(12): Error: accessing non-static variable `nodes` requires an instance of `Foo` +fail_compilation/fail120.d(13): Error: accessing non-static variable `nodes` requires an instance of `Foo` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail142.d b/gcc/testsuite/gdc.test/fail_compilation/fail142.d index 343b2e3..c31a317 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail142.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail142.d @@ -1,8 +1,9 @@ /* TEST_OUTPUT: --- -fail_compilation/fail142.d(20): Error: cannot create instance of abstract class `B` -fail_compilation/fail142.d(20): function `void test()` is not implemented +fail_compilation/fail142.d(21): Error: cannot create instance of abstract class `B` +fail_compilation/fail142.d(15): class `B` is declared here +fail_compilation/fail142.d(12): function `void test()` is not implemented --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail143.d b/gcc/testsuite/gdc.test/fail_compilation/fail143.d index 6df232f..e5ccb0f 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail143.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail143.d @@ -1,7 +1,7 @@ /* TEST_OUTPUT: --- -fail_compilation/fail143.d(23): Error: need `this` for `next` of type `uint()` +fail_compilation/fail143.d(23): Error: calling non-static function `next` requires an instance of type `Quux` fail_compilation/fail143.d(30): Error: template instance `fail143.Foo!int` error instantiating --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail144.d b/gcc/testsuite/gdc.test/fail_compilation/fail144.d index 6e73d3b..4977e4d 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail144.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail144.d @@ -1,7 +1,7 @@ /* TEST_OUTPUT: --- -fail_compilation/fail144.d(13): Error: `"message"` +fail_compilation/fail144.d(13): Error: message fail_compilation/fail144.d(26): called from here: `bar(7)` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail145.d b/gcc/testsuite/gdc.test/fail_compilation/fail145.d index 5a7a4ca..1e90237 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail145.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail145.d @@ -2,7 +2,7 @@ REQUIRED_ARGS: -checkaction=context TEST_OUTPUT: --- -fail_compilation/fail145.d(14): Error: `"assert(i && (i < 0)) failed"` +fail_compilation/fail145.d(14): Error: `assert(i && (i < 0))` failed fail_compilation/fail145.d(27): called from here: `bar(7)` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail17955.d b/gcc/testsuite/gdc.test/fail_compilation/fail17955.d index 0832919..43ce5cc 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail17955.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail17955.d @@ -2,19 +2,20 @@ /* TEST_OUTPUT: --- -fail_compilation/fail17955.d(81): Error: cannot create instance of abstract class `SimpleTimeZone` -fail_compilation/fail17955.d(81): function `bool hasDST()` is not implemented -fail_compilation/fail17955.d(93): Error: template instance `fail17955.SimpleTimeZone.fromISOExtString!dstring` error instantiating -fail_compilation/fail17955.d(25): instantiated from here: `fromISOExtString!string` -fail_compilation/fail17955.d(56): instantiated from here: `isISOExtStringSerializable!(SysTime)` -fail_compilation/fail17955.d(49): instantiated from here: `toRedis!(SysTime)` -fail_compilation/fail17955.d(40): ... (2 instantiations, -v to show) ... -fail_compilation/fail17955.d(32): instantiated from here: `indicesOf!(isRedisType, resetCodeExpireTime)` -fail_compilation/fail17955.d(67): instantiated from here: `RedisStripped!(User, true)` -fail_compilation/fail17955.d(93): Error: need `this` for `fromISOExtString` of type `pure nothrow @nogc @safe immutable(SimpleTimeZone)(dstring __param_0)` -fail_compilation/fail17955.d(95): Error: undefined identifier `DateTimeException` -fail_compilation/fail17955.d(25): Error: variable `fail17955.isISOExtStringSerializable!(SysTime).isISOExtStringSerializable` - type `void` is inferred from initializer `fromISOExtString("")`, and variables cannot be of type `void` -fail_compilation/fail17955.d(54): Error: function `fail17955.toRedis!(SysTime).toRedis` has no `return` statement, but is expected to return a value of type `string` +fail_compilation/fail17955.d(82): Error: cannot create instance of abstract class `SimpleTimeZone` +fail_compilation/fail17955.d(76): class `SimpleTimeZone` is declared here +fail_compilation/fail17955.d(73): function `bool hasDST()` is not implemented +fail_compilation/fail17955.d(94): Error: template instance `fail17955.SimpleTimeZone.fromISOExtString!dstring` error instantiating +fail_compilation/fail17955.d(26): instantiated from here: `fromISOExtString!string` +fail_compilation/fail17955.d(57): instantiated from here: `isISOExtStringSerializable!(SysTime)` +fail_compilation/fail17955.d(50): instantiated from here: `toRedis!(SysTime)` +fail_compilation/fail17955.d(41): ... (2 instantiations, -v to show) ... +fail_compilation/fail17955.d(33): instantiated from here: `indicesOf!(isRedisType, resetCodeExpireTime)` +fail_compilation/fail17955.d(68): instantiated from here: `RedisStripped!(User, true)` +fail_compilation/fail17955.d(94): Error: calling non-static function `fromISOExtString` requires an instance of type `SimpleTimeZone` +fail_compilation/fail17955.d(96): Error: undefined identifier `DateTimeException` +fail_compilation/fail17955.d(26): Error: variable `fail17955.isISOExtStringSerializable!(SysTime).isISOExtStringSerializable` - type `void` is inferred from initializer `fromISOExtString("")`, and variables cannot be of type `void` +fail_compilation/fail17955.d(55): Error: function `fail17955.toRedis!(SysTime).toRedis` has no `return` statement, but is expected to return a value of type `string` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail20538.d b/gcc/testsuite/gdc.test/fail_compilation/fail20538.d index df7f142e..e07af6c 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail20538.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail20538.d @@ -1,8 +1,9 @@ /* TEST_OUTPUT: --- -fail_compilation/fail20538.d(12): Error: assignment must be preceded by an identifier -fail_compilation/fail20538.d(12): Error: found `1` when expecting `,` +fail_compilation/fail20538.d(13): Error: found `=` when expecting `identifier` +fail_compilation/fail20538.d(13): Error: found `1` when expecting `identifier` +fail_compilation/fail20538.d(14): Error: named enum cannot declare member with type --- */ @@ -10,5 +11,6 @@ enum smth { a, = 1, + int x = 1, @disable b } diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail25.d b/gcc/testsuite/gdc.test/fail_compilation/fail25.d index 11c0f0b..abb795e 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail25.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail25.d @@ -1,7 +1,7 @@ /* TEST_OUTPUT: --- -fail_compilation/fail25.d(14): Error: need `this` for `yuiop` of type `int` +fail_compilation/fail25.d(14): Error: accessing non-static variable `yuiop` requires an instance of `Qwert` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail301.d b/gcc/testsuite/gdc.test/fail_compilation/fail301.d index bf90f55..f527819 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail301.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail301.d @@ -1,7 +1,7 @@ /* TEST_OUTPUT: --- -fail_compilation/fail301.d(11): Error: need `this` for `guard` of type `int` +fail_compilation/fail301.d(11): Error: accessing non-static variable `guard` requires an instance of `bug3305b` fail_compilation/fail301.d(22): Error: template instance `fail301.bug3305!0` error instantiating --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail46.d b/gcc/testsuite/gdc.test/fail_compilation/fail46.d index 9401b92..9d97ba1 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail46.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail46.d @@ -2,7 +2,7 @@ /* TEST_OUTPUT: --- -fail_compilation/fail46.d(19): Error: need `this` for `bug` of type `int()` +fail_compilation/fail46.d(19): Error: calling non-static function `bug` requires an instance of type `MyStruct` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail4923.d b/gcc/testsuite/gdc.test/fail_compilation/fail4923.d index 3239cff..836b14a 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail4923.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail4923.d @@ -1,13 +1,17 @@ /* TEST_OUTPUT: --- -fail_compilation/fail4923.d(4): Error: immutable variable `bar` initialization is not allowed in `static this` -fail_compilation/fail4923.d(4): Use `shared static this` instead. +fail_compilation/fail4923.d(5): Error: immutable variable `bar` initialization is not allowed in `static this` +fail_compilation/fail4923.d(5): Use `shared static this` instead. +fail_compilation/fail4923.d(6): Deprecation: const variable `baz` initialization is not allowed in `static this` +fail_compilation/fail4923.d(6): Use `shared static this` instead. --- */ #line 1 immutable int bar; +const int baz; // https://issues.dlang.org/show_bug.cgi?id=24056 static this() { bar = 42; + baz = 43; } diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail50.d b/gcc/testsuite/gdc.test/fail_compilation/fail50.d index 36bf382..c6aa178 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail50.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail50.d @@ -1,7 +1,7 @@ /* TEST_OUTPUT: --- -fail_compilation/fail50.d(12): Error: need `this` for address of `a` +fail_compilation/fail50.d(12): Error: taking the address of non-static variable `a` requires an instance of `Marko` fail_compilation/fail50.d(12): Error: variable `a` cannot be read at compile time --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail61.d b/gcc/testsuite/gdc.test/fail_compilation/fail61.d index 1386bd6..a2f01d7 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail61.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail61.d @@ -4,7 +4,7 @@ TEST_OUTPUT: fail_compilation/fail61.d(22): Error: no property `B` for type `fail61.A.B` fail_compilation/fail61.d(23): Error: no property `B` for type `fail61.A.B` fail_compilation/fail61.d(32): Error: no property `A2` for type `fail61.B2` -fail_compilation/fail61.d(41): Error: need `this` for `foo` of type `void()` +fail_compilation/fail61.d(41): Error: calling non-static function `foo` requires an instance of type `B3` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail66.d b/gcc/testsuite/gdc.test/fail_compilation/fail66.d index 5820ca5..825074e 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail66.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail66.d @@ -53,7 +53,7 @@ fail_compilation/fail66.d(59): Error: cannot modify `const` expression `x` class C4 { static const int x; - static this() { x = 5; } + shared static this() { x = 5; } void foo() { x = 4; @@ -67,7 +67,7 @@ fail_compilation/fail66.d(73): Error: cannot modify `const` expression `z5` --- */ const int z5; -static this() { z5 = 3; } +shared static this() { z5 = 3; } void test5() { z5 = 4; diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail7851.d b/gcc/testsuite/gdc.test/fail_compilation/fail7851.d index 399192d..acc49f1 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail7851.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail7851.d @@ -2,9 +2,9 @@ /* TEST_OUTPUT: --- -fail_compilation/fail7851.d(38): Error: need `this` for `__mem_field_0` of type `int` -fail_compilation/fail7851.d(38): Error: need `this` for `__mem_field_1` of type `long` -fail_compilation/fail7851.d(38): Error: need `this` for `__mem_field_2` of type `float` +fail_compilation/fail7851.d(38): Error: accessing non-static variable `__mem_field_0` requires an instance of `Tuple` +fail_compilation/fail7851.d(38): Error: accessing non-static variable `__mem_field_1` requires an instance of `Tuple` +fail_compilation/fail7851.d(38): Error: accessing non-static variable `__mem_field_2` requires an instance of `Tuple` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail9613.d b/gcc/testsuite/gdc.test/fail_compilation/fail9613.d index 31ca808..d88cd2f 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail9613.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail9613.d @@ -2,7 +2,7 @@ /* TEST_OUTPUT: --- -fail_compilation/fail9613.d(12): Error: `(arguments)` expected following `const(byte)` +fail_compilation/fail9613.d(12): Error: `(arguments)` expected following `const(byte)`, not `.` fail_compilation/fail9613.d(12): Error: semicolon expected following auto declaration, not `.` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail_scope.d b/gcc/testsuite/gdc.test/fail_compilation/fail_scope.d index f209592..8508b27 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail_scope.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail_scope.d @@ -1,5 +1,5 @@ /* -REQUIRED_ARGS: +REQUIRED_ARGS: -wo TEST_OUTPUT: --- fail_compilation/fail_scope.d(30): Deprecation: scope parameter `da` may not be returned @@ -16,7 +16,7 @@ fail_compilation/fail_scope.d(82): Error: returning `& string` escapes a referen fail_compilation/fail_scope.d(92): Error: returning `cast(int[])a` escapes a reference to local variable `a` fail_compilation/fail_scope.d(100): Error: returning `cast(int[])a` escapes a reference to local variable `a` fail_compilation/fail_scope.d(108): Error: escaping reference to outer local variable `x` -fail_compilation/fail_scope.d(127): Deprecation: returning `s.bar()` escapes a reference to local variable `s` +fail_compilation/fail_scope.d(127): Warning: returning `s.bar()` escapes a reference to local variable `s` fail_compilation/fail_scope.d(137): Error: returning `foo16226(i)` escapes a reference to local variable `i` --- //fail_compilation/fail_scope.d(35): Error: scope variable `da` may not be returned diff --git a/gcc/testsuite/gdc.test/fail_compilation/failcontracts.d b/gcc/testsuite/gdc.test/fail_compilation/failcontracts.d index 9ba2970..51275d0 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/failcontracts.d +++ b/gcc/testsuite/gdc.test/fail_compilation/failcontracts.d @@ -1,15 +1,14 @@ /* TEST_OUTPUT: --- -fail_compilation/failcontracts.d(18): Error: missing `{ ... }` for function literal -fail_compilation/failcontracts.d(18): Error: semicolon expected following auto declaration, not `bode` -fail_compilation/failcontracts.d(19): Error: function declaration without return type. (Note that constructors are always named `this`) -fail_compilation/failcontracts.d(19): Error: no identifier for declarator `test1()` +fail_compilation/failcontracts.d(17): Error: missing `{ ... }` for function literal +fail_compilation/failcontracts.d(17): Error: semicolon expected following auto declaration, not `bode` +fail_compilation/failcontracts.d(18): Error: function declaration without return type. (Note that constructors are always named `this`) +fail_compilation/failcontracts.d(18): Error: no identifier for declarator `test1()` +fail_compilation/failcontracts.d(18): Error: semicolon expected following function declaration, not `bode` fail_compilation/failcontracts.d(19): Error: semicolon expected following function declaration, not `bode` -fail_compilation/failcontracts.d(20): Error: semicolon expected following function declaration, not `bode` -fail_compilation/failcontracts.d(22): Error: unexpected `(` in declarator -fail_compilation/failcontracts.d(22): Error: found `T` when expecting `)` -fail_compilation/failcontracts.d(22): Error: enum declaration is invalid -fail_compilation/failcontracts.d(22): Error: found `)` instead of statement +fail_compilation/failcontracts.d(21): Error: unexpected `(` in declarator +fail_compilation/failcontracts.d(21): Error: found `T` when expecting `)` +fail_compilation/failcontracts.d(21): Error: expected `{`, not `;` for enum declaration --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/ice15332.d b/gcc/testsuite/gdc.test/fail_compilation/ice15332.d index dbedc73..6789583 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/ice15332.d +++ b/gcc/testsuite/gdc.test/fail_compilation/ice15332.d @@ -1,8 +1,8 @@ /* TEST_OUTPUT: --- -fail_compilation/ice15332.d(16): Error: need `this` for `fun` of type `int()` -fail_compilation/ice15332.d(17): Error: need `this` for `var` of type `int` +fail_compilation/ice15332.d(16): Error: calling non-static function `fun` requires an instance of type `C` +fail_compilation/ice15332.d(17): Error: accessing non-static variable `var` requires an instance of `C` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/ice15922.d b/gcc/testsuite/gdc.test/fail_compilation/ice15922.d index d98404c..624124b 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/ice15922.d +++ b/gcc/testsuite/gdc.test/fail_compilation/ice15922.d @@ -4,7 +4,7 @@ TEST_OUTPUT: fail_compilation/ice15922.d(23): Error: function `ice15922.ValidSparseDataStore!int.ValidSparseDataStore.correctedInsert!false.correctedInsert` has no `return` statement, but is expected to return a value of type `int` fail_compilation/ice15922.d(21): Error: template instance `ice15922.ValidSparseDataStore!int.ValidSparseDataStore.correctedInsert!false` error instantiating fail_compilation/ice15922.d(26): instantiated from here: `ValidSparseDataStore!int` -fail_compilation/ice15922.d(14): Error: need `this` for `insert` of type `pure nothrow @nogc @safe int()` +fail_compilation/ice15922.d(14): Error: calling non-static function `insert` requires an instance of type `ValidSparseDataStore` fail_compilation/ice15922.d(26): Error: template instance `ice15922.StorageAttributes!(ValidSparseDataStore!int)` error instantiating --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/ice20056.d b/gcc/testsuite/gdc.test/fail_compilation/ice20056.d index 1b991ca..519ada1 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/ice20056.d +++ b/gcc/testsuite/gdc.test/fail_compilation/ice20056.d @@ -1,7 +1,7 @@ /* TEST_OUTPUT: --- -fail_compilation/ice20056.d(19): Error: need `this` for `iter` of type `void()` +fail_compilation/ice20056.d(19): Error: calling non-static function `iter` requires an instance of type `RangeWrapper` --- */ struct Def(alias fn) diff --git a/gcc/testsuite/gdc.test/fail_compilation/ice7645.d b/gcc/testsuite/gdc.test/fail_compilation/ice7645.d index 379ac67..3fd332c 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/ice7645.d +++ b/gcc/testsuite/gdc.test/fail_compilation/ice7645.d @@ -1,8 +1,8 @@ /* TEST_OUTPUT: --- -fail_compilation/ice7645.d(28): Error: need `this` for `t` of type `char` -fail_compilation/ice7645.d(31): Error: need `this` for `fn` of type `pure nothrow @nogc @safe void()` +fail_compilation/ice7645.d(28): Error: accessing non-static variable `t` requires an instance of `C2` +fail_compilation/ice7645.d(31): Error: calling non-static function `fn` requires an instance of type `S2` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/ice9439.d b/gcc/testsuite/gdc.test/fail_compilation/ice9439.d index 5b2a8b1..9f08e40 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/ice9439.d +++ b/gcc/testsuite/gdc.test/fail_compilation/ice9439.d @@ -1,7 +1,7 @@ /* TEST_OUTPUT: --- -fail_compilation/ice9439.d(12): Error: need `this` for `foo` of type `int()` +fail_compilation/ice9439.d(12): Error: calling non-static function `foo` requires an instance of type `Derived` fail_compilation/ice9439.d(12): while evaluating: `static assert(foo())` fail_compilation/ice9439.d(19): Error: template instance `ice9439.Base.boo!(foo)` error instantiating --- diff --git a/gcc/testsuite/gdc.test/fail_compilation/misc_parser_err_cov1.d b/gcc/testsuite/gdc.test/fail_compilation/misc_parser_err_cov1.d index a719b12..57706b59 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/misc_parser_err_cov1.d +++ b/gcc/testsuite/gdc.test/fail_compilation/misc_parser_err_cov1.d @@ -17,7 +17,7 @@ fail_compilation/misc_parser_err_cov1.d(38): Error: template argument expected f fail_compilation/misc_parser_err_cov1.d(38): Error: missing closing `)` after `if (parseShift!()` fail_compilation/misc_parser_err_cov1.d(38): Error: found `)` when expecting `(` fail_compilation/misc_parser_err_cov1.d(39): Error: missing closing `)` after `if (` -fail_compilation/misc_parser_err_cov1.d(39): Error: identifier expected following `(type)`. +fail_compilation/misc_parser_err_cov1.d(39): Error: identifier expected following `immutable(int).`, not `+` fail_compilation/misc_parser_err_cov1.d(39): Error: expression expected, not `;` fail_compilation/misc_parser_err_cov1.d(40): Error: semicolon expected following auto declaration, not `auto` fail_compilation/misc_parser_err_cov1.d(40): Error: identifier or `new` expected following `.`, not `+` diff --git a/gcc/testsuite/gdc.test/fail_compilation/mixintype2.d b/gcc/testsuite/gdc.test/fail_compilation/mixintype2.d index b18627d..13cc827 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/mixintype2.d +++ b/gcc/testsuite/gdc.test/fail_compilation/mixintype2.d @@ -1,8 +1,11 @@ /* TEST_OUTPUT: --- -fail_compilation/mixintype2.d(10): Error: alias `mixintype2.Foo.T` recursive alias declaration -fail_compilation/mixintype2.d(16): Error: `mixin(0)` does not give a valid type +fail_compilation/mixintype2.d(13): Error: alias `mixintype2.Foo.T` recursive alias declaration +fail_compilation/mixintype2.d(19): Error: `mixin(0)` does not give a valid type +fail_compilation/mixintype2.d(20): Error: unexpected token `{` after type `int()` +fail_compilation/mixintype2.d(20): while parsing string mixin type `int() {}` +fail_compilation/mixintype2.d(20): Error: `mixin(_error_)` does not give a valid type --- */ @@ -14,3 +17,4 @@ alias T2 = mixin("T1"); void func (T2 p) {} enum mixin(0) a = 0; +mixin("int() {}") f; diff --git a/gcc/testsuite/gdc.test/fail_compilation/noreturn.d b/gcc/testsuite/gdc.test/fail_compilation/noreturn.d index d47d449..087b9e7 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/noreturn.d +++ b/gcc/testsuite/gdc.test/fail_compilation/noreturn.d @@ -3,18 +3,18 @@ REQUIRED_ARGS: -w -o- TEST_OUTPUT: --- -fail_compilation\noreturn.d(38): Error: `"Accessed expression of type `noreturn`"` +fail_compilation\noreturn.d(38): Error: Accessed expression of type `noreturn` fail_compilation\noreturn.d(42): called from here: `assign()` -fail_compilation\noreturn.d(49): Error: `"Accessed expression of type `noreturn`"` +fail_compilation\noreturn.d(49): Error: Accessed expression of type `noreturn` fail_compilation\noreturn.d(49): called from here: `foo(n)` fail_compilation\noreturn.d(53): called from here: `calling()` -fail_compilation\noreturn.d(59): Error: `"Accessed expression of type `noreturn`"` +fail_compilation\noreturn.d(59): Error: Accessed expression of type `noreturn` fail_compilation\noreturn.d(62): called from here: `nested()` -fail_compilation\noreturn.d(68): Error: `"Accessed expression of type `noreturn`"` +fail_compilation\noreturn.d(68): Error: Accessed expression of type `noreturn` fail_compilation\noreturn.d(78): called from here: `casting(0)` -fail_compilation\noreturn.d(69): Error: `"Accessed expression of type `noreturn`"` +fail_compilation\noreturn.d(69): Error: Accessed expression of type `noreturn` fail_compilation\noreturn.d(79): called from here: `casting(1)` -fail_compilation\noreturn.d(72): Error: `"Accessed expression of type `noreturn`"` +fail_compilation\noreturn.d(72): Error: Accessed expression of type `noreturn` fail_compilation\noreturn.d(80): called from here: `casting(2)` fail_compilation/noreturn.d(120): Error: uncaught CTFE exception `object.Exception("")` --- @@ -125,7 +125,7 @@ https://issues.dlang.org/show_bug.cgi?id=23063 TEST_OUTPUT: --- -fail_compilation/noreturn.d(135): Error: `"Accessed expression of type `noreturn`"` +fail_compilation/noreturn.d(135): Error: Accessed expression of type `noreturn` fail_compilation/noreturn.d(138): called from here: `func()` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/noreturn2.d b/gcc/testsuite/gdc.test/fail_compilation/noreturn2.d index 7bb2fa9..66c1d52 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/noreturn2.d +++ b/gcc/testsuite/gdc.test/fail_compilation/noreturn2.d @@ -139,3 +139,16 @@ int throwInvalid(int i) nothrow UnkownException("") ; } + +/+ +https://issues.dlang.org/show_bug.cgi?id=24054 +TEST_OUTPUT: +--- +fail_compilation/noreturn2.d(153): Error: cannot return from `noreturn` function +fail_compilation/noreturn2.d(153): Consider adding an endless loop, `assert(0)`, or another `noreturn` expression +--- ++/ +const(noreturn) f() +{ + return; +} diff --git a/gcc/testsuite/gdc.test/fail_compilation/systemvariables.d b/gcc/testsuite/gdc.test/fail_compilation/systemvariables.d index 0079719..796eda6 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/systemvariables.d +++ b/gcc/testsuite/gdc.test/fail_compilation/systemvariables.d @@ -2,15 +2,24 @@ REQUIRED_ARGS: -preview=systemVariables TEST_OUTPUT: --- -fail_compilation/systemvariables.d(30): Error: cannot access `@system` variable `gInt` in @safe code -fail_compilation/systemvariables.d(31): Error: cannot access `@system` variable `gInt` in @safe code -fail_compilation/systemvariables.d(32): Error: cannot access `@system` variable `gArr` in @safe code -fail_compilation/systemvariables.d(33): Error: cannot access `@system` variable `gArr` in @safe code -fail_compilation/systemvariables.d(34): Error: cannot access `@system` variable `gInt` in @safe code -fail_compilation/systemvariables.d(37): Error: cannot access `@system` variable `lSys` in @safe code -fail_compilation/systemvariables.d(38): Error: cannot access `@system` variable `lSys` in @safe code -fail_compilation/systemvariables.d(39): Error: cannot access `@system` variable `lSys` in @safe code -fail_compilation/systemvariables.d(41): Error: cannot access `@system` variable `eInt` in @safe code +fail_compilation/systemvariables.d(39): Error: cannot access `@system` variable `gInt` in @safe code +fail_compilation/systemvariables.d(29): `gInt` is declared here +fail_compilation/systemvariables.d(40): Error: cannot access `@system` variable `gInt` in @safe code +fail_compilation/systemvariables.d(29): `gInt` is declared here +fail_compilation/systemvariables.d(41): Error: cannot access `@system` variable `gArr` in @safe code +fail_compilation/systemvariables.d(31): `gArr` is declared here +fail_compilation/systemvariables.d(42): Error: cannot access `@system` variable `gArr` in @safe code +fail_compilation/systemvariables.d(31): `gArr` is declared here +fail_compilation/systemvariables.d(43): Error: cannot access `@system` variable `gInt` in @safe code +fail_compilation/systemvariables.d(29): `gInt` is declared here +fail_compilation/systemvariables.d(46): Error: cannot access `@system` variable `lSys` in @safe code +fail_compilation/systemvariables.d(45): `lSys` is declared here +fail_compilation/systemvariables.d(47): Error: cannot access `@system` variable `lSys` in @safe code +fail_compilation/systemvariables.d(45): `lSys` is declared here +fail_compilation/systemvariables.d(48): Error: cannot access `@system` variable `lSys` in @safe code +fail_compilation/systemvariables.d(45): `lSys` is declared here +fail_compilation/systemvariables.d(50): Error: cannot access `@system` variable `eInt` in @safe code +fail_compilation/systemvariables.d(30): `eInt` is declared here --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/test13536.d b/gcc/testsuite/gdc.test/fail_compilation/test13536.d index f4e2cac..4a4bb26 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/test13536.d +++ b/gcc/testsuite/gdc.test/fail_compilation/test13536.d @@ -1,8 +1,8 @@ -/* +/* REQUIRED_ARGS: -wo TEST_OUTPUT: --- fail_compilation/test13536.d(23): Error: field `U.sysDg` cannot access pointers in `@safe` code that overlap other fields -fail_compilation/test13536.d(23): Deprecation: address of variable `s` assigned to `u` with longer lifetime +fail_compilation/test13536.d(23): Warning: address of variable `s` assigned to `u` with longer lifetime fail_compilation/test13536.d(24): Error: field `U.safeDg` cannot access pointers in `@safe` code that overlap other fields --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/test16365.d b/gcc/testsuite/gdc.test/fail_compilation/test16365.d index c987969..4d49365 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/test16365.d +++ b/gcc/testsuite/gdc.test/fail_compilation/test16365.d @@ -1,9 +1,9 @@ -/* +/* REQUIRED_ARGS: -wo TEST_OUTPUT: --- fail_compilation/test16365.d(21): Error: `this` reference necessary to take address of member `f1` in `@safe` function `main` fail_compilation/test16365.d(23): Error: cannot implicitly convert expression `&f2` of type `void delegate() pure nothrow @nogc @safe` to `void function() @safe` -fail_compilation/test16365.d(27): Deprecation: address of variable `s` assigned to `dg` with longer lifetime +fail_compilation/test16365.d(27): Warning: address of variable `s` assigned to `dg` with longer lifetime fail_compilation/test16365.d(28): Error: `dg.funcptr` cannot be used in `@safe` code --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/test21008.d b/gcc/testsuite/gdc.test/fail_compilation/test21008.d index 7d5bb37..9949107 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/test21008.d +++ b/gcc/testsuite/gdc.test/fail_compilation/test21008.d @@ -2,8 +2,8 @@ TEST_OUTPUT: --- fail_compilation/test21008.d(110): Error: function `test21008.C.after` circular reference to class `C` -fail_compilation/test21008.d(117): Error: need `this` for `toString` of type `string()` -fail_compilation/test21008.d(117): Error: need `this` for `toHash` of type `nothrow @trusted $?:32=uint|64=ulong$()` +fail_compilation/test21008.d(117): Error: calling non-static function `toString` requires an instance of type `Object` +fail_compilation/test21008.d(117): Error: calling non-static function `toHash` requires an instance of type `Object` fail_compilation/test21008.d(117): Error: function `object.Object.opCmp(Object o)` is not callable using argument types `()` fail_compilation/test21008.d(117): too few arguments, expected 1, got 0 fail_compilation/test21008.d(117): Error: function `object.Object.opEquals(Object o)` is not callable using argument types `()` diff --git a/gcc/testsuite/gdc.test/fail_compilation/test9701.d b/gcc/testsuite/gdc.test/fail_compilation/test9701.d index a0310c4..67f38fc 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/test9701.d +++ b/gcc/testsuite/gdc.test/fail_compilation/test9701.d @@ -5,27 +5,27 @@ fail_compilation/test9701.d(38): Error: `@safe` is not a valid attribute for enu fail_compilation/test9701.d(39): Error: `@system` is not a valid attribute for enum members fail_compilation/test9701.d(40): Error: `@trusted` is not a valid attribute for enum members fail_compilation/test9701.d(41): Error: `@nogc` is not a valid attribute for enum members -fail_compilation/test9701.d(42): Error: `pure` is not a valid attribute for enum members -fail_compilation/test9701.d(43): Error: `shared` is not a valid attribute for enum members -fail_compilation/test9701.d(44): Error: `inout` is not a valid attribute for enum members -fail_compilation/test9701.d(45): Error: `immutable` is not a valid attribute for enum members -fail_compilation/test9701.d(46): Error: `const` is not a valid attribute for enum members -fail_compilation/test9701.d(47): Error: `synchronized` is not a valid attribute for enum members -fail_compilation/test9701.d(48): Error: `scope` is not a valid attribute for enum members -fail_compilation/test9701.d(49): Error: `auto` is not a valid attribute for enum members -fail_compilation/test9701.d(50): Error: `ref` is not a valid attribute for enum members -fail_compilation/test9701.d(51): Error: `__gshared` is not a valid attribute for enum members -fail_compilation/test9701.d(52): Error: `final` is not a valid attribute for enum members -fail_compilation/test9701.d(53): Error: `extern` is not a valid attribute for enum members -fail_compilation/test9701.d(54): Error: `export` is not a valid attribute for enum members -fail_compilation/test9701.d(55): Error: `nothrow` is not a valid attribute for enum members -fail_compilation/test9701.d(56): Error: `public` is not a valid attribute for enum members -fail_compilation/test9701.d(57): Error: `private` is not a valid attribute for enum members -fail_compilation/test9701.d(58): Error: `package` is not a valid attribute for enum members -fail_compilation/test9701.d(59): Error: `static` is not a valid attribute for enum members -fail_compilation/test9701.d(60): Error: `static` is not a valid attribute for enum members -fail_compilation/test9701.d(61): Error: `static` is not a valid attribute for enum members -fail_compilation/test9701.d(62): Error: `static` is not a valid attribute for enum members +fail_compilation/test9701.d(42): Error: found `pure` when expecting `identifier` +fail_compilation/test9701.d(43): Error: found `shared` when expecting `identifier` +fail_compilation/test9701.d(44): Error: found `inout` when expecting `identifier` +fail_compilation/test9701.d(45): Error: found `immutable` when expecting `identifier` +fail_compilation/test9701.d(46): Error: found `const` when expecting `identifier` +fail_compilation/test9701.d(47): Error: found `synchronized` when expecting `identifier` +fail_compilation/test9701.d(48): Error: found `scope` when expecting `identifier` +fail_compilation/test9701.d(49): Error: found `auto` when expecting `identifier` +fail_compilation/test9701.d(50): Error: found `ref` when expecting `identifier` +fail_compilation/test9701.d(51): Error: found `__gshared` when expecting `identifier` +fail_compilation/test9701.d(52): Error: found `final` when expecting `identifier` +fail_compilation/test9701.d(53): Error: found `extern` when expecting `identifier` +fail_compilation/test9701.d(54): Error: found `export` when expecting `identifier` +fail_compilation/test9701.d(55): Error: found `nothrow` when expecting `identifier` +fail_compilation/test9701.d(56): Error: found `public` when expecting `identifier` +fail_compilation/test9701.d(57): Error: found `private` when expecting `identifier` +fail_compilation/test9701.d(58): Error: found `package` when expecting `identifier` +fail_compilation/test9701.d(59): Error: found `static` when expecting `identifier` +fail_compilation/test9701.d(60): Error: found `static` when expecting `identifier` +fail_compilation/test9701.d(61): Error: found `static` when expecting `identifier` +fail_compilation/test9701.d(62): Error: found `static` when expecting `identifier` --- */ diff --git a/gcc/testsuite/gdc.test/runnable/aliasthis.d b/gcc/testsuite/gdc.test/runnable/aliasthis.d index 50e5c4d..db5913c 100644 --- a/gcc/testsuite/gdc.test/runnable/aliasthis.d +++ b/gcc/testsuite/gdc.test/runnable/aliasthis.d @@ -1,16 +1,7 @@ /* TEST_OUTPUT: --- -runnable/aliasthis.d(103): Deprecation: alias this for classes/interfaces is deprecated -runnable/aliasthis.d(291): Deprecation: alias this for classes/interfaces is deprecated -runnable/aliasthis.d(292): Deprecation: alias this for classes/interfaces is deprecated -runnable/aliasthis.d(294): Deprecation: alias this for classes/interfaces is deprecated -runnable/aliasthis.d(465): Deprecation: alias this for classes/interfaces is deprecated -runnable/aliasthis.d(466): Deprecation: alias this for classes/interfaces is deprecated -runnable/aliasthis.d(477): Deprecation: alias this for classes/interfaces is deprecated -runnable/aliasthis.d(1013): Deprecation: alias this for classes/interfaces is deprecated false -runnable/aliasthis.d(2100): Deprecation: alias this for classes/interfaces is deprecated [] = int [] = string [0] = int @@ -19,7 +10,6 @@ runnable/aliasthis.d(2100): Deprecation: alias this for classes/interfaces is de [] = int [1] = string [0] = int -runnable/aliasthis.d(741): Deprecation: alias this for classes/interfaces is deprecated --- RUN_OUTPUT: diff --git a/gcc/testsuite/gdc.test/runnable/complex.d b/gcc/testsuite/gdc.test/runnable/complex.d index 50e793e..3a7291d 100644 --- a/gcc/testsuite/gdc.test/runnable/complex.d +++ b/gcc/testsuite/gdc.test/runnable/complex.d @@ -243,11 +243,11 @@ void test12() { real x = 3; creal a = (2 + 4i) % 3; - printf("%Lg %Lgi\n", a.re, a.im); + //printf("%Lg %Lgi\n", a.re, a.im); assert(a == 2 + 1i); creal b = (2 + 4i) % x; - printf("%Lg %Lgi\n", b.re, b.im); + //printf("%Lg %Lgi\n", b.re, b.im); assert(b == a); } @@ -257,7 +257,7 @@ void test13() { ireal a = 5i; ireal b = a % 2; - printf("%Lg %Lgi\n", b.re, b.im); + //printf("%Lg %Lgi\n", b.re, b.im); assert(b == 1i); } @@ -530,9 +530,9 @@ void test22() { static creal[] params = [1+0i, 3+0i, 5+0i]; - printf("params[0] = %Lf + %Lfi\n", params[0].re, params[0].im); - printf("params[1] = %Lf + %Lfi\n", params[1].re, params[1].im); - printf("params[2] = %Lf + %Lfi\n", params[2].re, params[2].im); + //printf("params[0] = %Lf + %Lfi\n", params[0].re, params[0].im); + //printf("params[1] = %Lf + %Lfi\n", params[1].re, params[1].im); + //printf("params[2] = %Lf + %Lfi\n", params[2].re, params[2].im); creal[] sums = new creal[3]; sums[] = 0+0i; @@ -603,19 +603,19 @@ float func_24_4(float f, double d) void test24() { ifloat f = func_24_1(10i, 8); - printf("%fi\n", f); + //printf("%fi\n", f); // assert(f == 1.25i); f = func_24_2(10i, 8); - printf("%fi\n", f); + //printf("%fi\n", f); assert(f == 1.25i); float g = func_24_3(10, 8); - printf("%f\n", g); + //printf("%f\n", g); // assert(g == 1.25); g = func_24_4(10, 8); - printf("%f\n", g); + //printf("%f\n", g); assert(g == 1.25); } @@ -647,9 +647,9 @@ void test26() foreach( cdouble z; A ) { s = toString26(z); - printf("%.*s ", cast(int)s.length, s.ptr); + //printf("%.*s ", cast(int)s.length, s.ptr); } - printf("\n"); + //printf("\n"); for(int ii=0; ii<A.length; ii++ ) A[ii] += -1i*A[ii]; @@ -661,9 +661,9 @@ void test26() foreach( cdouble z; A ) { s = toString26(z); - printf("%.*s ", cast(int)s.length, s.ptr); + //printf("%.*s ", cast(int)s.length, s.ptr); } - printf("\n"); + //printf("\n"); } /*************************************/ @@ -698,19 +698,19 @@ void test28() void test29() { ireal a = 6.5i % 3i; - printf("%Lfi %Lfi\n", a, a - .5i); + //printf("%Lfi %Lfi\n", a, a - .5i); assert(a == .5i); a = 6.5i % 3; - printf("%Lfi %Lfi\n", a, a - .5i); + //printf("%Lfi %Lfi\n", a, a - .5i); assert(a == .5i); real b = 6.5 % 3i; - printf("%Lf %Lf\n", b, b - .5); + //printf("%Lf %Lf\n", b, b - .5); assert(b == .5); b = 6.5 % 3; - printf("%Lf %Lf\n", b, b - .5); + //printf("%Lf %Lf\n", b, b - .5); assert(b == .5); } @@ -720,17 +720,17 @@ void test30() { cfloat f = 1+0i; f %= 2fi; - printf("%f + %fi\n", f.re, f.im); + //printf("%f + %fi\n", f.re, f.im); assert(f == 1 + 0i); cdouble d = 1+0i; d %= 2i; - printf("%f + %fi\n", d.re, d.im); + //printf("%f + %fi\n", d.re, d.im); assert(d == 1 + 0i); creal r = 1+0i; r %= 2i; - printf("%Lf + %Lfi\n", r.re, r.im); + //printf("%Lf + %Lfi\n", r.re, r.im); assert(r == 1 + 0i); } @@ -740,17 +740,17 @@ void test31() { cfloat f = 1+0i; f %= 2i; - printf("%f + %fi\n", f.re, f.im); + //printf("%f + %fi\n", f.re, f.im); assert(f == 1); cdouble d = 1+0i; d = d % 2i; - printf("%f + %fi\n", d.re, d.im); + //printf("%f + %fi\n", d.re, d.im); assert(d == 1); creal r = 1+0i; r = r % 2i; - printf("%Lf + %Lfi\n", r.re, r.im); + //printf("%Lf + %Lfi\n", r.re, r.im); assert(r == 1); } @@ -770,7 +770,7 @@ void assertEqual(real* a, real* b, string file = __FILE__, size_t line = __LINE_ { if (x[i] != y[i]) { - printf("%02zd: %02x %02x\n", i, x[i], y[i]); + //printf("%02zd: %02x %02x\n", i, x[i], y[i]); import core.exception; throw new AssertError(file, line); } @@ -856,7 +856,7 @@ void test35() void test36() { ireal imag = 2.5i; - printf ("test of imag*imag = %Lf\n",imag*imag); + //printf ("test of imag*imag = %Lf\n",imag*imag); assert(imag * imag == -6.25); } @@ -885,7 +885,7 @@ void test39() creal z = 1 + 2.5i; real e = z.im; - printf ("e = %Lf\n", e); + //printf ("e = %Lf\n", e); assert(e == 2.5); } @@ -942,7 +942,7 @@ void test44() { ifloat f = 1.0fi; // f *= 2.0fi; // illegal but compiles - printf("%g\n", f); + //printf("%g\n", f); // assert(f == 0i); } diff --git a/gcc/testsuite/gdc.test/runnable/interpret.d b/gcc/testsuite/gdc.test/runnable/interpret.d index f9972f2..ee324d7 100644 --- a/gcc/testsuite/gdc.test/runnable/interpret.d +++ b/gcc/testsuite/gdc.test/runnable/interpret.d @@ -4,7 +4,6 @@ TEST_OUTPUT: true g &Test109S(&Test109S(<recursion>)) -runnable/interpret.d(3742): Deprecation: alias this for classes/interfaces is deprecated tfoo tfoo Crash! @@ -2197,7 +2196,7 @@ struct Q Q opOpAssign(string op)(int w) if (op == "-") { x -= w; - version(D_Version2) { mixin("return this;"); } else { mixin("return *this;"); } + return this; } int boo() { return 4; } int coo() { return x; } @@ -2427,7 +2426,7 @@ static assert(bug1605() == 27); int bug2564() { - version(D_Version2) { mixin("enum int Q = 0;"); }else {mixin("int Q = 0;"); } + enum int Q = 0; string [2] s = ["a", "b"]; assert(s[Q].dup == "a"); return 0; @@ -2646,8 +2645,6 @@ static assert(lazyTest2(17) == 18); /************************************************/ -version(D_Version2) -{ // https://issues.dlang.org/show_bug.cgi?id=4020 // https://issues.dlang.org/show_bug.cgi?id=4027 // D2 only @@ -2677,7 +2674,6 @@ static if (is(typeof((){ static const s = bug4027("aaa")(); }()))) { static assert(bug4027("aaa")() == "aaa"); static assert(bug4027("bbb")() == "bbb"); } -} // --- diff --git a/gcc/testsuite/gdc.test/runnable/template9.d b/gcc/testsuite/gdc.test/runnable/template9.d index dbad3f1..fa70b81 100644 --- a/gcc/testsuite/gdc.test/runnable/template9.d +++ b/gcc/testsuite/gdc.test/runnable/template9.d @@ -1991,7 +1991,7 @@ void test8976() // https://issues.dlang.org/show_bug.cgi?id=8940 const int n8940; // or `immutable` -static this() { n8940 = 3; } +shared static this() { n8940 = 3; } void f8940(T)(ref int val) { diff --git a/gcc/testsuite/gdc.test/runnable/test17684.d b/gcc/testsuite/gdc.test/runnable/test17684.d index e102655..efdce08 100644 --- a/gcc/testsuite/gdc.test/runnable/test17684.d +++ b/gcc/testsuite/gdc.test/runnable/test17684.d @@ -1,13 +1,3 @@ -/* -TEST_OUTPUT: ---- -runnable/test17684.d(37): Deprecation: alias this for classes/interfaces is deprecated -runnable/test17684.d(54): Deprecation: alias this for classes/interfaces is deprecated -runnable/test17684.d(54): Deprecation: alias this for classes/interfaces is deprecated -runnable/test17684.d(37): Deprecation: alias this for classes/interfaces is deprecated ---- -*/ - struct StructField(T) { static T Field; diff --git a/gcc/testsuite/gdc.test/runnable/test19782.d b/gcc/testsuite/gdc.test/runnable/test19782.d index 61a168b..a24d841 100644 --- a/gcc/testsuite/gdc.test/runnable/test19782.d +++ b/gcc/testsuite/gdc.test/runnable/test19782.d @@ -1,12 +1,4 @@ // https://issues.dlang.org/show_bug.cgi?id=19782 - -/* -TEST_OUTPUT: ---- -runnable/test19782.d(17): Deprecation: alias this for classes/interfaces is deprecated ---- -*/ - class Inner { int a; diff --git a/gcc/testsuite/gdc.test/runnable/test20.d b/gcc/testsuite/gdc.test/runnable/test20.d index 5d47b06..5036ef2 100644 --- a/gcc/testsuite/gdc.test/runnable/test20.d +++ b/gcc/testsuite/gdc.test/runnable/test20.d @@ -1104,7 +1104,7 @@ class C60 { } - static this() + shared static this() { x = 5; } @@ -1117,7 +1117,7 @@ class C60 const int z60; -static this() +shared static this() { z60 = 3; } diff --git a/gcc/testsuite/gdc.test/runnable/test21039.d b/gcc/testsuite/gdc.test/runnable/test21039.d index f32267a..c58600f 100644 --- a/gcc/testsuite/gdc.test/runnable/test21039.d +++ b/gcc/testsuite/gdc.test/runnable/test21039.d @@ -1,12 +1,5 @@ // https://issues.dlang.org/show_bug.cgi?id=21039 -/* -TEST_OUTPUT: ---- -runnable/test21039.d(14): Deprecation: alias this for classes/interfaces is deprecated ---- -*/ - class Inner {} class Outer { diff --git a/gcc/testsuite/gdc.test/runnable/test23234.d b/gcc/testsuite/gdc.test/runnable/test23234.d index f974864..7872aa7 100644 --- a/gcc/testsuite/gdc.test/runnable/test23234.d +++ b/gcc/testsuite/gdc.test/runnable/test23234.d @@ -1,12 +1,5 @@ // https://issues.dlang.org/show_bug.cgi?id=23234 -/* -TEST_OUTPUT: ---- -runnable/test23234.d(17): Deprecation: alias this for classes/interfaces is deprecated ---- -*/ - class Bar { } diff --git a/gcc/testsuite/gdc.test/runnable/test3449.d b/gcc/testsuite/gdc.test/runnable/test3449.d index 8d38918..c06674a 100644 --- a/gcc/testsuite/gdc.test/runnable/test3449.d +++ b/gcc/testsuite/gdc.test/runnable/test3449.d @@ -12,11 +12,11 @@ immutable int ig1; static this() { mg1 = 10; - cg1 = 10; } shared static this() { + cg1 = 10; ig1 = 10; } static assert(!__traits(compiles, { static assert(mg1 == 0); })); diff --git a/gcc/testsuite/gdc.test/runnable/test42.d b/gcc/testsuite/gdc.test/runnable/test42.d index 436f707..d89c152 100644 --- a/gcc/testsuite/gdc.test/runnable/test42.d +++ b/gcc/testsuite/gdc.test/runnable/test42.d @@ -6167,7 +6167,7 @@ void test5332() const int x11472 = void; -static this() { x11472 = 10; } +shared static this() { x11472 = 10; } void test11472() { diff --git a/gcc/testsuite/gdc.test/runnable/testaliascast.d b/gcc/testsuite/gdc.test/runnable/testaliascast.d index ed5091d..c55f820 100644 --- a/gcc/testsuite/gdc.test/runnable/testaliascast.d +++ b/gcc/testsuite/gdc.test/runnable/testaliascast.d @@ -1,13 +1,5 @@ // https://issues.dlang.org/show_bug.cgi?id=11294 -/* -TEST_OUTPUT: ---- -runnable/testaliascast.d(29): Deprecation: alias this for classes/interfaces is deprecated -runnable/testaliascast.d(58): Deprecation: alias this for classes/interfaces is deprecated ---- -*/ - string result; extern(C) void rt_finalize(void *ptr, bool det=true); diff --git a/gcc/testsuite/gdc.test/runnable/testassign.d b/gcc/testsuite/gdc.test/runnable/testassign.d index 79a4c57..c2b8a51 100644 --- a/gcc/testsuite/gdc.test/runnable/testassign.d +++ b/gcc/testsuite/gdc.test/runnable/testassign.d @@ -2,8 +2,6 @@ REQUIRED_ARGS: -preview=rvaluerefparam TEST_OUTPUT: --- -runnable/testassign.d(802): Deprecation: alias this for classes/interfaces is deprecated -runnable/testassign.d(808): Deprecation: alias this for classes/interfaces is deprecated \ S1 S2a S2b S3a S3b S4a S4b - true true true true true true true Xa true true true true true true true @@ -363,7 +361,7 @@ struct CtorTest6174(Data) const char gc6174; const char[1] ga6174; -static this() +shared static this() { gc6174 = 'a'; // OK ga6174[0] = 'a'; // line 5, Err @@ -728,7 +726,7 @@ struct Foo8783 const Foo8783[1] foos8783; -static this() +shared static this() { foreach (i; 0 .. foos8783.length) foos8783[i].bar[i] = 1; // OK diff --git a/gcc/testsuite/gdc.test/runnable/testconst.d b/gcc/testsuite/gdc.test/runnable/testconst.d index 17e3236..43f986d 100644 --- a/gcc/testsuite/gdc.test/runnable/testconst.d +++ b/gcc/testsuite/gdc.test/runnable/testconst.d @@ -551,7 +551,7 @@ void test38() static const int x39; const int y39; -static this() +shared static this() { x39 = 3; y39 = 4; @@ -613,7 +613,7 @@ class C42 static const int d; static const int e = ctfe() + 2; - static this() + shared static this() { d = 4; } @@ -1302,7 +1302,7 @@ void test78() const bool[string] stopWords79; -static this() +shared static this() { stopWords79 = [ "a"[]:1 ]; } diff --git a/gcc/testsuite/gdc.test/runnable/testswitch.d b/gcc/testsuite/gdc.test/runnable/testswitch.d index c7b9378..4744697 100644 --- a/gcc/testsuite/gdc.test/runnable/testswitch.d +++ b/gcc/testsuite/gdc.test/runnable/testswitch.d @@ -353,15 +353,11 @@ int foo15(int i) return y; } -static this() -{ - X15 = 4; - Z15 = 5; -} - shared static this() { + X15 = 4; Y15 = 4; + Z15 = 5; } void test15() diff --git a/gcc/testsuite/gdc.test/runnable/traits_getPointerBitmap.d b/gcc/testsuite/gdc.test/runnable/traits_getPointerBitmap.d index ffa0b80..8996c9e 100644 --- a/gcc/testsuite/gdc.test/runnable/traits_getPointerBitmap.d +++ b/gcc/testsuite/gdc.test/runnable/traits_getPointerBitmap.d @@ -1,3 +1,4 @@ + module traits_getPointerBitmap; import core.stdc.stdio; @@ -75,6 +76,19 @@ template pOff(T) enum pOff = T.p.offsetof / bytesPerPtr; } +class C(T, aliasTo = void) +{ + static if(!is(aliasTo == void)) + { + aliasTo a; + alias a this; + } + + size_t x; + T t = void; + void* p; +} + /////////////////////////////////////// void _testType(T)(size_t[] expected) @@ -104,6 +118,21 @@ void testType(T)(size_t[] expected) // prepend string sexp[0] = (expected[0] << tOff!(S!(T, string))) | (1 << pOff!(S!(T, string))) | 2; // arr ptr _testType!(S!(T, string))(sexp); + + // generate bit pattern for C!T + C!T ct = null; + size_t mutexBit = (RTInfoMark__Monitor ? 2 : 0); + size_t ctpOff = ct.p.offsetof / bytesPerPtr; + size_t cttOff = ct.t.offsetof / bytesPerPtr; + sexp[0] = (expected[0] << cttOff) | (1 << ctpOff) | mutexBit; + _testType!(C!(T))(sexp); + + C!(T, string) cts = null; + size_t ctspOff = cts.p.offsetof / bytesPerPtr; + size_t ctstOff = cts.t.offsetof / bytesPerPtr; + // generate bit pattern for C!T + sexp[0] = (expected[0] << ctstOff) | (1 << ctspOff) | mutexBit | 0b1000; // arr ptr + _testType!(C!(T, string))(sexp); } /////////////////////////////////////// diff --git a/gcc/testsuite/gdc.test/runnable/xtest46.d b/gcc/testsuite/gdc.test/runnable/xtest46.d index 972de90..aeb2aab 100644 --- a/gcc/testsuite/gdc.test/runnable/xtest46.d +++ b/gcc/testsuite/gdc.test/runnable/xtest46.d @@ -2,14 +2,11 @@ // /* TEST_OUTPUT: --- -runnable/xtest46.d(165): Deprecation: alias this for classes/interfaces is deprecated Boo!double Boo!int true int !! immutable(int)[] -runnable/xtest46.d(2932): Deprecation: alias this for classes/interfaces is deprecated -runnable/xtest46.d(2964): Deprecation: alias this for classes/interfaces is deprecated int(int i, long j = 7L) long C10390(C10390(C10390(<recursion>))) @@ -22,7 +19,6 @@ string[] double[] double[] {} -runnable/xtest46.d(4670): Deprecation: alias this for classes/interfaces is deprecated AliasSeq!("m") true TFunction1: extern (C) void function() diff --git a/gcc/testsuite/gdc.test/runnable/xtest46_gc.d b/gcc/testsuite/gdc.test/runnable/xtest46_gc.d index aab6227..38c136d 100644 --- a/gcc/testsuite/gdc.test/runnable/xtest46_gc.d +++ b/gcc/testsuite/gdc.test/runnable/xtest46_gc.d @@ -3,14 +3,11 @@ REQUIRED_ARGS: -lowmem -Jrunnable -preview=rvaluerefparam EXTRA_FILES: xtest46.d TEST_OUTPUT: --- -runnable/xtest46_gc.d-mixin-33(197): Deprecation: alias this for classes/interfaces is deprecated Boo!double Boo!int true int !! immutable(int)[] -runnable/xtest46_gc.d-mixin-33(2964): Deprecation: alias this for classes/interfaces is deprecated -runnable/xtest46_gc.d-mixin-33(2996): Deprecation: alias this for classes/interfaces is deprecated int(int i, long j = 7L) long C10390(C10390(<recursion>)) @@ -23,7 +20,6 @@ string[] double[] double[] {} -runnable/xtest46_gc.d-mixin-33(4702): Deprecation: alias this for classes/interfaces is deprecated AliasSeq!("m") true TFunction1: extern (C) void function() diff --git a/gcc/testsuite/gfortran.dg/pr68155.f90 b/gcc/testsuite/gfortran.dg/pr68155.f90 new file mode 100644 index 0000000..2bd6f78 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr68155.f90 @@ -0,0 +1,29 @@ +! { dg-do run } +! +! Fix for PR68155 in which initializers of constant length, character +! components of derived types were not being padded if they were too short. +! Originally, mismatched lengths caused ICEs. This seems to have been fixed +! in 9-branch. +! +! Contributed by Gerhard Steinmetz <gerhard.steinmetz.fortran@t-online.de> +! +program p + implicit none + type t + character(3) :: c1(2) = [ 'b', 'c'] ! OK + character(3) :: c2(2) = [ character(1) :: 'b', 'c'] // "" ! OK + character(3) :: c3(2) = [ 'b', 'c'] // "" ! was not padded + character(3) :: c4(2) = [ '' , '' ] // "" ! was not padded + character(3) :: c5(2) = [ 'b', 'c'] // 'a' ! was not padded + character(3) :: c6(2) = [ 'b', 'c'] // 'ax' ! OK + character(3) :: c7(2) = [ 'b', 'c'] // 'axy' ! OK trimmed + end type t + type(t) :: z + if (z%c1(2) .ne. 'c ') stop 1 + if (z%c2(2) .ne. 'c ') stop 2 + if (z%c3(2) .ne. 'c ') stop 3 + if (z%c4(2) .ne. ' ') stop 4 + if (z%c5(2) .ne. 'ca ') stop 5 + if (z%c6(2) .ne. 'cax') stop 6 + if (z%c7(2) .ne. 'cax') stop 7 +end diff --git a/gcc/testsuite/gfortran.dg/pr95710.f90 b/gcc/testsuite/gfortran.dg/pr95710.f90 new file mode 100644 index 0000000..566c38d --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr95710.f90 @@ -0,0 +1,17 @@ +! { dg-do compile } +! PR fortran/95710 - ICE on duplicate declaration of class variable +! Contributed by G.Steinmetz + +module m + interface + module function s() + end + end interface +end +submodule(m) m2 +contains + module function s() + class(*), allocatable :: x + class(*), allocatable :: x ! { dg-error "Unclassifiable statement" } + end +end diff --git a/gcc/testsuite/gnat.dg/opt102.adb b/gcc/testsuite/gnat.dg/opt102.adb new file mode 100644 index 0000000..2b5bec5 --- /dev/null +++ b/gcc/testsuite/gnat.dg/opt102.adb @@ -0,0 +1,10 @@ +-- { dg-do run } +-- { dg-options "-O2 -gnata" } + +with Opt102_Pkg; use Opt102_Pkg; + +procedure Opt102 is + I, F : aliased Integer; +begin + I := Get (Two, F'Access, null); +end; diff --git a/gcc/testsuite/gnat.dg/opt102_pkg.adb b/gcc/testsuite/gnat.dg/opt102_pkg.adb new file mode 100644 index 0000000..09c338d --- /dev/null +++ b/gcc/testsuite/gnat.dg/opt102_pkg.adb @@ -0,0 +1,12 @@ +package body Opt102_Pkg is + + function Get (E : Enum; F, M : access Integer) return Integer is + begin + case E is + when One => return 0; + when Two => return F.all; + when Three => return M.all; + end case; + end; + +end Opt102_Pkg; diff --git a/gcc/testsuite/gnat.dg/opt102_pkg.ads b/gcc/testsuite/gnat.dg/opt102_pkg.ads new file mode 100644 index 0000000..7afc3fe --- /dev/null +++ b/gcc/testsuite/gnat.dg/opt102_pkg.ads @@ -0,0 +1,10 @@ +package Opt102_Pkg is + + type Enum is (One, Two, Three); + + function Get (E : Enum; F, M : access Integer) return Integer + with Pre => (E = One) = (F = null and M = null) and + (E = Two) = (F /= null) and + (E = Three) = (M /= null); + +end Opt102_Pkg; diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 2de41ce..f3043b2 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -1812,18 +1812,6 @@ proc check_linker_plugin_available { } { } "-flto -fuse-linker-plugin"] } -# Return 1 if the target has RISC-V vector extension, 0 otherwise. -# Cache the result. - -proc check_effective_target_riscv_vector { } { - # Check that we are compiling for v by checking the __riscv_v marco. - return [check_no_compiler_messages riscv_vector assembly { - #if !defined(__riscv_v) - #error "__riscv_v not defined!" - #endif - }] -} - # Return 1 if the we can build a vector example with proper -march flags # and the current target can execute it, 0 otherwise. Cache the result. @@ -1903,6 +1891,167 @@ proc check_effective_target_rv64 { } { }] } +# Return 1 if the target abi is __riscv_float_abi_soft, 0 otherwise. +# Cache the result. + +proc check_effective_target_rv_float_abi_soft { } { + # Check that we are compiling for RV64 by checking the xlen size. + return [check_no_compiler_messages riscv_riscv_float_abi_soft assembly { + #ifndef __riscv_float_abi_soft + #error "Not __riscv_float_abi_soft" + #endif + }] +} + +# Return 1 if the target arch supports the double precision floating point +# extension, 0 otherwise. Cache the result. + +proc check_effective_target_riscv_d { } { + return [check_no_compiler_messages riscv_ext_d assembly { + #ifndef __riscv_d + #error "Not __riscv_d" + #endif + }] +} + +# Return 1 if the target arch supports the vector extension, 0 otherwise. +# Cache the result. + +proc check_effective_target_riscv_v { } { + return [check_no_compiler_messages riscv_ext_v assembly { + #ifndef __riscv_v + #error "Not __riscv_v" + #endif + }] +} + +# Return 1 if the target arch supports half float, 0 otherwise. +# Note, this differs from the test performed by +# /* dg-skip-if "" { *-*-* } { "*" } { "-march=rv*zfh*" } */ +# in that it takes default behaviour into account. +# Cache the result. + +proc check_effective_target_riscv_zfh { } { + return [check_no_compiler_messages riscv_ext_zfh assembly { + #ifndef __riscv_zfh + #error "Not __riscv_zfh" + #endif + }] +} + +# Return 1 if we can execute code when using dg-add-options riscv_v + +proc check_effective_target_riscv_v_ok { } { + # If the target already supports v without any added options, + # we may assume we can execute just fine. + if { [check_effective_target_riscv_v] } { + return 1 + } + + # check if we can execute vector insns with the given hardware or + # simulator + set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &v] + if { [check_runtime ${gcc_march}_exec { + int main() { asm("vsetivli t0, 9, e8, m1, tu, ma"); return 0; } } "-march=${gcc_march}"] } { + return 1 + } + + # Possible future extensions: If the target is a simulator, dg-add-options + # might change its config to make it allow vector insns, or we might use + # options to set special elf flags / sections to effect that. + + return 0 +} + +# Return 1 if we can execute code when using dg-add-options riscv_zfh + +proc check_effective_target_riscv_zfh_ok { } { + # If the target already supports zfh without any added options, + # we may assume we can execute just fine. + # ??? Other cases we should consider: + # - target / simulator already supports zfh extension - test for that. + # - target is a simulator, and dg-add-options knows how to enable zfh support in that simulator + if { [check_effective_target_riscv_zfh] } { + return 1 + } + + # check if we can execute zfh insns with the given hardware or + # simulator + set gcc_march [riscv_get_arch] + if { [check_runtime ${gcc_march}_zfh_exec { + int main() { asm("feq.h a3,fa5,fa4"); return 0; } } "-march=${gcc_march}_zfh"] } { + return 1 + } + + # Possible future extensions: If the target is a simulator, dg-add-options + # might change its config to make it allow half float insns, or we might + # use options to set special elf flags / sections to effect that. + + return 0 +} + +proc riscv_get_arch { } { + set gcc_march "" + # ??? do we neeed to add more extensions to the list below? + foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs } { + if { [check_no_compiler_messages riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] { + #ifndef DEF + #error "Not DEF" + #endif + }]] } { + if { [string length $ext] > 1 } { + set ext _${ext} + } + set gcc_march $gcc_march$ext + } + if { [string equal $gcc_march "imafd"] } { + set gcc_march "g" + } + } + if { [check_effective_target_rv32] } { + set gcc_march rv32$gcc_march + } elseif { [check_effective_target_rv64] } { + set gcc_march rv64$gcc_march + } else { + set gcc_march "" + } + return "$gcc_march" +} + +proc add_options_for_riscv_d { flags } { + if { [lsearch $flags -march=*] >= 0 } { + # If there are multiple -march flags, we have to adjust all of them. + return [regsub -all -- {((?^|[[:space:]])-march=rv[[:digit:]]*[a-ce-rt-wy]*)d*} $flags \\1d ] + } + if { [check_effective_target_riscv_d] } { + return "$flags" + } + return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &d]" +} + +proc add_options_for_riscv_v { flags } { + if { [lsearch $flags -march=*] >= 0 } { + # If there are multiple -march flags, we have to adjust all of them. + return [regsub -all -- {((?^|[[:space:]])-march=rv[[:digit:]]*[a-rt-uwy]*)v*} $flags \\1v ] + } + if { [check_effective_target_riscv_v] } { + return "$flags" + } + return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &v]" +} + +proc add_options_for_riscv_zfh { flags } { + if { [lsearch $flags -march=*] >= 0 } { + # If there are multiple -march flags, we have to adjust all of them. + set flags [regsub -all -- {(?^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zfh ] + return [regsub -all -- {((?^|[[:space:]])-march=[[:alnum:]_.]*_zfh[[:alnum:]_.]*)_zfh} $flags \\1 ] + } + if { [check_effective_target_riscv_zfh] } { + return "$flags" + } + return "$flags -march=[riscv_get_arch]_zfh" +} + # Return 1 if the target OS supports running SSE executables, 0 # otherwise. Cache the result. @@ -7960,7 +8109,7 @@ proc check_effective_target_vect_check_ptrs { } { proc check_effective_target_vect_fully_masked { } { return [expr { [check_effective_target_aarch64_sve] || [istarget amdgcn*-*-*] - || [check_effective_target_riscv_vector] }] + || [check_effective_target_riscv_v] }] } # Return true if the target supports the @code{len_load} and @@ -7969,7 +8118,7 @@ proc check_effective_target_vect_fully_masked { } { proc check_effective_target_vect_len_load_store { } { return [expr { [check_effective_target_has_arch_pwr9] || [check_effective_target_s390_vx] - || [check_effective_target_riscv_vector] }] + || [check_effective_target_riscv_v] }] } # Return the value of parameter vect-partial-vector-usage specified for @@ -8032,7 +8181,7 @@ proc check_effective_target_vect_partial_vectors { } { proc check_effective_target_vect_element_align_preferred { } { return [expr { ([check_effective_target_aarch64_sve] && [check_effective_target_vect_variable_length]) - || [check_effective_target_riscv_vector] }] + || [check_effective_target_riscv_v] }] } # Return true if vectorization of v2qi/v4qi/v8qi/v16qi/v2hi store is enabed. @@ -8455,7 +8604,7 @@ proc check_effective_target_vect_masked_store { } { return [expr { [check_avx_available] || [check_effective_target_aarch64_sve] || [istarget amdgcn*-*-*] - || [check_effective_target_riscv_vector] }] + || [check_effective_target_riscv_v] }] } # Return 1 if the target supports vector gather loads via internal functions. @@ -8675,7 +8824,7 @@ proc available_vector_sizes { } { # 6 different lane counts, and 4 element sizes lappend result 4096 2048 1024 512 256 128 64 32 16 8 4 2 } elseif { [istarget riscv*-*-*] } { - if { [check_effective_target_riscv_vector] } { + if { [check_effective_target_riscv_v] } { lappend result 0 32 } lappend result 128 diff --git a/gcc/tree-data-ref.cc b/gcc/tree-data-ref.cc index 6d3b7c2..689aaee 100644 --- a/gcc/tree-data-ref.cc +++ b/gcc/tree-data-ref.cc @@ -100,6 +100,7 @@ along with GCC; see the file COPYING3. If not see #include "vr-values.h" #include "range-op.h" #include "tree-ssa-loop-ivopts.h" +#include "calls.h" static struct datadep_stats { @@ -5816,6 +5817,15 @@ get_references_in_stmt (gimple *stmt, vec<data_ref_loc, va_heap> *references) } case IFN_MASK_LOAD: case IFN_MASK_STORE: + break; + case IFN_MASK_CALL: + { + tree orig_fndecl + = gimple_call_addr_fndecl (gimple_call_arg (stmt, 0)); + if (!orig_fndecl + || (flags_from_decl_or_type (orig_fndecl) & ECF_CONST) == 0) + clobbers_memory = true; + } break; default: clobbers_memory = true; @@ -5852,7 +5862,7 @@ get_references_in_stmt (gimple *stmt, vec<data_ref_loc, va_heap> *references) } else if (stmt_code == GIMPLE_CALL) { - unsigned i, n; + unsigned i = 0, n; tree ptr, type; unsigned int align; @@ -5879,13 +5889,16 @@ get_references_in_stmt (gimple *stmt, vec<data_ref_loc, va_heap> *references) ptr); references->safe_push (ref); return false; + case IFN_MASK_CALL: + i = 1; + gcc_fallthrough (); default: break; } op0 = gimple_call_lhs (stmt); n = gimple_call_num_args (stmt); - for (i = 0; i < n; i++) + for (; i < n; i++) { op1 = gimple_call_arg (stmt, i); diff --git a/gcc/tree-if-conv.cc b/gcc/tree-if-conv.cc index 799f071..a8c9159 100644 --- a/gcc/tree-if-conv.cc +++ b/gcc/tree-if-conv.cc @@ -1747,11 +1747,11 @@ is_cond_scalar_reduction (gimple *phi, gimple **reduc, tree arg_0, tree arg_1, and convert to - reduc_2 = PHI <0, reduc_3> - tmp1 = (unsigned type)reduce_1; + reduc_2 = PHI <0, reduc_1> + tmp1 = (unsigned type)reduc_1; ifcvt = cond_expr ? rhs2 : 0 tmp2 = tmp1 +/- ifcvt; - reduce_1 = (signed type)tmp2; */ + reduc_1 = (signed type)tmp2; */ if (CONVERT_EXPR_CODE_P (reduction_op)) { diff --git a/gcc/tree-ssa-phiopt.cc b/gcc/tree-ssa-phiopt.cc index 3835d25..312a6f9 100644 --- a/gcc/tree-ssa-phiopt.cc +++ b/gcc/tree-ssa-phiopt.cc @@ -1823,7 +1823,9 @@ minmax_replacement (basic_block cond_bb, basic_block middle_bb, basic_block alt_ arg_false = arg0; } - if (empty_block_p (middle_bb)) + if (empty_block_p (middle_bb) + && (!threeway_p + || empty_block_p (alt_middle_bb))) { if ((operand_equal_for_phi_arg_p (arg_true, smaller) || (alt_smaller @@ -2006,7 +2008,8 @@ minmax_replacement (basic_block cond_bb, basic_block middle_bb, basic_block alt_ return true; } - else + else if (!threeway_p + || empty_block_p (alt_middle_bb)) { /* Recognize the following case, assuming d <= u: @@ -2182,6 +2185,8 @@ minmax_replacement (basic_block cond_bb, basic_block middle_bb, basic_block alt_ SSA_OP_DEF)); gsi_move_before (&gsi_from, &gsi); } + else + return false; /* Emit the statement to compute min/max. */ gimple_seq stmts = NULL; diff --git a/gcc/tree-ssa-reassoc.cc b/gcc/tree-ssa-reassoc.cc index eda03bf..41ee364 100644 --- a/gcc/tree-ssa-reassoc.cc +++ b/gcc/tree-ssa-reassoc.cc @@ -2102,12 +2102,24 @@ undistribute_bitref_for_vector (enum tree_code opcode, { sum = build_and_add_sum (vec_type, sum_vec, valid_vecs[i + 1], opcode); + /* Update the operands only after build_and_add_sum, + so that we don't have to repeat the placement algorithm + of build_and_add_sum. */ + if (sum_vec == tvec + && !useless_type_conversion_p (vec_type, TREE_TYPE (sum_vec))) + { + gimple_stmt_iterator gsi = gsi_for_stmt (sum); + tree vce = build1 (VIEW_CONVERT_EXPR, vec_type, sum_vec); + tree lhs = make_ssa_name (vec_type); + gimple *g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR, vce); + gimple_set_uid (g, gimple_uid (sum)); + gsi_insert_before (&gsi, g, GSI_NEW_STMT); + gimple_assign_set_rhs1 (sum, lhs); + update_stmt (sum); + } if (!useless_type_conversion_p (vec_type, TREE_TYPE (valid_vecs[i + 1]))) { - /* Update the operands only after build_and_add_sum, - so that we don't have to repeat the placement algorithm - of build_and_add_sum. */ gimple_stmt_iterator gsi = gsi_for_stmt (sum); tree vce = build1 (VIEW_CONVERT_EXPR, vec_type, valid_vecs[i + 1]); @@ -2116,15 +2128,6 @@ undistribute_bitref_for_vector (enum tree_code opcode, gimple_set_uid (g, gimple_uid (sum)); gsi_insert_before (&gsi, g, GSI_NEW_STMT); gimple_assign_set_rhs2 (sum, lhs); - if (sum_vec == tvec) - { - vce = build1 (VIEW_CONVERT_EXPR, vec_type, sum_vec); - lhs = make_ssa_name (vec_type); - g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR, vce); - gimple_set_uid (g, gimple_uid (sum)); - gsi_insert_before (&gsi, g, GSI_NEW_STMT); - gimple_assign_set_rhs1 (sum, lhs); - } update_stmt (sum); } sum_vec = gimple_get_lhs (sum); diff --git a/gcc/value-relation.cc b/gcc/value-relation.cc index f2c668a..8fea4aa 100644 --- a/gcc/value-relation.cc +++ b/gcc/value-relation.cc @@ -274,9 +274,12 @@ relation_oracle::valid_equivs (bitmap b, const_bitmap equivs, basic_block bb) EXECUTE_IF_SET_IN_BITMAP (equivs, 0, i, bi) { tree ssa = ssa_name (i); - const_bitmap ssa_equiv = equiv_set (ssa, bb); - if (ssa_equiv == equivs) - bitmap_set_bit (b, i); + if (ssa && !SSA_NAME_IN_FREE_LIST (ssa)) + { + const_bitmap ssa_equiv = equiv_set (ssa, bb); + if (ssa_equiv == equivs) + bitmap_set_bit (b, i); + } } } @@ -512,21 +512,6 @@ template <typename T> inline void vec_default_construct (T *dst, unsigned n) { -#ifdef BROKEN_VALUE_INITIALIZATION - /* Versions of GCC before 4.4 sometimes leave certain objects - uninitialized when value initialized, though if the type has - user defined default ctor, that ctor is invoked. As a workaround - perform clearing first and then the value initialization, which - fixes the case when value initialization doesn't initialize due to - the bugs and should initialize to all zeros, but still allows - vectors for types with user defined default ctor that initializes - some or all elements to non-zero. If T has no user defined - default ctor and some non-static data members have user defined - default ctors that initialize to non-zero the workaround will - still not work properly; in that case we just need to provide - user defined default ctor. */ - memset (dst, '\0', sizeof (T) * n); -#endif for ( ; n; ++dst, --n) ::new (static_cast<void*>(dst)) T (); } |