diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/c4x/c4x.md | 33 |
2 files changed, 41 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4f38848..83d6683 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +Thu Jan 7 00:12:24 1999 Michael Hayes <m.hayes@elec.canterbury.ac.nz> + + * config/c4x/c4x.md (addqi3): If the destination operand is + a hard register other than an extended precision register, + emit addqi3_noclobber. + (*addqi3_noclobber_reload): New pattern added so that reload + will recognise a store of a pseudo, equivalent to the sum + of the frame pointer and a constant, as an add insn. + Wed Jan 6 03:18:53 1999 Mark Elbrecht <snowball3@usa.net. * configure.in (pc-msdosdjgpp): Set x_make to x-go32. diff --git a/gcc/config/c4x/c4x.md b/gcc/config/c4x/c4x.md index 380435c..0830142 100644 --- a/gcc/config/c4x/c4x.md +++ b/gcc/config/c4x/c4x.md @@ -1537,7 +1537,9 @@ (clobber (reg:CC_NOOV 21))])] "" "legitimize_operands (PLUS, operands, QImode); - if (reload_in_progress) + if (reload_in_progress + || (! IS_PSEUDO_REGNO (operands[0]) + && ! IS_EXT_REG (REGNO (operands[0])))) { emit_insn (gen_addqi3_noclobber (operands[0], operands[1], operands[2])); DONE; @@ -1631,6 +1633,35 @@ ; Default to int16 data attr. +; This pattern is required during reload when eliminate_regs_in_insn +; effectively converts a move insn into an add insn when the src +; operand is the frame pointer plus a constant. Without this +; pattern, gen_addqi3 can be called with a register for operand0 +; that can clobber CC. +; For example, we may have (set (mem (reg ar0)) (reg 99)) +; with (set (reg 99) (plus (reg ar3) (const_int 8))) +; Now since ar3, the frame pointer, is unchanging within the function, +; (plus (reg ar3) (const_int 8)) is considered a constant. +; eliminate_regs_in_insn substitutes this constant to give +; (set (mem (reg ar0)) (plus (reg ar3) (const_int 8))). +; This is an invalid C4x insn but if we don't provide a pattern +; for it, it will be considered to be a move insn for reloading. +; The nasty bit is that a GENERAL_REGS class register, say r0, +; may be allocated to reload the PLUS and thus gen_reload will +; emit an add insn that may clobber CC. +(define_insn "*addqi3_noclobber_reload" + [(set (match_operand:QI 0 "general_operand" "=c,?c,c") + (plus:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0") + (match_operand:QI 2 "src_operand" "JR,rS<>,g")))] + "reload_in_progress" + "@ + addi3\\t%2,%1,%0 + addi3\\t%2,%1,%0 + addi\\t%2,%0" + [(set_attr "type" "binary,binary,binary")]) +; Default to int16 data attr. + + (define_insn "*addqi3_carry_clobber" [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c") (plus:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,rR,rS<>,0") |