diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.c-torture/execute/20101011-1.c | 21 |
2 files changed, 24 insertions, 3 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 75b8d09..9b87996 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2012-07-23 Julian Brown <julian@codesourcery.com> + + * gcc.c-torture/execute/20101011-1.c (__aeabi_idiv0): Define for + ARM. + (DO_TEST): Define to 1 for appropriate ARM targets. + 2012-07-22 Steven Bosscher <steven@gcc.gnu.org> PR tree-optimization/53881 diff --git a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c index 2ee70e5..b98454e 100644 --- a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c @@ -15,9 +15,6 @@ #elif defined (__TMS320C6X__) /* On TI C6X division by zero does not trap. */ # define DO_TEST 0 -#elif defined (__arm__) - /* We cannot rely on division by zero generating a trap. */ -# define DO_TEST 0 #elif defined (__mips__) && !defined(__linux__) /* MIPS divisions do trap by default, but libgloss targets do not intercept the trap and raise a SIGFPE. The same is probably @@ -39,6 +36,24 @@ #elif defined (__CRIS__) /* No SIGFPE for CRIS integer division. */ # define DO_TEST 0 +#elif defined (__arm__) && defined (__ARM_EABI__) +# ifdef __ARM_ARCH_EXT_IDIV__ + /* Hardware division instructions may not trap, and handle trapping + differently anyway. Skip the test if we have those instructions. */ +# define DO_TEST 0 +# else +# include <signal.h> + /* ARM division-by-zero behaviour is to call a helper function, which + can do several different things, depending on requirements. Emulate + the behaviour of other targets here by raising SIGFPE. */ +int __attribute__((used)) +__aeabi_idiv0 (int return_value) +{ + raise (SIGFPE); + return return_value; +} +# define DO_TEST 1 +# endif #else # define DO_TEST 1 #endif |