3 files changed, 54 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/arm/neon-vcond-gt.c b/gcc/testsuite/gcc.target/arm/neon-vcond-gt.c
new file mode 100644
index 0000000..86ccf95
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon-vcond-gt.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O1 -funsafe-math-optimizations -ftree-vectorize" }  */
+/* { dg-add-options arm_neon } */
+
+#define MAX(a, b) (a > b ? a : b)
+void foo (int ilast,float* w, float* w2)
+{
+  int i;
+  for (i = 0; i < ilast; ++i)
+  {
+    w[i] = MAX (0.0f, w2[i]);
+  }
+}
+
+/* { dg-final { scan-assembler "vcgt\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vbit\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon-vcond-ltgt.c b/gcc/testsuite/gcc.target/arm/neon-vcond-ltgt.c
new file mode 100644
index 0000000..acb23a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon-vcond-ltgt.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O1 -funsafe-math-optimizations -ftree-vectorize" }  */
+/* { dg-add-options arm_neon } */
+
+#define LTGT(a, b) (__builtin_islessgreater (a, b) ? a : b)
+void foo (int ilast,float* w, float* w2)
+{
+  int i;
+  for (i = 0; i < ilast; ++i)
+  {
+    w[i] = LTGT (0.0f, w2[i]);
+  }
+}
+
+/* { dg-final { scan-assembler-times "vcgt\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler "vorr\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vbsl\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon-vcond-unordered.c b/gcc/testsuite/gcc.target/arm/neon-vcond-unordered.c
new file mode 100644
index 0000000..c3e448d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon-vcond-unordered.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O1 -funsafe-math-optimizations -ftree-vectorize" }  */
+/* { dg-add-options arm_neon } */
+
+#define UNORD(a, b) (__builtin_isunordered (a, b) ? a : b)
+void foo (int ilast,float* w, float* w2)
+{
+  int i;
+  for (i = 0; i < ilast; ++i)
+  {
+    w[i] = UNORD (0.0f, w2[i]);
+  }
+}
+
+/* { dg-final { scan-assembler "vcgt\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vcge\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vorr\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vbsl\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */