diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv-v.cc | 8 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c | 35 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c | 32 |
3 files changed, 71 insertions, 4 deletions
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index fb97034..34fdb53 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -863,7 +863,7 @@ emit_vlmax_masked_gather_mu_insn (rtx target, rtx op, rtx sel, rtx mask) e q r d c b v a # v11 destination after vrgather using viota.m under mask */ static void -emit_vlmax_decompress_insn (rtx target, rtx op, rtx mask) +emit_vlmax_decompress_insn (rtx target, rtx op0, rtx op1, rtx mask) { machine_mode data_mode = GET_MODE (target); machine_mode sel_mode = related_int_vector_mode (data_mode).require (); @@ -873,7 +873,8 @@ emit_vlmax_decompress_insn (rtx target, rtx op, rtx mask) rtx sel = gen_reg_rtx (sel_mode); rtx iota_ops[] = {sel, mask}; emit_vlmax_insn (code_for_pred_iota (sel_mode), RVV_UNOP, iota_ops); - emit_vlmax_masked_gather_mu_insn (target, op, sel, mask); + emit_vlmax_gather_insn (target, op0, sel); + emit_vlmax_masked_gather_mu_insn (target, op1, sel, mask); } /* Emit merge instruction. */ @@ -2441,8 +2442,7 @@ shuffle_decompress_patterns (struct expand_vec_perm_d *d) rtx const_vec = gen_const_vector_dup (sel_mode, 1); rtx mask = gen_reg_rtx (mask_mode); expand_vec_cmp (mask, EQ, vid_repeat, const_vec); - emit_move_insn (d->target, op0); - emit_vlmax_decompress_insn (d->target, op1, mask); + emit_vlmax_decompress_insn (d->target, op0, op1, mask); return true; } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c new file mode 100644 index 0000000..03529f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include <stdint-gcc.h> + +#define VEC_PERM(TYPE) \ + TYPE __attribute__ ((noinline, noclone)) \ + vec_slp_##TYPE (TYPE *restrict a, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + a[i * 8] += 99; \ + a[i * 8 + 1] += 11; \ + a[i * 8 + 2] += 17; \ + a[i * 8 + 3] += 80; \ + a[i * 8 + 4] += 63; \ + a[i * 8 + 5] += 37; \ + a[i * 8 + 6] += 24; \ + a[i * 8 + 7] += 81; \ + } \ + } + +#define TEST_ALL(T) \ + T (int8_t) \ + T (uint8_t) \ + T (int16_t) \ + T (uint16_t) \ + T (int32_t) \ + T (uint32_t) \ + T (int64_t) \ + T (uint64_t) + +TEST_ALL (VEC_PERM) +/* This testcase is from aarch64 and floating-point operations are removed. + TODO: We will add floating-point operations back and make them as common test in the future. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c new file mode 100644 index 0000000..af892ad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "slp-12.c" + +#define N (59 * 8) + +#define HARNESS(TYPE) \ + { \ + TYPE a[N], b[8] = { 99, 11, 17, 80, 63, 37, 24, 81 }; \ + for (unsigned int i = 0; i < N; ++i) \ + { \ + a[i] = i * 2 + i % 5; \ + asm volatile ("" ::: "memory"); \ + } \ + vec_slp_##TYPE (a, N / 8); \ + for (unsigned int i = 0; i < N; ++i) \ + { \ + TYPE orig = i * 2 + i % 5; \ + TYPE expected = orig + b[i % 8]; \ + if (a[i] != expected) \ + __builtin_abort (); \ + } \ + } + +int __attribute__ ((optimize (1))) +main (void) +{ + TEST_ALL (HARNESS) +} +/* This testcase is from aarch64 and floating-point operations are removed. + TODO: We will add floating-point operations back and make them as common test in the future. */ |