diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/combine.c | 6 |
2 files changed, 11 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d28402f..103bc94 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2002-09-20 Jim Wilson <wilson@redhat.com> + + * combine.c (try_combine): When split an instruction pair, where the + first has a sign_extend src, verify that the src and dest modes match. + 2002-09-20 Richard Henderson <rth@redhat.com> * config/mips/mips.c (dfhigh, dflow, sfhigh, sflow): Remove. diff --git a/gcc/combine.c b/gcc/combine.c index 2313619..1d6a5b2 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -2316,6 +2316,10 @@ try_combine (i3, i2, i1, new_direct_jump_p) copy. This saves at least one insn, more if register allocation can eliminate the copy. + We cannot do this if the destination of the first assignment is a + condition code register or cc0. We eliminate this case by making sure + the SET_DEST and SET_SRC have the same mode. + We cannot do this if the destination of the second assignment is a register that we have already assumed is zero-extended. Similarly for a SUBREG of such a register. */ @@ -2325,6 +2329,8 @@ try_combine (i3, i2, i1, new_direct_jump_p) && XVECLEN (newpat, 0) == 2 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND + && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))) + == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0)))) && GET_CODE (XVECEXP (newpat, 0, 1)) == SET && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) |