diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/ia64/ia64.c | 18 |
2 files changed, 13 insertions, 11 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3595e5c..a27d064 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2010-10-18 Steve Ellcey <sje@cup.hp.com> + + PR target/36898 + PR middle-end/43760 + * config/ia64/ia64.c (rws_access_regno): Remove predicate check. + 2010-10-18 Joseph Myers <joseph@codesourcery.com> * config/i386/i386.c (ix86_option_override_internal): Define and diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index f7489f9..c1135f9 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -5875,15 +5875,14 @@ rws_access_regno (int regno, struct reg_flags flags, int pred) break; case 1: - /* The register has been written via a predicate. If this is - not a complementary predicate, then we need a barrier. */ - /* ??? This assumes that P and P+1 are always complementary - predicates for P even. */ + /* The register has been written via a predicate. Treat + it like a unconditional write and do not try to check + for complementary pred reg in earlier write. */ if (flags.is_and && rws_sum[regno].written_by_and) ; else if (flags.is_or && rws_sum[regno].written_by_or) ; - else if ((rws_sum[regno].first_pred ^ 1) != pred) + else need_barrier = 1; if (!in_safe_group_barrier) rws_update (regno, flags, pred); @@ -5944,12 +5943,9 @@ rws_access_regno (int regno, struct reg_flags flags, int pred) break; case 1: - /* The register has been written via a predicate. If this is - not a complementary predicate, then we need a barrier. */ - /* ??? This assumes that P and P+1 are always complementary - predicates for P even. */ - if ((rws_sum[regno].first_pred ^ 1) != pred) - need_barrier = 1; + /* The register has been written via a predicate, assume we + need a barrier (don't check for complementary regs). */ + need_barrier = 1; break; case 2: |