diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 16 | ||||
| -rw-r--r-- | gcc/combine.c | 12 | ||||
| -rw-r--r-- | gcc/cse.c | 4 | ||||
| -rw-r--r-- | gcc/defaults.h | 4 | ||||
| -rw-r--r-- | gcc/fold-const.c | 4 | ||||
| -rw-r--r-- | gcc/fwprop.c | 2 | ||||
| -rw-r--r-- | gcc/postreload.c | 4 | ||||
| -rw-r--r-- | gcc/reload.c | 48 | ||||
| -rw-r--r-- | gcc/reload1.c | 10 | ||||
| -rw-r--r-- | gcc/rtlanal.c | 13 |
10 files changed, 49 insertions, 68 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ae6910c..c8cfc05 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2016-11-04 Eric Botcazou <ebotcazou@adacore.com> + + * defaults.h (LOAD_EXTEND_OP): Define if not already defined. + * combine.c (LOAD_EXTEND_OP): Delete. + (simplify_comparison): Fix comment about LOAD_EXTEND_OP. + * cse.c (LOAD_EXTEND_OP): Delete. + * fold-const.c (LOAD_EXTEND_OP): Likewise. + * fwprop.c (free_load_extend): Remove #ifdef LOAD_EXTEND_OP/#endif. + * postreload.c (LOAD_EXTEND_OP): Delete. + * reload.c (push_reload): Remove #ifdef LOAD_EXTEND_OP/#endif. + Convert conditional compilation based on WORD_REGISTER_OPERATIONS. + (find_reloads): Likewise. + * reload1.c (eliminate_regs_1): Likewise. + * rtlanal.c (nonzero_bits1): Remove #ifdef LOAD_EXTEND_OP/#endif. + (num_sign_bit_copies1): Likewise. + 2016-11-04 David Malcolm <dmalcolm@redhat.com> * config/i386/i386.c: Include "selftest.h" and "selftest-rtl.h". diff --git a/gcc/combine.c b/gcc/combine.c index c605b1a..f772878 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -104,10 +104,6 @@ along with GCC; see the file COPYING3. If not see #include "rtl-iter.h" #include "print-rtl.h" -#ifndef LOAD_EXTEND_OP -#define LOAD_EXTEND_OP(M) UNKNOWN -#endif - /* Number of attempts to combine instructions in this function. */ static int combine_attempts; @@ -12465,14 +12461,14 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1) care bits and we can assume they have any convenient value. So making the transformation is safe. - 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined. + 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN. In this case the upper bits of op0 are undefined. We should not make the simplification in that case as we do not know the contents of those bits. - 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not - UNKNOWN. In that case we know those bits are zeros or ones. We must - also be sure that they are the same as the upper bits of op1. + 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN. + In that case we know those bits are zeros or ones. We must also be + sure that they are the same as the upper bits of op1. We can never remove a SUBREG for a non-equality comparison because the sign bit is in a different place in the underlying object. */ @@ -43,10 +43,6 @@ along with GCC; see the file COPYING3. If not see #include "dbgcnt.h" #include "rtl-iter.h" -#ifndef LOAD_EXTEND_OP -#define LOAD_EXTEND_OP(M) UNKNOWN -#endif - /* The basic idea of common subexpression elimination is to go through the code, keeping a record of expressions that would have the same value at the current scan point, and replacing diff --git a/gcc/defaults.h b/gcc/defaults.h index 74d41e7..9c40002 100644 --- a/gcc/defaults.h +++ b/gcc/defaults.h @@ -1259,6 +1259,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define WORD_REGISTER_OPERATIONS 0 #endif +#ifndef LOAD_EXTEND_OP +#define LOAD_EXTEND_OP(M) UNKNOWN +#endif + #ifndef CONSTANT_ALIGNMENT #define CONSTANT_ALIGNMENT(EXP, ALIGN) ALIGN #endif diff --git a/gcc/fold-const.c b/gcc/fold-const.c index 593ea16..603aff0 100644 --- a/gcc/fold-const.c +++ b/gcc/fold-const.c @@ -80,10 +80,6 @@ along with GCC; see the file COPYING3. If not see #include "tree-ssanames.h" #include "selftest.h" -#ifndef LOAD_EXTEND_OP -#define LOAD_EXTEND_OP(M) UNKNOWN -#endif - /* Nonzero if we are folding constants inside an initializer; zero otherwise. */ int folding_initializer = 0; diff --git a/gcc/fwprop.c b/gcc/fwprop.c index 4365ff0..b2d6700 100644 --- a/gcc/fwprop.c +++ b/gcc/fwprop.c @@ -1051,9 +1051,7 @@ free_load_extend (rtx src, rtx_insn *insn) df_ref def, use; reg = XEXP (src, 0); -#ifdef LOAD_EXTEND_OP if (LOAD_EXTEND_OP (GET_MODE (reg)) != GET_CODE (src)) -#endif return false; FOR_EACH_INSN_USE (use, insn) diff --git a/gcc/postreload.c b/gcc/postreload.c index 26871e8..8a44562 100644 --- a/gcc/postreload.c +++ b/gcc/postreload.c @@ -41,10 +41,6 @@ along with GCC; see the file COPYING3. If not see #include "tree-pass.h" #include "dbgcnt.h" -#ifndef LOAD_EXTEND_OP -#define LOAD_EXTEND_OP(M) UNKNOWN -#endif - static int reload_cse_noop_set_p (rtx); static bool reload_cse_simplify (rtx_insn *, rtx); static void reload_cse_regs_1 (void); diff --git a/gcc/reload.c b/gcc/reload.c index 3ec4b31..7d16817 100644 --- a/gcc/reload.c +++ b/gcc/reload.c @@ -1064,7 +1064,6 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc, || MEM_P (SUBREG_REG (in))) && ((GET_MODE_PRECISION (inmode) > GET_MODE_PRECISION (GET_MODE (SUBREG_REG (in)))) -#ifdef LOAD_EXTEND_OP || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) <= UNITS_PER_WORD) @@ -1072,15 +1071,12 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc, > GET_MODE_PRECISION (GET_MODE (SUBREG_REG (in)))) && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (in))) && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != UNKNOWN) -#endif -#if WORD_REGISTER_OPERATIONS - || ((GET_MODE_PRECISION (inmode) - < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (in)))) + || (WORD_REGISTER_OPERATIONS + && (GET_MODE_PRECISION (inmode) + < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (in)))) && ((GET_MODE_SIZE (inmode) - 1) / UNITS_PER_WORD == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) - 1) - / UNITS_PER_WORD))) -#endif - )) + / UNITS_PER_WORD))))) || (REG_P (SUBREG_REG (in)) && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER /* The case where out is nonzero @@ -1111,13 +1107,14 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc, #endif inloc = &SUBREG_REG (in); in = *inloc; -#if ! defined (LOAD_EXTEND_OP) + if (!WORD_REGISTER_OPERATIONS + && LOAD_EXTEND_OP (GET_MODE (in)) == UNKNOWN && MEM_P (in)) /* This is supposed to happen only for paradoxical subregs made by combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */ gcc_assert (GET_MODE_SIZE (GET_MODE (in)) <= GET_MODE_SIZE (inmode)); -#endif + inmode = GET_MODE (in); } @@ -1175,14 +1172,12 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc, || MEM_P (SUBREG_REG (out))) && ((GET_MODE_PRECISION (outmode) > GET_MODE_PRECISION (GET_MODE (SUBREG_REG (out)))) -#if WORD_REGISTER_OPERATIONS - || ((GET_MODE_PRECISION (outmode) - < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (out)))) + || (WORD_REGISTER_OPERATIONS + && (GET_MODE_PRECISION (outmode) + < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (out)))) && ((GET_MODE_SIZE (outmode) - 1) / UNITS_PER_WORD == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) - 1) - / UNITS_PER_WORD))) -#endif - )) + / UNITS_PER_WORD))))) || (REG_P (SUBREG_REG (out)) && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER /* The case of a word mode subreg @@ -3139,24 +3134,21 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known, || ((MEM_P (operand) || (REG_P (operand) && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) -#if !WORD_REGISTER_OPERATIONS - && (((GET_MODE_BITSIZE (GET_MODE (operand)) - < BIGGEST_ALIGNMENT) - && (GET_MODE_SIZE (operand_mode[i]) - > GET_MODE_SIZE (GET_MODE (operand)))) + && (WORD_REGISTER_OPERATIONS + || ((GET_MODE_BITSIZE (GET_MODE (operand)) + < BIGGEST_ALIGNMENT) + && (GET_MODE_SIZE (operand_mode[i]) + > GET_MODE_SIZE (GET_MODE (operand)))) || BYTES_BIG_ENDIAN -#ifdef LOAD_EXTEND_OP - || (GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD + || ((GET_MODE_SIZE (operand_mode[i]) + <= UNITS_PER_WORD) && (GET_MODE_SIZE (GET_MODE (operand)) <= UNITS_PER_WORD) && (GET_MODE_SIZE (operand_mode[i]) > GET_MODE_SIZE (GET_MODE (operand))) && INTEGRAL_MODE_P (GET_MODE (operand)) - && LOAD_EXTEND_OP (GET_MODE (operand)) != UNKNOWN) -#endif - ) -#endif - ) + && LOAD_EXTEND_OP (GET_MODE (operand)) + != UNKNOWN))) ) force_reload = 1; } diff --git a/gcc/reload1.c b/gcc/reload1.c index 876f7ef..4ee3840 100644 --- a/gcc/reload1.c +++ b/gcc/reload1.c @@ -2819,18 +2819,16 @@ eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn, if (MEM_P (new_rtx) && ((x_size < new_size -#if WORD_REGISTER_OPERATIONS - /* On these machines, combine can create rtl of the form + /* On RISC machines, combine can create rtl of the form (set (subreg:m1 (reg:m2 R) 0) ...) where m1 < m2, and expects something interesting to happen to the entire word. Moreover, it will use the (reg:m2 R) later, expecting all bits to be preserved. So if the number of words is the same, preserve the subreg so that push_reload can see it. */ - && ! ((x_size - 1) / UNITS_PER_WORD - == (new_size -1 ) / UNITS_PER_WORD) -#endif - ) + && !(WORD_REGISTER_OPERATIONS + && (x_size - 1) / UNITS_PER_WORD + == (new_size -1 ) / UNITS_PER_WORD)) || x_size == new_size) ) return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x)); diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c index 4ebb314..c98a708 100644 --- a/gcc/rtlanal.c +++ b/gcc/rtlanal.c @@ -4361,13 +4361,11 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x, return UINTVAL (x); case MEM: -#ifdef LOAD_EXTEND_OP /* In many, if not most, RISC machines, reading a byte from memory zeros the rest of the register. Noticing that fact saves a lot of extra zero-extends. */ if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND) nonzero &= GET_MODE_MASK (GET_MODE (x)); -#endif break; case EQ: case NE: @@ -4567,7 +4565,6 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x, nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode, known_x, known_mode, known_ret); -#ifdef LOAD_EXTEND_OP /* On many CISC machines, accessing an object in a wider mode causes the high-order bits to become undefined. So they are not known to be zero. */ @@ -4578,7 +4575,6 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x, ? val_signbit_known_set_p (inner_mode, nonzero) : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND) || !MEM_P (SUBREG_REG (x)))) -#endif { if (GET_MODE_PRECISION (GET_MODE (x)) > GET_MODE_PRECISION (inner_mode)) @@ -4824,10 +4820,7 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x, than a word and loads of that size don't sign extend, we can say nothing about the high order bits. */ if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD -#ifdef LOAD_EXTEND_OP - && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND -#endif - ) + && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND) return 1; } @@ -4868,12 +4861,10 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x, break; case MEM: -#ifdef LOAD_EXTEND_OP /* Some RISC machines sign-extend all loads of smaller than a word. */ if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND) return MAX (1, ((int) bitwidth - (int) GET_MODE_PRECISION (GET_MODE (x)) + 1)); -#endif break; case CONST_INT: @@ -4910,7 +4901,6 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x, - bitwidth))); } -#ifdef LOAD_EXTEND_OP /* For paradoxical SUBREGs on machines where all register operations affect the entire register, just look inside. Note that we are passing MODE to the recursive call, so the number of sign bit copies @@ -4927,7 +4917,6 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x, && MEM_P (SUBREG_REG (x))) return cached_num_sign_bit_copies (SUBREG_REG (x), mode, known_x, known_mode, known_ret); -#endif break; case SIGN_EXTRACT: |