diff options
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 18 | ||||
-rw-r--r-- | gcc/config/i386/i386.md | 225 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 8 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/bt-3.c | 14 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/bt-4.c | 14 |
5 files changed, 174 insertions, 105 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0650557..d325d90 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2015-07-07 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.md (*jcc_bt<mode>): Only split before reload. + Remove operand constraints. Change operand 2 predicate to + nonmemory operand. Limit const_int values to mode bitsize. Only + allow const_int values less than 32 when optimizing for size. + (*jcc_bt<mode>_1, *jcc_bt<mode>_mask): Only split before reload. + Remove operand constraints. + (*bt<mode>): Use SImode for const_int values less than 32. + (regmode): Remove mode attribute. + 2015-07-07 Anatoly Sokolov <aesok@post.ru> * config/moxie/moxie.h (GO_IF_LEGITIMATE_ADDRESS): Remove macros. @@ -10,8 +21,8 @@ PR tree-optimization/66642 * tree-parloops.c (transform_to_exit_first_loop_alt): Update function header comment. Rename split_edge variable to edge_at_split. Split - exit edge to create new loop exit bb. Insert loop exit phis in new loop - exit bb. + exit edge to create new loop exit bb. Insert loop exit phis in new + loop exit bb. 2015-07-07 Tom de Vries <tom@codesourcery.com> @@ -46,7 +57,8 @@ 2015-07-07 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> - * function.c (free_after_compilation): Clear PROP_cfg in f->curr_properties. + * function.c (free_after_compilation): Clear PROP_cfg in + f->curr_properties. 2015-07-07 Richard Biener <rguenther@suse.de> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index dcf1d58..93c5772 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -10765,8 +10765,6 @@ DONE; }) -(define_mode_attr regmode [(SI "k") (DI "q")]) - (define_insn "*bt<mode>" [(set (reg:CCC FLAGS_REG) (compare:CCC @@ -10775,11 +10773,132 @@ (const_int 1) (match_operand:SI 1 "nonmemory_operand" "rN")) (const_int 0)))] - "TARGET_USE_BT || optimize_function_for_size_p (cfun)" - "bt{<imodesuffix>}\t{%<regmode>1, %0|%0, %<regmode>1}" + "" +{ + switch (get_attr_mode (insn)) + { + case MODE_SI: + return "bt{l}\t{%1, %k0|%k0, %1}"; + + case MODE_DI: + return "bt{q}\t{%q1, %0|%0, %q1}"; + + default: + gcc_unreachable (); + } +} [(set_attr "type" "alu1") (set_attr "prefix_0f" "1") - (set_attr "mode" "<MODE>")]) + (set (attr "mode") + (if_then_else + (and (match_test "CONST_INT_P (operands[1])") + (match_test "INTVAL (operands[1]) < 32")) + (const_string "SI") + (const_string "<MODE>")))]) + +(define_insn_and_split "*jcc_bt<mode>" + [(set (pc) + (if_then_else (match_operator 0 "bt_comparison_operator" + [(zero_extract:SWI48 + (match_operand:SWI48 1 "register_operand") + (const_int 1) + (match_operand:SI 2 "nonmemory_operand")) + (const_int 0)]) + (label_ref (match_operand 3)) + (pc))) + (clobber (reg:CC FLAGS_REG))] + "(TARGET_USE_BT || optimize_function_for_size_p (cfun)) + && (CONST_INT_P (operands[2]) + ? (INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode) + && INTVAL (operands[2]) + >= (optimize_function_for_size_p (cfun) ? 0 : 32)) + : register_operand (operands[2], SImode)) + && can_create_pseudo_p ()" + "#" + "&& 1" + [(set (reg:CCC FLAGS_REG) + (compare:CCC + (zero_extract:SWI48 + (match_dup 1) + (const_int 1) + (match_dup 2)) + (const_int 0))) + (set (pc) + (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)]) + (label_ref (match_dup 3)) + (pc)))] +{ + operands[0] = shallow_copy_rtx (operands[0]); + PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0]))); +}) + +(define_insn_and_split "*jcc_bt<mode>_1" + [(set (pc) + (if_then_else (match_operator 0 "bt_comparison_operator" + [(zero_extract:SWI48 + (match_operand:SWI48 1 "register_operand") + (const_int 1) + (zero_extend:SI + (match_operand:QI 2 "register_operand"))) + (const_int 0)]) + (label_ref (match_operand 3)) + (pc))) + (clobber (reg:CC FLAGS_REG))] + "(TARGET_USE_BT || optimize_function_for_size_p (cfun)) + && can_create_pseudo_p ()" + "#" + "&& 1" + [(set (reg:CCC FLAGS_REG) + (compare:CCC + (zero_extract:SWI48 + (match_dup 1) + (const_int 1) + (match_dup 2)) + (const_int 0))) + (set (pc) + (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)]) + (label_ref (match_dup 3)) + (pc)))] +{ + operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0); + operands[0] = shallow_copy_rtx (operands[0]); + PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0]))); +}) + +;; Avoid useless masking of bit offset operand. +(define_insn_and_split "*jcc_bt<mode>_mask" + [(set (pc) + (if_then_else (match_operator 0 "bt_comparison_operator" + [(zero_extract:SWI48 + (match_operand:SWI48 1 "register_operand") + (const_int 1) + (and:SI + (match_operand:SI 2 "register_operand") + (match_operand 3 "const_int_operand")))]) + (label_ref (match_operand 4)) + (pc))) + (clobber (reg:CC FLAGS_REG))] + "(TARGET_USE_BT || optimize_function_for_size_p (cfun)) + && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1)) + == GET_MODE_BITSIZE (<MODE>mode)-1 + && can_create_pseudo_p ()" + "#" + "&& 1" + [(set (reg:CCC FLAGS_REG) + (compare:CCC + (zero_extract:SWI48 + (match_dup 1) + (const_int 1) + (match_dup 2)) + (const_int 0))) + (set (pc) + (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)]) + (label_ref (match_dup 4)) + (pc)))] +{ + operands[0] = shallow_copy_rtx (operands[0]); + PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0]))); +}) ;; Store-flag instructions. @@ -11036,102 +11155,6 @@ FAIL; }) -(define_insn_and_split "*jcc_bt<mode>" - [(set (pc) - (if_then_else (match_operator 0 "bt_comparison_operator" - [(zero_extract:SWI48 - (match_operand:SWI48 1 "register_operand" "r") - (const_int 1) - (match_operand:SI 2 "register_operand" "r")) - (const_int 0)]) - (label_ref (match_operand 3)) - (pc))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_USE_BT || optimize_function_for_size_p (cfun)" - "#" - "&& 1" - [(set (reg:CCC FLAGS_REG) - (compare:CCC - (zero_extract:SWI48 - (match_dup 1) - (const_int 1) - (match_dup 2)) - (const_int 0))) - (set (pc) - (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)]) - (label_ref (match_dup 3)) - (pc)))] -{ - operands[0] = shallow_copy_rtx (operands[0]); - PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0]))); -}) - -(define_insn_and_split "*jcc_bt<mode>_1" - [(set (pc) - (if_then_else (match_operator 0 "bt_comparison_operator" - [(zero_extract:SWI48 - (match_operand:SWI48 1 "register_operand" "r") - (const_int 1) - (zero_extend:SI - (match_operand:QI 2 "register_operand" "r"))) - (const_int 0)]) - (label_ref (match_operand 3)) - (pc))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_USE_BT || optimize_function_for_size_p (cfun)" - "#" - "&& 1" - [(set (reg:CCC FLAGS_REG) - (compare:CCC - (zero_extract:SWI48 - (match_dup 1) - (const_int 1) - (match_dup 2)) - (const_int 0))) - (set (pc) - (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)]) - (label_ref (match_dup 3)) - (pc)))] -{ - operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0); - operands[0] = shallow_copy_rtx (operands[0]); - PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0]))); -}) - -;; Avoid useless masking of bit offset operand. -(define_insn_and_split "*jcc_bt<mode>_mask" - [(set (pc) - (if_then_else (match_operator 0 "bt_comparison_operator" - [(zero_extract:SWI48 - (match_operand:SWI48 1 "register_operand" "r") - (const_int 1) - (and:SI - (match_operand:SI 2 "register_operand" "r") - (match_operand 3 "const_int_operand" "n")))]) - (label_ref (match_operand 4)) - (pc))) - (clobber (reg:CC FLAGS_REG))] - "(TARGET_USE_BT || optimize_function_for_size_p (cfun)) - && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1)) - == GET_MODE_BITSIZE (<MODE>mode)-1" - "#" - "&& 1" - [(set (reg:CCC FLAGS_REG) - (compare:CCC - (zero_extract:SWI48 - (match_dup 1) - (const_int 1) - (match_dup 2)) - (const_int 0))) - (set (pc) - (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)]) - (label_ref (match_dup 4)) - (pc)))] -{ - operands[0] = shallow_copy_rtx (operands[0]); - PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0]))); -}) - ;; Define combination compare-and-branch fp compare instructions to help ;; combine. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 57705bc..4c632d8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2015-07-07 Uros Bizjak <ubizjak@gmail.com> + + * gcc.target/i386/bt-3.c: New test. + * gcc.target/i386/bt-4.c: Ditto. + 2015-07-07 Eric Botcazou <ebotcazou@adacore.com> * g++.dg/other/dump-ada-spec-8.C: New test. @@ -252,7 +257,8 @@ 2015-07-01 Jiong Wang <jiong.wang@arm.com> - * lib/target-supports.exp (check_effective_target_aarch64_small_fpic):New function. + * lib/target-supports.exp (check_effective_target_aarch64_small_fpic): + New function. * gcc.target/aarch64/pic-small.c: Restrict this test under check_effective_target_aarch64_small_fpic. diff --git a/gcc/testsuite/gcc.target/i386/bt-3.c b/gcc/testsuite/gcc.target/i386/bt-3.c new file mode 100644 index 0000000..aa13c5d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bt-3.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mtune=core2" } */ + +extern void foo (void); + +int test (long long x) +{ + if (x & ( 0x01ULL << 60 )) + foo (); + + return 0; +} + +/* { dg-final { scan-assembler "btq\[ \t\]" } } */ diff --git a/gcc/testsuite/gcc.target/i386/bt-4.c b/gcc/testsuite/gcc.target/i386/bt-4.c new file mode 100644 index 0000000..7a5e873 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bt-4.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -mtune=core2" } */ + +extern void foo (void); + +int test (long x) +{ + if (x & ( 0x01UL << 10 )) + foo (); + + return 0; +} + +/* { dg-final { scan-assembler "btl\[ \t\]" } } */ |