diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 13 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 65 |
2 files changed, 49 insertions, 29 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 88e39ab..da58116d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2016-05-16 Wilco Dijkstra <wdijkstr@arm.com> + + * gcc/config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_<mode>3): + Split integer shifts into shift_reg and bfm. + (aarch64_lshr_sisd_or_int_<mode>3): Likewise. + (aarch64_ashr_sisd_or_int_<mode>3): Likewise. + (ror<mode>3_insn): Likewise. + (<optab>si3_insn_uxtw): Likewise. + (<optab><mode>3_insn): Change to rotate_imm. + (extr<mode>5_insn_alt): Likewise. + (extrsi5_insn_uxtw): Likewise. + (extrsi5_insn_uxtw_alt): Likewise. + 2016-05-16 Matthew Wahab <matthew.wahab@arm.com> * doc/tm.texi: Regenerate. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 9b282f1..f6bc12d 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3936,33 +3936,35 @@ ;; Logical left shift using SISD or Integer instruction (define_insn "*aarch64_ashl_sisd_or_int_<mode>3" - [(set (match_operand:GPI 0 "register_operand" "=r,w,w") - (ashift:GPI - (match_operand:GPI 1 "register_operand" "r,w,w") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "rUs<cmode>,Us<cmode>,w")))] + [(set (match_operand:GPI 0 "register_operand" "=r,r,w,w") + (ashift:GPI + (match_operand:GPI 1 "register_operand" "r,r,w,w") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "Us<cmode>,r,Us<cmode>,w")))] "" "@ + lsl\t%<w>0, %<w>1, %2 lsl\t%<w>0, %<w>1, %<w>2 shl\t%<rtn>0<vas>, %<rtn>1<vas>, %2 ushl\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas>" - [(set_attr "simd" "no,yes,yes") - (set_attr "type" "shift_reg,neon_shift_imm<q>, neon_shift_reg<q>")] + [(set_attr "simd" "no,no,yes,yes") + (set_attr "type" "bfm,shift_reg,neon_shift_imm<q>, neon_shift_reg<q>")] ) ;; Logical right shift using SISD or Integer instruction (define_insn "*aarch64_lshr_sisd_or_int_<mode>3" - [(set (match_operand:GPI 0 "register_operand" "=r,w,&w,&w") - (lshiftrt:GPI - (match_operand:GPI 1 "register_operand" "r,w,w,w") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "rUs<cmode>,Us<cmode>,w,0")))] + [(set (match_operand:GPI 0 "register_operand" "=r,r,w,&w,&w") + (lshiftrt:GPI + (match_operand:GPI 1 "register_operand" "r,r,w,w,w") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "Us<cmode>,r,Us<cmode>,w,0")))] "" "@ + lsr\t%<w>0, %<w>1, %2 lsr\t%<w>0, %<w>1, %<w>2 ushr\t%<rtn>0<vas>, %<rtn>1<vas>, %2 # #" - [(set_attr "simd" "no,yes,yes,yes") - (set_attr "type" "shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")] + [(set_attr "simd" "no,no,yes,yes,yes") + (set_attr "type" "bfm,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")] ) (define_split @@ -3997,18 +3999,19 @@ ;; Arithmetic right shift using SISD or Integer instruction (define_insn "*aarch64_ashr_sisd_or_int_<mode>3" - [(set (match_operand:GPI 0 "register_operand" "=r,w,&w,&w") + [(set (match_operand:GPI 0 "register_operand" "=r,r,w,&w,&w") (ashiftrt:GPI - (match_operand:GPI 1 "register_operand" "r,w,w,w") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_di" "rUs<cmode>,Us<cmode>,w,0")))] + (match_operand:GPI 1 "register_operand" "r,r,w,w,w") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_di" "Us<cmode>,r,Us<cmode>,w,0")))] "" "@ + asr\t%<w>0, %<w>1, %2 asr\t%<w>0, %<w>1, %<w>2 sshr\t%<rtn>0<vas>, %<rtn>1<vas>, %2 # #" - [(set_attr "simd" "no,yes,yes,yes") - (set_attr "type" "shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")] + [(set_attr "simd" "no,no,yes,yes,yes") + (set_attr "type" "bfm,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")] ) (define_split @@ -4100,21 +4103,25 @@ [(set (match_operand:GPI 0 "register_operand" "=r,r") (rotatert:GPI (match_operand:GPI 1 "register_operand" "r,r") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "r,Us<cmode>")))] + (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "Us<cmode>,r")))] "" - "ror\\t%<w>0, %<w>1, %<w>2" - [(set_attr "type" "shift_reg, rotate_imm")] + "@ + ror\\t%<w>0, %<w>1, %2 + ror\\t%<w>0, %<w>1, %<w>2" + [(set_attr "type" "rotate_imm,shift_reg")] ) ;; zero_extend version of above (define_insn "*<optab>si3_insn_uxtw" - [(set (match_operand:DI 0 "register_operand" "=r") + [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (SHIFT:SI - (match_operand:SI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "rUss"))))] + (match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "Uss,r"))))] "" - "<shift>\\t%w0, %w1, %w2" - [(set_attr "type" "shift_reg")] + "@ + <shift>\\t%w0, %w1, %2 + <shift>\\t%w0, %w1, %w2" + [(set_attr "type" "bfm,shift_reg")] ) (define_insn "*<optab><mode>3_insn" @@ -4138,7 +4145,7 @@ "UINTVAL (operands[3]) < GET_MODE_BITSIZE (<MODE>mode) && (UINTVAL (operands[3]) + UINTVAL (operands[4]) == GET_MODE_BITSIZE (<MODE>mode))" "extr\\t%<w>0, %<w>1, %<w>2, %4" - [(set_attr "type" "shift_imm")] + [(set_attr "type" "rotate_imm")] ) ;; There are no canonicalisation rules for ashift and lshiftrt inside an ior @@ -4153,7 +4160,7 @@ && (UINTVAL (operands[3]) + UINTVAL (operands[4]) == GET_MODE_BITSIZE (<MODE>mode))" "extr\\t%<w>0, %<w>1, %<w>2, %4" - [(set_attr "type" "shift_imm")] + [(set_attr "type" "rotate_imm")] ) ;; zero_extend version of the above @@ -4167,7 +4174,7 @@ "UINTVAL (operands[3]) < 32 && (UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)" "extr\\t%w0, %w1, %w2, %4" - [(set_attr "type" "shift_imm")] + [(set_attr "type" "rotate_imm")] ) (define_insn "*extrsi5_insn_uxtw_alt" @@ -4180,7 +4187,7 @@ "UINTVAL (operands[3]) < 32 && (UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)" "extr\\t%w0, %w1, %w2, %4" - [(set_attr "type" "shift_imm")] + [(set_attr "type" "rotate_imm")] ) (define_insn "*ror<mode>3_insn" |