diff options
Diffstat (limited to 'gcc')
44 files changed, 2081 insertions, 1274 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 98453b0..fc67dd4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,98 @@ +2021-02-02 Richard Biener <rguenther@suse.de> + + * gimple-loop-interchange.cc (prepare_data_references): + Release vectors. + * gimple-loop-jam.c (tree_loop_unroll_and_jam): Likewise. + * tree-ssa-loop-im.c (hoist_memory_references): Likewise. + * tree-vect-stmts.c (vectorizable_condition): Do not + allocate vectors. + (vectorizable_comparison): Likewise. + +2021-02-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64-simd-builtins.def (ursqrte): Define builtin. + * config/aarch64/aarch64-simd.md (aarch64_ursqrte<mode>): New pattern. + * config/aarch64/arm_neon.h (vrsqrte_u32): Reimplement using builtin. + (vrsqrteq_u32): Likewise. + +2021-02-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64-simd-builtins.def (sqxtun2): Define builtin. + * config/aarch64/aarch64-simd.md (aarch64_sqxtun2<mode>_le): Define. + (aarch64_sqxtun2<mode>_be): Likewise. + (aarch64_sqxtun2<mode>): Likewise. + * config/aarch64/arm_neon.h (vqmovun_high_s16): Reimplement using builtin. + (vqmovun_high_s32): Likewise. + (vqmovun_high_s64): Likewise. + * config/aarch64/iterators.md (UNSPEC_SQXTUN2): Define. + +2021-02-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64-simd-builtins.def (bfdot_lane, bfdot_laneq): Use + AUTO_FP flags. + (bfmlalb_lane, bfmlalt_lane, bfmlalb_lane_q, bfmlalt_lane_q): Use FP flags. + +2021-02-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64-simd-builtins.def (fcmla_lane0, fcmla_lane90, + fcmla_lane180, fcmla_lane270, fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, + fcmlaq_lane270, scvtf, ucvtf, fcvtzs, fcvtzu, scvtfsi, scvtfdi, ucvtfsi, + ucvtfdi, fcvtzshf, fcvtzuhf, fmlal_lane_low, fmlsl_lane_low, + fmlal_laneq_low, fmlsl_laneq_low, fmlalq_lane_low, fmlslq_lane_low, + fmlalq_laneq_low, fmlslq_laneq_low, fmlal_lane_high, fmlsl_lane_high, + fmlal_laneq_high, fmlsl_laneq_high, fmlalq_lane_high, fmlslq_lane_high, + fmlalq_laneq_high, fmlslq_laneq_high): Use FP flags. + +2021-02-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64-builtins.c (FLAG_LOAD): Define. + * config/aarch64/aarch64-simd-builtins.def (ld1x2, ld2, ld3, ld4, ld2r, + ld3r, ld4r, ld1, ld1x3, ld1x4): Use LOAD flags. + +2021-02-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64-simd-builtins.def (combine, zip1, zip2, + uzp1, uzp2, trn1, trn2, simd_bsl): Use AUTO_FP flags. + +2021-02-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64-simd-builtins.def (clrsb, clz, ctz, popcount, + vec_smult_lane_, vec_smlal_lane_, vec_smult_laneq_, vec_smlal_laneq_, + vec_umult_lane_, vec_umlal_lane_, vec_umult_laneq_, vec_umlal_laneq_, + ashl, sshl, ushl, srshl, urshl, sdot_lane, udot_lane, sdot_laneq, + udot_laneq, usdot_lane, usdot_laneq, sudot_lane, sudot_laneq, ashr, + ashr_simd, lshr, lshr_simd, srshr_n, urshr_n, ssra_n, usra_n, srsra_n, + ursra_n, sshll_n, ushll_n, sshll2_n, ushll2_n, ssri_n, usri_n, ssli_n, + ssli_n, usli_n, bswap, rbit, simd_bsl, eor3q, rax1q, xarq, bcaxq): Use + NONE builtin flags. + +2021-02-02 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/98848 + * tree-vect-patterns.c (vect_recog_over_widening_pattern): Punt if + STMT_VINFO_DEF_TYPE (last_stmt_info) is vect_reduction_def. + +2021-02-02 Kito Cheng <kito.cheng@sifive.com> + + PR target/98743 + * expr.c: Check mode before calling store_expr. + +2021-02-02 Christophe Lyon <christophe.lyon@linaro.org> + + * config/arm/iterators.md (supf): Remove VORNQ_S and VORNQ_U. + (VORNQ): Remove. + * config/arm/mve.md (mve_vornq_s<mode>): New entry for vorn + instruction using expression ior. + (mve_vornq_u<mode>): New expander. + (mve_vornq_f<mode>): Use ior code instead of unspec. + * config/arm/unspecs.md (VORNQ_S, VORNQ_U, VORNQ_F): Remove. + +2021-02-02 Alexandre Oliva <oliva@adacore.com> + + * tree-nested.c (convert_nonlocal_reference_op): Move + current_function_decl restore after re-gimplification. + (convert_local_reference_op): Likewise. + 2021-02-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/aarch64/aarch64-simd-builtins.def (rshrn, rshrn2): diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 43c7f94..465eb04 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20210202 +20210203 diff --git a/gcc/ada/gcc-interface/decl.c b/gcc/ada/gcc-interface/decl.c index 5ea1b16..aea191c 100644 --- a/gcc/ada/gcc-interface/decl.c +++ b/gcc/ada/gcc-interface/decl.c @@ -2197,14 +2197,16 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, bool definition) } else { + /* We make the fields addressable for the sake of compatibility + with languages for which the regular fields are addressable. */ tem = create_field_decl (get_identifier ("P_ARRAY"), ptr_type_node, gnu_fat_type, - NULL_TREE, NULL_TREE, 0, 0); + NULL_TREE, NULL_TREE, 0, 1); DECL_CHAIN (tem) = create_field_decl (get_identifier ("P_BOUNDS"), gnu_ptr_template, gnu_fat_type, - NULL_TREE, NULL_TREE, 0, 0); + NULL_TREE, NULL_TREE, 0, 1); finish_fat_pointer_type (gnu_fat_type, tem); SET_TYPE_UNCONSTRAINED_ARRAY (gnu_fat_type, gnu_type); } @@ -2327,7 +2329,6 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, bool definition) finish_record_type (gnu_template_type, gnu_template_fields, 0, debug_info_p); TYPE_CONTEXT (gnu_template_type) = current_function_decl; - TYPE_READONLY (gnu_template_type) = 1; /* If Component_Size is not already specified, annotate it with the size of the component. */ @@ -3054,15 +3055,24 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, bool definition) || type_annotate_only); } - /* Make a node for the record. If we are not defining the record, - suppress expanding incomplete types. */ + /* Make a node for the record type. */ gnu_type = make_node (tree_code_for_record_type (gnat_entity)); TYPE_NAME (gnu_type) = gnu_entity_name; TYPE_PACKED (gnu_type) = (packed != 0) || has_align || has_rep; TYPE_REVERSE_STORAGE_ORDER (gnu_type) = Reverse_Storage_Order (gnat_entity); + + /* If the record type has discriminants, pointers to it may also point + to constrained subtypes of it, so mark it as may_alias for LTO. */ + if (has_discr) + prepend_one_attribute + (&attr_list, ATTR_MACHINE_ATTRIBUTE, + get_identifier ("may_alias"), NULL_TREE, + gnat_entity); + process_attributes (&gnu_type, &attr_list, true, gnat_entity); + /* If we are not defining it, suppress expanding incomplete types. */ if (!definition) { defer_incomplete_level++; @@ -8320,12 +8330,12 @@ components_to_record (Node_Id gnat_component_list, Entity_Id gnat_record_type, if (p_gnu_rep_list && gnu_rep_list) *p_gnu_rep_list = chainon (*p_gnu_rep_list, gnu_rep_list); - /* Deal with the annoying case of an extension of a record with variable size - and partial rep clause, for which the _Parent field is forced at offset 0 - and has variable size, which we do not support below. Note that we cannot - do it if the field has fixed size because we rely on the presence of the - REP part built below to trigger the reordering of the fields in a derived - record type when all the fields have a fixed position. */ + /* Deal with the case of an extension of a record type with variable size and + partial rep clause, for which the _Parent field is forced at offset 0 and + has variable size. Note that we cannot do it if the field has fixed size + because we rely on the presence of the REP part built below to trigger the + reordering of the fields in a derived record type when all the fields have + a fixed position. */ else if (gnu_rep_list && !DECL_CHAIN (gnu_rep_list) && TREE_CODE (DECL_SIZE (gnu_rep_list)) != INTEGER_CST @@ -8343,33 +8353,52 @@ components_to_record (Node_Id gnat_component_list, Entity_Id gnat_record_type, record, before the others, if we also have fields without rep clause. */ else if (gnu_rep_list) { - tree gnu_rep_type, gnu_rep_part; - int i, len = list_length (gnu_rep_list); - tree *gnu_arr = XALLOCAVEC (tree, len); + tree gnu_parent, gnu_rep_type; /* If all the fields have a rep clause, we can do a flat layout. */ layout_with_rep = !gnu_field_list && (!gnu_variant_part || variants_have_rep); + + /* Same as above but the extension itself has a rep clause, in which case + we need to set aside the _Parent field to lay out the REP part. */ + if (TREE_CODE (DECL_SIZE (gnu_rep_list)) != INTEGER_CST + && !layout_with_rep + && !variants_have_rep + && first_free_pos + && integer_zerop (first_free_pos) + && integer_zerop (bit_position (gnu_rep_list))) + { + gnu_parent = gnu_rep_list; + gnu_rep_list = DECL_CHAIN (gnu_rep_list); + } + else + gnu_parent = NULL_TREE; + gnu_rep_type = layout_with_rep ? gnu_record_type : make_node (RECORD_TYPE); - for (gnu_field = gnu_rep_list, i = 0; - gnu_field; - gnu_field = DECL_CHAIN (gnu_field), i++) - gnu_arr[i] = gnu_field; + /* Sort the fields in order of increasing bit position. */ + const int len = list_length (gnu_rep_list); + tree *gnu_arr = XALLOCAVEC (tree, len); + + gnu_field = gnu_rep_list; + for (int i = 0; i < len; i++) + { + gnu_arr[i] = gnu_field; + gnu_field = DECL_CHAIN (gnu_field); + } qsort (gnu_arr, len, sizeof (tree), compare_field_bitpos); - /* Put the fields in the list in order of increasing position, which - means we start from the end. */ gnu_rep_list = NULL_TREE; - for (i = len - 1; i >= 0; i--) + for (int i = len - 1; i >= 0; i--) { DECL_CHAIN (gnu_arr[i]) = gnu_rep_list; gnu_rep_list = gnu_arr[i]; DECL_CONTEXT (gnu_arr[i]) = gnu_rep_type; } + /* Do the layout of the REP part, if any. */ if (layout_with_rep) gnu_field_list = gnu_rep_list; else @@ -8378,14 +8407,36 @@ components_to_record (Node_Id gnat_component_list, Entity_Id gnat_record_type, = create_concat_name (gnat_record_type, "REP"); TYPE_REVERSE_STORAGE_ORDER (gnu_rep_type) = TYPE_REVERSE_STORAGE_ORDER (gnu_record_type); - finish_record_type (gnu_rep_type, gnu_rep_list, 1, debug_info); + finish_record_type (gnu_rep_type, gnu_rep_list, 1, false); /* If FIRST_FREE_POS is nonzero, we need to ensure that the fields without rep clause are laid out starting from this position. Therefore, we force it as a minimal size on the REP part. */ - gnu_rep_part + tree gnu_rep_part = create_rep_part (gnu_rep_type, gnu_record_type, first_free_pos); + /* If this is an extension, put back the _Parent field as the first + field of the REP part at offset 0 and update its layout. */ + if (gnu_parent) + { + const unsigned int align = DECL_ALIGN (gnu_parent); + DECL_CHAIN (gnu_parent) = TYPE_FIELDS (gnu_rep_type); + TYPE_FIELDS (gnu_rep_type) = gnu_parent; + DECL_CONTEXT (gnu_parent) = gnu_rep_type; + if (align > TYPE_ALIGN (gnu_rep_type)) + { + SET_TYPE_ALIGN (gnu_rep_type, align); + TYPE_SIZE (gnu_rep_type) + = round_up (TYPE_SIZE (gnu_rep_type), align); + TYPE_SIZE_UNIT (gnu_rep_type) + = round_up (TYPE_SIZE_UNIT (gnu_rep_type), align); + SET_DECL_ALIGN (gnu_rep_part, align); + } + } + + if (debug_info) + rest_of_record_type_compilation (gnu_rep_type); + /* Chain the REP part at the beginning of the field list. */ DECL_CHAIN (gnu_rep_part) = gnu_field_list; gnu_field_list = gnu_rep_part; diff --git a/gcc/ada/gcc-interface/utils.c b/gcc/ada/gcc-interface/utils.c index c503bfb..952f032 100644 --- a/gcc/ada/gcc-interface/utils.c +++ b/gcc/ada/gcc-interface/utils.c @@ -467,6 +467,11 @@ make_dummy_type (Entity_Id gnat_type) = create_type_stub_decl (TYPE_NAME (gnu_type), gnu_type); if (Is_By_Reference_Type (gnat_equiv)) TYPE_BY_REFERENCE_P (gnu_type) = 1; + if (Has_Discriminants (gnat_equiv)) + decl_attributes (&gnu_type, + tree_cons (get_identifier ("may_alias"), NULL_TREE, + NULL_TREE), + ATTR_FLAG_TYPE_IN_PLACE); SET_DUMMY_NODE (gnat_equiv, gnu_type); @@ -516,10 +521,10 @@ build_dummy_unc_pointer_types (Entity_Id gnat_desig_type, tree gnu_desig_type) = create_type_stub_decl (create_concat_name (gnat_desig_type, "XUP"), gnu_fat_type); fields = create_field_decl (get_identifier ("P_ARRAY"), gnu_ptr_array, - gnu_fat_type, NULL_TREE, NULL_TREE, 0, 0); + gnu_fat_type, NULL_TREE, NULL_TREE, 0, 1); DECL_CHAIN (fields) = create_field_decl (get_identifier ("P_BOUNDS"), gnu_ptr_template, - gnu_fat_type, NULL_TREE, NULL_TREE, 0, 0); + gnu_fat_type, NULL_TREE, NULL_TREE, 0, 1); finish_fat_pointer_type (gnu_fat_type, fields); SET_TYPE_UNCONSTRAINED_ARRAY (gnu_fat_type, gnu_desig_type); /* Suppress debug info until after the type is completed. */ @@ -2046,7 +2051,6 @@ finish_record_type (tree record_type, tree field_list, int rep_level, this_ada_size = this_size; const bool variant_part = (TREE_CODE (type) == QUAL_UNION_TYPE); - const bool variant_part_at_zero = variant_part && integer_zerop (pos); /* Clear DECL_BIT_FIELD for the cases layout_decl does not handle. */ if (DECL_BIT_FIELD (field) @@ -2089,7 +2093,7 @@ finish_record_type (tree record_type, tree field_list, int rep_level, /* Clear DECL_BIT_FIELD_TYPE for a variant part at offset 0, it's simply not supported by the DECL_BIT_FIELD_REPRESENTATIVE machinery because the variant part is always the last field in the list. */ - if (variant_part_at_zero) + if (variant_part && integer_zerop (pos)) DECL_BIT_FIELD_TYPE (field) = NULL_TREE; /* If we still have DECL_BIT_FIELD set at this point, we know that the @@ -2124,18 +2128,20 @@ finish_record_type (tree record_type, tree field_list, int rep_level, case RECORD_TYPE: /* Since we know here that all fields are sorted in order of increasing bit position, the size of the record is one - higher than the ending bit of the last field processed, - unless we have a variant part at offset 0, since in this - case we might have a field outside the variant part that - has a higher ending position; so use a MAX in this case. - Also, if this field is a QUAL_UNION_TYPE, we need to take - into account the previous size in the case of empty variants. */ + higher than the ending bit of the last field processed + unless we have a rep clause, because we might be processing + the REP part of a record with a variant part for which the + variant part has a rep clause but not the fixed part, in + which case this REP part may contain overlapping fields + and thus needs to be treated like a union tyoe above, so + use a MAX in that case. Also, if this field is a variant + part, we need to take into account the previous size in + the case of empty variants. */ ada_size - = merge_sizes (ada_size, pos, this_ada_size, variant_part, - variant_part_at_zero); + = merge_sizes (ada_size, pos, this_ada_size, rep_level > 0, + variant_part); size - = merge_sizes (size, pos, this_size, variant_part, - variant_part_at_zero); + = merge_sizes (size, pos, this_size, rep_level > 0, variant_part); break; default: @@ -2427,14 +2433,14 @@ rest_of_record_type_compilation (tree record_type) } /* Utility function of above to merge LAST_SIZE, the previous size of a record - with FIRST_BIT and SIZE that describe a field. SPECIAL is true if this - represents a QUAL_UNION_TYPE in which case we must look for COND_EXPRs and - replace a value of zero with the old size. If MAX is true, we take the + with FIRST_BIT and SIZE that describe a field. If MAX is true, we take the MAX of the end position of this field with LAST_SIZE. In all other cases, - we use FIRST_BIT plus SIZE. Return an expression for the size. */ + we use FIRST_BIT plus SIZE. SPECIAL is true if it's for a QUAL_UNION_TYPE, + in which case we must look for COND_EXPRs and replace a value of zero with + the old size. Return an expression for the size. */ static tree -merge_sizes (tree last_size, tree first_bit, tree size, bool special, bool max) +merge_sizes (tree last_size, tree first_bit, tree size, bool max, bool special) { tree type = TREE_TYPE (last_size); tree new_size; @@ -2451,11 +2457,11 @@ merge_sizes (tree last_size, tree first_bit, tree size, bool special, bool max) integer_zerop (TREE_OPERAND (size, 1)) ? last_size : merge_sizes (last_size, first_bit, TREE_OPERAND (size, 1), - 1, max), + max, special), integer_zerop (TREE_OPERAND (size, 2)) ? last_size : merge_sizes (last_size, first_bit, TREE_OPERAND (size, 2), - 1, max)); + max, special)); /* We don't need any NON_VALUE_EXPRs and they can confuse us (especially when fed through SUBSTITUTE_IN_EXPR) into thinking that a constant diff --git a/gcc/analyzer/ChangeLog b/gcc/analyzer/ChangeLog index 197df60..f976848 100644 --- a/gcc/analyzer/ChangeLog +++ b/gcc/analyzer/ChangeLog @@ -1,3 +1,16 @@ +2021-02-02 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/93355 + PR analyzer/96374 + * engine.cc (toplevel_function_p): Simplify so that + we only reject functions with a "__analyzer_" prefix. + (add_any_callbacks): Delete. + (exploded_graph::build_initial_worklist): Update for + dropped param of toplevel_function_p. + (exploded_graph::build_initial_worklist): Don't bother + looking for callbacks that are reachable from global + initializers. + 2021-02-01 David Malcolm <dmalcolm@redhat.com> PR analyzer/98918 diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 48e481c..b787cb9 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -240,6 +240,18 @@ BUILTIN_VQW (TERNOP, smlsl_hi, 0, NONE) BUILTIN_VQW (TERNOPU, umlsl_hi, 0, NONE) + /* Implemented by aarch64_<su>mlsl_hi_n<mode>. */ + BUILTIN_VQ_HSI (TERNOP, smlsl_hi_n, 0, NONE) + BUILTIN_VQ_HSI (TERNOPU, umlsl_hi_n, 0, NONE) + + /* Implemented by aarch64_<su>mlal_hi<mode>. */ + BUILTIN_VQW (TERNOP, smlal_hi, 0, NONE) + BUILTIN_VQW (TERNOPU, umlal_hi, 0, NONE) + + /* Implemented by aarch64_<su>mlal_hi_n<mode>. */ + BUILTIN_VQ_HSI (TERNOP, smlal_hi_n, 0, NONE) + BUILTIN_VQ_HSI (TERNOPU, umlal_hi_n, 0, NONE) + BUILTIN_VSQN_HSDI (UNOPUS, sqmovun, 0, NONE) /* Implemented by aarch64_sqxtun2<mode>. */ @@ -302,6 +314,16 @@ BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlsl_lane_, 0, NONE) BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlsl_laneq_, 0, NONE) + BUILTIN_VQ_HSI (QUADOP_LANE, smlal_hi_lane, 0, NONE) + BUILTIN_VQ_HSI (QUADOP_LANE, smlal_hi_laneq, 0, NONE) + BUILTIN_VQ_HSI (QUADOPU_LANE, umlal_hi_lane, 0, NONE) + BUILTIN_VQ_HSI (QUADOPU_LANE, umlal_hi_laneq, 0, NONE) + + BUILTIN_VQ_HSI (QUADOP_LANE, smlsl_hi_lane, 0, NONE) + BUILTIN_VQ_HSI (QUADOP_LANE, smlsl_hi_laneq, 0, NONE) + BUILTIN_VQ_HSI (QUADOPU_LANE, umlsl_hi_lane, 0, NONE) + BUILTIN_VQ_HSI (QUADOPU_LANE, umlsl_hi_laneq, 0, NONE) + BUILTIN_VSD_HSI (BINOP, sqdmull, 0, NONE) BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0, NONE) BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_laneq, 0, NONE) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 767d673..393bab1 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1976,7 +1976,7 @@ [(set_attr "type" "neon_mla_<Vetype>_long")] ) -(define_insn "*aarch64_<su>mlal_hi<mode>" +(define_insn "aarch64_<su>mlal_hi<mode>_insn" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") (plus:<VWIDE> (mult:<VWIDE> @@ -1992,6 +1992,49 @@ [(set_attr "type" "neon_mla_<Vetype>_long")] ) +(define_expand "aarch64_<su>mlal_hi<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (match_operand:<VWIDE> 1 "register_operand") + (ANY_EXTEND:<VWIDE>(match_operand:VQW 2 "register_operand")) + (match_operand:VQW 3 "register_operand")] + "TARGET_SIMD" +{ + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); + emit_insn (gen_aarch64_<su>mlal_hi<mode>_insn (operands[0], operands[1], + operands[2], p, operands[3])); + DONE; +} +) + +(define_insn "aarch64_<su>mlal_hi_n<mode>_insn" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (plus:<VWIDE> + (mult:<VWIDE> + (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> + (match_operand:VQ_HSI 2 "register_operand" "w") + (match_operand:VQ_HSI 3 "vect_par_cnst_hi_half" ""))) + (ANY_EXTEND:<VWIDE> (vec_duplicate:<VCOND> + (match_operand:<VEL> 4 "register_operand" "<h_con>")))) + (match_operand:<VWIDE> 1 "register_operand" "0")))] + "TARGET_SIMD" + "<su>mlal2\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[0]" + [(set_attr "type" "neon_mla_<Vetype>_long")] +) + +(define_expand "aarch64_<su>mlal_hi_n<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (match_operand:<VWIDE> 1 "register_operand") + (ANY_EXTEND:<VWIDE>(match_operand:VQ_HSI 2 "register_operand")) + (match_operand:<VEL> 3 "register_operand")] + "TARGET_SIMD" +{ + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); + emit_insn (gen_aarch64_<su>mlal_hi_n<mode>_insn (operands[0], + operands[1], operands[2], p, operands[3])); + DONE; +} +) + (define_insn "*aarch64_<su>mlsl_lo<mode>" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") (minus:<VWIDE> @@ -2038,6 +2081,35 @@ } ) +(define_insn "aarch64_<su>mlsl_hi_n<mode>_insn" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (minus:<VWIDE> + (match_operand:<VWIDE> 1 "register_operand" "0") + (mult:<VWIDE> + (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> + (match_operand:VQ_HSI 2 "register_operand" "w") + (match_operand:VQ_HSI 3 "vect_par_cnst_hi_half" ""))) + (ANY_EXTEND:<VWIDE> (vec_duplicate:<VCOND> + (match_operand:<VEL> 4 "register_operand" "<h_con>"))))))] + "TARGET_SIMD" + "<su>mlsl2\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[0]" + [(set_attr "type" "neon_mla_<Vetype>_long")] +) + +(define_expand "aarch64_<su>mlsl_hi_n<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (match_operand:<VWIDE> 1 "register_operand") + (ANY_EXTEND:<VWIDE>(match_operand:VQ_HSI 2 "register_operand")) + (match_operand:<VEL> 3 "register_operand")] + "TARGET_SIMD" +{ + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); + emit_insn (gen_aarch64_<su>mlsl_hi_n<mode>_insn (operands[0], + operands[1], operands[2], p, operands[3])); + DONE; +} +) + (define_insn "aarch64_<su>mlal<mode>" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") (plus:<VWIDE> @@ -2215,6 +2287,76 @@ [(set_attr "type" "neon_mla_<Vetype>_scalar_long")] ) +(define_insn "aarch64_<su>mlal_hi_lane<mode>_insn" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (plus:<VWIDE> + (mult:<VWIDE> + (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> + (match_operand:VQ_HSI 2 "register_operand" "w") + (match_operand:VQ_HSI 3 "vect_par_cnst_hi_half" ""))) + (ANY_EXTEND:<VWIDE> (vec_duplicate:<VHALF> + (vec_select:<VEL> + (match_operand:<VCOND> 4 "register_operand" "<vwx>") + (parallel [(match_operand:SI 5 "immediate_operand" "i")]))))) + (match_operand:<VWIDE> 1 "register_operand" "0")))] + "TARGET_SIMD" + { + operands[5] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[5])); + return "<su>mlal2\\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[%5]"; + } + [(set_attr "type" "neon_mla_<Vetype>_scalar_long")] +) + +(define_expand "aarch64_<su>mlal_hi_lane<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (match_operand:<VWIDE> 1 "register_operand") + (ANY_EXTEND:<VWIDE>(match_operand:VQ_HSI 2 "register_operand")) + (match_operand:<VCOND> 3 "register_operand") + (match_operand:SI 4 "immediate_operand")] + "TARGET_SIMD" +{ + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); + emit_insn (gen_aarch64_<su>mlal_hi_lane<mode>_insn (operands[0], + operands[1], operands[2], p, operands[3], operands[4])); + DONE; +} +) + +(define_insn "aarch64_<su>mlal_hi_laneq<mode>_insn" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (plus:<VWIDE> + (mult:<VWIDE> + (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> + (match_operand:VQ_HSI 2 "register_operand" "w") + (match_operand:VQ_HSI 3 "vect_par_cnst_hi_half" ""))) + (ANY_EXTEND:<VWIDE> (vec_duplicate:<VHALF> + (vec_select:<VEL> + (match_operand:<VCONQ> 4 "register_operand" "<vwx>") + (parallel [(match_operand:SI 5 "immediate_operand" "i")]))))) + (match_operand:<VWIDE> 1 "register_operand" "0")))] + "TARGET_SIMD" + { + operands[5] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[5])); + return "<su>mlal2\\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[%5]"; + } + [(set_attr "type" "neon_mla_<Vetype>_scalar_long")] +) + +(define_expand "aarch64_<su>mlal_hi_laneq<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (match_operand:<VWIDE> 1 "register_operand") + (ANY_EXTEND:<VWIDE>(match_operand:VQ_HSI 2 "register_operand")) + (match_operand:<VCONQ> 3 "register_operand") + (match_operand:SI 4 "immediate_operand")] + "TARGET_SIMD" +{ + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); + emit_insn (gen_aarch64_<su>mlal_hi_laneq<mode>_insn (operands[0], + operands[1], operands[2], p, operands[3], operands[4])); + DONE; +} +) + (define_insn "aarch64_vec_<su>mlsl_lane<Qlane>" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") (minus:<VWIDE> @@ -2235,6 +2377,78 @@ [(set_attr "type" "neon_mla_<Vetype>_scalar_long")] ) +(define_insn "aarch64_<su>mlsl_hi_lane<mode>_insn" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (minus:<VWIDE> + (match_operand:<VWIDE> 1 "register_operand" "0") + (mult:<VWIDE> + (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> + (match_operand:VQ_HSI 2 "register_operand" "w") + (match_operand:VQ_HSI 3 "vect_par_cnst_hi_half" ""))) + (ANY_EXTEND:<VWIDE> (vec_duplicate:<VHALF> + (vec_select:<VEL> + (match_operand:<VCOND> 4 "register_operand" "<vwx>") + (parallel [(match_operand:SI 5 "immediate_operand" "i")])))) + )))] + "TARGET_SIMD" + { + operands[5] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[5])); + return "<su>mlsl2\\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[%5]"; + } + [(set_attr "type" "neon_mla_<Vetype>_scalar_long")] +) + +(define_expand "aarch64_<su>mlsl_hi_lane<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (match_operand:<VWIDE> 1 "register_operand") + (ANY_EXTEND:<VWIDE>(match_operand:VQ_HSI 2 "register_operand")) + (match_operand:<VCOND> 3 "register_operand") + (match_operand:SI 4 "immediate_operand")] + "TARGET_SIMD" +{ + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); + emit_insn (gen_aarch64_<su>mlsl_hi_lane<mode>_insn (operands[0], + operands[1], operands[2], p, operands[3], operands[4])); + DONE; +} +) + +(define_insn "aarch64_<su>mlsl_hi_laneq<mode>_insn" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (minus:<VWIDE> + (match_operand:<VWIDE> 1 "register_operand" "0") + (mult:<VWIDE> + (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> + (match_operand:VQ_HSI 2 "register_operand" "w") + (match_operand:VQ_HSI 3 "vect_par_cnst_hi_half" ""))) + (ANY_EXTEND:<VWIDE> (vec_duplicate:<VHALF> + (vec_select:<VEL> + (match_operand:<VCONQ> 4 "register_operand" "<vwx>") + (parallel [(match_operand:SI 5 "immediate_operand" "i")])))) + )))] + "TARGET_SIMD" + { + operands[5] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[5])); + return "<su>mlsl2\\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[%5]"; + } + [(set_attr "type" "neon_mla_<Vetype>_scalar_long")] +) + +(define_expand "aarch64_<su>mlsl_hi_laneq<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (match_operand:<VWIDE> 1 "register_operand") + (ANY_EXTEND:<VWIDE>(match_operand:VQ_HSI 2 "register_operand")) + (match_operand:<VCONQ> 3 "register_operand") + (match_operand:SI 4 "immediate_operand")] + "TARGET_SIMD" +{ + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); + emit_insn (gen_aarch64_<su>mlsl_hi_laneq<mode>_insn (operands[0], + operands[1], operands[2], p, operands[3], operands[4])); + DONE; +} +) + ;; FP vector operations. ;; AArch64 AdvSIMD supports single-precision (32-bit) and ;; double-precision (64-bit) floating-point data types and arithmetic as diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 4b905d9..d50bd65 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -7152,236 +7152,138 @@ vmla_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c) (int32x2_t) __c); } -#define vmlal_high_lane_s16(a, b, c, d) \ - __extension__ \ - ({ \ - int16x4_t c_ = (c); \ - int16x8_t b_ = (b); \ - int32x4_t a_ = (a); \ - int32x4_t result; \ - __asm__ ("smlal2 %0.4s, %2.8h, %3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlal_high_lane_s16(int32x4_t __a, int16x8_t __b, int16x4_t __v, + const int __lane) +{ + return __builtin_aarch64_smlal_hi_lanev8hi (__a, __b, __v, __lane); +} -#define vmlal_high_lane_s32(a, b, c, d) \ - __extension__ \ - ({ \ - int32x2_t c_ = (c); \ - int32x4_t b_ = (b); \ - int64x2_t a_ = (a); \ - int64x2_t result; \ - __asm__ ("smlal2 %0.2d, %2.4s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlal_high_lane_s32(int64x2_t __a, int32x4_t __b, int32x2_t __v, + const int __lane) +{ + return __builtin_aarch64_smlal_hi_lanev4si (__a, __b, __v, __lane); +} -#define vmlal_high_lane_u16(a, b, c, d) \ - __extension__ \ - ({ \ - uint16x4_t c_ = (c); \ - uint16x8_t b_ = (b); \ - uint32x4_t a_ = (a); \ - uint32x4_t result; \ - __asm__ ("umlal2 %0.4s, %2.8h, %3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlal_high_lane_u16(uint32x4_t __a, uint16x8_t __b, uint16x4_t __v, + const int __lane) +{ + return __builtin_aarch64_umlal_hi_lanev8hi_uuuus (__a, __b, __v, __lane); +} -#define vmlal_high_lane_u32(a, b, c, d) \ - __extension__ \ - ({ \ - uint32x2_t c_ = (c); \ - uint32x4_t b_ = (b); \ - uint64x2_t a_ = (a); \ - uint64x2_t result; \ - __asm__ ("umlal2 %0.2d, %2.4s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlal_high_lane_u32(uint64x2_t __a, uint32x4_t __b, uint32x2_t __v, + const int __lane) +{ + return __builtin_aarch64_umlal_hi_lanev4si_uuuus (__a, __b, __v, __lane); +} -#define vmlal_high_laneq_s16(a, b, c, d) \ - __extension__ \ - ({ \ - int16x8_t c_ = (c); \ - int16x8_t b_ = (b); \ - int32x4_t a_ = (a); \ - int32x4_t result; \ - __asm__ ("smlal2 %0.4s, %2.8h, %3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlal_high_laneq_s16(int32x4_t __a, int16x8_t __b, int16x8_t __v, + const int __lane) +{ + return __builtin_aarch64_smlal_hi_laneqv8hi (__a, __b, __v, __lane); +} -#define vmlal_high_laneq_s32(a, b, c, d) \ - __extension__ \ - ({ \ - int32x4_t c_ = (c); \ - int32x4_t b_ = (b); \ - int64x2_t a_ = (a); \ - int64x2_t result; \ - __asm__ ("smlal2 %0.2d, %2.4s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlal_high_laneq_s32(int64x2_t __a, int32x4_t __b, int32x4_t __v, + const int __lane) +{ + return __builtin_aarch64_smlal_hi_laneqv4si (__a, __b, __v, __lane); +} -#define vmlal_high_laneq_u16(a, b, c, d) \ - __extension__ \ - ({ \ - uint16x8_t c_ = (c); \ - uint16x8_t b_ = (b); \ - uint32x4_t a_ = (a); \ - uint32x4_t result; \ - __asm__ ("umlal2 %0.4s, %2.8h, %3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlal_high_laneq_u16(uint32x4_t __a, uint16x8_t __b, uint16x8_t __v, + const int __lane) +{ + return __builtin_aarch64_umlal_hi_laneqv8hi_uuuus (__a, __b, __v, __lane); +} -#define vmlal_high_laneq_u32(a, b, c, d) \ - __extension__ \ - ({ \ - uint32x4_t c_ = (c); \ - uint32x4_t b_ = (b); \ - uint64x2_t a_ = (a); \ - uint64x2_t result; \ - __asm__ ("umlal2 %0.2d, %2.4s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlal_high_laneq_u32(uint64x2_t __a, uint32x4_t __b, uint32x4_t __v, + const int __lane) +{ + return __builtin_aarch64_umlal_hi_laneqv4si_uuuus (__a, __b, __v, __lane); +} __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c) { - int32x4_t __result; - __asm__ ("smlal2 %0.4s,%2.8h,%3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlal_hi_nv8hi (__a, __b, __c); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c) { - int64x2_t __result; - __asm__ ("smlal2 %0.2d,%2.4s,%3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlal_hi_nv4si (__a, __b, __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_high_n_u16 (uint32x4_t __a, uint16x8_t __b, uint16_t __c) { - uint32x4_t __result; - __asm__ ("umlal2 %0.4s,%2.8h,%3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlal_hi_nv8hi_uuuu (__a, __b, __c); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_high_n_u32 (uint64x2_t __a, uint32x4_t __b, uint32_t __c) { - uint64x2_t __result; - __asm__ ("umlal2 %0.2d,%2.4s,%3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlal_hi_nv4si_uuuu (__a, __b, __c); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_high_s8 (int16x8_t __a, int8x16_t __b, int8x16_t __c) { - int16x8_t __result; - __asm__ ("smlal2 %0.8h,%2.16b,%3.16b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlal_hiv16qi (__a, __b, __c); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c) { - int32x4_t __result; - __asm__ ("smlal2 %0.4s,%2.8h,%3.8h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlal_hiv8hi (__a, __b, __c); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c) { - int64x2_t __result; - __asm__ ("smlal2 %0.2d,%2.4s,%3.4s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlal_hiv4si (__a, __b, __c); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_high_u8 (uint16x8_t __a, uint8x16_t __b, uint8x16_t __c) { - uint16x8_t __result; - __asm__ ("umlal2 %0.8h,%2.16b,%3.16b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlal_hiv16qi_uuuu (__a, __b, __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_high_u16 (uint32x4_t __a, uint16x8_t __b, uint16x8_t __c) { - uint32x4_t __result; - __asm__ ("umlal2 %0.4s,%2.8h,%3.8h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlal_hiv8hi_uuuu (__a, __b, __c); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_high_u32 (uint64x2_t __a, uint32x4_t __b, uint32x4_t __c) { - uint64x2_t __result; - __asm__ ("umlal2 %0.2d,%2.4s,%3.4s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlal_hiv4si_uuuu (__a, __b, __c); } __extension__ extern __inline int32x4_t @@ -7696,164 +7598,96 @@ vmls_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c) (int32x2_t) __c); } -#define vmlsl_high_lane_s16(a, b, c, d) \ - __extension__ \ - ({ \ - int16x4_t c_ = (c); \ - int16x8_t b_ = (b); \ - int32x4_t a_ = (a); \ - int32x4_t result; \ - __asm__ ("smlsl2 %0.4s, %2.8h, %3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_high_lane_s16(int32x4_t __a, int16x8_t __b, int16x4_t __v, + const int __lane) +{ + return __builtin_aarch64_smlsl_hi_lanev8hi (__a, __b, __v, __lane); +} -#define vmlsl_high_lane_s32(a, b, c, d) \ - __extension__ \ - ({ \ - int32x2_t c_ = (c); \ - int32x4_t b_ = (b); \ - int64x2_t a_ = (a); \ - int64x2_t result; \ - __asm__ ("smlsl2 %0.2d, %2.4s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_high_lane_s32(int64x2_t __a, int32x4_t __b, int32x2_t __v, + const int __lane) +{ + return __builtin_aarch64_smlsl_hi_lanev4si (__a, __b, __v, __lane); +} -#define vmlsl_high_lane_u16(a, b, c, d) \ - __extension__ \ - ({ \ - uint16x4_t c_ = (c); \ - uint16x8_t b_ = (b); \ - uint32x4_t a_ = (a); \ - uint32x4_t result; \ - __asm__ ("umlsl2 %0.4s, %2.8h, %3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_high_lane_u16(uint32x4_t __a, uint16x8_t __b, uint16x4_t __v, + const int __lane) +{ + return __builtin_aarch64_umlsl_hi_lanev8hi_uuuus (__a, __b, __v, __lane); +} -#define vmlsl_high_lane_u32(a, b, c, d) \ - __extension__ \ - ({ \ - uint32x2_t c_ = (c); \ - uint32x4_t b_ = (b); \ - uint64x2_t a_ = (a); \ - uint64x2_t result; \ - __asm__ ("umlsl2 %0.2d, %2.4s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_high_lane_u32(uint64x2_t __a, uint32x4_t __b, uint32x2_t __v, + const int __lane) +{ + return __builtin_aarch64_umlsl_hi_lanev4si_uuuus (__a, __b, __v, __lane); +} -#define vmlsl_high_laneq_s16(a, b, c, d) \ - __extension__ \ - ({ \ - int16x8_t c_ = (c); \ - int16x8_t b_ = (b); \ - int32x4_t a_ = (a); \ - int32x4_t result; \ - __asm__ ("smlsl2 %0.4s, %2.8h, %3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_high_laneq_s16(int32x4_t __a, int16x8_t __b, int16x8_t __v, + const int __lane) +{ + return __builtin_aarch64_smlsl_hi_laneqv8hi (__a, __b, __v, __lane); +} -#define vmlsl_high_laneq_s32(a, b, c, d) \ - __extension__ \ - ({ \ - int32x4_t c_ = (c); \ - int32x4_t b_ = (b); \ - int64x2_t a_ = (a); \ - int64x2_t result; \ - __asm__ ("smlsl2 %0.2d, %2.4s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_high_laneq_s32(int64x2_t __a, int32x4_t __b, int32x4_t __v, + const int __lane) +{ + return __builtin_aarch64_smlsl_hi_laneqv4si (__a, __b, __v, __lane); +} -#define vmlsl_high_laneq_u16(a, b, c, d) \ - __extension__ \ - ({ \ - uint16x8_t c_ = (c); \ - uint16x8_t b_ = (b); \ - uint32x4_t a_ = (a); \ - uint32x4_t result; \ - __asm__ ("umlsl2 %0.4s, %2.8h, %3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_high_laneq_u16(uint32x4_t __a, uint16x8_t __b, uint16x8_t __v, + const int __lane) +{ + return __builtin_aarch64_umlsl_hi_laneqv8hi_uuuus (__a, __b, __v, __lane); +} -#define vmlsl_high_laneq_u32(a, b, c, d) \ - __extension__ \ - ({ \ - uint32x4_t c_ = (c); \ - uint32x4_t b_ = (b); \ - uint64x2_t a_ = (a); \ - uint64x2_t result; \ - __asm__ ("umlsl2 %0.2d, %2.4s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_high_laneq_u32(uint64x2_t __a, uint32x4_t __b, uint32x4_t __v, + const int __lane) +{ + return __builtin_aarch64_umlsl_hi_laneqv4si_uuuus (__a, __b, __v, __lane); +} __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c) { - int32x4_t __result; - __asm__ ("smlsl2 %0.4s, %2.8h, %3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlsl_hi_nv8hi (__a, __b, __c); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c) { - int64x2_t __result; - __asm__ ("smlsl2 %0.2d, %2.4s, %3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlsl_hi_nv4si (__a, __b, __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_high_n_u16 (uint32x4_t __a, uint16x8_t __b, uint16_t __c) { - uint32x4_t __result; - __asm__ ("umlsl2 %0.4s, %2.8h, %3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlsl_hi_nv8hi_uuuu (__a, __b, __c); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_high_n_u32 (uint64x2_t __a, uint32x4_t __b, uint32_t __c) { - uint64x2_t __result; - __asm__ ("umlsl2 %0.2d, %2.4s, %3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlsl_hi_nv4si_uuuu (__a, __b, __c); } __extension__ extern __inline int16x8_t diff --git a/gcc/config/gcn/gcn-opts.h b/gcc/config/gcn/gcn-opts.h index ed9b451..ed67d01 100644 --- a/gcc/config/gcn/gcn-opts.h +++ b/gcc/config/gcn/gcn-opts.h @@ -22,7 +22,8 @@ enum processor_type { PROCESSOR_FIJI, // gfx803 PROCESSOR_VEGA10, // gfx900 - PROCESSOR_VEGA20 // gfx906 + PROCESSOR_VEGA20, // gfx906 + PROCESSOR_GFX908 // as yet unnamed }; /* Set in gcn_option_override. */ diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c index 2351b24..e8bb0b6 100644 --- a/gcc/config/gcn/gcn.c +++ b/gcc/config/gcn/gcn.c @@ -2589,6 +2589,8 @@ gcn_omp_device_kind_arch_isa (enum omp_device_kind_arch_isa trait, return gcn_arch == PROCESSOR_VEGA10; if (strcmp (name, "gfx906") == 0) return gcn_arch == PROCESSOR_VEGA20; + if (strcmp (name, "gfx908") == 0) + return gcn_arch == PROCESSOR_GFX908; return 0; default: gcc_unreachable (); @@ -5030,6 +5032,7 @@ output_file_start (void) case PROCESSOR_FIJI: cpu = "gfx803"; break; case PROCESSOR_VEGA10: cpu = "gfx900"; break; case PROCESSOR_VEGA20: cpu = "gfx906"; break; + case PROCESSOR_GFX908: cpu = "gfx908+sram-ecc"; break; default: gcc_unreachable (); } diff --git a/gcc/config/gcn/gcn.opt b/gcc/config/gcn/gcn.opt index 7fd84f8..767d458 100644 --- a/gcc/config/gcn/gcn.opt +++ b/gcc/config/gcn/gcn.opt @@ -34,6 +34,9 @@ Enum(gpu_type) String(gfx900) Value(PROCESSOR_VEGA10) EnumValue Enum(gpu_type) String(gfx906) Value(PROCESSOR_VEGA20) +EnumValue +Enum(gpu_type) String(gfx908) Value(PROCESSOR_GFX908) + march= Target RejectNegative Joined ToLower Enum(gpu_type) Var(gcn_arch) Init(PROCESSOR_FIJI) Specify the name of the target GPU. diff --git a/gcc/config/gcn/mkoffload.c b/gcc/config/gcn/mkoffload.c index eb1c717..dc9d518 100644 --- a/gcc/config/gcn/mkoffload.c +++ b/gcc/config/gcn/mkoffload.c @@ -51,6 +51,8 @@ #define EF_AMDGPU_MACH_AMDGCN_GFX900 0x2c #undef EF_AMDGPU_MACH_AMDGCN_GFX906 #define EF_AMDGPU_MACH_AMDGCN_GFX906 0x2f +#undef EF_AMDGPU_MACH_AMDGCN_GFX908 +#define EF_AMDGPU_MACH_AMDGCN_GFX908 0x230 // Assume SRAM-ECC enabled. #ifndef R_AMDGPU_NONE #define R_AMDGPU_NONE 0 @@ -856,6 +858,8 @@ main (int argc, char **argv) elf_arch = EF_AMDGPU_MACH_AMDGCN_GFX900; else if (strcmp (argv[i], "-march=gfx906") == 0) elf_arch = EF_AMDGPU_MACH_AMDGCN_GFX906; + else if (strcmp (argv[i], "-march=gfx908") == 0) + elf_arch = EF_AMDGPU_MACH_AMDGCN_GFX908; } if (!(fopenacc ^ fopenmp)) diff --git a/gcc/config/gcn/t-gcn-hsa b/gcc/config/gcn/t-gcn-hsa index bf47da7..ee4d9b3 100644 --- a/gcc/config/gcn/t-gcn-hsa +++ b/gcc/config/gcn/t-gcn-hsa @@ -42,8 +42,8 @@ ALL_HOST_OBJS += gcn-run.o gcn-run$(exeext): gcn-run.o +$(LINKER) $(ALL_LINKERFLAGS) $(LDFLAGS) -o $@ $< -ldl -MULTILIB_OPTIONS = march=gfx900/march=gfx906 -MULTILIB_DIRNAMES = gfx900 gfx906 +MULTILIB_OPTIONS = march=gfx900/march=gfx906/march=gfx908 +MULTILIB_DIRNAMES = gfx900 gfx906 gfx908 gcn-tree.o: $(srcdir)/config/gcn/gcn-tree.c $(COMPILE) $< diff --git a/gcc/config/gcn/t-omp-device b/gcc/config/gcn/t-omp-device index d9809d5..8461c43 100644 --- a/gcc/config/gcn/t-omp-device +++ b/gcc/config/gcn/t-omp-device @@ -1,4 +1,4 @@ omp-device-properties-gcn: $(srcdir)/config/gcn/gcn.c echo kind: gpu > $@ echo arch: gcn >> $@ - echo isa: fiji gfx900 gfx906 >> $@ + echo isa: fiji gfx900 gfx906 gfx908 >> $@ diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index a6ddc71..9e5a4d1 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1528,9 +1528,9 @@ (set_attr "mode" "DI,TI,TI")]) (define_expand "<insn><mode>3" - [(set (match_operand:MMXMODE248 0 "register_operand") - (any_lshift:MMXMODE248 - (match_operand:MMXMODE248 1 "register_operand") + [(set (match_operand:MMXMODE24 0 "register_operand") + (any_lshift:MMXMODE24 + (match_operand:MMXMODE24 1 "register_operand") (match_operand:DI 2 "nonmemory_operand")))] "TARGET_MMX_WITH_SSE") diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md index 1ddbe7f..737a6da 100644 --- a/gcc/config/rs6000/fusion.md +++ b/gcc/config/rs6000/fusion.md @@ -357,2176 +357,2304 @@ ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: and op and rtl and inv 0 comp 0 -;; inner: and op and rtl and inv 0 comp 0 +;; scalar and -> and (define_insn "*fuse_and_and" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ and %3,%1,%0\;and %3,%3,%2 - and %0,%1,%0\;and %0,%0,%2 - and %1,%1,%0\;and %1,%1,%2 + and %3,%1,%0\;and %3,%3,%2 + and %3,%1,%0\;and %3,%3,%2 and %4,%1,%0\;and %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: and op and rtl and inv 0 comp 0 -;; inner: andc op andc rtl and inv 0 comp 1 +;; scalar andc -> and (define_insn "*fuse_andc_and" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ andc %3,%1,%0\;and %3,%3,%2 - andc %0,%1,%0\;and %0,%0,%2 - andc %1,%1,%0\;and %1,%1,%2 + andc %3,%1,%0\;and %3,%3,%2 + andc %3,%1,%0\;and %3,%3,%2 andc %4,%1,%0\;and %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: and op and rtl and inv 0 comp 0 -;; inner: eqv op eqv rtl xor inv 1 comp 0 +;; scalar eqv -> and (define_insn "*fuse_eqv_and" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ eqv %3,%1,%0\;and %3,%3,%2 - eqv %0,%1,%0\;and %0,%0,%2 - eqv %1,%1,%0\;and %1,%1,%2 + eqv %3,%1,%0\;and %3,%3,%2 + eqv %3,%1,%0\;and %3,%3,%2 eqv %4,%1,%0\;and %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: and op and rtl and inv 0 comp 0 -;; inner: nand op nand rtl ior inv 0 comp 3 +;; scalar nand -> and (define_insn "*fuse_nand_and" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nand %3,%1,%0\;and %3,%3,%2 - nand %0,%1,%0\;and %0,%0,%2 - nand %1,%1,%0\;and %1,%1,%2 + nand %3,%1,%0\;and %3,%3,%2 + nand %3,%1,%0\;and %3,%3,%2 nand %4,%1,%0\;and %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: and op and rtl and inv 0 comp 0 -;; inner: nor op nor rtl and inv 0 comp 3 +;; scalar nor -> and (define_insn "*fuse_nor_and" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nor %3,%1,%0\;and %3,%3,%2 - nor %0,%1,%0\;and %0,%0,%2 - nor %1,%1,%0\;and %1,%1,%2 + nor %3,%1,%0\;and %3,%3,%2 + nor %3,%1,%0\;and %3,%3,%2 nor %4,%1,%0\;and %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: and op and rtl and inv 0 comp 0 -;; inner: or op or rtl ior inv 0 comp 0 +;; scalar or -> and (define_insn "*fuse_or_and" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ or %3,%1,%0\;and %3,%3,%2 - or %0,%1,%0\;and %0,%0,%2 - or %1,%1,%0\;and %1,%1,%2 + or %3,%1,%0\;and %3,%3,%2 + or %3,%1,%0\;and %3,%3,%2 or %4,%1,%0\;and %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: and op and rtl and inv 0 comp 0 -;; inner: orc op orc rtl ior inv 0 comp 1 +;; scalar orc -> and (define_insn "*fuse_orc_and" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ orc %3,%1,%0\;and %3,%3,%2 - orc %0,%1,%0\;and %0,%0,%2 - orc %1,%1,%0\;and %1,%1,%2 + orc %3,%1,%0\;and %3,%3,%2 + orc %3,%1,%0\;and %3,%3,%2 orc %4,%1,%0\;and %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: and op and rtl and inv 0 comp 0 -;; inner: xor op xor rtl xor inv 0 comp 0 +;; scalar xor -> and (define_insn "*fuse_xor_and" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ xor %3,%1,%0\;and %3,%3,%2 - xor %0,%1,%0\;and %0,%0,%2 - xor %1,%1,%0\;and %1,%1,%2 + xor %3,%1,%0\;and %3,%3,%2 + xor %3,%1,%0\;and %3,%3,%2 xor %4,%1,%0\;and %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 -;; inner: and op and rtl and inv 0 comp 0 +;; scalar and -> andc (define_insn "*fuse_and_andc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ and %3,%1,%0\;andc %3,%3,%2 - and %0,%1,%0\;andc %0,%0,%2 - and %1,%1,%0\;andc %1,%1,%2 + and %3,%1,%0\;andc %3,%3,%2 + and %3,%1,%0\;andc %3,%3,%2 and %4,%1,%0\;andc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 -;; inner: andc op andc rtl and inv 0 comp 1 +;; scalar andc -> andc (define_insn "*fuse_andc_andc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ andc %3,%1,%0\;andc %3,%3,%2 - andc %0,%1,%0\;andc %0,%0,%2 - andc %1,%1,%0\;andc %1,%1,%2 + andc %3,%1,%0\;andc %3,%3,%2 + andc %3,%1,%0\;andc %3,%3,%2 andc %4,%1,%0\;andc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 -;; inner: eqv op eqv rtl xor inv 1 comp 0 +;; scalar eqv -> andc (define_insn "*fuse_eqv_andc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ eqv %3,%1,%0\;andc %3,%3,%2 - eqv %0,%1,%0\;andc %0,%0,%2 - eqv %1,%1,%0\;andc %1,%1,%2 + eqv %3,%1,%0\;andc %3,%3,%2 + eqv %3,%1,%0\;andc %3,%3,%2 eqv %4,%1,%0\;andc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 -;; inner: nand op nand rtl ior inv 0 comp 3 +;; scalar nand -> andc (define_insn "*fuse_nand_andc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nand %3,%1,%0\;andc %3,%3,%2 - nand %0,%1,%0\;andc %0,%0,%2 - nand %1,%1,%0\;andc %1,%1,%2 + nand %3,%1,%0\;andc %3,%3,%2 + nand %3,%1,%0\;andc %3,%3,%2 nand %4,%1,%0\;andc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 -;; inner: nor op nor rtl and inv 0 comp 3 +;; scalar nor -> andc (define_insn "*fuse_nor_andc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nor %3,%1,%0\;andc %3,%3,%2 - nor %0,%1,%0\;andc %0,%0,%2 - nor %1,%1,%0\;andc %1,%1,%2 + nor %3,%1,%0\;andc %3,%3,%2 + nor %3,%1,%0\;andc %3,%3,%2 nor %4,%1,%0\;andc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 -;; inner: or op or rtl ior inv 0 comp 0 +;; scalar or -> andc (define_insn "*fuse_or_andc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ or %3,%1,%0\;andc %3,%3,%2 - or %0,%1,%0\;andc %0,%0,%2 - or %1,%1,%0\;andc %1,%1,%2 + or %3,%1,%0\;andc %3,%3,%2 + or %3,%1,%0\;andc %3,%3,%2 or %4,%1,%0\;andc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 -;; inner: orc op orc rtl ior inv 0 comp 1 +;; scalar orc -> andc (define_insn "*fuse_orc_andc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ orc %3,%1,%0\;andc %3,%3,%2 - orc %0,%1,%0\;andc %0,%0,%2 - orc %1,%1,%0\;andc %1,%1,%2 + orc %3,%1,%0\;andc %3,%3,%2 + orc %3,%1,%0\;andc %3,%3,%2 orc %4,%1,%0\;andc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 -;; inner: xor op xor rtl xor inv 0 comp 0 +;; scalar xor -> andc (define_insn "*fuse_xor_andc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ xor %3,%1,%0\;andc %3,%3,%2 - xor %0,%1,%0\;andc %0,%0,%2 - xor %1,%1,%0\;andc %1,%1,%2 + xor %3,%1,%0\;andc %3,%3,%2 + xor %3,%1,%0\;andc %3,%3,%2 xor %4,%1,%0\;andc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 -;; inner: and op and rtl and inv 0 comp 0 +;; scalar and -> eqv (define_insn "*fuse_and_eqv" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (not:GPR (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (not:GPR (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ and %3,%1,%0\;eqv %3,%3,%2 - and %0,%1,%0\;eqv %0,%0,%2 - and %1,%1,%0\;eqv %1,%1,%2 + and %3,%1,%0\;eqv %3,%3,%2 + and %3,%1,%0\;eqv %3,%3,%2 and %4,%1,%0\;eqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 -;; inner: andc op andc rtl and inv 0 comp 1 +;; scalar andc -> eqv (define_insn "*fuse_andc_eqv" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ andc %3,%1,%0\;eqv %3,%3,%2 - andc %0,%1,%0\;eqv %0,%0,%2 - andc %1,%1,%0\;eqv %1,%1,%2 + andc %3,%1,%0\;eqv %3,%3,%2 + andc %3,%1,%0\;eqv %3,%3,%2 andc %4,%1,%0\;eqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 -;; inner: eqv op eqv rtl xor inv 1 comp 0 +;; scalar eqv -> eqv (define_insn "*fuse_eqv_eqv" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (not:GPR (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (not:GPR (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ eqv %3,%1,%0\;eqv %3,%3,%2 - eqv %0,%1,%0\;eqv %0,%0,%2 - eqv %1,%1,%0\;eqv %1,%1,%2 + eqv %3,%1,%0\;eqv %3,%3,%2 + eqv %3,%1,%0\;eqv %3,%3,%2 eqv %4,%1,%0\;eqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 -;; inner: nand op nand rtl ior inv 0 comp 3 +;; scalar nand -> eqv (define_insn "*fuse_nand_eqv" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nand %3,%1,%0\;eqv %3,%3,%2 - nand %0,%1,%0\;eqv %0,%0,%2 - nand %1,%1,%0\;eqv %1,%1,%2 + nand %3,%1,%0\;eqv %3,%3,%2 + nand %3,%1,%0\;eqv %3,%3,%2 nand %4,%1,%0\;eqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 -;; inner: nor op nor rtl and inv 0 comp 3 +;; scalar nor -> eqv (define_insn "*fuse_nor_eqv" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nor %3,%1,%0\;eqv %3,%3,%2 - nor %0,%1,%0\;eqv %0,%0,%2 - nor %1,%1,%0\;eqv %1,%1,%2 + nor %3,%1,%0\;eqv %3,%3,%2 + nor %3,%1,%0\;eqv %3,%3,%2 nor %4,%1,%0\;eqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 -;; inner: or op or rtl ior inv 0 comp 0 +;; scalar or -> eqv (define_insn "*fuse_or_eqv" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (not:GPR (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (not:GPR (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ or %3,%1,%0\;eqv %3,%3,%2 - or %0,%1,%0\;eqv %0,%0,%2 - or %1,%1,%0\;eqv %1,%1,%2 + or %3,%1,%0\;eqv %3,%3,%2 + or %3,%1,%0\;eqv %3,%3,%2 or %4,%1,%0\;eqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 -;; inner: orc op orc rtl ior inv 0 comp 1 +;; scalar orc -> eqv (define_insn "*fuse_orc_eqv" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ orc %3,%1,%0\;eqv %3,%3,%2 - orc %0,%1,%0\;eqv %0,%0,%2 - orc %1,%1,%0\;eqv %1,%1,%2 + orc %3,%1,%0\;eqv %3,%3,%2 + orc %3,%1,%0\;eqv %3,%3,%2 orc %4,%1,%0\;eqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 -;; inner: xor op xor rtl xor inv 0 comp 0 +;; scalar xor -> eqv (define_insn "*fuse_xor_eqv" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (not:GPR (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (not:GPR (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ xor %3,%1,%0\;eqv %3,%3,%2 - xor %0,%1,%0\;eqv %0,%0,%2 - xor %1,%1,%0\;eqv %1,%1,%2 + xor %3,%1,%0\;eqv %3,%3,%2 + xor %3,%1,%0\;eqv %3,%3,%2 xor %4,%1,%0\;eqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 -;; inner: and op and rtl and inv 0 comp 0 +;; scalar and -> nand (define_insn "*fuse_and_nand" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ and %3,%1,%0\;nand %3,%3,%2 - and %0,%1,%0\;nand %0,%0,%2 - and %1,%1,%0\;nand %1,%1,%2 + and %3,%1,%0\;nand %3,%3,%2 + and %3,%1,%0\;nand %3,%3,%2 and %4,%1,%0\;nand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 -;; inner: andc op andc rtl and inv 0 comp 1 +;; scalar andc -> nand (define_insn "*fuse_andc_nand" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ andc %3,%1,%0\;nand %3,%3,%2 - andc %0,%1,%0\;nand %0,%0,%2 - andc %1,%1,%0\;nand %1,%1,%2 + andc %3,%1,%0\;nand %3,%3,%2 + andc %3,%1,%0\;nand %3,%3,%2 andc %4,%1,%0\;nand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 -;; inner: eqv op eqv rtl xor inv 1 comp 0 +;; scalar eqv -> nand (define_insn "*fuse_eqv_nand" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ eqv %3,%1,%0\;nand %3,%3,%2 - eqv %0,%1,%0\;nand %0,%0,%2 - eqv %1,%1,%0\;nand %1,%1,%2 + eqv %3,%1,%0\;nand %3,%3,%2 + eqv %3,%1,%0\;nand %3,%3,%2 eqv %4,%1,%0\;nand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 -;; inner: nand op nand rtl ior inv 0 comp 3 +;; scalar nand -> nand (define_insn "*fuse_nand_nand" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nand %3,%1,%0\;nand %3,%3,%2 - nand %0,%1,%0\;nand %0,%0,%2 - nand %1,%1,%0\;nand %1,%1,%2 + nand %3,%1,%0\;nand %3,%3,%2 + nand %3,%1,%0\;nand %3,%3,%2 nand %4,%1,%0\;nand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 -;; inner: nor op nor rtl and inv 0 comp 3 +;; scalar nor -> nand (define_insn "*fuse_nor_nand" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nor %3,%1,%0\;nand %3,%3,%2 - nor %0,%1,%0\;nand %0,%0,%2 - nor %1,%1,%0\;nand %1,%1,%2 + nor %3,%1,%0\;nand %3,%3,%2 + nor %3,%1,%0\;nand %3,%3,%2 nor %4,%1,%0\;nand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 -;; inner: or op or rtl ior inv 0 comp 0 +;; scalar or -> nand (define_insn "*fuse_or_nand" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ or %3,%1,%0\;nand %3,%3,%2 - or %0,%1,%0\;nand %0,%0,%2 - or %1,%1,%0\;nand %1,%1,%2 + or %3,%1,%0\;nand %3,%3,%2 + or %3,%1,%0\;nand %3,%3,%2 or %4,%1,%0\;nand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 -;; inner: orc op orc rtl ior inv 0 comp 1 +;; scalar orc -> nand (define_insn "*fuse_orc_nand" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ orc %3,%1,%0\;nand %3,%3,%2 - orc %0,%1,%0\;nand %0,%0,%2 - orc %1,%1,%0\;nand %1,%1,%2 + orc %3,%1,%0\;nand %3,%3,%2 + orc %3,%1,%0\;nand %3,%3,%2 orc %4,%1,%0\;nand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 -;; inner: xor op xor rtl xor inv 0 comp 0 +;; scalar xor -> nand (define_insn "*fuse_xor_nand" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ xor %3,%1,%0\;nand %3,%3,%2 - xor %0,%1,%0\;nand %0,%0,%2 - xor %1,%1,%0\;nand %1,%1,%2 + xor %3,%1,%0\;nand %3,%3,%2 + xor %3,%1,%0\;nand %3,%3,%2 xor %4,%1,%0\;nand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 -;; inner: and op and rtl and inv 0 comp 0 +;; scalar and -> nor (define_insn "*fuse_and_nor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ and %3,%1,%0\;nor %3,%3,%2 - and %0,%1,%0\;nor %0,%0,%2 - and %1,%1,%0\;nor %1,%1,%2 + and %3,%1,%0\;nor %3,%3,%2 + and %3,%1,%0\;nor %3,%3,%2 and %4,%1,%0\;nor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 -;; inner: andc op andc rtl and inv 0 comp 1 +;; scalar andc -> nor (define_insn "*fuse_andc_nor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ andc %3,%1,%0\;nor %3,%3,%2 - andc %0,%1,%0\;nor %0,%0,%2 - andc %1,%1,%0\;nor %1,%1,%2 + andc %3,%1,%0\;nor %3,%3,%2 + andc %3,%1,%0\;nor %3,%3,%2 andc %4,%1,%0\;nor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 -;; inner: eqv op eqv rtl xor inv 1 comp 0 +;; scalar eqv -> nor (define_insn "*fuse_eqv_nor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ eqv %3,%1,%0\;nor %3,%3,%2 - eqv %0,%1,%0\;nor %0,%0,%2 - eqv %1,%1,%0\;nor %1,%1,%2 + eqv %3,%1,%0\;nor %3,%3,%2 + eqv %3,%1,%0\;nor %3,%3,%2 eqv %4,%1,%0\;nor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 -;; inner: nand op nand rtl ior inv 0 comp 3 +;; scalar nand -> nor (define_insn "*fuse_nand_nor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nand %3,%1,%0\;nor %3,%3,%2 - nand %0,%1,%0\;nor %0,%0,%2 - nand %1,%1,%0\;nor %1,%1,%2 + nand %3,%1,%0\;nor %3,%3,%2 + nand %3,%1,%0\;nor %3,%3,%2 nand %4,%1,%0\;nor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 -;; inner: nor op nor rtl and inv 0 comp 3 +;; scalar nor -> nor (define_insn "*fuse_nor_nor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nor %3,%1,%0\;nor %3,%3,%2 - nor %0,%1,%0\;nor %0,%0,%2 - nor %1,%1,%0\;nor %1,%1,%2 + nor %3,%1,%0\;nor %3,%3,%2 + nor %3,%1,%0\;nor %3,%3,%2 nor %4,%1,%0\;nor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 -;; inner: or op or rtl ior inv 0 comp 0 +;; scalar or -> nor (define_insn "*fuse_or_nor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ or %3,%1,%0\;nor %3,%3,%2 - or %0,%1,%0\;nor %0,%0,%2 - or %1,%1,%0\;nor %1,%1,%2 + or %3,%1,%0\;nor %3,%3,%2 + or %3,%1,%0\;nor %3,%3,%2 or %4,%1,%0\;nor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 -;; inner: orc op orc rtl ior inv 0 comp 1 +;; scalar orc -> nor (define_insn "*fuse_orc_nor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ orc %3,%1,%0\;nor %3,%3,%2 - orc %0,%1,%0\;nor %0,%0,%2 - orc %1,%1,%0\;nor %1,%1,%2 + orc %3,%1,%0\;nor %3,%3,%2 + orc %3,%1,%0\;nor %3,%3,%2 orc %4,%1,%0\;nor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 -;; inner: xor op xor rtl xor inv 0 comp 0 +;; scalar xor -> nor (define_insn "*fuse_xor_nor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ xor %3,%1,%0\;nor %3,%3,%2 - xor %0,%1,%0\;nor %0,%0,%2 - xor %1,%1,%0\;nor %1,%1,%2 + xor %3,%1,%0\;nor %3,%3,%2 + xor %3,%1,%0\;nor %3,%3,%2 xor %4,%1,%0\;nor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: or op or rtl ior inv 0 comp 0 -;; inner: and op and rtl and inv 0 comp 0 +;; scalar and -> or (define_insn "*fuse_and_or" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ and %3,%1,%0\;or %3,%3,%2 - and %0,%1,%0\;or %0,%0,%2 - and %1,%1,%0\;or %1,%1,%2 + and %3,%1,%0\;or %3,%3,%2 + and %3,%1,%0\;or %3,%3,%2 and %4,%1,%0\;or %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: or op or rtl ior inv 0 comp 0 -;; inner: andc op andc rtl and inv 0 comp 1 +;; scalar andc -> or (define_insn "*fuse_andc_or" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ andc %3,%1,%0\;or %3,%3,%2 - andc %0,%1,%0\;or %0,%0,%2 - andc %1,%1,%0\;or %1,%1,%2 + andc %3,%1,%0\;or %3,%3,%2 + andc %3,%1,%0\;or %3,%3,%2 andc %4,%1,%0\;or %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: or op or rtl ior inv 0 comp 0 -;; inner: eqv op eqv rtl xor inv 1 comp 0 +;; scalar eqv -> or (define_insn "*fuse_eqv_or" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ eqv %3,%1,%0\;or %3,%3,%2 - eqv %0,%1,%0\;or %0,%0,%2 - eqv %1,%1,%0\;or %1,%1,%2 + eqv %3,%1,%0\;or %3,%3,%2 + eqv %3,%1,%0\;or %3,%3,%2 eqv %4,%1,%0\;or %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: or op or rtl ior inv 0 comp 0 -;; inner: nand op nand rtl ior inv 0 comp 3 +;; scalar nand -> or (define_insn "*fuse_nand_or" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nand %3,%1,%0\;or %3,%3,%2 - nand %0,%1,%0\;or %0,%0,%2 - nand %1,%1,%0\;or %1,%1,%2 + nand %3,%1,%0\;or %3,%3,%2 + nand %3,%1,%0\;or %3,%3,%2 nand %4,%1,%0\;or %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: or op or rtl ior inv 0 comp 0 -;; inner: nor op nor rtl and inv 0 comp 3 +;; scalar nor -> or (define_insn "*fuse_nor_or" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nor %3,%1,%0\;or %3,%3,%2 - nor %0,%1,%0\;or %0,%0,%2 - nor %1,%1,%0\;or %1,%1,%2 + nor %3,%1,%0\;or %3,%3,%2 + nor %3,%1,%0\;or %3,%3,%2 nor %4,%1,%0\;or %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: or op or rtl ior inv 0 comp 0 -;; inner: or op or rtl ior inv 0 comp 0 +;; scalar or -> or (define_insn "*fuse_or_or" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ or %3,%1,%0\;or %3,%3,%2 - or %0,%1,%0\;or %0,%0,%2 - or %1,%1,%0\;or %1,%1,%2 + or %3,%1,%0\;or %3,%3,%2 + or %3,%1,%0\;or %3,%3,%2 or %4,%1,%0\;or %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: or op or rtl ior inv 0 comp 0 -;; inner: orc op orc rtl ior inv 0 comp 1 +;; scalar orc -> or (define_insn "*fuse_orc_or" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ orc %3,%1,%0\;or %3,%3,%2 - orc %0,%1,%0\;or %0,%0,%2 - orc %1,%1,%0\;or %1,%1,%2 + orc %3,%1,%0\;or %3,%3,%2 + orc %3,%1,%0\;or %3,%3,%2 orc %4,%1,%0\;or %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: or op or rtl ior inv 0 comp 0 -;; inner: xor op xor rtl xor inv 0 comp 0 +;; scalar xor -> or (define_insn "*fuse_xor_or" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ xor %3,%1,%0\;or %3,%3,%2 - xor %0,%1,%0\;or %0,%0,%2 - xor %1,%1,%0\;or %1,%1,%2 + xor %3,%1,%0\;or %3,%3,%2 + xor %3,%1,%0\;or %3,%3,%2 xor %4,%1,%0\;or %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 -;; inner: and op and rtl and inv 0 comp 0 +;; scalar and -> orc (define_insn "*fuse_and_orc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ and %3,%1,%0\;orc %3,%3,%2 - and %0,%1,%0\;orc %0,%0,%2 - and %1,%1,%0\;orc %1,%1,%2 + and %3,%1,%0\;orc %3,%3,%2 + and %3,%1,%0\;orc %3,%3,%2 and %4,%1,%0\;orc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 -;; inner: andc op andc rtl and inv 0 comp 1 +;; scalar andc -> orc (define_insn "*fuse_andc_orc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ andc %3,%1,%0\;orc %3,%3,%2 - andc %0,%1,%0\;orc %0,%0,%2 - andc %1,%1,%0\;orc %1,%1,%2 + andc %3,%1,%0\;orc %3,%3,%2 + andc %3,%1,%0\;orc %3,%3,%2 andc %4,%1,%0\;orc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 -;; inner: eqv op eqv rtl xor inv 1 comp 0 +;; scalar eqv -> orc (define_insn "*fuse_eqv_orc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ eqv %3,%1,%0\;orc %3,%3,%2 - eqv %0,%1,%0\;orc %0,%0,%2 - eqv %1,%1,%0\;orc %1,%1,%2 + eqv %3,%1,%0\;orc %3,%3,%2 + eqv %3,%1,%0\;orc %3,%3,%2 eqv %4,%1,%0\;orc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 -;; inner: nand op nand rtl ior inv 0 comp 3 +;; scalar nand -> orc (define_insn "*fuse_nand_orc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nand %3,%1,%0\;orc %3,%3,%2 - nand %0,%1,%0\;orc %0,%0,%2 - nand %1,%1,%0\;orc %1,%1,%2 + nand %3,%1,%0\;orc %3,%3,%2 + nand %3,%1,%0\;orc %3,%3,%2 nand %4,%1,%0\;orc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 -;; inner: nor op nor rtl and inv 0 comp 3 +;; scalar nor -> orc (define_insn "*fuse_nor_orc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nor %3,%1,%0\;orc %3,%3,%2 - nor %0,%1,%0\;orc %0,%0,%2 - nor %1,%1,%0\;orc %1,%1,%2 + nor %3,%1,%0\;orc %3,%3,%2 + nor %3,%1,%0\;orc %3,%3,%2 nor %4,%1,%0\;orc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 -;; inner: or op or rtl ior inv 0 comp 0 +;; scalar or -> orc (define_insn "*fuse_or_orc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ or %3,%1,%0\;orc %3,%3,%2 - or %0,%1,%0\;orc %0,%0,%2 - or %1,%1,%0\;orc %1,%1,%2 + or %3,%1,%0\;orc %3,%3,%2 + or %3,%1,%0\;orc %3,%3,%2 or %4,%1,%0\;orc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 -;; inner: orc op orc rtl ior inv 0 comp 1 +;; scalar orc -> orc (define_insn "*fuse_orc_orc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ orc %3,%1,%0\;orc %3,%3,%2 - orc %0,%1,%0\;orc %0,%0,%2 - orc %1,%1,%0\;orc %1,%1,%2 + orc %3,%1,%0\;orc %3,%3,%2 + orc %3,%1,%0\;orc %3,%3,%2 orc %4,%1,%0\;orc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 -;; inner: xor op xor rtl xor inv 0 comp 0 +;; scalar xor -> orc (define_insn "*fuse_xor_orc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ xor %3,%1,%0\;orc %3,%3,%2 - xor %0,%1,%0\;orc %0,%0,%2 - xor %1,%1,%0\;orc %1,%1,%2 + xor %3,%1,%0\;orc %3,%3,%2 + xor %3,%1,%0\;orc %3,%3,%2 xor %4,%1,%0\;orc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 -;; inner: and op and rtl and inv 0 comp 0 +;; scalar and -> xor (define_insn "*fuse_and_xor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ and %3,%1,%0\;xor %3,%3,%2 - and %0,%1,%0\;xor %0,%0,%2 - and %1,%1,%0\;xor %1,%1,%2 + and %3,%1,%0\;xor %3,%3,%2 + and %3,%1,%0\;xor %3,%3,%2 and %4,%1,%0\;xor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 -;; inner: andc op andc rtl and inv 0 comp 1 +;; scalar andc -> xor (define_insn "*fuse_andc_xor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ andc %3,%1,%0\;xor %3,%3,%2 - andc %0,%1,%0\;xor %0,%0,%2 - andc %1,%1,%0\;xor %1,%1,%2 + andc %3,%1,%0\;xor %3,%3,%2 + andc %3,%1,%0\;xor %3,%3,%2 andc %4,%1,%0\;xor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 -;; inner: eqv op eqv rtl xor inv 1 comp 0 +;; scalar eqv -> xor (define_insn "*fuse_eqv_xor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ eqv %3,%1,%0\;xor %3,%3,%2 - eqv %0,%1,%0\;xor %0,%0,%2 - eqv %1,%1,%0\;xor %1,%1,%2 + eqv %3,%1,%0\;xor %3,%3,%2 + eqv %3,%1,%0\;xor %3,%3,%2 eqv %4,%1,%0\;xor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 -;; inner: nand op nand rtl ior inv 0 comp 3 +;; scalar nand -> xor (define_insn "*fuse_nand_xor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nand %3,%1,%0\;xor %3,%3,%2 - nand %0,%1,%0\;xor %0,%0,%2 - nand %1,%1,%0\;xor %1,%1,%2 + nand %3,%1,%0\;xor %3,%3,%2 + nand %3,%1,%0\;xor %3,%3,%2 nand %4,%1,%0\;xor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 -;; inner: nor op nor rtl and inv 0 comp 3 +;; scalar nor -> xor (define_insn "*fuse_nor_xor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nor %3,%1,%0\;xor %3,%3,%2 - nor %0,%1,%0\;xor %0,%0,%2 - nor %1,%1,%0\;xor %1,%1,%2 + nor %3,%1,%0\;xor %3,%3,%2 + nor %3,%1,%0\;xor %3,%3,%2 nor %4,%1,%0\;xor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 -;; inner: or op or rtl ior inv 0 comp 0 +;; scalar or -> xor (define_insn "*fuse_or_xor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ or %3,%1,%0\;xor %3,%3,%2 - or %0,%1,%0\;xor %0,%0,%2 - or %1,%1,%0\;xor %1,%1,%2 + or %3,%1,%0\;xor %3,%3,%2 + or %3,%1,%0\;xor %3,%3,%2 or %4,%1,%0\;xor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 -;; inner: orc op orc rtl ior inv 0 comp 1 +;; scalar orc -> xor (define_insn "*fuse_orc_xor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ orc %3,%1,%0\;xor %3,%3,%2 - orc %0,%1,%0\;xor %0,%0,%2 - orc %1,%1,%0\;xor %1,%1,%2 + orc %3,%1,%0\;xor %3,%3,%2 + orc %3,%1,%0\;xor %3,%3,%2 orc %4,%1,%0\;xor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 -;; inner: xor op xor rtl xor inv 0 comp 0 +;; scalar xor -> xor (define_insn "*fuse_xor_xor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ xor %3,%1,%0\;xor %3,%3,%2 - xor %0,%1,%0\;xor %0,%0,%2 - xor %1,%1,%0\;xor %1,%1,%2 + xor %3,%1,%0\;xor %3,%3,%2 + xor %3,%1,%0\;xor %3,%3,%2 xor %4,%1,%0\;xor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: and op vand rtl and inv 0 comp 0 -;; inner: and op vand rtl and inv 0 comp 0 +;; vector vand -> vand (define_insn "*fuse_vand_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vand %3,%1,%0\;vand %3,%3,%2 - vand %0,%1,%0\;vand %0,%0,%2 - vand %1,%1,%0\;vand %1,%1,%2 + vand %3,%1,%0\;vand %3,%3,%2 + vand %3,%1,%0\;vand %3,%3,%2 vand %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: and op vand rtl and inv 0 comp 0 -;; inner: andc op vandc rtl and inv 0 comp 1 +;; vector vandc -> vand (define_insn "*fuse_vandc_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vandc %3,%1,%0\;vand %3,%3,%2 - vandc %0,%1,%0\;vand %0,%0,%2 - vandc %1,%1,%0\;vand %1,%1,%2 + vandc %3,%1,%0\;vand %3,%3,%2 + vandc %3,%1,%0\;vand %3,%3,%2 vandc %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: and op vand rtl and inv 0 comp 0 -;; inner: eqv op veqv rtl xor inv 1 comp 0 +;; vector veqv -> vand (define_insn "*fuse_veqv_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ veqv %3,%1,%0\;vand %3,%3,%2 - veqv %0,%1,%0\;vand %0,%0,%2 - veqv %1,%1,%0\;vand %1,%1,%2 + veqv %3,%1,%0\;vand %3,%3,%2 + veqv %3,%1,%0\;vand %3,%3,%2 veqv %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: and op vand rtl and inv 0 comp 0 -;; inner: nand op vnand rtl ior inv 0 comp 3 +;; vector vnand -> vand (define_insn "*fuse_vnand_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnand %3,%1,%0\;vand %3,%3,%2 - vnand %0,%1,%0\;vand %0,%0,%2 - vnand %1,%1,%0\;vand %1,%1,%2 + vnand %3,%1,%0\;vand %3,%3,%2 + vnand %3,%1,%0\;vand %3,%3,%2 vnand %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: and op vand rtl and inv 0 comp 0 -;; inner: nor op vnor rtl and inv 0 comp 3 +;; vector vnor -> vand (define_insn "*fuse_vnor_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnor %3,%1,%0\;vand %3,%3,%2 - vnor %0,%1,%0\;vand %0,%0,%2 - vnor %1,%1,%0\;vand %1,%1,%2 + vnor %3,%1,%0\;vand %3,%3,%2 + vnor %3,%1,%0\;vand %3,%3,%2 vnor %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: and op vand rtl and inv 0 comp 0 -;; inner: or op vor rtl ior inv 0 comp 0 +;; vector vor -> vand (define_insn "*fuse_vor_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vor %3,%1,%0\;vand %3,%3,%2 - vor %0,%1,%0\;vand %0,%0,%2 - vor %1,%1,%0\;vand %1,%1,%2 + vor %3,%1,%0\;vand %3,%3,%2 + vor %3,%1,%0\;vand %3,%3,%2 vor %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: and op vand rtl and inv 0 comp 0 -;; inner: orc op vorc rtl ior inv 0 comp 1 +;; vector vorc -> vand (define_insn "*fuse_vorc_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vorc %3,%1,%0\;vand %3,%3,%2 - vorc %0,%1,%0\;vand %0,%0,%2 - vorc %1,%1,%0\;vand %1,%1,%2 + vorc %3,%1,%0\;vand %3,%3,%2 + vorc %3,%1,%0\;vand %3,%3,%2 vorc %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: and op vand rtl and inv 0 comp 0 -;; inner: xor op vxor rtl xor inv 0 comp 0 +;; vector vxor -> vand (define_insn "*fuse_vxor_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vxor %3,%1,%0\;vand %3,%3,%2 - vxor %0,%1,%0\;vand %0,%0,%2 - vxor %1,%1,%0\;vand %1,%1,%2 + vxor %3,%1,%0\;vand %3,%3,%2 + vxor %3,%1,%0\;vand %3,%3,%2 vxor %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 -;; inner: and op vand rtl and inv 0 comp 0 +;; vector vand -> vandc (define_insn "*fuse_vand_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vand %3,%1,%0\;vandc %3,%3,%2 - vand %0,%1,%0\;vandc %0,%0,%2 - vand %1,%1,%0\;vandc %1,%1,%2 + vand %3,%1,%0\;vandc %3,%3,%2 + vand %3,%1,%0\;vandc %3,%3,%2 vand %4,%1,%0\;vandc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 -;; inner: andc op vandc rtl and inv 0 comp 1 +;; vector vandc -> vandc (define_insn "*fuse_vandc_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vandc %3,%1,%0\;vandc %3,%3,%2 - vandc %0,%1,%0\;vandc %0,%0,%2 - vandc %1,%1,%0\;vandc %1,%1,%2 + vandc %3,%1,%0\;vandc %3,%3,%2 + vandc %3,%1,%0\;vandc %3,%3,%2 vandc %4,%1,%0\;vandc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 -;; inner: eqv op veqv rtl xor inv 1 comp 0 +;; vector veqv -> vandc (define_insn "*fuse_veqv_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ veqv %3,%1,%0\;vandc %3,%3,%2 - veqv %0,%1,%0\;vandc %0,%0,%2 - veqv %1,%1,%0\;vandc %1,%1,%2 + veqv %3,%1,%0\;vandc %3,%3,%2 + veqv %3,%1,%0\;vandc %3,%3,%2 veqv %4,%1,%0\;vandc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 -;; inner: nand op vnand rtl ior inv 0 comp 3 +;; vector vnand -> vandc (define_insn "*fuse_vnand_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnand %3,%1,%0\;vandc %3,%3,%2 - vnand %0,%1,%0\;vandc %0,%0,%2 - vnand %1,%1,%0\;vandc %1,%1,%2 + vnand %3,%1,%0\;vandc %3,%3,%2 + vnand %3,%1,%0\;vandc %3,%3,%2 vnand %4,%1,%0\;vandc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 -;; inner: nor op vnor rtl and inv 0 comp 3 +;; vector vnor -> vandc (define_insn "*fuse_vnor_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnor %3,%1,%0\;vandc %3,%3,%2 - vnor %0,%1,%0\;vandc %0,%0,%2 - vnor %1,%1,%0\;vandc %1,%1,%2 + vnor %3,%1,%0\;vandc %3,%3,%2 + vnor %3,%1,%0\;vandc %3,%3,%2 vnor %4,%1,%0\;vandc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 -;; inner: or op vor rtl ior inv 0 comp 0 +;; vector vor -> vandc (define_insn "*fuse_vor_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vor %3,%1,%0\;vandc %3,%3,%2 - vor %0,%1,%0\;vandc %0,%0,%2 - vor %1,%1,%0\;vandc %1,%1,%2 + vor %3,%1,%0\;vandc %3,%3,%2 + vor %3,%1,%0\;vandc %3,%3,%2 vor %4,%1,%0\;vandc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 -;; inner: orc op vorc rtl ior inv 0 comp 1 +;; vector vorc -> vandc (define_insn "*fuse_vorc_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vorc %3,%1,%0\;vandc %3,%3,%2 - vorc %0,%1,%0\;vandc %0,%0,%2 - vorc %1,%1,%0\;vandc %1,%1,%2 + vorc %3,%1,%0\;vandc %3,%3,%2 + vorc %3,%1,%0\;vandc %3,%3,%2 vorc %4,%1,%0\;vandc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 -;; inner: xor op vxor rtl xor inv 0 comp 0 +;; vector vxor -> vandc (define_insn "*fuse_vxor_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vxor %3,%1,%0\;vandc %3,%3,%2 - vxor %0,%1,%0\;vandc %0,%0,%2 - vxor %1,%1,%0\;vandc %1,%1,%2 + vxor %3,%1,%0\;vandc %3,%3,%2 + vxor %3,%1,%0\;vandc %3,%3,%2 vxor %4,%1,%0\;vandc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 -;; inner: and op vand rtl and inv 0 comp 0 +;; vector vand -> veqv (define_insn "*fuse_vand_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (not:VM (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (not:VM (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vand %3,%1,%0\;veqv %3,%3,%2 - vand %0,%1,%0\;veqv %0,%0,%2 - vand %1,%1,%0\;veqv %1,%1,%2 + vand %3,%1,%0\;veqv %3,%3,%2 + vand %3,%1,%0\;veqv %3,%3,%2 vand %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 -;; inner: andc op vandc rtl and inv 0 comp 1 +;; vector vandc -> veqv (define_insn "*fuse_vandc_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vandc %3,%1,%0\;veqv %3,%3,%2 - vandc %0,%1,%0\;veqv %0,%0,%2 - vandc %1,%1,%0\;veqv %1,%1,%2 + vandc %3,%1,%0\;veqv %3,%3,%2 + vandc %3,%1,%0\;veqv %3,%3,%2 vandc %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 -;; inner: eqv op veqv rtl xor inv 1 comp 0 +;; vector veqv -> veqv (define_insn "*fuse_veqv_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (not:VM (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (not:VM (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ veqv %3,%1,%0\;veqv %3,%3,%2 - veqv %0,%1,%0\;veqv %0,%0,%2 - veqv %1,%1,%0\;veqv %1,%1,%2 + veqv %3,%1,%0\;veqv %3,%3,%2 + veqv %3,%1,%0\;veqv %3,%3,%2 veqv %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 -;; inner: nand op vnand rtl ior inv 0 comp 3 +;; vector vnand -> veqv (define_insn "*fuse_vnand_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnand %3,%1,%0\;veqv %3,%3,%2 - vnand %0,%1,%0\;veqv %0,%0,%2 - vnand %1,%1,%0\;veqv %1,%1,%2 + vnand %3,%1,%0\;veqv %3,%3,%2 + vnand %3,%1,%0\;veqv %3,%3,%2 vnand %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 -;; inner: nor op vnor rtl and inv 0 comp 3 +;; vector vnor -> veqv (define_insn "*fuse_vnor_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnor %3,%1,%0\;veqv %3,%3,%2 - vnor %0,%1,%0\;veqv %0,%0,%2 - vnor %1,%1,%0\;veqv %1,%1,%2 + vnor %3,%1,%0\;veqv %3,%3,%2 + vnor %3,%1,%0\;veqv %3,%3,%2 vnor %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 -;; inner: or op vor rtl ior inv 0 comp 0 +;; vector vor -> veqv (define_insn "*fuse_vor_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (not:VM (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (not:VM (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vor %3,%1,%0\;veqv %3,%3,%2 - vor %0,%1,%0\;veqv %0,%0,%2 - vor %1,%1,%0\;veqv %1,%1,%2 + vor %3,%1,%0\;veqv %3,%3,%2 + vor %3,%1,%0\;veqv %3,%3,%2 vor %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 -;; inner: orc op vorc rtl ior inv 0 comp 1 +;; vector vorc -> veqv (define_insn "*fuse_vorc_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vorc %3,%1,%0\;veqv %3,%3,%2 - vorc %0,%1,%0\;veqv %0,%0,%2 - vorc %1,%1,%0\;veqv %1,%1,%2 + vorc %3,%1,%0\;veqv %3,%3,%2 + vorc %3,%1,%0\;veqv %3,%3,%2 vorc %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 -;; inner: xor op vxor rtl xor inv 0 comp 0 +;; vector vxor -> veqv (define_insn "*fuse_vxor_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (not:VM (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (not:VM (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vxor %3,%1,%0\;veqv %3,%3,%2 - vxor %0,%1,%0\;veqv %0,%0,%2 - vxor %1,%1,%0\;veqv %1,%1,%2 + vxor %3,%1,%0\;veqv %3,%3,%2 + vxor %3,%1,%0\;veqv %3,%3,%2 vxor %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 -;; inner: and op vand rtl and inv 0 comp 0 +;; vector vand -> vnand (define_insn "*fuse_vand_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vand %3,%1,%0\;vnand %3,%3,%2 - vand %0,%1,%0\;vnand %0,%0,%2 - vand %1,%1,%0\;vnand %1,%1,%2 + vand %3,%1,%0\;vnand %3,%3,%2 + vand %3,%1,%0\;vnand %3,%3,%2 vand %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 -;; inner: andc op vandc rtl and inv 0 comp 1 +;; vector vandc -> vnand (define_insn "*fuse_vandc_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vandc %3,%1,%0\;vnand %3,%3,%2 - vandc %0,%1,%0\;vnand %0,%0,%2 - vandc %1,%1,%0\;vnand %1,%1,%2 + vandc %3,%1,%0\;vnand %3,%3,%2 + vandc %3,%1,%0\;vnand %3,%3,%2 vandc %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 -;; inner: eqv op veqv rtl xor inv 1 comp 0 +;; vector veqv -> vnand (define_insn "*fuse_veqv_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ veqv %3,%1,%0\;vnand %3,%3,%2 - veqv %0,%1,%0\;vnand %0,%0,%2 - veqv %1,%1,%0\;vnand %1,%1,%2 + veqv %3,%1,%0\;vnand %3,%3,%2 + veqv %3,%1,%0\;vnand %3,%3,%2 veqv %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 -;; inner: nand op vnand rtl ior inv 0 comp 3 +;; vector vnand -> vnand (define_insn "*fuse_vnand_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnand %3,%1,%0\;vnand %3,%3,%2 - vnand %0,%1,%0\;vnand %0,%0,%2 - vnand %1,%1,%0\;vnand %1,%1,%2 + vnand %3,%1,%0\;vnand %3,%3,%2 + vnand %3,%1,%0\;vnand %3,%3,%2 vnand %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 -;; inner: nor op vnor rtl and inv 0 comp 3 +;; vector vnor -> vnand (define_insn "*fuse_vnor_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnor %3,%1,%0\;vnand %3,%3,%2 - vnor %0,%1,%0\;vnand %0,%0,%2 - vnor %1,%1,%0\;vnand %1,%1,%2 + vnor %3,%1,%0\;vnand %3,%3,%2 + vnor %3,%1,%0\;vnand %3,%3,%2 vnor %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 -;; inner: or op vor rtl ior inv 0 comp 0 +;; vector vor -> vnand (define_insn "*fuse_vor_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vor %3,%1,%0\;vnand %3,%3,%2 - vor %0,%1,%0\;vnand %0,%0,%2 - vor %1,%1,%0\;vnand %1,%1,%2 + vor %3,%1,%0\;vnand %3,%3,%2 + vor %3,%1,%0\;vnand %3,%3,%2 vor %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 -;; inner: orc op vorc rtl ior inv 0 comp 1 +;; vector vorc -> vnand (define_insn "*fuse_vorc_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vorc %3,%1,%0\;vnand %3,%3,%2 - vorc %0,%1,%0\;vnand %0,%0,%2 - vorc %1,%1,%0\;vnand %1,%1,%2 + vorc %3,%1,%0\;vnand %3,%3,%2 + vorc %3,%1,%0\;vnand %3,%3,%2 vorc %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 -;; inner: xor op vxor rtl xor inv 0 comp 0 +;; vector vxor -> vnand (define_insn "*fuse_vxor_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vxor %3,%1,%0\;vnand %3,%3,%2 - vxor %0,%1,%0\;vnand %0,%0,%2 - vxor %1,%1,%0\;vnand %1,%1,%2 + vxor %3,%1,%0\;vnand %3,%3,%2 + vxor %3,%1,%0\;vnand %3,%3,%2 vxor %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 -;; inner: and op vand rtl and inv 0 comp 0 +;; vector vand -> vnor (define_insn "*fuse_vand_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vand %3,%1,%0\;vnor %3,%3,%2 - vand %0,%1,%0\;vnor %0,%0,%2 - vand %1,%1,%0\;vnor %1,%1,%2 + vand %3,%1,%0\;vnor %3,%3,%2 + vand %3,%1,%0\;vnor %3,%3,%2 vand %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 -;; inner: andc op vandc rtl and inv 0 comp 1 +;; vector vandc -> vnor (define_insn "*fuse_vandc_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vandc %3,%1,%0\;vnor %3,%3,%2 - vandc %0,%1,%0\;vnor %0,%0,%2 - vandc %1,%1,%0\;vnor %1,%1,%2 + vandc %3,%1,%0\;vnor %3,%3,%2 + vandc %3,%1,%0\;vnor %3,%3,%2 vandc %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 -;; inner: eqv op veqv rtl xor inv 1 comp 0 +;; vector veqv -> vnor (define_insn "*fuse_veqv_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ veqv %3,%1,%0\;vnor %3,%3,%2 - veqv %0,%1,%0\;vnor %0,%0,%2 - veqv %1,%1,%0\;vnor %1,%1,%2 + veqv %3,%1,%0\;vnor %3,%3,%2 + veqv %3,%1,%0\;vnor %3,%3,%2 veqv %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 -;; inner: nand op vnand rtl ior inv 0 comp 3 +;; vector vnand -> vnor (define_insn "*fuse_vnand_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnand %3,%1,%0\;vnor %3,%3,%2 - vnand %0,%1,%0\;vnor %0,%0,%2 - vnand %1,%1,%0\;vnor %1,%1,%2 + vnand %3,%1,%0\;vnor %3,%3,%2 + vnand %3,%1,%0\;vnor %3,%3,%2 vnand %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 -;; inner: nor op vnor rtl and inv 0 comp 3 +;; vector vnor -> vnor (define_insn "*fuse_vnor_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnor %3,%1,%0\;vnor %3,%3,%2 - vnor %0,%1,%0\;vnor %0,%0,%2 - vnor %1,%1,%0\;vnor %1,%1,%2 + vnor %3,%1,%0\;vnor %3,%3,%2 + vnor %3,%1,%0\;vnor %3,%3,%2 vnor %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 -;; inner: or op vor rtl ior inv 0 comp 0 +;; vector vor -> vnor (define_insn "*fuse_vor_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vor %3,%1,%0\;vnor %3,%3,%2 - vor %0,%1,%0\;vnor %0,%0,%2 - vor %1,%1,%0\;vnor %1,%1,%2 + vor %3,%1,%0\;vnor %3,%3,%2 + vor %3,%1,%0\;vnor %3,%3,%2 vor %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 -;; inner: orc op vorc rtl ior inv 0 comp 1 +;; vector vorc -> vnor (define_insn "*fuse_vorc_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vorc %3,%1,%0\;vnor %3,%3,%2 - vorc %0,%1,%0\;vnor %0,%0,%2 - vorc %1,%1,%0\;vnor %1,%1,%2 + vorc %3,%1,%0\;vnor %3,%3,%2 + vorc %3,%1,%0\;vnor %3,%3,%2 vorc %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 -;; inner: xor op vxor rtl xor inv 0 comp 0 +;; vector vxor -> vnor (define_insn "*fuse_vxor_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vxor %3,%1,%0\;vnor %3,%3,%2 - vxor %0,%1,%0\;vnor %0,%0,%2 - vxor %1,%1,%0\;vnor %1,%1,%2 + vxor %3,%1,%0\;vnor %3,%3,%2 + vxor %3,%1,%0\;vnor %3,%3,%2 vxor %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: or op vor rtl ior inv 0 comp 0 -;; inner: and op vand rtl and inv 0 comp 0 +;; vector vand -> vor (define_insn "*fuse_vand_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vand %3,%1,%0\;vor %3,%3,%2 - vand %0,%1,%0\;vor %0,%0,%2 - vand %1,%1,%0\;vor %1,%1,%2 + vand %3,%1,%0\;vor %3,%3,%2 + vand %3,%1,%0\;vor %3,%3,%2 vand %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: or op vor rtl ior inv 0 comp 0 -;; inner: andc op vandc rtl and inv 0 comp 1 +;; vector vandc -> vor (define_insn "*fuse_vandc_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vandc %3,%1,%0\;vor %3,%3,%2 - vandc %0,%1,%0\;vor %0,%0,%2 - vandc %1,%1,%0\;vor %1,%1,%2 + vandc %3,%1,%0\;vor %3,%3,%2 + vandc %3,%1,%0\;vor %3,%3,%2 vandc %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: or op vor rtl ior inv 0 comp 0 -;; inner: eqv op veqv rtl xor inv 1 comp 0 +;; vector veqv -> vor (define_insn "*fuse_veqv_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ veqv %3,%1,%0\;vor %3,%3,%2 - veqv %0,%1,%0\;vor %0,%0,%2 - veqv %1,%1,%0\;vor %1,%1,%2 + veqv %3,%1,%0\;vor %3,%3,%2 + veqv %3,%1,%0\;vor %3,%3,%2 veqv %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: or op vor rtl ior inv 0 comp 0 -;; inner: nand op vnand rtl ior inv 0 comp 3 +;; vector vnand -> vor (define_insn "*fuse_vnand_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnand %3,%1,%0\;vor %3,%3,%2 - vnand %0,%1,%0\;vor %0,%0,%2 - vnand %1,%1,%0\;vor %1,%1,%2 + vnand %3,%1,%0\;vor %3,%3,%2 + vnand %3,%1,%0\;vor %3,%3,%2 vnand %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: or op vor rtl ior inv 0 comp 0 -;; inner: nor op vnor rtl and inv 0 comp 3 +;; vector vnor -> vor (define_insn "*fuse_vnor_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnor %3,%1,%0\;vor %3,%3,%2 - vnor %0,%1,%0\;vor %0,%0,%2 - vnor %1,%1,%0\;vor %1,%1,%2 + vnor %3,%1,%0\;vor %3,%3,%2 + vnor %3,%1,%0\;vor %3,%3,%2 vnor %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: or op vor rtl ior inv 0 comp 0 -;; inner: or op vor rtl ior inv 0 comp 0 +;; vector vor -> vor (define_insn "*fuse_vor_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vor %3,%1,%0\;vor %3,%3,%2 - vor %0,%1,%0\;vor %0,%0,%2 - vor %1,%1,%0\;vor %1,%1,%2 + vor %3,%1,%0\;vor %3,%3,%2 + vor %3,%1,%0\;vor %3,%3,%2 vor %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: or op vor rtl ior inv 0 comp 0 -;; inner: orc op vorc rtl ior inv 0 comp 1 +;; vector vorc -> vor (define_insn "*fuse_vorc_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vorc %3,%1,%0\;vor %3,%3,%2 - vorc %0,%1,%0\;vor %0,%0,%2 - vorc %1,%1,%0\;vor %1,%1,%2 + vorc %3,%1,%0\;vor %3,%3,%2 + vorc %3,%1,%0\;vor %3,%3,%2 vorc %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: or op vor rtl ior inv 0 comp 0 -;; inner: xor op vxor rtl xor inv 0 comp 0 +;; vector vxor -> vor (define_insn "*fuse_vxor_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vxor %3,%1,%0\;vor %3,%3,%2 - vxor %0,%1,%0\;vor %0,%0,%2 - vxor %1,%1,%0\;vor %1,%1,%2 + vxor %3,%1,%0\;vor %3,%3,%2 + vxor %3,%1,%0\;vor %3,%3,%2 vxor %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 -;; inner: and op vand rtl and inv 0 comp 0 +;; vector vand -> vorc (define_insn "*fuse_vand_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vand %3,%1,%0\;vorc %3,%3,%2 - vand %0,%1,%0\;vorc %0,%0,%2 - vand %1,%1,%0\;vorc %1,%1,%2 + vand %3,%1,%0\;vorc %3,%3,%2 + vand %3,%1,%0\;vorc %3,%3,%2 vand %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 -;; inner: andc op vandc rtl and inv 0 comp 1 +;; vector vandc -> vorc (define_insn "*fuse_vandc_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vandc %3,%1,%0\;vorc %3,%3,%2 - vandc %0,%1,%0\;vorc %0,%0,%2 - vandc %1,%1,%0\;vorc %1,%1,%2 + vandc %3,%1,%0\;vorc %3,%3,%2 + vandc %3,%1,%0\;vorc %3,%3,%2 vandc %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 -;; inner: eqv op veqv rtl xor inv 1 comp 0 +;; vector veqv -> vorc (define_insn "*fuse_veqv_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ veqv %3,%1,%0\;vorc %3,%3,%2 - veqv %0,%1,%0\;vorc %0,%0,%2 - veqv %1,%1,%0\;vorc %1,%1,%2 + veqv %3,%1,%0\;vorc %3,%3,%2 + veqv %3,%1,%0\;vorc %3,%3,%2 veqv %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 -;; inner: nand op vnand rtl ior inv 0 comp 3 +;; vector vnand -> vorc (define_insn "*fuse_vnand_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnand %3,%1,%0\;vorc %3,%3,%2 - vnand %0,%1,%0\;vorc %0,%0,%2 - vnand %1,%1,%0\;vorc %1,%1,%2 + vnand %3,%1,%0\;vorc %3,%3,%2 + vnand %3,%1,%0\;vorc %3,%3,%2 vnand %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 -;; inner: nor op vnor rtl and inv 0 comp 3 +;; vector vnor -> vorc (define_insn "*fuse_vnor_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnor %3,%1,%0\;vorc %3,%3,%2 - vnor %0,%1,%0\;vorc %0,%0,%2 - vnor %1,%1,%0\;vorc %1,%1,%2 + vnor %3,%1,%0\;vorc %3,%3,%2 + vnor %3,%1,%0\;vorc %3,%3,%2 vnor %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 -;; inner: or op vor rtl ior inv 0 comp 0 +;; vector vor -> vorc (define_insn "*fuse_vor_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vor %3,%1,%0\;vorc %3,%3,%2 - vor %0,%1,%0\;vorc %0,%0,%2 - vor %1,%1,%0\;vorc %1,%1,%2 + vor %3,%1,%0\;vorc %3,%3,%2 + vor %3,%1,%0\;vorc %3,%3,%2 vor %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 -;; inner: orc op vorc rtl ior inv 0 comp 1 +;; vector vorc -> vorc (define_insn "*fuse_vorc_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vorc %3,%1,%0\;vorc %3,%3,%2 - vorc %0,%1,%0\;vorc %0,%0,%2 - vorc %1,%1,%0\;vorc %1,%1,%2 + vorc %3,%1,%0\;vorc %3,%3,%2 + vorc %3,%1,%0\;vorc %3,%3,%2 vorc %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 -;; inner: xor op vxor rtl xor inv 0 comp 0 +;; vector vxor -> vorc (define_insn "*fuse_vxor_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vxor %3,%1,%0\;vorc %3,%3,%2 - vxor %0,%1,%0\;vorc %0,%0,%2 - vxor %1,%1,%0\;vorc %1,%1,%2 + vxor %3,%1,%0\;vorc %3,%3,%2 + vxor %3,%1,%0\;vorc %3,%3,%2 vxor %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 -;; inner: and op vand rtl and inv 0 comp 0 +;; vector vand -> vxor (define_insn "*fuse_vand_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vand %3,%1,%0\;vxor %3,%3,%2 - vand %0,%1,%0\;vxor %0,%0,%2 - vand %1,%1,%0\;vxor %1,%1,%2 + vand %3,%1,%0\;vxor %3,%3,%2 + vand %3,%1,%0\;vxor %3,%3,%2 vand %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 -;; inner: andc op vandc rtl and inv 0 comp 1 +;; vector vandc -> vxor (define_insn "*fuse_vandc_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vandc %3,%1,%0\;vxor %3,%3,%2 - vandc %0,%1,%0\;vxor %0,%0,%2 - vandc %1,%1,%0\;vxor %1,%1,%2 + vandc %3,%1,%0\;vxor %3,%3,%2 + vandc %3,%1,%0\;vxor %3,%3,%2 vandc %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 -;; inner: eqv op veqv rtl xor inv 1 comp 0 +;; vector veqv -> vxor (define_insn "*fuse_veqv_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ veqv %3,%1,%0\;vxor %3,%3,%2 - veqv %0,%1,%0\;vxor %0,%0,%2 - veqv %1,%1,%0\;vxor %1,%1,%2 + veqv %3,%1,%0\;vxor %3,%3,%2 + veqv %3,%1,%0\;vxor %3,%3,%2 veqv %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 -;; inner: nand op vnand rtl ior inv 0 comp 3 +;; vector vnand -> vxor (define_insn "*fuse_vnand_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnand %3,%1,%0\;vxor %3,%3,%2 - vnand %0,%1,%0\;vxor %0,%0,%2 - vnand %1,%1,%0\;vxor %1,%1,%2 + vnand %3,%1,%0\;vxor %3,%3,%2 + vnand %3,%1,%0\;vxor %3,%3,%2 vnand %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 -;; inner: nor op vnor rtl and inv 0 comp 3 +;; vector vnor -> vxor (define_insn "*fuse_vnor_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnor %3,%1,%0\;vxor %3,%3,%2 - vnor %0,%1,%0\;vxor %0,%0,%2 - vnor %1,%1,%0\;vxor %1,%1,%2 + vnor %3,%1,%0\;vxor %3,%3,%2 + vnor %3,%1,%0\;vxor %3,%3,%2 vnor %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 -;; inner: or op vor rtl ior inv 0 comp 0 +;; vector vor -> vxor (define_insn "*fuse_vor_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vor %3,%1,%0\;vxor %3,%3,%2 - vor %0,%1,%0\;vxor %0,%0,%2 - vor %1,%1,%0\;vxor %1,%1,%2 + vor %3,%1,%0\;vxor %3,%3,%2 + vor %3,%1,%0\;vxor %3,%3,%2 vor %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 -;; inner: orc op vorc rtl ior inv 0 comp 1 +;; vector vorc -> vxor (define_insn "*fuse_vorc_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vorc %3,%1,%0\;vxor %3,%3,%2 - vorc %0,%1,%0\;vxor %0,%0,%2 - vorc %1,%1,%0\;vxor %1,%1,%2 + vorc %3,%1,%0\;vxor %3,%3,%2 + vorc %3,%1,%0\;vxor %3,%3,%2 vorc %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 -;; inner: xor op vxor rtl xor inv 0 comp 0 +;; vector vxor -> vxor (define_insn "*fuse_vxor_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vxor %3,%1,%0\;vxor %3,%3,%2 - vxor %0,%1,%0\;vxor %0,%0,%2 - vxor %1,%1,%0\;vxor %1,%1,%2 + vxor %3,%1,%0\;vxor %3,%3,%2 + vxor %3,%1,%0\;vxor %3,%3,%2 vxor %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl index 837af7a..e1c45f5 100755 --- a/gcc/config/rs6000/genfusion.pl +++ b/gcc/config/rs6000/genfusion.pl @@ -192,7 +192,8 @@ sub gen_2logical if ( ($inner_comp & 2) == 2 ) { $inner_arg1 = "(not:${mode} $inner_arg1)"; } - $inner_exp = "(${inner_rtl}:${mode} ${inner_arg0} ${inner_arg1})"; + $inner_exp = "(${inner_rtl}:${mode} ${inner_arg0} + ${inner_arg1})"; if ( $inner_inv == 1 ) { $inner_exp = "(not:${mode} $inner_exp)"; } @@ -203,7 +204,8 @@ sub gen_2logical if ( ($outer_comp & 2) == 2 ) { $inner_exp = "(not:${mode} $inner_exp)"; } - $outer_exp = "(${outer_rtl}:${mode} ${inner_exp} ${outer_arg2})"; + $outer_exp = "(${outer_rtl}:${mode} ${inner_exp} + ${outer_arg2})"; if ( $outer_inv == 1 ) { $outer_exp = "(not:${mode} $outer_exp)"; } @@ -211,17 +213,16 @@ sub gen_2logical $insn = <<"EOF"; ;; logical-logical fusion pattern generated by gen_2logical -;; kind: $kind outer: $outer op $outer_op rtl $outer_rtl inv $outer_inv comp $outer_comp -;; inner: $inner op $inner_op rtl $inner_rtl inv $inner_inv comp $inner_comp +;; $kind $inner_op -> $outer_op (define_insn "*fuse_${inner_op}_${outer_op}" - [(set (match_operand:${mode} 3 "${pred}" "=&${constraint},0,1,${constraint}") + [(set (match_operand:${mode} 3 "${pred}" "=0,1,&${constraint},${constraint}") ${outer_exp}) - (clobber (match_scratch:${mode} 4 "=X,X,X,r"))] + (clobber (match_scratch:${mode} 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2 - ${inner_op} %0,%1,%0\\;${outer_op} %0,%0,%2 - ${inner_op} %1,%1,%0\\;${outer_op} %1,%1,%2 + ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2 + ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2 ${inner_op} %4,%1,%0\\;${outer_op} %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") diff --git a/gcc/config/rs6000/t-rs6000 b/gcc/config/rs6000/t-rs6000 index e3a58bf..1541a65 100644 --- a/gcc/config/rs6000/t-rs6000 +++ b/gcc/config/rs6000/t-rs6000 @@ -47,8 +47,8 @@ rs6000-call.o: $(srcdir)/config/rs6000/rs6000-call.c $(COMPILE) $< $(POSTCOMPILE) -$(srcdir)/config/rs6000/fusion.md: $(srcdir)/config/rs6000/genfusion.pl - $(srcdir)/config/rs6000/genfusion.pl > $(srcdir)/config/rs6000/fusion.md +#$(srcdir)/config/rs6000/fusion.md: $(srcdir)/config/rs6000/genfusion.pl +# $(srcdir)/config/rs6000/genfusion.pl > $(srcdir)/config/rs6000/fusion.md $(srcdir)/config/rs6000/rs6000-tables.opt: $(srcdir)/config/rs6000/genopt.sh \ $(srcdir)/config/rs6000/rs6000-cpus.def diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index bac41f1..de69476 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,10 @@ +2021-02-02 Jason Merrill <jason@redhat.com> + + PR c++/98929 + PR c++/96199 + * error.c (dump_expr): Ignore dummy object. + * pt.c (tsubst_baselink): Handle dependent scope. + 2021-02-01 Patrick Palka <ppalka@redhat.com> PR c++/98295 diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c index abadaf9..5da8670 100644 --- a/gcc/cp/parser.c +++ b/gcc/cp/parser.c @@ -25026,8 +25026,8 @@ cp_parser_class_specifier_1 (cp_parser* parser) pushed_scope = push_scope (class_type); } - tree spec = TYPE_RAISES_EXCEPTIONS (TREE_TYPE (decl)); - spec = TREE_PURPOSE (spec); + tree def_parse = TYPE_RAISES_EXCEPTIONS (TREE_TYPE (decl)); + def_parse = TREE_PURPOSE (def_parse); /* Make sure that any template parameters are in scope. */ maybe_begin_member_template_processing (decl); @@ -25044,7 +25044,7 @@ cp_parser_class_specifier_1 (cp_parser* parser) parser->local_variables_forbidden_p |= THIS_FORBIDDEN; /* Now we can parse the noexcept-specifier. */ - spec = cp_parser_late_noexcept_specifier (parser, spec); + tree spec = cp_parser_late_noexcept_specifier (parser, def_parse); if (spec == error_mark_node) spec = NULL_TREE; @@ -25052,6 +25052,12 @@ cp_parser_class_specifier_1 (cp_parser* parser) /* Update the fn's type directly -- it might have escaped beyond this decl :( */ fixup_deferred_exception_variants (TREE_TYPE (decl), spec); + /* Update any instantiations we've already created. We must + keep the new noexcept-specifier wrapped in a DEFERRED_NOEXCEPT + so that maybe_instantiate_noexcept can tsubst the NOEXCEPT_EXPR + in the pattern. */ + for (tree i : DEFPARSE_INSTANTIATIONS (def_parse)) + DEFERRED_NOEXCEPT_PATTERN (TREE_PURPOSE (i)) = TREE_PURPOSE (spec); /* Restore the state of local_variables_forbidden_p. */ parser->local_variables_forbidden_p = local_variables_forbidden_p; @@ -26695,6 +26701,7 @@ cp_parser_save_noexcept (cp_parser *parser) /* Save away the noexcept-specifier; we will process it when the class is complete. */ DEFPARSE_TOKENS (expr) = cp_token_cache_new (first, last); + DEFPARSE_INSTANTIATIONS (expr) = nullptr; expr = build_tree_list (expr, NULL_TREE); return expr; } diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index aa1687a..4781519 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -15189,6 +15189,22 @@ tsubst_exception_specification (tree fntype, /*integral_constant_expression_p=*/true); } new_specs = build_noexcept_spec (new_specs, complain); + /* We've instantiated a template before a noexcept-specifier + contained therein has been parsed. This can happen for + a nested template class: + + struct S { + template<typename> struct B { B() noexcept(...); }; + struct A : B<int> { ... use B() ... }; + }; + + where completing B<int> will trigger instantiating the + noexcept, even though we only parse it at the end of S. */ + if (UNPARSED_NOEXCEPT_SPEC_P (specs)) + { + gcc_checking_assert (defer_ok); + vec_safe_push (DEFPARSE_INSTANTIATIONS (expr), new_specs); + } } else if (specs) { diff --git a/gcc/cp/tree.c b/gcc/cp/tree.c index 2e5a1f1..e6ced27 100644 --- a/gcc/cp/tree.c +++ b/gcc/cp/tree.c @@ -2738,8 +2738,7 @@ fixup_deferred_exception_variants (tree type, tree raises) tree original = TYPE_RAISES_EXCEPTIONS (type); tree cr = flag_noexcept_type ? canonical_eh_spec (raises) : NULL_TREE; - gcc_checking_assert (TREE_CODE (TREE_PURPOSE (original)) - == DEFERRED_PARSE); + gcc_checking_assert (UNPARSED_NOEXCEPT_SPEC_P (original)); /* Though sucky, this walk will process the canonical variants first. */ diff --git a/gcc/d/ChangeLog b/gcc/d/ChangeLog index 83dfb28..354f65f 100644 --- a/gcc/d/ChangeLog +++ b/gcc/d/ChangeLog @@ -1,3 +1,8 @@ +2021-02-02 Iain Buclaw <ibuclaw@gdcproject.org> + + PR d/98921 + * dmd/MERGE: Merge upstream dmd 5e2a81d9c. + 2021-01-30 Iain Buclaw <ibuclaw@gdcproject.org> * typeinfo.cc (TypeInfoVisitor::visit (TypeInfoDeclaration *)): Don't diff --git a/gcc/fortran/dependency.c b/gcc/fortran/dependency.c index c9baca8..5de3b2c 100644 --- a/gcc/fortran/dependency.c +++ b/gcc/fortran/dependency.c @@ -30,6 +30,7 @@ along with GCC; see the file COPYING3. If not see #include "dependency.h" #include "constructor.h" #include "arith.h" +#include "options.h" /* static declarations */ /* Enums */ @@ -2142,9 +2143,17 @@ gfc_dep_resolver (gfc_ref *lref, gfc_ref *rref, gfc_reverse *reverse, return (fin_dep == GFC_DEP_OVERLAP) ? 1 : 0; case REF_ARRAY: - - /* For now, treat all coarrays as dangerous. */ - if (lref->u.ar.codimen || rref->u.ar.codimen) + /* Coarrays: If there is a coindex, either the image differs and there + is no overlap or the image is the same - then the normal analysis + applies. Hence, return early only if 'identical' is required and + either ref is coindexed and more than one image can exist. */ + if (identical && flag_coarray != GFC_FCOARRAY_SINGLE + && ((lref->u.ar.codimen + && lref->u.ar.dimen_type[lref->u.ar.dimen] + != DIMEN_THIS_IMAGE) + || (rref->u.ar.codimen + && lref->u.ar.dimen_type[lref->u.ar.dimen] + != DIMEN_THIS_IMAGE))) return 1; if (ref_same_as_full_array (lref, rref)) diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index cb12c83a..905c6fe 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -271a043537f2f0ae93bde2cf4f4897e68a476ece +78770fd9c29037dec8b2919c0f02067915c6ad33 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c index 1480a94a..b467eb5 100644 --- a/gcc/ifcvt.c +++ b/gcc/ifcvt.c @@ -885,6 +885,60 @@ noce_emit_store_flag (struct noce_if_info *if_info, rtx x, int reversep, || code == GEU || code == GTU), normalize); } +/* Return true if X can be safely forced into a register by copy_to_mode_reg + / force_operand. */ + +static bool +noce_can_force_operand (rtx x) +{ + if (general_operand (x, VOIDmode)) + return true; + if (SUBREG_P (x)) + { + if (!noce_can_force_operand (SUBREG_REG (x))) + return false; + return true; + } + if (ARITHMETIC_P (x)) + { + if (!noce_can_force_operand (XEXP (x, 0)) + || !noce_can_force_operand (XEXP (x, 1))) + return false; + switch (GET_CODE (x)) + { + case MULT: + case DIV: + case MOD: + case UDIV: + case UMOD: + return true; + default: + return code_to_optab (GET_CODE (x)); + } + } + if (UNARY_P (x)) + { + if (!noce_can_force_operand (XEXP (x, 0))) + return false; + switch (GET_CODE (x)) + { + case ZERO_EXTEND: + case SIGN_EXTEND: + case TRUNCATE: + case FLOAT_EXTEND: + case FLOAT_TRUNCATE: + case FIX: + case UNSIGNED_FIX: + case FLOAT: + case UNSIGNED_FLOAT: + return true; + default: + return code_to_optab (GET_CODE (x)); + } + } + return false; +} + /* Emit instruction to move an rtx, possibly into STRICT_LOW_PART. X is the destination/target and Y is the value to copy. */ @@ -943,7 +997,7 @@ noce_emit_move_insn (rtx x, rtx y) { case RTX_UNARY: ot = code_to_optab (GET_CODE (y)); - if (ot) + if (ot && noce_can_force_operand (XEXP (y, 0))) { start_sequence (); target = expand_unop (GET_MODE (y), ot, XEXP (y, 0), x, 0); @@ -960,7 +1014,9 @@ noce_emit_move_insn (rtx x, rtx y) case RTX_BIN_ARITH: case RTX_COMM_ARITH: ot = code_to_optab (GET_CODE (y)); - if (ot) + if (ot + && noce_can_force_operand (XEXP (y, 0)) + && noce_can_force_operand (XEXP (y, 1))) { start_sequence (); target = expand_binop (GET_MODE (y), ot, @@ -2763,15 +2819,18 @@ noce_try_sign_mask (struct noce_if_info *if_info) INSN_B which can happen for e.g. conditional stores to memory. For the cost computation use the block TEST_BB where the evaluation will end up after the transformation. */ - t_unconditional = - (t == if_info->b - && (if_info->insn_b == NULL_RTX - || BLOCK_FOR_INSN (if_info->insn_b) == if_info->test_bb)); + t_unconditional + = (t == if_info->b + && (if_info->insn_b == NULL_RTX + || BLOCK_FOR_INSN (if_info->insn_b) == if_info->test_bb)); if (!(t_unconditional || (set_src_cost (t, mode, if_info->speed_p) < COSTS_N_INSNS (2)))) return FALSE; + if (!noce_can_force_operand (t)) + return FALSE; + start_sequence (); /* Use emit_store_flag to generate "m < 0 ? -1 : 0" instead of expanding "(signed) m >> 31" directly. This benefits targets with specialized diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c index e739a46..6a5aa41 100644 --- a/gcc/lra-constraints.c +++ b/gcc/lra-constraints.c @@ -3106,8 +3106,13 @@ process_alt_operands (int only_alternative) && operand_reg[j] != NULL_RTX && HARD_REGISTER_P (operand_reg[j]) && REG_USERVAR_P (operand_reg[j])) - fatal_insn ("unable to generate reloads for " - "impossible constraints:", curr_insn); + { + /* For asm, let curr_insn_transform diagnose it. */ + if (INSN_CODE (curr_insn) < 0) + return false; + fatal_insn ("unable to generate reloads for " + "impossible constraints:", curr_insn); + } } if (last_conflict_j < 0) continue; diff --git a/gcc/lra-spills.c b/gcc/lra-spills.c index 26f56b2..01bd825 100644 --- a/gcc/lra-spills.c +++ b/gcc/lra-spills.c @@ -431,7 +431,7 @@ remove_pseudos (rtx *loc, rtx_insn *insn) alter_subreg (loc, false); if (GET_CODE (*loc) == MEM) { - lra_get_insn_recog_data (insn)->used_insn_alternative = -1; + lra_update_insn_recog_data (insn); if (lra_dump_file != NULL) fprintf (lra_dump_file, "Memory subreg was simplified in insn #%u\n", diff --git a/gcc/lto-streamer-out.c b/gcc/lto-streamer-out.c index 405f3bf..a26d488 100644 --- a/gcc/lto-streamer-out.c +++ b/gcc/lto-streamer-out.c @@ -2670,7 +2670,7 @@ produce_lto_section () bool slim_object = flag_generate_lto && !flag_fat_lto_objects; lto_section s - = { LTO_major_version, LTO_minor_version, slim_object, 0 }; + = { LTO_major_version, LTO_minor_version, slim_object, 0, 0 }; s.set_compression (compression); lto_write_data (&s, sizeof s); lto_end_section (); diff --git a/gcc/lto-streamer.c b/gcc/lto-streamer.c index 36e6735..84db5eb 100644 --- a/gcc/lto-streamer.c +++ b/gcc/lto-streamer.c @@ -106,6 +106,7 @@ lto_get_section_name (int section_type, const char *name, const char *add; char post[32]; const char *sep; + char *buffer = NULL; if (section_type == LTO_section_function_body) { @@ -113,7 +114,7 @@ lto_get_section_name (int section_type, const char *name, if (name[0] == '*') name++; - char *buffer = (char *)xmalloc (strlen (name) + 32); + buffer = (char *)xmalloc (strlen (name) + 32); sprintf (buffer, "%s.%d", name, node_order); add = buffer; @@ -138,7 +139,10 @@ lto_get_section_name (int section_type, const char *name, sprintf (post, "." HOST_WIDE_INT_PRINT_HEX_PURE, f->id); else sprintf (post, "." HOST_WIDE_INT_PRINT_HEX_PURE, get_random_seed (false)); - return concat (section_name_prefix, sep, add, post, NULL); + char *res = concat (section_name_prefix, sep, add, post, NULL); + if (buffer) + free (buffer); + return res; } diff --git a/gcc/lto-streamer.h b/gcc/lto-streamer.h index 7736ae7..5c7cd84 100644 --- a/gcc/lto-streamer.h +++ b/gcc/lto-streamer.h @@ -369,6 +369,7 @@ struct lto_section int16_t major_version; int16_t minor_version; unsigned char slim_object; + unsigned char _padding; /* Flags is a private field that is not defined publicly. */ uint16_t flags; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0614da1..a0c6e73 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,73 @@ +2021-02-02 Martin Liska <mliska@suse.cz> + + PR target/97510 + * gcc.target/i386/pr97510.c: New test. + +2021-02-02 Jason Merrill <jason@redhat.com> + + PR c++/98929 + * g++.dg/cpp1z/class-deduction-decltype1.C: New test. + +2021-02-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * gcc.target/aarch64/narrow_high-intrinsics.c: Adjust sqxtun2 scan. + +2021-02-02 Paul Thomas <pault@gcc.gnu.org> + + PR fortran/91862 + * gfortran.dg/pr91862.f90: New test. + +2021-02-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * gcc.target/aarch64/arg-type-diagnostics-1.c: Return result from foo. + +2021-02-02 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/98848 + * gcc.dg/vect/pr98848.c: New test. + * gcc.dg/vect/pr92205.c: Remove xfail. + +2021-02-02 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/97960 + * g++.dg/torture/pr97960.C: New test. + +2021-02-02 Kito Cheng <kito.cheng@sifive.com> + + PR target/98743 + * g++.dg/opt/pr98743.C: New. + +2021-02-02 Christophe Lyon <christophe.lyon@linaro.org> + + * gcc.target/arm/simd/mve-vorn.c: Add vorn tests. + +2021-02-02 Alexandre Oliva <oliva@adacore.com> + + * gcc.dg/asan/nested-1.c: New. + +2021-02-02 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/93355 + PR analyzer/96374 + * gcc.dg/analyzer/conditionals-3.c: Add "__analyzer_" + prefix to support subroutines where necessary. + * gcc.dg/analyzer/data-model-1.c: Likewise. + * gcc.dg/analyzer/feasibility-1.c (called_by_test_6a): New. + (test_6a): New. + * gcc.dg/analyzer/params.c: Add "__analyzer_" prefix to support + subroutines where necessary. + * gcc.dg/analyzer/pr96651-2.c: Likewise. + * gcc.dg/analyzer/signal-4b.c: Likewise. + * gcc.dg/analyzer/single-field.c: Likewise. + * gcc.dg/analyzer/torture/conditionals-2.c: Likewise. + +2021-02-02 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/93355 + PR analyzer/96374 + * gcc.dg/analyzer/pr93355-localealias-feasibility-2.c: New test. + * gcc.dg/analyzer/pr93355-localealias-feasibility-3.c: New test. + 2021-02-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * gcc.target/aarch64/narrow_high-intrinsics.c: Adjust rshrn2 diff --git a/gcc/testsuite/g++.dg/cpp0x/noexcept65.C b/gcc/testsuite/g++.dg/cpp0x/noexcept65.C new file mode 100644 index 0000000..f593377 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/noexcept65.C @@ -0,0 +1,35 @@ +// PR c++/98899 +// { dg-do compile { target c++11 } } + +template <int __v> struct integral_constant { + static constexpr int value = __v; +}; + +struct S { + template<class> struct B { + B() noexcept(noexcept(x)); + int x; + }; + struct A : B<int> { + A() : B() {} + }; +}; + +struct S2 { + template<class> struct B { + B() noexcept(integral_constant<false>::value); + }; + struct A : B<int> { + A() : B() {} + }; +}; + +struct S3 { + template<class> struct B { + B() noexcept(b); + }; + struct A : B<int> { + A() : B() {} + }; + static constexpr bool b = false; +}; diff --git a/gcc/testsuite/g++.dg/cpp2a/no_unique_address11.C b/gcc/testsuite/g++.dg/cpp2a/no_unique_address11.C new file mode 100644 index 0000000..9ca6184 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp2a/no_unique_address11.C @@ -0,0 +1,18 @@ +// PR c++/97804 +// { dg-do compile { target c++17 } } + +template <typename a> struct b { + constexpr b() : c() {} + [[no_unique_address]] a c; +}; +template <unsigned long, typename...> struct d; +template <unsigned long e, typename a, typename... f> +struct d<e, a, f...> : d<1, f...>, b<a> {}; +template <unsigned long e, typename a> struct d<e, a> : b<a> {}; +template <typename... g> class h : d<0, g...> {}; +struct i {}; +class j { + using k = int; + h<k, i> l; + float m = 0.025f; +} n; diff --git a/gcc/testsuite/gcc.dg/pr97487-1.c b/gcc/testsuite/gcc.dg/pr97487-1.c new file mode 100644 index 0000000..e79d1f1 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr97487-1.c @@ -0,0 +1,9 @@ +/* PR middle-end/97487 */ +/* { dg-do compile } */ +/* { dg-options "-O2 --param max-rtl-if-conversion-unpredictable-cost=0" } */ + +long int __attribute__ ((simd)) +foo (long int x, long int y) +{ + return x < 0 ? y : 0; +} diff --git a/gcc/testsuite/gcc.dg/pr97487-2.c b/gcc/testsuite/gcc.dg/pr97487-2.c new file mode 100644 index 0000000..0b62381 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr97487-2.c @@ -0,0 +1,18 @@ +/* PR middle-end/97487 */ +/* { dg-do compile } */ +/* { dg-options "-O2 --param max-rtl-if-conversion-unpredictable-cost=0 -Wno-psabi -w" } */ + +typedef long long int V __attribute__((vector_size (16))); + +long long int +foo (V x, V y) +{ + long long int t1 = y[0]; + long long int t2 = x[0]; + long long int t3; + if (t2 < 0) + t3 = t1; + else + t3 = 0; + return t3; +} diff --git a/gcc/testsuite/gcc.dg/pr98287.c b/gcc/testsuite/gcc.dg/pr98287.c new file mode 100644 index 0000000..0314428 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr98287.c @@ -0,0 +1,19 @@ +/* PR tree-optimization/98287 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-tree-ccp -fno-tree-forwprop -Wno-psabi -w" } */ + +typedef unsigned long __attribute__((__vector_size__ (8))) V; +V v; + +static __attribute__((noinline, noclone)) V +bar (unsigned short s) +{ + return v >> s << s | v >> s >> 63; +} + +unsigned long +foo (void) +{ + V x = bar (1); + return x[0]; +} diff --git a/gcc/testsuite/gcc.target/i386/pr97971.c b/gcc/testsuite/gcc.target/i386/pr97971.c new file mode 100644 index 0000000..d07a310 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr97971.c @@ -0,0 +1,12 @@ +/* PR middle-end/97971 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int +foo (void) +{ + register _Complex long a asm ("rax"); + register int b asm ("rdx"); + asm ("# %0 %1" : "=&r" (a), "=r" (b)); /* { dg-error "inconsistent operand constraints in an 'asm'" } */ + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/pr98928.c b/gcc/testsuite/gcc.target/i386/pr98928.c new file mode 100644 index 0000000..9503b57 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr98928.c @@ -0,0 +1,59 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-Ofast -march=skylake-avx512 -fwhole-program -w" } */ + +typedef float MagickRealType; +typedef short Quantum; +float InterpolateMagickPixelPacket_alpha[1]; +int InterpolateMagickPixelPacket_i; + +void InterpolateMagickPixelPacket(); + +void main() { InterpolateMagickPixelPacket(); } + +typedef struct { + MagickRealType red, green, blue, opacity, index; +} MagickPixelPacket; +typedef struct { + Quantum blue, green, red, opacity; +} PixelPacket; +struct _Image { + int colorspace; + int matte; +} GetMagickPixelPacket(MagickPixelPacket *pixel) { + pixel->red = pixel->green = pixel->blue = 0.0; +} +int AlphaBlendMagickPixelPacket(struct _Image *image, PixelPacket *color, + Quantum *indexes, MagickPixelPacket *pixel, + MagickRealType *alpha) { + if (image->matte) { + *alpha = pixel->red = pixel->green = pixel->blue = pixel->opacity = + color->opacity; + pixel->index = 0.0; + if (image->colorspace) + pixel->index = *indexes; + return 0; + } + *alpha = 1.0 / 0.2; + pixel->red = *alpha * color->red; + pixel->green = *alpha * color->green; + pixel->blue = *alpha * color->blue; + pixel->opacity = pixel->index = 0.0; + if (image->colorspace && indexes) + pixel->index = *indexes; +} +MagickPixelPacket InterpolateMagickPixelPacket_pixels[1]; +PixelPacket InterpolateMagickPixelPacket_p; + +void +InterpolateMagickPixelPacket(struct _Image *image) { + Quantum *indexes; + for (; InterpolateMagickPixelPacket_i; InterpolateMagickPixelPacket_i++) { + GetMagickPixelPacket(InterpolateMagickPixelPacket_pixels + + InterpolateMagickPixelPacket_i); + AlphaBlendMagickPixelPacket( + image, &InterpolateMagickPixelPacket_p + InterpolateMagickPixelPacket_i, + indexes + InterpolateMagickPixelPacket_i, + InterpolateMagickPixelPacket_pixels + InterpolateMagickPixelPacket_i, + InterpolateMagickPixelPacket_alpha + InterpolateMagickPixelPacket_i); + } +} diff --git a/gcc/testsuite/gfortran.dg/coarray/array_temporary.f90 b/gcc/testsuite/gfortran.dg/coarray/array_temporary.f90 new file mode 100644 index 0000000..86460a7 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/coarray/array_temporary.f90 @@ -0,0 +1,74 @@ +! { dg-do compile } +! { dg-additional-options "-Warray-temporaries" } +! +! PR fortran/98913 +! +! Contributed by Jorge D'Elia +! +! Did create an array temporary for local access to coarray +! (but not for identical noncoarray use). +! + +program test + implicit none + integer, parameter :: iin = kind (1) + integer, parameter :: idp = kind (1.0d0) + real (kind=idp), allocatable :: AA (:,:)[:] + real (kind=idp), allocatable :: BB (:,:) + real (kind=idp), allocatable :: UU (:) + integer (kind=iin) :: nn, n1, n2 + integer (kind=iin) :: j, k, k1 + ! + nn = 5 + n1 = 1 + n2 = 10 + ! + allocate (AA (1:nn,n1:n2)[*]) + allocate (BB (1:nn,n1:n2)) + allocate (UU (1:nn)) + ! + k = 1 + k1 = k + 1 + ! + AA = 1.0_idp + BB = 1.0_idp + UU = 2.0_idp + + ! AA - coarrays + ! No temporary needed: + do j = 1, nn + AA (k1:nn,j) = AA (k1:nn,j) - UU (k1:nn) * AA (k,j) ! { dg-bogus "Creating array temporary" } + end do + do j = 1, nn + AA (k1:nn,j) = AA (k1:nn,j) - UU (k1:nn) * AA (k,j) - UU(k) * AA (k1-1:nn-1,j) ! { dg-bogus "Creating array temporary" } + end do + do j = 1, nn + AA (k1:nn,j) = AA (k1:nn,j) - UU (k1:nn) * AA (k,j) - UU(k) * AA (k1+1:nn+1,j) ! { dg-bogus "Creating array temporary" } + end do + + ! But: + do j = 1, nn + AA (k1:nn,j) = AA (k1-1:nn-1,j) - UU (k1:nn) * AA (k,j) - UU(k) * AA (k1+1:nn+1,j) ! { dg-warning "Creating array temporary" } + end do + + ! BB - no coarrays + ! No temporary needed: + do j = 1, nn + BB (k1:nn,j) = BB (k1:nn,j) - UU (k1:nn) * BB (k,j) ! { dg-bogus "Creating array temporary" } + end do + do j = 1, nn + BB (k1:nn,j) = BB (k1:nn,j) - UU (k1:nn) * BB (k,j) - UU(k) * BB (k1-1:nn-1,j) ! { dg-bogus "Creating array temporary" } + end do + do j = 1, nn + BB (k1:nn,j) = BB (k1:nn,j) - UU (k1:nn) * BB (k,j) - UU(k) * BB (k1+1:nn+1,j) ! { dg-bogus "Creating array temporary" } + end do + + ! But: + do j = 1, nn + BB (k1:nn,j) = BB (k1-1:nn-1,j) - UU (k1:nn) * BB (k,j) - UU(k) * BB (k1+1:nn+1,j) ! { dg-warning "Creating array temporary" } + end do + + deallocate (AA) + deallocate (BB) + deallocate (UU) +end program test diff --git a/gcc/tree-loop-distribution.c b/gcc/tree-loop-distribution.c index bb15fd3..7ee19fc 100644 --- a/gcc/tree-loop-distribution.c +++ b/gcc/tree-loop-distribution.c @@ -2358,6 +2358,7 @@ loop_distribution::merge_dep_scc_partitions (struct graph *rdg, sort_partitions_by_post_order (pg, partitions); gcc_assert (partitions->length () == (unsigned)num_sccs); free_partition_graph_vdata (pg); + for_each_edge (pg, free_partition_graph_edata_cb, NULL); free_graph (pg); } diff --git a/gcc/tree-vect-loop.c b/gcc/tree-vect-loop.c index acfd195..200ed27 100644 --- a/gcc/tree-vect-loop.c +++ b/gcc/tree-vect-loop.c @@ -2700,7 +2700,7 @@ again: { stmt_vec_info pattern_stmt_info = STMT_VINFO_RELATED_STMT (stmt_info); - if (STMT_VINFO_SLP_VECT_ONLY (pattern_stmt_info)) + if (STMT_VINFO_SLP_VECT_ONLY_PATTERN (pattern_stmt_info)) STMT_VINFO_IN_PATTERN_P (stmt_info) = false; gimple *pattern_def_seq = STMT_VINFO_PATTERN_DEF_SEQ (stmt_info); diff --git a/gcc/tree-vect-slp-patterns.c b/gcc/tree-vect-slp-patterns.c index d25560f..f0817da 100644 --- a/gcc/tree-vect-slp-patterns.c +++ b/gcc/tree-vect-slp-patterns.c @@ -599,7 +599,7 @@ complex_pattern::build (vec_info *vinfo) the call there. */ vect_mark_pattern_stmts (vinfo, stmt_info, call_stmt, SLP_TREE_VECTYPE (node)); - STMT_VINFO_SLP_VECT_ONLY (call_stmt_info) = true; + STMT_VINFO_SLP_VECT_ONLY_PATTERN (call_stmt_info) = true; /* Since we are replacing all the statements in the group with the same thing it doesn't really matter. So just set it every time a new stmt diff --git a/gcc/tree-vectorizer.h b/gcc/tree-vectorizer.h index f8bf448..e564fcf 100644 --- a/gcc/tree-vectorizer.h +++ b/gcc/tree-vectorizer.h @@ -1215,6 +1215,10 @@ public: /* True if this is only suitable for SLP vectorization. */ bool slp_vect_only_p; + + /* True if this is a pattern that can only be handled by SLP + vectorization. */ + bool slp_vect_pattern_only_p; }; /* Information about a gather/scatter call. */ @@ -1301,6 +1305,7 @@ struct gather_scatter_info { #define STMT_VINFO_REDUC_VECTYPE(S) (S)->reduc_vectype #define STMT_VINFO_REDUC_VECTYPE_IN(S) (S)->reduc_vectype_in #define STMT_VINFO_SLP_VECT_ONLY(S) (S)->slp_vect_only_p +#define STMT_VINFO_SLP_VECT_ONLY_PATTERN(S) (S)->slp_vect_pattern_only_p #define DR_GROUP_FIRST_ELEMENT(S) \ (gcc_checking_assert ((S)->dr_aux.dr), (S)->first_element) |