diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.c | 8 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.md | 2 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/sparc/bmaskbshuf.c | 3 |
5 files changed, 18 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 40ebbf3..cd218ab 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2013-05-28 Eric Botcazou <ebotcazou@adacore.com> + * config/sparc/sparc.c (sparc_expand_vec_perm_bmask): Use %g0 as + destination register for bmasksi_vis. + (vector_init_bshuffle): Likewise. + * config/sparc/sparc.md (vec_perm_constv8qi): Likewise. + +2013-05-28 Eric Botcazou <ebotcazou@adacore.com> + * doc/invoke.texi (SPARC Options): Document -mfix-ut699. * builtins.c (expand_builtin_mathfn) <BUILT_IN_SQRT>: Try to widen the mode if the instruction isn't available in the original mode. diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 1dc4e36..d473d6f 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -11527,7 +11527,7 @@ sparc_expand_vec_perm_bmask (enum machine_mode vmode, rtx sel) } /* Always perform the final addition/merge within the bmask insn. */ - emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, t_1)); + emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, t_1)); } /* Implement TARGET_FRAME_POINTER_REQUIRED. */ @@ -11766,7 +11766,7 @@ static void vector_init_bshuffle (rtx target, rtx elt, enum machine_mode mode, enum machine_mode inner_mode) { - rtx t1, final_insn; + rtx t1, final_insn, sel; int bmask; t1 = gen_reg_rtx (mode); @@ -11792,8 +11792,8 @@ vector_init_bshuffle (rtx target, rtx elt, enum machine_mode mode, gcc_unreachable (); } - emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), CONST0_RTX (SImode), - force_reg (SImode, GEN_INT (bmask)))); + sel = force_reg (SImode, GEN_INT (bmask)); + emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, const0_rtx)); emit_insn (final_insn); } diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index f710cc7..7f8d425 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -8589,7 +8589,7 @@ mask |= (INTVAL (XVECEXP (sel, 0, i)) & 0xf) << (28 - i*4); sel = force_reg (SImode, gen_int_mode (mask, SImode)); - emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, const0_rtx)); + emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, const0_rtx)); emit_insn (gen_bshufflev8qi_vis (operands[0], operands[1], operands[2])); DONE; }) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index da2e53c..592bb51 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2013-05-28 Eric Botcazou <ebotcazou@adacore.com> + + * gcc.target/sparc/bmaskbshuf.c: Remove superfluous options. + 2013-05-27 Richard Biener <rguenther@suse.de> PR middle-end/57412 diff --git a/gcc/testsuite/gcc.target/sparc/bmaskbshuf.c b/gcc/testsuite/gcc.target/sparc/bmaskbshuf.c index 7108a01..22809b5 100644 --- a/gcc/testsuite/gcc.target/sparc/bmaskbshuf.c +++ b/gcc/testsuite/gcc.target/sparc/bmaskbshuf.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-O -mcpu=ultrasparc3 -mvis -mvis2" } */ +/* { dg-options "-O -mvis2" } */ + typedef long long int64_t; typedef int vec32 __attribute__((vector_size(8))); typedef short vec16 __attribute__((vector_size(8))); |