diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/arm/thumb2.md | 7 |
2 files changed, 12 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 52e076e..bc8b105 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2012-02-21 Richard Earnshaw <rearnsha@arm.com> + + PR target/52294 + * thumb2.md (thumb2_shiftsi3_short): Split register and + immediate shifts. For register shifts tie operands 0 and 1. + (peephole2 for above): Check that register-controlled shifts + have suitably tied operands. + 2012-02-21 Quentin Neill <quentin.neill@amd.com> PR target/52137 diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index ad05feb..39a2138 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -686,6 +686,7 @@ (match_operand:SI 2 "low_reg_or_int_operand" "")]))] "TARGET_THUMB2 && peep2_regno_dead_p(0, CC_REGNUM) + && (CONST_INT_P (operands[2]) || operands[1] == operands[0]) && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT) || REG_P(operands[2]))" [(parallel @@ -698,10 +699,10 @@ ) (define_insn "*thumb2_shiftsi3_short" - [(set (match_operand:SI 0 "low_register_operand" "=l") + [(set (match_operand:SI 0 "low_register_operand" "=l,l") (match_operator:SI 3 "shift_operator" - [(match_operand:SI 1 "low_register_operand" "l") - (match_operand:SI 2 "low_reg_or_int_operand" "lM")])) + [(match_operand:SI 1 "low_register_operand" "0,l") + (match_operand:SI 2 "low_reg_or_int_operand" "l,M")])) (clobber (reg:CC CC_REGNUM))] "TARGET_THUMB2 && reload_completed && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT) |