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-rw-r--r--gcc/config/aarch64/aarch64-protos.h2
-rw-r--r--gcc/config/aarch64/aarch64-simd.md20
-rw-r--r--gcc/config/aarch64/aarch64.cc10
-rw-r--r--gcc/config/aarch64/predicates.md12
4 files changed, 20 insertions, 24 deletions
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index a20a20c..70303d6 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -759,7 +759,7 @@ bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT);
bool aarch64_const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT,
HOST_WIDE_INT);
bool aarch64_const_vec_rnd_cst_p (rtx, rtx);
-bool aarch64_const_vec_rsra_rnd_imm_p (rtx);
+bool aarch64_rnd_imm_p (rtx);
bool aarch64_constant_address_p (rtx);
bool aarch64_emit_approx_div (rtx, rtx, rtx);
bool aarch64_emit_approx_sqrt (rtx, rtx, bool);
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 90118c6..0ea1123 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1323,7 +1323,7 @@
(plus:<V2XWIDE>
(<SHIFTEXTEND>:<V2XWIDE>
(match_operand:VSDQ_I_DI 2 "register_operand" "w"))
- (match_operand:<V2XWIDE> 4 "aarch64_simd_rsra_rnd_imm_vec"))
+ (match_operand:<V2XWIDE> 4 "aarch64_int_rnd_operand"))
(match_operand:VSDQ_I_DI 3 "aarch64_simd_shift_imm_<vec_or_offset>_<Vel>")))
(match_operand:VSDQ_I_DI 1 "register_operand" "0")))]
"TARGET_SIMD
@@ -6437,7 +6437,7 @@
(plus:<V2XWIDE>
(<SHIFTEXTEND>:<V2XWIDE>
(match_operand:VSDQ_I_DI 1 "register_operand" "w"))
- (match_operand:<V2XWIDE> 3 "aarch64_simd_rsra_rnd_imm_vec"))
+ (match_operand:<V2XWIDE> 3 "aarch64_int_rnd_operand"))
(match_operand:VSDQ_I_DI 2 "aarch64_simd_shift_imm_<vec_or_offset>_<Vel>"))))]
"TARGET_SIMD
&& aarch64_const_vec_rnd_cst_p (operands[3], operands[2])"
@@ -6557,7 +6557,7 @@
(plus:<V2XWIDE>
(<TRUNCEXTEND>:<V2XWIDE>
(match_operand:VQN 1 "register_operand" "w"))
- (match_operand:<V2XWIDE> 3 "aarch64_simd_rsra_rnd_imm_vec"))
+ (match_operand:<V2XWIDE> 3 "aarch64_int_rnd_operand"))
(match_operand:VQN 2 "aarch64_simd_shift_imm_vec_<vn_mode>"))))]
"TARGET_SIMD
&& aarch64_const_vec_rnd_cst_p (operands[3], operands[2])"
@@ -6572,7 +6572,7 @@
(plus:<DWI>
(<TRUNCEXTEND>:<DWI>
(match_operand:SD_HSDI 1 "register_operand" "w"))
- (match_operand:<DWI> 3 "aarch64_simd_rsra_rnd_imm_vec"))
+ (match_operand:<DWI> 3 "aarch64_int_rnd_operand"))
(match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))))]
"TARGET_SIMD
&& aarch64_const_vec_rnd_cst_p (operands[3], operands[2])"
@@ -6702,7 +6702,7 @@
(plus:<V2XWIDE>
(sign_extend:<V2XWIDE>
(match_operand:VQN 1 "register_operand" "w"))
- (match_operand:<V2XWIDE> 3 "aarch64_simd_rsra_rnd_imm_vec"))
+ (match_operand:<V2XWIDE> 3 "aarch64_int_rnd_operand"))
(match_operand:VQN 2 "aarch64_simd_shift_imm_vec_<vn_mode>"))
(match_operand:<V2XWIDE> 4 "aarch64_simd_imm_zero"))
(match_operand:<V2XWIDE> 5 "aarch64_simd_umax_quarter_mode"))))]
@@ -6720,7 +6720,7 @@
(plus:<V2XWIDE>
(sign_extend:<V2XWIDE>
(match_operand:SD_HSDI 1 "register_operand" "w"))
- (match_operand:<V2XWIDE> 3 "aarch64_simd_rsra_rnd_imm_vec"))
+ (match_operand:<V2XWIDE> 3 "aarch64_int_rnd_operand"))
(match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))
(const_int 0))
(const_int <half_mask>)))]
@@ -6831,7 +6831,7 @@
(plus:<V2XWIDE>
(<TRUNCEXTEND>:<V2XWIDE>
(match_operand:VQN 2 "register_operand" "w"))
- (match_operand:<V2XWIDE> 4 "aarch64_simd_rsra_rnd_imm_vec"))
+ (match_operand:<V2XWIDE> 4 "aarch64_int_rnd_operand"))
(match_operand:VQN 3 "aarch64_simd_shift_imm_vec_<vn_mode>")))))]
"TARGET_SIMD && !BYTES_BIG_ENDIAN
&& aarch64_const_vec_rnd_cst_p (operands[4], operands[3])"
@@ -6847,7 +6847,7 @@
(plus:<V2XWIDE>
(<TRUNCEXTEND>:<V2XWIDE>
(match_operand:VQN 2 "register_operand" "w"))
- (match_operand:<V2XWIDE> 4 "aarch64_simd_rsra_rnd_imm_vec"))
+ (match_operand:<V2XWIDE> 4 "aarch64_int_rnd_operand"))
(match_operand:VQN 3 "aarch64_simd_shift_imm_vec_<vn_mode>")))
(match_operand:<VNARROWQ> 1 "register_operand" "0")))]
"TARGET_SIMD && BYTES_BIG_ENDIAN
@@ -6965,7 +6965,7 @@
(plus:<V2XWIDE>
(sign_extend:<V2XWIDE>
(match_operand:VQN 2 "register_operand" "w"))
- (match_operand:<V2XWIDE> 4 "aarch64_simd_rsra_rnd_imm_vec"))
+ (match_operand:<V2XWIDE> 4 "aarch64_int_rnd_operand"))
(match_operand:VQN 3 "aarch64_simd_shift_imm_vec_<vn_mode>"))
(match_operand:<V2XWIDE> 5 "aarch64_simd_imm_zero"))
(match_operand:<V2XWIDE> 6 "aarch64_simd_umax_quarter_mode")))))]
@@ -6985,7 +6985,7 @@
(plus:<V2XWIDE>
(sign_extend:<V2XWIDE>
(match_operand:VQN 2 "register_operand" "w"))
- (match_operand:<V2XWIDE> 4 "aarch64_simd_rsra_rnd_imm_vec"))
+ (match_operand:<V2XWIDE> 4 "aarch64_int_rnd_operand"))
(match_operand:VQN 3 "aarch64_simd_shift_imm_vec_<vn_mode>"))
(match_operand:<V2XWIDE> 5 "aarch64_simd_imm_zero"))
(match_operand:<V2XWIDE> 6 "aarch64_simd_umax_quarter_mode")))
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 644ebde..560e543 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -11761,14 +11761,14 @@ aarch64_extract_vec_duplicate_wide_int (rtx x, wide_int *ret_wi)
return true;
}
-/* Return true if X is a TImode constant or a constant vector of integer
- immediates that represent the rounding constant used in the RSRA
- instructions.
- The accepted form of the constant is (1 << (C - 1)) where C is within
+/* Return true if X is a scalar or a constant vector of integer
+ immediates that represent the rounding constant used in the fixed-point
+ arithmetic instructions.
+ The accepted form of the constant is (1 << (C - 1)) where C is in the range
[1, MODE_WIDTH/2]. */
bool
-aarch64_const_vec_rsra_rnd_imm_p (rtx x)
+aarch64_rnd_imm_p (rtx x)
{
wide_int rnd_cst;
if (!aarch64_extract_vec_duplicate_wide_int (x, &rnd_cst))
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index b31ba6e..d5a4a1c 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -626,15 +626,11 @@
(and (match_code "const_vector")
(match_test "aarch64_const_vec_all_same_in_range_p (op, 1, 64)")))
-(define_predicate "aarch64_simd_rsra_rnd_imm_vec"
+;; A constant or vector of constants that represents an integer rounding
+;; constant added during fixed-point arithmetic calculations
+(define_predicate "aarch64_int_rnd_operand"
(and (match_code "const_vector,const_int,const_wide_int")
- (match_test "aarch64_const_vec_rsra_rnd_imm_p (op)")))
-
-(define_predicate "aarch64_simd_rshrn_imm_vec"
- (and (match_code "const_vector")
- (match_test "aarch64_const_vec_all_same_in_range_p (op, 1,
- HOST_WIDE_INT_1U
- << (GET_MODE_UNIT_BITSIZE (mode) - 1))")))
+ (match_test "aarch64_rnd_imm_p (op)")))
(define_predicate "aarch64_simd_raddsubhn_imm_vec"
(and (match_code "const_vector")
generated by cgit v1.1 at 2025-04-23 16:35:20 +0000