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-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/aarch64/aarch64-simd-builtins.def14
2 files changed, 19 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 98bd3f6..8609f0d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2015-11-26 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/aarch64/aarch64-simd-builtins.def:
+ Add missing changes from r230962.
+
2015-11-26 Nathan Sidwell <nathan@acm.org>
* config/nvptx/nvptx.c (write_func_decl_from_insn): Replace callee
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index aad66b1..1952333 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -431,3 +431,17 @@
/* Implemented by aarch64_qtbx4<mode>. */
VAR1 (TERNOP, qtbx4, 0, v8qi)
VAR1 (TERNOP, qtbx4, 0, v16qi)
+
+ /* Builtins for ARMv8.1 Adv.SIMD instructions. */
+
+ /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>. */
+ BUILTIN_VSDQ_HSI (TERNOP, sqrdmlah, 0)
+ BUILTIN_VSDQ_HSI (TERNOP, sqrdmlsh, 0)
+
+ /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>. */
+ BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_lane, 0)
+ BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_lane, 0)
+
+ /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>. */
+ BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_laneq, 0)
+ BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0)