diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 14 | ||||
| -rw-r--r-- | gcc/config/arm/arm-cores.def | 1 | ||||
| -rw-r--r-- | gcc/config/arm/arm-tune.md | 2 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 9 | ||||
| -rw-r--r-- | gcc/config/arm/arm.h | 23 | ||||
| -rw-r--r-- | gcc/config/arm/constraints.md | 2 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 6 |
7 files changed, 44 insertions, 13 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e0933bd..7444d7e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2008-08-05 Paul Brook <paul@codesourcery.com> + + * doc/invoke.texi: Document new ARM -mfpu= and -mcpu= options. + * config/arm/arm.c (all_fpus): Add vfpv3 and vfpv3-d16. + (fp_model_for_fpu): Add entry for FPUTYPE_VFP3D16. + (arm_file_start): Add FPUTYPE_VFP3D16. Rename vfp3 to vfpv3. + * config/arm/arm.h (TARGET_VFPD32): Define. + (TARGET_VFP3): Use TARGET_VFPD32. + (fputype): Add FPUTYPE_VFP3D16. + (LAST_VFP_REGNUM): Use TARGET_VFPD32. + * config/arm/constraints.md ("w"): Use TARGET_VFPD32. + * config/arm/arm-cores.def: Add cortex-r4f. + * config/arm/arm-tune.md: Regenerate. + 2008-08-05 Ulrich Weigand <Ulrich.Weigand@de.ibm.com> * config/spu_spu_mfcio.h: Wrap in extern "C" if __cplusplus. diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index cce3195..c7e425b 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -117,5 +117,6 @@ ARM_CORE("mpcore", mpcore, 6K, FL_LDSCHED | FL_VFPV2, 9e) ARM_CORE("arm1156t2-s", arm1156t2s, 6T2, FL_LDSCHED, 9e) ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, 9e) ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, 9e) +ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, 9e) ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, 9e) ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, 9e) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index d73382b..ee5606b 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from arm-cores.def (define_attr "tune" - "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,cortexa8,cortexr4,cortexm3,cortexm1" + "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,cortexa8,cortexr4,cortexr4f,cortexm3,cortexm1" (const (symbol_ref "arm_tune"))) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 8b89904..f449d08 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -700,6 +700,8 @@ static const struct fpu_desc all_fpus[] = {"maverick", FPUTYPE_MAVERICK}, {"vfp", FPUTYPE_VFP}, {"vfp3", FPUTYPE_VFP3}, + {"vfpv3", FPUTYPE_VFP3}, + {"vfpv3-d16", FPUTYPE_VFP3D16}, {"neon", FPUTYPE_NEON} }; @@ -716,6 +718,7 @@ static const enum fputype fp_model_for_fpu[] = ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */ ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */ ARM_FP_MODEL_VFP, /* FPUTYPE_VFP */ + ARM_FP_MODEL_VFP, /* FPUTYPE_VFP3D16 */ ARM_FP_MODEL_VFP, /* FPUTYPE_VFP3 */ ARM_FP_MODEL_VFP /* FPUTYPE_NEON */ }; @@ -17738,8 +17741,12 @@ arm_file_start (void) fpu_name = "vfp"; set_float_abi_attributes = 1; break; + case FPUTYPE_VFP3D16: + fpu_name = "vfpv3-d16"; + set_float_abi_attributes = 1; + break; case FPUTYPE_VFP3: - fpu_name = "vfp3"; + fpu_name = "vfpv3"; set_float_abi_attributes = 1; break; case FPUTYPE_NEON: diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 2ab44c2..d99f77d 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -212,15 +212,20 @@ extern void (*arm_lang_output_object_attributes_hook)(void); #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) /* The following two macros concern the ability to execute coprocessor - instructions for VFPv3 or NEON. TARGET_VFP3 is currently only ever - tested when we know we are generating for VFP hardware; we need to - be more careful with TARGET_NEON as noted below. */ + instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently + only ever tested when we know we are generating for VFP hardware; we need + to be more careful with TARGET_NEON as noted below. */ -/* FPU is VFPv3 (with twice the number of D registers). Setting the FPU to - Neon automatically enables VFPv3 too. */ +/* FPU is has the full VFPv3/NEON register file of 32 D registers. */ +#define TARGET_VFPD32 (arm_fp_model == ARM_FP_MODEL_VFP \ + && (arm_fpu_arch == FPUTYPE_VFP3 \ + || arm_fpu_arch == FPUTYPE_NEON)) + +/* FPU supports VFPv3 instructions. */ #define TARGET_VFP3 (arm_fp_model == ARM_FP_MODEL_VFP \ - && (arm_fpu_arch == FPUTYPE_VFP3 \ - || arm_fpu_arch == FPUTYPE_NEON)) + && (arm_fpu_arch == FPUTYPE_VFP3D16 \ + || TARGET_VFPD32)) + /* FPU supports Neon instructions. The setting of this macro gets revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT and TARGET_HARD_FLOAT to ensure that NEON instructions are @@ -299,6 +304,8 @@ enum fputype FPUTYPE_MAVERICK, /* VFP. */ FPUTYPE_VFP, + /* VFPv3-D16. */ + FPUTYPE_VFP3D16, /* VFPv3. */ FPUTYPE_VFP3, /* Neon. */ @@ -945,7 +952,7 @@ extern int arm_structure_size_boundary; #define FIRST_VFP_REGNUM 63 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */ #define LAST_VFP_REGNUM \ - (TARGET_VFP3 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) + (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) #define IS_VFP_REGNUM(REGNUM) \ (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index 0f441ad..a671eb0 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -46,7 +46,7 @@ "The Cirrus Maverick co-processor registers.") (define_register_constraint "w" - "TARGET_32BIT ? (TARGET_VFP3 ? VFP_REGS : VFP_LO_REGS) : NO_REGS" + "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS" "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.") (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS" diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index c2495b3..1cc7984 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -8602,7 +8602,8 @@ assembly code. Permissible names are: @samp{arm2}, @samp{arm250}, @samp{arm10e}, @samp{arm1020e}, @samp{arm1022e}, @samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp}, @samp{arm1156t2-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s}, -@samp{cortex-a8}, @samp{cortex-r4}, @samp{cortex-m3}, @samp{cortex-m1}, +@samp{cortex-a8}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m3}, +@samp{cortex-m1}, @samp{xscale}, @samp{iwmmxt}, @samp{ep9312}. @item -mtune=@var{name} @@ -8636,7 +8637,8 @@ of the @option{-mcpu=} option. Permissible names are: @samp{armv2}, @opindex mfp This specifies what floating point hardware (or hardware emulation) is available on the target. Permissible names are: @samp{fpa}, @samp{fpe2}, -@samp{fpe3}, @samp{maverick}, @samp{vfp}. @option{-mfp} and @option{-mfpe} +@samp{fpe3}, @samp{maverick}, @samp{vfp}, @samp{vfpv3}, @samp{vfpv3-d16} and +@samp{neon}. @option{-mfp} and @option{-mfpe} are synonyms for @option{-mfpu}=@samp{fpe}@var{number}, for compatibility with older versions of GCC@. |