diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/vector.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c | 14 |
2 files changed, 16 insertions, 2 deletions
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 8bbae41..c29e69d 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1175,7 +1175,7 @@ - We can not leave it to TARGET_SECONDARY_RELOAD since it happens before spilling. The clobber scratch is used by spilling fractional registers in IRA/LRA so it's too early. */ - if (TARGET_XTHEADVECTOR) + if (TARGET_XTHEADVECTOR && reg_or_mem_operand (operands[1], <MODE>mode)) { emit_insn (gen_pred_th_whole_mov (<MODE>mode, operands[0], operands[1], RVV_VLMAX, GEN_INT(riscv_vector::VLMAX))); @@ -1238,7 +1238,7 @@ (match_operand:VB 1 "general_operand"))] "TARGET_VECTOR" { - if (TARGET_XTHEADVECTOR) + if (TARGET_XTHEADVECTOR && reg_or_mem_operand (operands[1], <MODE>mode)) { emit_insn (gen_pred_th_whole_mov (<MODE>mode, operands[0], operands[1], RVV_VLMAX, GEN_INT(riscv_vector::VLMAX))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c new file mode 100644 index 0000000..dfaf82c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c @@ -0,0 +1,14 @@ +/* { dg-do assemble } */ +/* { dg-options "-march=rv32gc_xtheadvector -mabi=ilp32d -O2 -save-temps" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O2 -save-temps" { target { rv64 } } } */ + +#include <riscv_vector.h> + +void +foo (float *a, int b) +{ + vfloat32m1x4_t c; + __riscv_vsseg4e32_v_f32m1x4(a, c, b); +} + +/* { dg-final { scan-assembler-times {th\.vmv\.v\.i\tv[0-9]+,0} 4 } } */ |