diff options
Diffstat (limited to 'gcc')
13 files changed, 219 insertions, 0 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d5a1023..2b31f8c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,30 @@ +2015-11-24 Bilyan Borisov <bilyan.borisov@arm.com> + + * gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f32_indices_1.c: + New. + * gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f64_indices_1.c: + New. + * gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f32_indices_1.c: + New. + * gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f64_indices_1.c: + New. + * gcc.target/aarch64/advsimd-intrinsics/vmulxd_lane_f64_indices_1.c: + New. + * gcc.target/aarch64/advsimd-intrinsics/vmulxd_laneq_f64_indices_1.c: + New. + * gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f32_indices_1.c: + New. + * gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f64_indices_1.c: + New. + * gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f32_indices_1.c: + New. + * gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f64_indices_1.c: + New. + * gcc.target/aarch64/advsimd-intrinsics/vmulxs_lane_f32_indices_1.c: + New. + * gcc.target/aarch64/advsimd-intrinsics/vmulxs_laneq_f32_indices_1.c: + New. + 2015-11-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com> PR middle-end/68375 diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f32_indices_1.c new file mode 100644 index 0000000..1494633 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +float32x2_t +f_vmulx_lane_f32 (float32x2_t v1, float32x2_t v2) +{ + float32x2_t res; + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vmulx_lane_f32 (v1, v2, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vmulx_lane_f32 (v1, v2, 2); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f64_indices_1.c new file mode 100644 index 0000000..3fdb557 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +float64x1_t +f_vmulx_lane_f64 (float64x1_t v1, float64x1_t v2) +{ + float64x1_t res; + /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vmulx_lane_f64 (v1, v2, -1); + /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */ + res = vmulx_lane_f64 (v1, v2, 1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f32_indices_1.c new file mode 100644 index 0000000..1f8dfd0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +float32x2_t +f_vmulx_laneq_f32 (float32x2_t v1, float32x4_t v2) +{ + float32x2_t res; + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + res = vmulx_laneq_f32 (v1, v2, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + res = vmulx_laneq_f32 (v1, v2, 4); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f64_indices_1.c new file mode 100644 index 0000000..8d54ebe --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +float64x1_t +f_vmulx_laneq_f64 (float64x1_t v1, float64x2_t v2) +{ + float64x1_t res; + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + res = vmulx_laneq_f64 (v1, v2, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + res = vmulx_laneq_f64 (v1, v2, 2); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxd_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxd_lane_f64_indices_1.c new file mode 100644 index 0000000..0db5cd0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxd_lane_f64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +float64_t +f_vmulxd_lane_f64 (float64_t v1, float64x1_t v2) +{ + float64_t res; + /* { dg-error "lane -1 out of range 0 - 0" "" {target *-*-*} 0 } */ + res = vmulxd_lane_f64 (v1, v2, -1); + /* { dg-error "lane 1 out of range 0 - 0" "" {target *-*-*} 0 } */ + res = vmulxd_lane_f64 (v1, v2, 1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxd_laneq_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxd_laneq_f64_indices_1.c new file mode 100644 index 0000000..6df1a0d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxd_laneq_f64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +float64_t +f_vmulxd_laneq_f64 (float64_t v1, float64x2_t v2) +{ + float64_t res; + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + res = vmulxd_laneq_f64 (v1, v2, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + res = vmulxd_laneq_f64 (v1, v2, 2); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f32_indices_1.c new file mode 100644 index 0000000..3fee966 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +float32x4_t +f_vmulxq_lane_f32 (float32x4_t v1, float32x2_t v2) +{ + float32x4_t res; + /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vmulxq_lane_f32 (v1, v2, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */ + res = vmulxq_lane_f32 (v1, v2, 2); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f64_indices_1.c new file mode 100644 index 0000000..2acddf2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +float64x2_t +f_vmulxq_lane_f64 (float64x2_t v1, float64x1_t v2) +{ + float64x2_t res; + /* { dg-error "lane -1 out of range 0 - 0" "" {target *-*-*} 0 } */ + res = vmulxq_lane_f64 (v1, v2, -1); + /* { dg-error "lane 1 out of range 0 - 0" "" {target *-*-*} 0 } */ + res = vmulxq_lane_f64 (v1, v2, 1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f32_indices_1.c new file mode 100644 index 0000000..bbd3e00 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +float32x4_t +f_vmulxq_laneq_f32 (float32x4_t v1, float32x4_t v2) +{ + float32x4_t res; + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + res = vmulxq_laneq_f32 (v1, v2, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + res = vmulxq_laneq_f32 (v1, v2, 4); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f64_indices_1.c new file mode 100644 index 0000000..0284193 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f64_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +float64x2_t +f_vmulxq_laneq_f64 (float64x2_t v1, float64x2_t v2) +{ + float64x2_t res; + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + res = vmulxq_laneq_f64 (v1, v2, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + res = vmulxq_laneq_f64 (v1, v2, 2); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxs_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxs_lane_f32_indices_1.c new file mode 100644 index 0000000..73a6e71 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxs_lane_f32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +float32_t +f_vmulxs_lane_f32 (float32_t v1, float32x2_t v2) +{ + float32_t res; + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + res = vmulxs_lane_f32 (v1, v2, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + res = vmulxs_lane_f32 (v1, v2, 2); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxs_laneq_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxs_laneq_f32_indices_1.c new file mode 100644 index 0000000..132ffb1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxs_laneq_f32_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-skip-if "" { arm*-*-* } } */ + +float32_t +f_vmulxs_laneq_f32 (float32_t v1, float32x4_t v2) +{ + float32_t res; + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + res = vmulxs_laneq_f32 (v1, v2, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + res = vmulxs_laneq_f32 (v1, v2, 4); + return res; +} |