diff options
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 10 | ||||
-rw-r--r-- | gcc/config/ia64/ia64.c | 142 | ||||
-rw-r--r-- | gcc/config/ia64/ia64.h | 6 | ||||
-rw-r--r-- | gcc/doc/invoke.texi | 6 |
4 files changed, 11 insertions, 153 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 760a480..691d485 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2005-02-18 James E. Wilson <wilson@specifixinc.com> + + * doc/invoke.texi (IA-64 Options): Delete -mb-step. + * config/ia64/ia64.c (last_group, group_idx): Delete variables. + (errata_find_address_regs, errata_emit_nops, fixup_errata): Delete + functions. + (ia64_reorg): Delete fixup_errata call. + * config/ia64/ia64.h (MASK_B_STEP, TARGET_B_STEP): Delete. + (TARGET_SWITCHES): Delete -mb-step entry. + 2005-02-19 Jakub Jelinek <jakub@redhat.com> PR c/20043 diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index ce72063..d67bb1f 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -5684,147 +5684,6 @@ emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED) } -static int errata_find_address_regs (rtx *, void *); -static void errata_emit_nops (rtx); -static void fixup_errata (void); - -/* This structure is used to track some details about the previous insns - groups so we can determine if it may be necessary to insert NOPs to - workaround hardware errata. */ -static struct group -{ - HARD_REG_SET p_reg_set; - HARD_REG_SET gr_reg_conditionally_set; -} last_group[2]; - -/* Index into the last_group array. */ -static int group_idx; - -/* Called through for_each_rtx; determines if a hard register that was - conditionally set in the previous group is used as an address register. - It ensures that for_each_rtx returns 1 in that case. */ -static int -errata_find_address_regs (rtx *xp, void *data ATTRIBUTE_UNUSED) -{ - rtx x = *xp; - if (GET_CODE (x) != MEM) - return 0; - x = XEXP (x, 0); - if (GET_CODE (x) == POST_MODIFY) - x = XEXP (x, 0); - if (GET_CODE (x) == REG) - { - struct group *prev_group = last_group + (group_idx ^ 1); - if (TEST_HARD_REG_BIT (prev_group->gr_reg_conditionally_set, - REGNO (x))) - return 1; - return -1; - } - return 0; -} - -/* Called for each insn; this function keeps track of the state in - last_group and emits additional NOPs if necessary to work around - an Itanium A/B step erratum. */ -static void -errata_emit_nops (rtx insn) -{ - struct group *this_group = last_group + group_idx; - struct group *prev_group = last_group + (group_idx ^ 1); - rtx pat = PATTERN (insn); - rtx cond = GET_CODE (pat) == COND_EXEC ? COND_EXEC_TEST (pat) : 0; - rtx real_pat = cond ? COND_EXEC_CODE (pat) : pat; - enum attr_type type; - rtx set = real_pat; - - if (GET_CODE (real_pat) == USE - || GET_CODE (real_pat) == CLOBBER - || GET_CODE (real_pat) == ASM_INPUT - || GET_CODE (real_pat) == ADDR_VEC - || GET_CODE (real_pat) == ADDR_DIFF_VEC - || asm_noperands (PATTERN (insn)) >= 0) - return; - - /* single_set doesn't work for COND_EXEC insns, so we have to duplicate - parts of it. */ - - if (GET_CODE (set) == PARALLEL) - { - int i; - set = XVECEXP (real_pat, 0, 0); - for (i = 1; i < XVECLEN (real_pat, 0); i++) - if (GET_CODE (XVECEXP (real_pat, 0, i)) != USE - && GET_CODE (XVECEXP (real_pat, 0, i)) != CLOBBER) - { - set = 0; - break; - } - } - - if (set && GET_CODE (set) != SET) - set = 0; - - type = get_attr_type (insn); - - if (type == TYPE_F - && set && REG_P (SET_DEST (set)) && PR_REGNO_P (REGNO (SET_DEST (set)))) - SET_HARD_REG_BIT (this_group->p_reg_set, REGNO (SET_DEST (set))); - - if ((type == TYPE_M || type == TYPE_A) && cond && set - && REG_P (SET_DEST (set)) - && GET_CODE (SET_SRC (set)) != PLUS - && GET_CODE (SET_SRC (set)) != MINUS - && (GET_CODE (SET_SRC (set)) != ASHIFT - || !shladd_operand (XEXP (SET_SRC (set), 1), VOIDmode)) - && (GET_CODE (SET_SRC (set)) != MEM - || GET_CODE (XEXP (SET_SRC (set), 0)) != POST_MODIFY) - && GENERAL_REGNO_P (REGNO (SET_DEST (set)))) - { - if (!COMPARISON_P (cond) - || !REG_P (XEXP (cond, 0))) - abort (); - - if (TEST_HARD_REG_BIT (prev_group->p_reg_set, REGNO (XEXP (cond, 0)))) - SET_HARD_REG_BIT (this_group->gr_reg_conditionally_set, REGNO (SET_DEST (set))); - } - if (for_each_rtx (&real_pat, errata_find_address_regs, NULL)) - { - emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn); - emit_insn_before (gen_nop (), insn); - emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn); - group_idx = 0; - memset (last_group, 0, sizeof last_group); - } -} - -/* Emit extra nops if they are required to work around hardware errata. */ - -static void -fixup_errata (void) -{ - rtx insn; - - if (! TARGET_B_STEP) - return; - - group_idx = 0; - memset (last_group, 0, sizeof last_group); - - for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) - { - if (!INSN_P (insn)) - continue; - - if (ia64_safe_type (insn) == TYPE_S) - { - group_idx ^= 1; - memset (last_group + group_idx, 0, sizeof last_group[group_idx]); - } - else - errata_emit_nops (insn); - } -} - /* Instruction scheduling support. */ @@ -7583,7 +7442,6 @@ ia64_reorg (void) } } - fixup_errata (); emit_predicate_relation_info (); if (ia64_flag_var_tracking) diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h index 36edb9e..a81cd2c 100644 --- a/gcc/config/ia64/ia64.h +++ b/gcc/config/ia64/ia64.h @@ -75,8 +75,6 @@ extern int target_flags; #define MASK_ILP32 0x00000020 /* Generate ILP32 code. */ -#define MASK_B_STEP 0x00000040 /* Emit code for Itanium B step. */ - #define MASK_REG_NAMES 0x00000080 /* Use in/loc/out register names. */ #define MASK_NO_SDATA 0x00000100 /* Disable sdata/scommon/sbss. */ @@ -113,8 +111,6 @@ extern int target_flags; #define TARGET_ILP32 (target_flags & MASK_ILP32) -#define TARGET_B_STEP (target_flags & MASK_B_STEP) - #define TARGET_REG_NAMES (target_flags & MASK_REG_NAMES) #define TARGET_NO_SDATA (target_flags & MASK_NO_SDATA) @@ -196,8 +192,6 @@ extern int ia64_tls_size; N_("Emit stop bits before and after volatile extended asms") }, \ { "no-volatile-asm-stop", -MASK_VOL_ASM_STOP, \ N_("Don't emit stop bits before and after volatile extended asms") }, \ - { "b-step", MASK_B_STEP, \ - N_("Emit code for Itanium (TM) processor B step")}, \ { "register-names", MASK_REG_NAMES, \ N_("Use in/loc/out register names")}, \ { "no-sdata", MASK_NO_SDATA, \ diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 88f19dc..048f495 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -499,7 +499,7 @@ Objective-C and Objective-C++ Dialects}. @emph{IA-64 Options} @gccoptlist{-mbig-endian -mlittle-endian -mgnu-as -mgnu-ld -mno-pic @gol --mvolatile-asm-stop -mb-step -mregister-names -mno-sdata @gol +-mvolatile-asm-stop -mregister-names -mno-sdata @gol -mconstant-gp -mauto-pic -minline-float-divide-min-latency @gol -minline-float-divide-max-throughput @gol -minline-int-divide-min-latency @gol @@ -8866,10 +8866,6 @@ is not position independent code, and violates the IA-64 ABI@. Generate (or don't) a stop bit immediately before and after volatile asm statements. -@item -mb-step -@opindex mb-step -Generate code that works around Itanium B step errata. - @item -mregister-names @itemx -mno-register-names @opindex mregister-names |