diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
444 files changed, 7456 insertions, 26 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/pr121853_1.c b/gcc/testsuite/gcc.target/aarch64/pr121853_1.c new file mode 100644 index 0000000..24b2fdc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr121853_1.c @@ -0,0 +1,64 @@ +/* { dg-do run } */ +/* { dg-additional-options "-O2 -std=c99" } */ + +#include <stdint.h> +#include <stdio.h> +#include <string.h> + +__attribute__ ((noipa)) +float convert(__bf16 value) { + return (float)value; +} + +static inline uint32_t f32_bits(float f) { + uint32_t u; memcpy(&u, &f, sizeof u); return u; +} +static inline __bf16 bf16_from_bits(uint16_t u) { + __bf16 b; memcpy(&b, &u, sizeof b); return b; +} + +/* Fixed bf16 inputs (as raw 16-bit payloads) covering edge cases. */ +static const uint16_t inputs[] = { + 0x0000, // +0 + 0x8000, // -0 + 0x7F80, // +inf + 0xFF80, // -inf + 0x7FC0, // qNaN (+) (quiet bit set in bf16) + 0xFFC0, // qNaN (-) + 0x7F01, // sNaN (+) (will be quieted by conversion) + 0xFF01, // sNaN (-) + 0x0001, // smallest +subnormal + 0x007F, // largest +subnormal + 0x8001, // smallest -subnormal + 0x807F, // largest -subnormal + 0x0080, // smallest +normal + 0x3F80, // +1.0 + 0xBF80, // -1.0 + 0x3F00, // +0.5 + 0xBF00, // -0.5 + 0x3FC0, // +1.5 + 0x7F7F, // max finite + + 0xFF7F, // max finite - +}; + +int main(void) { + const size_t N = sizeof(inputs)/sizeof(inputs[0]); + size_t fails = 0; + + for (size_t i = 0; i < N; ++i) { + __bf16 in = bf16_from_bits(inputs[i]); + float out = convert(in); + uint32_t got = f32_bits(out); + uint32_t exp = inputs[i] << 16; + + if (got != exp) { + printf("FAIL[%zu]: in_bf16=0x%04X exp_f32=0x%08X got_f32=0x%08X\n", + i, inputs[i], exp, got); + ++fails; + } + } + + if (fails != 0) + __builtin_abort (); +} + diff --git a/gcc/testsuite/gcc.target/aarch64/pr121853_2.c b/gcc/testsuite/gcc.target/aarch64/pr121853_2.c new file mode 100644 index 0000000..e9fb401 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr121853_2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O1" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +float convert(__bf16 value) { + return (float)value; +} + +/* +** convert: +** movi v[0-9]+.4s, 0 +** ext v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b, #14 +** ret +*/ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-1.c b/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-1.c new file mode 100644 index 0000000..41dcbba --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fdump-tree-optimized" } */ +/* PR target/116075 */ + +#include <arm_sve.h> + +svint8_t f(void) +{ + svint8_t tt; + tt = svdup_s8 (0); + tt = svinsr (tt, 0); + return tt; +} + +svint8_t f1(int8_t t) +{ + svint8_t tt; + tt = svdup_s8 (t); + tt = svinsr (tt, t); + return tt; +} + +/* The above 2 functions should have removed the VEC_SHL_INSERT. */ + +/* { dg-final { scan-tree-dump-not ".VEC_SHL_INSERT " "optimized" } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-2.c b/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-2.c new file mode 100644 index 0000000..8eafe97 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-2.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fdump-tree-optimized" } */ +/* PR target/116075 */ + +#include <arm_sve.h> + +svint8_t f(int8_t t) +{ + svint8_t tt; + tt = svdup_s8 (0); + tt = svinsr (tt, t); + return tt; +} + +svint8_t f1(int8_t t) +{ + svint8_t tt; + tt = svdup_s8 (t); + tt = svinsr (tt, 0); + return tt; +} + +/* The above 2 functions should not have removed the VEC_SHL_INSERT. */ + +/* { dg-final { scan-tree-dump-times ".VEC_SHL_INSERT " 2 "optimized" } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pr121599.c b/gcc/testsuite/gcc.target/aarch64/sve2/pr121599.c index 90c5ac9..da4b7aa 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/pr121599.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pr121599.c @@ -7,7 +7,7 @@ /* ** foo: -** movi d([0-9]+), #0 +** movi? [vdz]([0-9]+)\.?b?, #0 ** movprfx z0\.b, p0/z, z0\.b ** usqadd z0\.b, p0/m, z0\.b, z\1\.b ** ret @@ -19,7 +19,7 @@ svuint8_t foo (svbool_t pg, svuint8_t op1) /* ** bar: -** movi d([0-9]+), #0 +** movi? [vdz]([0-9]+)\.?b?, #0 ** movprfx z0\.b, p0/z, z0\.b ** suqadd z0\.b, p0/m, z0\.b, z\1\.b ** ret diff --git a/gcc/testsuite/gcc.target/avr/pr121198.c b/gcc/testsuite/gcc.target/avr/pr121198.c new file mode 100644 index 0000000..551247e --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr121198.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -mmcu=atmega8" } */ + +long +test (void) +{ + long x; + __asm__ ("" : "={r22}" (x)); + return x; +} diff --git a/gcc/testsuite/gcc.target/i386/builtin-copysign-8b.c b/gcc/testsuite/gcc.target/i386/builtin-copysign-8b.c index 8f0cb27..dc9e461 100644 --- a/gcc/testsuite/gcc.target/i386/builtin-copysign-8b.c +++ b/gcc/testsuite/gcc.target/i386/builtin-copysign-8b.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mno-avx512f -mavx" } */ +/* { dg-options "-O2 -mno-avx512f -mavx -mtune=generic" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/cf_check-10.c b/gcc/testsuite/gcc.target/i386/cf_check-10.c new file mode 100644 index 0000000..a131672 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/cf_check-10.c @@ -0,0 +1,19 @@ +/* PR c/122427 */ +/* { dg-do compile { target { "i?86-*-* x86_64-*-*" } } } */ +/* { dg-options "-O2 -fcf-protection" } */ + +extern void foo (void) __attribute__((nocf_check)); +extern void foo (void); + +void +foo (void) +{ +} + +extern void bar (void); +extern void bar (void) __attribute__((nocf_check)); /* { dg-error "conflicting types" } */ + +void +bar (void) +{ +} diff --git a/gcc/testsuite/gcc.target/i386/cf_check-11.c b/gcc/testsuite/gcc.target/i386/cf_check-11.c new file mode 100644 index 0000000..9ed65ab --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/cf_check-11.c @@ -0,0 +1,24 @@ +/* PR c/122427 */ +/* { dg-do compile { target { "i?86-*-* x86_64-*-*" } } } */ +/* { dg-require-weak "" } */ +/* { dg-options "-O2 -fcf-protection" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** ret +**... +*/ + +extern void foo (void) __attribute__((nocf_check)); + +__attribute__((weak)) +void +foo (void) +{ +} + +/* { dg-final { scan-assembler ".weak\[ \t\]_?foo" } } */ diff --git a/gcc/testsuite/gcc.target/i386/cf_check-7.c b/gcc/testsuite/gcc.target/i386/cf_check-7.c new file mode 100644 index 0000000..b9a3b39 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/cf_check-7.c @@ -0,0 +1,20 @@ +/* PR c/122427 */ +/* { dg-do compile { target { "i?86-*-* x86_64-*-*" } } } */ +/* { dg-options "-O2 -fcf-protection" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** ret +**... +*/ + +extern void foo (void) __attribute__((nocf_check)); + +void +foo (void) +{ +} diff --git a/gcc/testsuite/gcc.target/i386/cf_check-8.c b/gcc/testsuite/gcc.target/i386/cf_check-8.c new file mode 100644 index 0000000..48e8cf1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/cf_check-8.c @@ -0,0 +1,11 @@ +/* PR c/122427 */ +/* { dg-do compile { target { "i?86-*-* x86_64-*-*" } } } */ +/* { dg-options "-O2 -fcf-protection" } */ + +extern void foo (void); + +__attribute__((nocf_check)) +void +foo (void) /* { dg-error "conflicting types" } */ +{ +} diff --git a/gcc/testsuite/gcc.target/i386/cf_check-9.c b/gcc/testsuite/gcc.target/i386/cf_check-9.c new file mode 100644 index 0000000..057c60f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/cf_check-9.c @@ -0,0 +1,15 @@ +/* PR c/122427 */ +/* { dg-do compile { target { "i?86-*-* x86_64-*-*" } } } */ +/* { dg-options "-O2 -fcf-protection" } */ + +extern void bar (void); +extern void bar (void) __attribute__((nocf_check)); /* { dg-error "conflicting types" } */ +extern void foo (void) __attribute__((nocf_check)); +extern void foo (void); + +void +func (void) +{ + bar (); + foo (); +} diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-12.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-12.c index 5524a4a..8f9b725 100644 --- a/gcc/testsuite/gcc.target/i386/no-callee-saved-12.c +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-12.c @@ -1,10 +1,9 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -extern void foo (void) __attribute__ ((no_callee_saved_registers)); /* { dg-note "previous declaration" } */ +extern void foo (void) __attribute__ ((no_callee_saved_registers)); void -foo (void) /* { dg-error "conflicting types" } */ +foo (void) { } - diff --git a/gcc/testsuite/gcc.target/i386/pr116815.c b/gcc/testsuite/gcc.target/i386/pr116815.c new file mode 100644 index 0000000..1cd2f72 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr116815.c @@ -0,0 +1,31 @@ +/* PR target/116815 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-additional-options "-march=pentiumpro" { target ia32 } } */ + +static inline __attribute__ ((always_inline)) +unsigned max (unsigned a, unsigned b) { return a > b ? a : b; } + +static inline __attribute__ ((always_inline)) +unsigned min (unsigned a, unsigned b) { return a < b ? a : b; } + +#define OPERATION(op, type, N, exp1, exp2) \ + unsigned u##op##type##N (unsigned a, unsigned b) { return op (exp1, exp2); } + +OPERATION (max, add, 1, a, a + b) +OPERATION (max, add, 2, a, b + a) +OPERATION (max, add, 3, a + b, a) +OPERATION (max, add, 4, b + a, a) + +OPERATION (min, add, 1, a, a + b) +OPERATION (min, add, 2, a, b + a) +OPERATION (min, add, 3, a + b, a) +OPERATION (min, add, 4, b + a, a) + +OPERATION (max, sub, 1, a, a - b) +OPERATION (max, sub, 2, a - b, a) + +OPERATION (min, sub, 1, a, a - b) +OPERATION (min, sub, 2, a - b, a) + +/* { dg-final { scan-assembler-not "cmp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr122457.c b/gcc/testsuite/gcc.target/i386/pr122457.c new file mode 100644 index 0000000..dc57fb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr122457.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -mavxvnniint16" } */ + +#include "vnniint16-auto-vectorize-2.c" diff --git a/gcc/testsuite/gcc.target/i386/preserve-none-17.c b/gcc/testsuite/gcc.target/i386/preserve-none-17.c index e105da1..0c62edd 100644 --- a/gcc/testsuite/gcc.target/i386/preserve-none-17.c +++ b/gcc/testsuite/gcc.target/i386/preserve-none-17.c @@ -1,10 +1,9 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -extern void foo (void) __attribute__ ((preserve_none)); /* { dg-note "previous declaration" } */ +extern void foo (void) __attribute__ ((preserve_none)); void -foo (void) /* { dg-error "conflicting types" } */ +foo (void) { } - diff --git a/gcc/testsuite/gcc.target/loongarch/compare-both-non-zero.c b/gcc/testsuite/gcc.target/loongarch/compare-both-non-zero.c new file mode 100644 index 0000000..b813df4 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/compare-both-non-zero.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { loongarch64*-*-* } } } */ +/* { dg-options "-O3" } */ + +int +test (int a, int b) +{ + return a && b; +} + +/* { dg-final { scan-assembler "maskeqz" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c b/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c index ed13471..47802aa 100644 --- a/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c +++ b/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c @@ -27,7 +27,7 @@ void test_lt () { if (lm < ln) - lr *= (1 << 16); + lr += (1 << 16); lr += lm; } @@ -35,7 +35,7 @@ void test_le () { if (lm <= ln) - lr = lm * ((long)1 << 32); + lr = lm + ((long)1 << 32); else lr = lm; lr += lm; diff --git a/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c b/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c index ac72d4d..743fd5e 100644 --- a/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c +++ b/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c @@ -29,7 +29,7 @@ void test_lez () { if (lm <= 0) - lr &= (1 << 16); + lr |= (1 << 16); lr += lm; } diff --git a/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-3.c b/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-3.c new file mode 100644 index 0000000..9588798 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-3.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "maskeqz" } } */ +/* { dg-final { scan-assembler "masknez" } } */ + +extern long lm, ln, lr; + +void +test_and () +{ + if (lm < 0) + lr &= (1 << 16); + lr += lm; +} diff --git a/gcc/testsuite/gcc.target/loongarch/fnmam4-vec.c b/gcc/testsuite/gcc.target/loongarch/fnmam4-vec.c new file mode 100644 index 0000000..0969303 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/fnmam4-vec.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast -mlasx -ftree-vectorize" } */ +/* { dg-require-effective-target loongarch_asx } */ + +void +foo (float *u, float x, float *y, float z) +{ + int i; + for (i = 0; i < 1024; i++) + *(u++) = (x - y[i] * z); +} + +/* { dg-final { scan-assembler-not "\tvori.b"} } */ +/* { dg-final { scan-assembler-not "\txvori.b"} } */ diff --git a/gcc/testsuite/gcc.target/loongarch/pr122097.c b/gcc/testsuite/gcc.target/loongarch/pr122097.c new file mode 100644 index 0000000..5d32b19 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/pr122097.c @@ -0,0 +1,271 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mabi=lp64d -mlsx" } */ +/* { dg-final { scan-assembler "vbitseti\.d\t\\\$vr\[0-9\]+,\\\$vr\[0-9\]+,63" } } */ + +typedef long unsigned int size_t; +typedef unsigned char simde__mmask8; +typedef long simde__m128i __attribute__ ((__aligned__ ((16)))) +__attribute__ ((__vector_size__ (16))) __attribute__ ((__may_alias__)); +typedef union +{ + + __attribute__ ((__aligned__ ((16)))) long i64 + __attribute__ ((__vector_size__ (16))) __attribute__ ((__may_alias__)); +} simde__m128i_private; +typedef double simde_float64; +typedef simde_float64 simde__m128d __attribute__ ((__aligned__ ((16)))) +__attribute__ ((__vector_size__ (16))) __attribute__ ((__may_alias__)); +typedef long int int_fast32_t; +typedef union +{ + + __attribute__ ((__aligned__ ((16)))) int_fast32_t i32f + __attribute__ ((__vector_size__ (16))) __attribute__ ((__may_alias__)); + __attribute__ ((__aligned__ ((16)))) long i64 + __attribute__ ((__vector_size__ (16))) __attribute__ ((__may_alias__)); + __attribute__ ((__aligned__ ((16)))) simde_float64 f64 + __attribute__ ((__vector_size__ (16))) __attribute__ ((__may_alias__)); +} simde__m128d_private; +__attribute__ ((__always_inline__)) inline static simde__m128d +simde__m128d_from_private (simde__m128d_private v) +{ + simde__m128d r; + __builtin_memcpy (&r, &v, sizeof (r)); + return r; +} + +__attribute__ ((__always_inline__)) inline static simde__m128d +simde_mm_set_pd (simde_float64 e1, simde_float64 e0) +{ + + simde__m128d_private r_; + r_.f64[0] = e0; + r_.f64[1] = e1; + + return simde__m128d_from_private (r_); +} +__attribute__ ((__always_inline__)) inline static simde__m128i +simde_mm_castpd_si128 (simde__m128d a) +{ + simde__m128i r; + __builtin_memcpy (&r, &a, sizeof (a)); + return r; +} + +__attribute__ ((__always_inline__)) inline static simde__m128i +simde__m128i_from_private (simde__m128i_private v) +{ + simde__m128i r; + __builtin_memcpy (&r, &v, sizeof (r)); + return r; +} + +__attribute__ ((__always_inline__)) inline static simde__m128i_private +simde__m128i_to_private (simde__m128i v) +{ + simde__m128i_private r; + __builtin_memcpy (&r, &v, sizeof (r)); + return r; +} +__attribute__ ((__always_inline__)) inline static simde__m128d +simde_mm_castsi128_pd (simde__m128i a) +{ + simde__m128d r; + __builtin_memcpy (&r, &a, sizeof (a)); + return r; +} + +__attribute__ ((__always_inline__)) inline static simde__m128i +simde_mm_mask_mov_epi64 (simde__m128i src, simde__mmask8 k, simde__m128i a) +{ + + simde__m128i_private src_ = simde__m128i_to_private (src), + a_ = simde__m128i_to_private (a), r_; + + for (size_t i = 0; i < (sizeof (r_.i64) / sizeof (r_.i64[0])); i++) + { + r_.i64[i] = ((k >> i) & 1) ? a_.i64[i] : src_.i64[i]; + } + + return simde__m128i_from_private (r_); +} + +__attribute__ ((__always_inline__)) inline static simde__m128d +simde_mm_mask_mov_pd (simde__m128d src, simde__mmask8 k, simde__m128d a) +{ + return simde_mm_castsi128_pd (simde_mm_mask_mov_epi64 ( + simde_mm_castpd_si128 (src), k, simde_mm_castpd_si128 (a))); +} + +static double +simde_test_f64_precision_to_slop (int precision) +{ + return __builtin_expect (!!(precision == 0x7fffffff), 0) + ? 0.0 + : __builtin_pow (10.0, -((double)(precision))); +} +__attribute__ ((__always_inline__)) inline static void +simde_mm_storeu_pd (simde_float64 *mem_addr, simde__m128d a) +{ + + __builtin_memcpy (mem_addr, &a, sizeof (a)); +} +int simde_test_equal_f64 (simde_float64 a, simde_float64 b, + simde_float64 slop); +void simde_test_debug_printf_ (const char *format, ...); +static int +simde_assert_equal_vf64_ (size_t vec_len, simde_float64 const a[(vec_len)], + simde_float64 const b[(vec_len)], simde_float64 slop, + const char *filename, int line, const char *astr, + const char *bstr) +{ + for (size_t i = 0; i < vec_len; i++) + { + if (__builtin_expect (!!(!simde_test_equal_f64 (a[i], b[i], slop)), 0)) + { + simde_test_debug_printf_ ( + "%s:%d: assertion failed: %s[%zu] ~= %s[%zu] (%f ~= %f)\n", + filename, line, astr, i, bstr, i, ((double)(a[i])), + ((double)(b[i]))); + return 1; + } + } + return 0; +} +static int +simde_test_x86_assert_equal_f64x2_ (simde__m128d a, simde__m128d b, + simde_float64 slop, const char *filename, + int line, const char *astr, + const char *bstr) +{ + simde_float64 a_[sizeof (a) / sizeof (simde_float64)], + b_[sizeof (a) / sizeof (simde_float64)]; + simde_mm_storeu_pd (a_, a); + simde_mm_storeu_pd (b_, b); + return simde_assert_equal_vf64_ (sizeof (a_) / sizeof (a_[0]), a_, b_, slop, + filename, line, astr, bstr); +} +__attribute__ ((__always_inline__)) inline static simde__m128d_private +simde__m128d_to_private (simde__m128d v) +{ + simde__m128d_private r; + __builtin_memcpy (&r, &v, sizeof (r)); + return r; +} +__attribute__ ((__always_inline__)) inline static simde__m128d +simde_mm_min_pd (simde__m128d a, simde__m128d b) +{ + + simde__m128d_private r_, a_ = simde__m128d_to_private (a), + b_ = simde__m128d_to_private (b); + + for (size_t i = 0; i < (sizeof (r_.f64) / sizeof (r_.f64[0])); i++) + { + r_.f64[i] = (a_.f64[i] < b_.f64[i]) ? a_.f64[i] : b_.f64[i]; + } + + return simde__m128d_from_private (r_); +} + +__attribute__ ((__always_inline__)) inline static simde__m128d +simde_mm_max_pd (simde__m128d a, simde__m128d b) +{ + + simde__m128d_private r_, a_ = simde__m128d_to_private (a), + b_ = simde__m128d_to_private (b); + + for (size_t i = 0; i < (sizeof (r_.f64) / sizeof (r_.f64[0])); i++) + { + r_.f64[i] = (a_.f64[i] > b_.f64[i]) ? a_.f64[i] : b_.f64[i]; + } + + return simde__m128d_from_private (r_); +} + +__attribute__ ((__always_inline__)) inline static simde__m128d +simde_x_mm_abs_pd (simde__m128d a) +{ + + simde__m128d_private r_, a_ = simde__m128d_to_private (a); + for (size_t i = 0; i < (sizeof (r_.f64) / sizeof (r_.f64[0])); i++) + { + r_.f64[i] = __builtin_fabs (a_.f64[i]); + } + + return simde__m128d_from_private (r_); +} +__attribute__ ((__always_inline__)) inline static simde__m128d +simde_mm_cmple_pd (simde__m128d a, simde__m128d b) +{ + + simde__m128d_private r_, a_ = simde__m128d_to_private (a), + b_ = simde__m128d_to_private (b); + + r_.i64 = ((__typeof__ (r_.i64))((a_.f64 <= b_.f64))); + return simde__m128d_from_private (r_); +} + +__attribute__ ((__always_inline__)) inline static simde__m128d +simde_x_mm_select_pd (simde__m128d a, simde__m128d b, simde__m128d mask) +{ + simde__m128d_private r_, a_ = simde__m128d_to_private (a), + b_ = simde__m128d_to_private (b), + mask_ = simde__m128d_to_private (mask); + + r_.i64 = a_.i64 ^ ((a_.i64 ^ b_.i64) & mask_.i64); + return simde__m128d_from_private (r_); +} +simde__m128d simde_mm_cmpge_pd (simde__m128d a, simde__m128d b); + +simde__m128d +simde_x_mm_copysign_pd (simde__m128d dest, simde__m128d src) +{ + simde__m128d_private r_, dest_ = simde__m128d_to_private (dest), + src_ = simde__m128d_to_private (src); + for (size_t i = 0; i < (sizeof (r_.f64) / sizeof (r_.f64[0])); i++) + { + r_.f64[i] = __builtin_copysign (dest_.f64[i], src_.f64[i]); + } + + return simde__m128d_from_private (r_); +} +simde__m128d simde_mm_or_pd (simde__m128d a, simde__m128d b); + +simde__m128d simde_mm_set1_pd (simde_float64 a); + +__attribute__ ((__always_inline__)) inline static simde__m128d +simde_mm_range_pd (simde__m128d a, simde__m128d b, int imm8) +{ + simde__m128d r; + + r = simde_x_mm_select_pd ( + b, a, simde_mm_cmple_pd (simde_x_mm_abs_pd (a), simde_x_mm_abs_pd (b))); + + r = simde_x_mm_copysign_pd (r, a); + + return r; +} +int +test_simde_mm_mask_range_pd (void) +{ + + simde__m128d src, a, b, e, r; + + src = simde_mm_set_pd (-2.92, -85.39); + a = simde_mm_set_pd (-47.59, -122.31); + b = simde_mm_set_pd (877.42, 69.15); + e = simde_mm_set_pd (-47.59, -69.15); + r = simde_mm_mask_mov_pd (src, 143, simde_mm_range_pd (a, b, 2)); + do + { + if (simde_test_x86_assert_equal_f64x2_ ( + r, e, simde_test_f64_precision_to_slop (1), + "../test/x86/avx512/range.c", 1454, "r", "e")) + { + return 1; + } + } + while (0); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/loongarch/sign_extend_ashift.c b/gcc/testsuite/gcc.target/loongarch/sign_extend_ashift.c new file mode 100644 index 0000000..921fda9 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/sign_extend_ashift.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { loongarch64*-*-* } } } */ +/* { dg-options "-O3" } */ +/* { dg-final { scan-assembler "slli\\.w" } } */ +/* { dg-final { scan-assembler-not "slli\\.d" } } */ +/* { dg-final { scan-assembler-not "ext\\.w\\.b" } } */ + +unsigned int +test (unsigned int id) +{ + return id << 24; +} diff --git a/gcc/testsuite/gcc.target/loongarch/trap-1.c b/gcc/testsuite/gcc.target/loongarch/trap-1.c new file mode 100644 index 0000000..8936f60 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/trap-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -w -fisolate-erroneous-paths-dereference -mbreak-code=1" } */ +/* { dg-final { scan-assembler "break\\t1" } } */ + +int +bug (void) +{ + return *(int *)0; +} diff --git a/gcc/testsuite/gcc.target/loongarch/trap-default.c b/gcc/testsuite/gcc.target/loongarch/trap-default.c new file mode 100644 index 0000000..32948d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/trap-default.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -w -fisolate-erroneous-paths-dereference" } */ +/* { dg-final { scan-assembler "amswap\\.w\\t\\\$r0,\\\$r1,\\\$r0" } } */ + +int +bug (void) +{ + return *(int *)0; +} diff --git a/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-signed.c b/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-signed.c new file mode 100644 index 0000000..1e1e75f --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-signed.c @@ -0,0 +1,13 @@ +/* Verify optimization for mulw.d.w, + which can help with the replacement of the high-latency div.w. */ +/* { dg-do compile { target { loongarch64*-*-* } } } */ +/* { dg-options "-O3" } */ + +int +test (int a) +{ + return a / 3; +} + +/* { dg-final { scan-assembler {\tmulw.d.w\t} } } */ +/* { dg-final { scan-assembler-not {\tdiv.w\t} } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-unsigned.c b/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-unsigned.c new file mode 100644 index 0000000..32a428f --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-unsigned.c @@ -0,0 +1,11 @@ +/* Verify optimization for mulh.wu, which can reduce insns. */ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +int +test (unsigned int a) +{ + return a / 3; +} + +/* { dg-final { scan-assembler {\tmulh.wu\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr120553-2.c b/gcc/testsuite/gcc.target/riscv/pr120553-2.c index 1501f86..000f4bb 100644 --- a/gcc/testsuite/gcc.target/riscv/pr120553-2.c +++ b/gcc/testsuite/gcc.target/riscv/pr120553-2.c @@ -83,8 +83,8 @@ T1(63) #endif /* { dg-final { scan-assembler-times "\\t(srai)" 128 { target rv64 } } } */ -/* { dg-final { scan-assembler-times "\\t(orn|ori|bset)" 128 { target rv64 } } } */ +/* { dg-final { scan-assembler-times "\\t(orn|ori|bset)" 196 { target rv64 } } } */ /* { dg-final { scan-assembler-times "\\t(srai)" 64 { target rv32 } } } */ -/* { dg-final { scan-assembler-times "\\t(orn|ori|bset)" 64 { target rv32 } } } */ +/* { dg-final { scan-assembler-times "\\t(orn|ori|bset)" 66 { target rv32 } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr64345.c b/gcc/testsuite/gcc.target/riscv/pr64345.c new file mode 100644 index 0000000..8ca4e24 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr64345.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gcbv_zicond -mabi=lp64d" { target rv64 } } */ +/* { dg-options "-O2 -march=rv32gcbv_zicond -mabi=ilp32" { target rv32 } } */ + + + +unsigned int test0 (unsigned int x) { return ((x >> 4) ^ 1) & 1; } + +unsigned int test1 (unsigned int x) { return ((x >> 4) & 1) ^ 1; } + +unsigned int test2 (unsigned int x) { return ~(x >> 4) & 1; } + +unsigned int test3 (unsigned int x) { return ((~x >> 4) & 1); } + +unsigned int test4 (unsigned int x) { return (x >> 4) & 1; } + +int test5 (int vi) { return vi - (((vi >> 6) & 0x01) << 1); } + +int test6 (int vi) { return vi - (((vi >> 6) & 0x01) << 1) - 1; } + + +/* { dg-final { scan-assembler-times "\\tbexti" 5 } } */ +/* { dg-final { scan-assembler-times "\\txori" 3 } } */ +/* { dg-final { scan-assembler-times "\\tnot" 1 } } */ +/* { dg-final { scan-assembler-times "\\tsrli" 2 } } */ +/* { dg-final { scan-assembler-times "\\tandi" 2 } } */ +/* { dg-final { scan-assembler-times "\\tsub" 2 } } */ +/* { dg-final { scan-assembler-times "\\taddi" 1 } } */ + + diff --git a/gcc/testsuite/gcc.target/riscv/pr67731.c b/gcc/testsuite/gcc.target/riscv/pr67731.c new file mode 100644 index 0000000..6f254fc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr67731.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gcbv -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-O2 -march=rv32gcbv -mabi=ilp32" { target { rv32 } } } */ + +typedef struct +{ + _Bool a : 1; + _Bool b : 1; + _Bool c : 1; + _Bool d : 1; + unsigned int e : 4; +} S; + +_Bool test_00 (S* s) +{ + return s->b | s->c; +} + +_Bool test_01 (S* s) +{ + return s->b | s->c | s->d; +} +/* { dg-final { scan-assembler-times {\tlw\ta0,0\(a0\).*?\n\tandi\ta0,a0,\d+.*?\n\tsnez\ta0,a0.*?\n\tret} 2 } } */ +/* { dg-final { scan-assembler-not {\tor} } } */ +/* { dg-final { scan-assembler-not {\tbexti} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c index 32db3a6..e0d757a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c @@ -6,5 +6,6 @@ /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*2,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 } } */ /* { dg-final { scan-assembler-times {vmv\.x\.s} 2 } } */ /* { dg-final { scan-assembler-times {vslidedown.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 1 } } */ -/* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,[a-x0-9]+,32} 1 } } */ +/* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,[a-x0-9]+,32} 2 } } */ +/* { dg-final { scan-assembler-times {srli\s+[a-x0-9]+,[a-x0-9]+,32} 1 } } */ /* { dg-final { scan-assembler-times {or\s+[a-x0-9]+,[a-x0-9]+,[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c new file mode 100644 index 0000000..0e34bc1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c @@ -0,0 +1,150 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -w -O0" { target rv64 } } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -w -O0" { target rv32 } } */ + + +typedef int a; +typedef signed char b; +typedef char c; +typedef short d; +typedef unsigned short e; +typedef a f; +typedef unsigned g; +typedef long h; +h j, k, l, m, n, o; +int p, q, r, s; +short t; +volatile a u; +a v[]; +char w, x; +a *y, *z; +a **aa; +__attribute__((always_inline)) b __attribute__((vector_size(16))) +ab(f __attribute__((vector_size(8 * sizeof(f)))), d ac, + d __attribute__((vector_size(2 * sizeof(d)))), d) { + return __builtin_shufflevector( + (b __attribute__((vector_size(16)))) __builtin_convertvector( + (d __attribute__((vector_size(16 *sizeof(d))))){ + ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac}, + c __attribute__((vector_size(16)))) | + __builtin_convertvector( + (d __attribute__((vector_size(16 *sizeof(d))))){ + ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac}, + c __attribute__((vector_size(16)))), + __builtin_convertvector( + (d __attribute__((vector_size(16 *sizeof(d))))){ + ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac}, + b __attribute__((vector_size(16)))), + 3, 21, 0, 2, 2, 7, 1, 8, 4, 0, 8, 0, 8, 9, 5, 6); +} +__attribute__((always_inline)) g +ad(d ae, h __attribute__((vector_size(32 * sizeof(h))))) { + g f = 6318; + return (8 ? ae / 786856318u : 0) & ae; +} +a(af)(a, int); +void(ag)(long); +char(ah)(char, char); +char(ai)(char); +short(aj)(short, short); +int ak(long, int *, int *, char, int); +void al(signed, a *, int *, long); +char am(int *, short, short); +void an(int *, long, int); +void ao(int, int *, a *); +a ap() { + int *aq, *ar, *as; + short at; + char au, av, aw = 2; + long ax, ay, az = j; + int ba, i; + g __attribute__((vector_size(16 * sizeof(g)))) bb = {80}; + b __attribute__((vector_size(4))) bc = {6}; + int bd[1]; + char *be = &w; + int bf, bg = q; + a **bh[] = { + &y, &z, &z, &y, &y, &y, &y, &y, &z, &z, &y, &z, &y, &y, &y, &y, &z, &y, + &z, &y, &y, &y, &z, &z, &z, &y, &z, &z, &z, &y, &z, &z, &y, &z, &z, &y, + &z, &z, &z, &y, 0, &z, 0, &y, 0, &y, &y, &z, &z, &y, &y, 0, &z, 0, + &z, 0, &y, &z, &z, 0, &z, 0, &z, &z, &z, &y, &z, &z, &y, &z, &z, &y, + 0, &z, 0, &z, &z, &y, 0, &z, 0, &y, 0, &y, &y, &z, &z, &y, &y, 0, + &z, 0, &z, 0, &y, &z, &z, 0, &z, 0, &z, &z, &z, &y, &z, &z, &y, &z, + &z, &y, 0, &z, 0, &z, &z, &y, 0, &z, 0, &y, 0, &y, &y, &z, &z, &y, + &y, 0, &z, 0, &z, 0, &y, &z, &z, 0, &z, 0, &z, &z, &z, &y, &z, &z, + &y, &z, &z, &y, 0, &z, 0, &z, &z, &y, 0, &z, 0, &y, 0, &y, &y, &z, + &z, &y, &y, 0, &z, 0, &z, 0, &y, &z, &z, 0, 0, &z, 0, &z, &z, &z, + &y, &z, &z, &y, &z, &z, &y, 0, &z, 0, 0, &z, &z}; + for (; i; i++) + bd[i] = p; + h __attribute__((vector_size(32 * sizeof(h)))) + bi = {2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, + 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, + 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681}, + bj = __builtin_convertvector( + (c __attribute__((vector_size(32)))){ + aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, + aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw}, + h __attribute__((vector_size(32 * sizeof(h))))), + bk = __builtin_convertvector( + __builtin_shufflevector(bb, bb, 4, 8, 7, 9, 1, 10, 4, 7, 0, 4, 3, 5, 6, 7, + 6, 2, 2, 20, 6, 4, 7, 7, 9, 7, 4, 9, 8, 6, 1, 0, + 6, 9), + h __attribute__((vector_size(32 * sizeof(h))))); + bb = __builtin_convertvector( + ab(__builtin_shufflevector( + __builtin_shufflevector( + __builtin_convertvector( + __builtin_shufflevector(bb, bb, 1, 31, 8, 2, 3, 7, 4, 0, 7, + 3, 4, 6, 7, 1, 9, 3, 8, 7, 1, 8, 5, + 3, 9, 9, 0, 3, 2, 8, 5, 2, 5, 3), + f __attribute__((vector_size(32 * sizeof(f))))), + (f __attribute__((vector_size(32 * sizeof(f))))){ + 800761418310502961587690471176286910032020044212442466872080013589354162852207417903424527024812447907811618435019152886919380169872910001752451018659493155196043018716516518746289614523948734758456011127254301274351182132760058399143431214610613191313926994549901191890929084305862034120561651877003645}, + 32, 44), + (f __attribute__((vector_size(2 * sizeof(f))))){o}, 1, 0, 3, 0, 2, + 1, 3, 3), + ad(__builtin_clzg((g)aw, (f)bb[9]), + (h __attribute__((vector_size(32 * sizeof(h))))){ + bi[0] ?: bk[0], bi[1] ? 1 : bk[1], bi[2] ? 2 : bk[2], + bi[3] ? 3 : bk[3], bi[4] ? 4 : bk[4], bi[5] ? 5 : bk[5], + bi[6] ? 6 : bk[6], bi[7] ? 7 : bk[7], bi[8] ? 8 : bk[8], + bi[9] ? 9 : bk[9], bi[0] ? 10 : bk[0], bi[1] ? 1 : bk[1], + bi[2] ? 2 : bk[2], bi[3] ? 3 : bk[3], bi[4] ? 4 : bk[4], + bi[5] ? 5 : bk[5], bi[6] ? 6 : bk[6], bi[7] ? 7 : bk[7], + bi[8] ? 8 : bk[8], bi[9] ? 9 : bk[9], bi[0] ? 20 : bk[0], + bi[1] ? 1 : bk[1], bi[2] ? 2 : bk[2], bi[3] ? 3 : bk[3], + bi[4] ? bj[4] : 4, bi[5] ?: 5, bi[6] ?: 6, + bi[7] ? 0 : 7, bi[8] ?: 8, bi[9] ? 0 : 9, + bi[0] ? 0 : 30, bi[1] ?: 1}), + (d __attribute__((vector_size(2 * sizeof(d))))) + __builtin_shufflevector( + __builtin_convertvector( + __builtin_shufflevector(bb, bb, 2, 7, 21, 6), + e __attribute__((vector_size(4 * sizeof(e))))), + __builtin_convertvector( + (c __attribute__((vector_size(4)))){aw, aw}, + e __attribute__((vector_size(4 * sizeof(e))))), + 5, 1) + + (__builtin_convertvector( + __builtin_shufflevector(bb, bb, 4, 5), + e __attribute__((vector_size(2 * sizeof(e))))) <= + __builtin_convertvector( + (c __attribute__((vector_size(2)))){aw}, + e __attribute__((vector_size(2 * sizeof(e)))))), + n ? bb[5] << n : aw), + g __attribute__((vector_size(16 * sizeof(g))))); + ag(aw & t); + at = aj(aw, v[1]); + au = ah(at, aw); + ba = af((1 == ax != aw) <= aw <= au, aw); + ao(0, &bd[0], &r); + o = ay; + an(aq, aw, k); + av = am(ar, l, k); + *be = ai(*be); + al(x, as, &bd[0], aw); + bg = ak(u, &s, &bf, aw, aw); + as = *aa; + return m; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122445.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122445.c new file mode 100644 index 0000000..4736868 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122445.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcbv_zvl256b -mabi=lp64d -O3 -mrvv-vector-bits=zvl --param=riscv-autovec-mode=V4QI -mtune=generic-ooo -fdump-rtl-avlprop-all" } */ + +typedef unsigned char uint8_t; +typedef short int16_t; + +#define FDEC_STRIDE 32 + +static inline uint8_t x264_clip_uint8( int x ) +{ + return x; +} + +void +x264_add4x4_idct (uint8_t *p_dst, int16_t d[16]) +{ + for( int y = 0; y < 4; y++ ) + { + for( int x = 0; x < 4; x++ ) + p_dst[x] = x264_clip_uint8( p_dst[x] + d[y*4+x] ); + p_dst += FDEC_STRIDE; + } +} + +/* { dg-final { scan-rtl-dump "Propagating AVL: \\(const_int 4" "avlprop" } } */ +/* { dg-final { scan-rtl-dump-not "Propagating AVL: \\(const_int 1" "avlprop" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr122270-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr122270-1.c new file mode 100644 index 0000000..a026a7e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr122270-1.c @@ -0,0 +1,10 @@ +/* { dg-options "" } */ +/* { dg-do compile } */ +/* { dg-add-options riscv_v } */ +/* PR target/122270 */ + +#include "riscv_vector.h" + +void a(vfloat32m1_t b, vfloat32m1x4_t *c) { + *c = __riscv_vset_v_f32m1_f32m1x4(*c, 3, b); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_128bit_vector.c new file mode 100644 index 0000000..7091d2a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_256bit_vector.c new file mode 100644 index 0000000..da3ff2a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_32bit_vector.c new file mode 100644 index 0000000..907aa706 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_64bit_vector.c new file mode 100644 index 0000000..3036ada --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_all_mixed.c new file mode 100644 index 0000000..1a57881 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_call_mixed_function.c new file mode 100644 index 0000000..90ab8c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vector_elements.c new file mode 100644 index 0000000..4309984 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vectors_struct.c new file mode 100644 index 0000000..66cd626 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_width_vectors_struct.c new file mode 100644 index 0000000..09def6d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_width_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_equivalent_struct.c new file mode 100644 index 0000000..8cd74f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_four_registers.c new file mode 100644 index 0000000..837932c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..1c1564a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..e44a8af --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_args.c new file mode 100644 index 0000000..8b3b2a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_float_vector.c new file mode 100644 index 0000000..32f3de4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_int_vector.c new file mode 100644 index 0000000..ac2ef23 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct.c new file mode 100644 index 0000000..5b2ea03 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct_advanced.c new file mode 100644 index 0000000..6962363 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..0eb676e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_vector_types_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_unions.c new file mode 100644 index 0000000..5be696c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_unions.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_vectors.c new file mode 100644 index 0000000..3f3c5e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..3bab9a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion.c new file mode 100644 index 0000000..7ab38ee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..6fd3c0b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion_mixed.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_pressure_scenarios.c new file mode 100644 index 0000000..ca0f8b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_same_vectors_struct.c new file mode 100644 index 0000000..92acb96 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_same_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_simple_union.c new file mode 100644 index 0000000..201ff4e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_simple_union.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_register.c new file mode 100644 index 0000000..bb92880 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_vector_struct.c new file mode 100644 index 0000000..9cfa866 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..24478f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_different_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..21c918c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_eight_128bit_vectors.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 8 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..f32b61c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_five_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..8efa10f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_four_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..0204829 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_two_registers.c new file mode 100644 index 0000000..8a40a16 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_vector_array_struct.c new file mode 100644 index 0000000..94e516c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_vector_array_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_128bit_vector.c new file mode 100644 index 0000000..12acdaa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_256bit_vector.c new file mode 100644 index 0000000..ead0e70 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_32bit_vector.c new file mode 100644 index 0000000..c97a7c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_64bit_vector.c new file mode 100644 index 0000000..f3fb86d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_all_mixed.c new file mode 100644 index 0000000..7eeaa6b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_call_mixed_function.c new file mode 100644 index 0000000..0676290 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vector_elements.c new file mode 100644 index 0000000..dff67ab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vectors_struct.c new file mode 100644 index 0000000..40d4442 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_width_vectors_struct.c new file mode 100644 index 0000000..2cd1322 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_width_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_equivalent_struct.c new file mode 100644 index 0000000..6463c5c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_four_registers.c new file mode 100644 index 0000000..4d84a37 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..7e992f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..ab3027b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_args.c new file mode 100644 index 0000000..d16d14b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_float_vector.c new file mode 100644 index 0000000..5cd6e52 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_int_vector.c new file mode 100644 index 0000000..fb4aff9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct.c new file mode 100644 index 0000000..3db1d27 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct_advanced.c new file mode 100644 index 0000000..a8c07f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..0a230ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_vector_types_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_unions.c new file mode 100644 index 0000000..18051f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_unions.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_vectors.c new file mode 100644 index 0000000..25a6042 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..c9959ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion.c new file mode 100644 index 0000000..3da8d8f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..7fc773b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion_mixed.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_pressure_scenarios.c new file mode 100644 index 0000000..9c3cd79 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_same_vectors_struct.c new file mode 100644 index 0000000..42041b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_same_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_simple_union.c new file mode 100644 index 0000000..9ea145f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_simple_union.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_register.c new file mode 100644 index 0000000..a52c0a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_vector_struct.c new file mode 100644 index 0000000..f467fd5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..7d7bedd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_different_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..8e576f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_eight_128bit_vectors.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 8 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..5575aab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_five_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..6e9fd33 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_four_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..734d929 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_two_registers.c new file mode 100644 index 0000000..743d773 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_vector_array_struct.c new file mode 100644 index 0000000..dc4623e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_vector_array_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_128bit_vector.c new file mode 100644 index 0000000..6ee5565 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_256bit_vector.c new file mode 100644 index 0000000..363dd61 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_32bit_vector.c new file mode 100644 index 0000000..63e2a84 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_64bit_vector.c new file mode 100644 index 0000000..5c1269a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_all_mixed.c new file mode 100644 index 0000000..7580504 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_call_mixed_function.c new file mode 100644 index 0000000..1d494e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vector_elements.c new file mode 100644 index 0000000..9650ea4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vectors_struct.c new file mode 100644 index 0000000..41335d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_width_vectors_struct.c new file mode 100644 index 0000000..da85d52 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_width_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_equivalent_struct.c new file mode 100644 index 0000000..d2d0f07 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_four_registers.c new file mode 100644 index 0000000..c11c3e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..3862322 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..1ec92f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_args.c new file mode 100644 index 0000000..d0a01e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_float_vector.c new file mode 100644 index 0000000..9acf247 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_int_vector.c new file mode 100644 index 0000000..4d3265c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct.c new file mode 100644 index 0000000..63b5ea0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct_advanced.c new file mode 100644 index 0000000..8721f44 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..10efd1e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_vector_types_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_unions.c new file mode 100644 index 0000000..ab90555 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_unions.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_vectors.c new file mode 100644 index 0000000..8ec429b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..bf8f4d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion.c new file mode 100644 index 0000000..892fa74 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..8f28061 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion_mixed.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_pressure_scenarios.c new file mode 100644 index 0000000..e16b945 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_same_vectors_struct.c new file mode 100644 index 0000000..9e9c55d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_same_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_simple_union.c new file mode 100644 index 0000000..34f83d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_simple_union.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_register.c new file mode 100644 index 0000000..141684c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_vector_struct.c new file mode 100644 index 0000000..c275b40 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..2704451 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_different_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..30209a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_eight_128bit_vectors.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 8 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..3a3f4b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_five_256bit_vectors.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v12 \[ s\+128 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..9822d96 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_four_256bit_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..5231401 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_two_registers.c new file mode 100644 index 0000000..c313cfc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_vector_array_struct.c new file mode 100644 index 0000000..33843a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_vector_array_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_128bit_vector.c new file mode 100644 index 0000000..87d7ac3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_256bit_vector.c new file mode 100644 index 0000000..1c5b27d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_32bit_vector.c new file mode 100644 index 0000000..b985252 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_64bit_vector.c new file mode 100644 index 0000000..b12c6a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_all_mixed.c new file mode 100644 index 0000000..770bec6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_call_mixed_function.c new file mode 100644 index 0000000..dc5a6cd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vector_elements.c new file mode 100644 index 0000000..bed512b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vectors_struct.c new file mode 100644 index 0000000..0b56802 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_width_vectors_struct.c new file mode 100644 index 0000000..361bff7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_width_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_equivalent_struct.c new file mode 100644 index 0000000..42d7c95 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_four_registers.c new file mode 100644 index 0000000..a4897e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..90f15c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..166bc8d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_args.c new file mode 100644 index 0000000..5f95941 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_float_vector.c new file mode 100644 index 0000000..7cef54c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_int_vector.c new file mode 100644 index 0000000..d383a34 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct.c new file mode 100644 index 0000000..44c80b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct_advanced.c new file mode 100644 index 0000000..c173c0a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..bda5096 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_vector_types_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_unions.c new file mode 100644 index 0000000..58bac01 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_unions.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_vectors.c new file mode 100644 index 0000000..8294c54 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..2f0c620 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion.c new file mode 100644 index 0000000..9538ba0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..118627d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion_mixed.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_pressure_scenarios.c new file mode 100644 index 0000000..7b6737b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_same_vectors_struct.c new file mode 100644 index 0000000..04e1bef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_same_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_simple_union.c new file mode 100644 index 0000000..beaa25e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_simple_union.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_register.c new file mode 100644 index 0000000..d21028e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_vector_struct.c new file mode 100644 index 0000000..bab73584 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..11dd3c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_different_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..b1199d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_eight_128bit_vectors.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 8 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..fe48ae0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_five_256bit_vectors.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v12 \[ s\+128 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..d4026ba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_four_256bit_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..c6111b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_two_registers.c new file mode 100644 index 0000000..7c919f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_vector_array_struct.c new file mode 100644 index 0000000..c4c57f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_vector_array_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_128bit_vector.c new file mode 100644 index 0000000..8452f93 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_256bit_vector.c new file mode 100644 index 0000000..3579523 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_32bit_vector.c new file mode 100644 index 0000000..310c607 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_64bit_vector.c new file mode 100644 index 0000000..d34af19 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_64bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_all_mixed.c new file mode 100644 index 0000000..763f9b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_call_mixed_function.c new file mode 100644 index 0000000..eb7a97f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vector_elements.c new file mode 100644 index 0000000..2e34be5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vector_elements.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v12 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ int_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vectors_struct.c new file mode 100644 index 0000000..e3a2fd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_width_vectors_struct.c new file mode 100644 index 0000000..f3fdc9c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_width_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_equivalent_struct.c new file mode 100644 index 0000000..ca39ab1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_four_registers.c new file mode 100644 index 0000000..78674a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_four_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..dd02323 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_fp_vs_int_vectors.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ float_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..a304c3a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_large_vector_small_abi_vlen.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_args.c new file mode 100644 index 0000000..12a8530 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_float_vector.c new file mode 100644 index 0000000..777e0b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_int_vector.c new file mode 100644 index 0000000..16d31f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct.c new file mode 100644 index 0000000..1ec749a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct_advanced.c new file mode 100644 index 0000000..9bc0eac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..1e4f8a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_vector_types_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_unions.c new file mode 100644 index 0000000..01e3762 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_unions.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_vectors.c new file mode 100644 index 0000000..9004567 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..4f4a78d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion.c new file mode 100644 index 0000000..5400b18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..0fce4dd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion_mixed.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_pressure_scenarios.c new file mode 100644 index 0000000..661e1ce --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_pressure_scenarios.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v10 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ medium2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_same_vectors_struct.c new file mode 100644 index 0000000..92d4204 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_same_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_simple_union.c new file mode 100644 index 0000000..581b350 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_simple_union.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_register.c new file mode 100644 index 0000000..beb8e04 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_vector_struct.c new file mode 100644 index 0000000..f569caf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..7801147 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_different_abi_vlen.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..72cb536 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_eight_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..ccc1d79 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_five_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..12c054f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_four_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..723c1f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_two_registers.c new file mode 100644 index 0000000..1cea3bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_vector_array_struct.c new file mode 100644 index 0000000..ede6525 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_vector_array_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_128bit_vector.c new file mode 100644 index 0000000..a5d4b1d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_256bit_vector.c new file mode 100644 index 0000000..2c405c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_32bit_vector.c new file mode 100644 index 0000000..917bc54 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_64bit_vector.c new file mode 100644 index 0000000..b158857 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_64bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_all_mixed.c new file mode 100644 index 0000000..51dc947 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_call_mixed_function.c new file mode 100644 index 0000000..3227893 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vector_elements.c new file mode 100644 index 0000000..a49f7a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vector_elements.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v12 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ int_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vectors_struct.c new file mode 100644 index 0000000..33dba6a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_width_vectors_struct.c new file mode 100644 index 0000000..4b16990 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_width_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_equivalent_struct.c new file mode 100644 index 0000000..c82fd43 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_four_registers.c new file mode 100644 index 0000000..42afa82 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_four_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..690c296 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_fp_vs_int_vectors.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ float_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..2a23285 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_large_vector_small_abi_vlen.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_args.c new file mode 100644 index 0000000..76d3252 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_float_vector.c new file mode 100644 index 0000000..97ac4b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_int_vector.c new file mode 100644 index 0000000..02327db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct.c new file mode 100644 index 0000000..609dd0e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct_advanced.c new file mode 100644 index 0000000..db015da --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..955543f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_vector_types_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_unions.c new file mode 100644 index 0000000..ca2fbb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_unions.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_vectors.c new file mode 100644 index 0000000..f6d8fa2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..1d033fa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion.c new file mode 100644 index 0000000..98e7e6f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..4a62377 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion_mixed.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_pressure_scenarios.c new file mode 100644 index 0000000..22b934c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_pressure_scenarios.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v10 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ medium2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_same_vectors_struct.c new file mode 100644 index 0000000..ae92296 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_same_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_simple_union.c new file mode 100644 index 0000000..9ca77c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_simple_union.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_register.c new file mode 100644 index 0000000..e78ac7c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_vector_struct.c new file mode 100644 index 0000000..db93b2a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..6ebb269 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_different_abi_vlen.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..06c309e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_eight_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..cd3d77a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_five_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..deaa87e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_four_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..82ef5ba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_two_registers.c new file mode 100644 index 0000000..da2d81f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_vector_array_struct.c new file mode 100644 index 0000000..7236598 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_vector_array_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 32 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_128bit_vector.c new file mode 100644 index 0000000..9681dd2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_256bit_vector.c new file mode 100644 index 0000000..cb54cd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_32bit_vector.c new file mode 100644 index 0000000..345dcac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_64bit_vector.c new file mode 100644 index 0000000..429d9e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_all_mixed.c new file mode 100644 index 0000000..30a46c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_call_mixed_function.c new file mode 100644 index 0000000..a108985 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vector_elements.c new file mode 100644 index 0000000..fe3aa71 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vectors_struct.c new file mode 100644 index 0000000..26ddf7d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_width_vectors_struct.c new file mode 100644 index 0000000..30670f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_width_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_equivalent_struct.c new file mode 100644 index 0000000..943629a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_four_registers.c new file mode 100644 index 0000000..d98678b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..8503f32 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..ebebf6d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_args.c new file mode 100644 index 0000000..ad0d837 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_float_vector.c new file mode 100644 index 0000000..2842f1b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_int_vector.c new file mode 100644 index 0000000..4b774e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct.c new file mode 100644 index 0000000..89a5e09 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct_advanced.c new file mode 100644 index 0000000..d8bdc98 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..779a4dc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_vector_types_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_unions.c new file mode 100644 index 0000000..6974e22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_unions.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_vectors.c new file mode 100644 index 0000000..d0257af --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..5e566db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion.c new file mode 100644 index 0000000..5fe493b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..4b484d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion_mixed.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_pressure_scenarios.c new file mode 100644 index 0000000..5bcd85c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_same_vectors_struct.c new file mode 100644 index 0000000..eae391f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_same_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_simple_union.c new file mode 100644 index 0000000..b3dcc28 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_simple_union.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_register.c new file mode 100644 index 0000000..af8afb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_vector_struct.c new file mode 100644 index 0000000..32c31920 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..615ed1d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_different_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..0ceab39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_eight_128bit_vectors.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 8 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..d41c3de --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_five_256bit_vectors.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v12 \[ s\+128 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..50360c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_four_256bit_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..7d75572 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_two_registers.c new file mode 100644 index 0000000..8eda297 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_vector_array_struct.c new file mode 100644 index 0000000..e006469 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_vector_array_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_128bit_vector.c new file mode 100644 index 0000000..905a938 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_256bit_vector.c new file mode 100644 index 0000000..ba3692d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_32bit_vector.c new file mode 100644 index 0000000..09a3fa0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_64bit_vector.c new file mode 100644 index 0000000..458541c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_all_mixed.c new file mode 100644 index 0000000..89037c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_call_mixed_function.c new file mode 100644 index 0000000..8658b79 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vector_elements.c new file mode 100644 index 0000000..662ce5c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vectors_struct.c new file mode 100644 index 0000000..66371f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_width_vectors_struct.c new file mode 100644 index 0000000..2888f17 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_width_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_equivalent_struct.c new file mode 100644 index 0000000..4f7b64b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_four_registers.c new file mode 100644 index 0000000..4cbb415 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..4a7d548 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..adf003c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_args.c new file mode 100644 index 0000000..7695777 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_float_vector.c new file mode 100644 index 0000000..8811b6f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_int_vector.c new file mode 100644 index 0000000..29753e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct.c new file mode 100644 index 0000000..113be1e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct_advanced.c new file mode 100644 index 0000000..be8fdca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..7ae31a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_vector_types_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_unions.c new file mode 100644 index 0000000..232afe4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_unions.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_vectors.c new file mode 100644 index 0000000..bbc2b80 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..2fcc2d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion.c new file mode 100644 index 0000000..489ea6f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..195d264 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion_mixed.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_pressure_scenarios.c new file mode 100644 index 0000000..78f336d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_same_vectors_struct.c new file mode 100644 index 0000000..9226884 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_same_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_simple_union.c new file mode 100644 index 0000000..409b863 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_simple_union.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_register.c new file mode 100644 index 0000000..1fb5c69 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_vector_struct.c new file mode 100644 index 0000000..68da0d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..0306514 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_different_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..ae6da97 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_eight_128bit_vectors.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 8 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..037f2ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_five_256bit_vectors.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v12 \[ s\+128 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..3027ab1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_four_256bit_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..3032001 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_two_registers.c new file mode 100644 index 0000000..698664a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_vector_array_struct.c new file mode 100644 index 0000000..c7663f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_vector_array_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 512 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_128bit_vector.c new file mode 100644 index 0000000..7a35b97 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_256bit_vector.c new file mode 100644 index 0000000..b6acb4e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_32bit_vector.c new file mode 100644 index 0000000..29a1542 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_64bit_vector.c new file mode 100644 index 0000000..8dd0416 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_all_mixed.c new file mode 100644 index 0000000..471ac7a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_call_mixed_function.c new file mode 100644 index 0000000..e0823a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vector_elements.c new file mode 100644 index 0000000..e014d94 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v10 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v14 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vectors_struct.c new file mode 100644 index 0000000..3bfc462 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_width_vectors_struct.c new file mode 100644 index 0000000..3d29761 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_width_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_equivalent_struct.c new file mode 100644 index 0000000..cbef719 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_four_registers.c new file mode 100644 index 0000000..96d92ca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..4f508e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v12 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..7de41a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_args.c new file mode 100644 index 0000000..dc83d6e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_float_vector.c new file mode 100644 index 0000000..86f7a14 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_int_vector.c new file mode 100644 index 0000000..ca07249 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct.c new file mode 100644 index 0000000..1247eed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct_advanced.c new file mode 100644 index 0000000..99b5313 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..a125bd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_vector_types_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_unions.c new file mode 100644 index 0000000..e6af0c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_unions.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_vectors.c new file mode 100644 index 0000000..403aee0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..91998a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion.c new file mode 100644 index 0000000..6805d40 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v8 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..f15093d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion_mixed.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v8 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_pressure_scenarios.c new file mode 100644 index 0000000..734b067 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_same_vectors_struct.c new file mode 100644 index 0000000..d28675d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_same_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_simple_union.c new file mode 100644 index 0000000..134c809 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_simple_union.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_register.c new file mode 100644 index 0000000..c2a5747b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_vector_struct.c new file mode 100644 index 0000000..892daa0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..9b19e20 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_different_abi_vlen.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..9172575 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_eight_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..bbf8033 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_five_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..980e363 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_four_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..8b0e14c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_two_registers.c new file mode 100644 index 0000000..61c7280 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_vector_array_struct.c new file mode 100644 index 0000000..22f7dc3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_vector_array_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_128bit_vector.c new file mode 100644 index 0000000..d61053a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_256bit_vector.c new file mode 100644 index 0000000..59a97df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_32bit_vector.c new file mode 100644 index 0000000..71553f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_64bit_vector.c new file mode 100644 index 0000000..8d46ab8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_all_mixed.c new file mode 100644 index 0000000..00c3e18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_call_mixed_function.c new file mode 100644 index 0000000..0f9a1f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vector_elements.c new file mode 100644 index 0000000..f2c8506 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v10 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v14 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vectors_struct.c new file mode 100644 index 0000000..64f917f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_width_vectors_struct.c new file mode 100644 index 0000000..6757c1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_width_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_equivalent_struct.c new file mode 100644 index 0000000..b30f25f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_four_registers.c new file mode 100644 index 0000000..2d0f69a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_fp_vs_int_vectors.c new file mode 100644 index 0000000..f9f846a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v12 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_large_vector_small_abi_vlen.c new file mode 100644 index 0000000..3c76859 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_args.c new file mode 100644 index 0000000..b596feb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_float_vector.c new file mode 100644 index 0000000..d68dcef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_int_vector.c new file mode 100644 index 0000000..69f03db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct.c new file mode 100644 index 0000000..c8523aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct_advanced.c new file mode 100644 index 0000000..08466aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_vector_types_struct.c new file mode 100644 index 0000000..70ad96e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_vector_types_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_unions.c new file mode 100644 index 0000000..44de280 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_unions.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_vectors.c new file mode 100644 index 0000000..40c61aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_with_small_abi_vlen.c new file mode 100644 index 0000000..e963bb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion.c new file mode 100644 index 0000000..71c2383 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v8 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion_mixed.c new file mode 100644 index 0000000..b209eac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion_mixed.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v8 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_pressure_scenarios.c new file mode 100644 index 0000000..bd31c14 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_same_vectors_struct.c new file mode 100644 index 0000000..2fe18f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_same_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_simple_union.c new file mode 100644 index 0000000..c5c3816 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_simple_union.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_register.c new file mode 100644 index 0000000..9adf114 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_vector_struct.c new file mode 100644 index 0000000..acaf297 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_different_abi_vlen.c new file mode 100644 index 0000000..3904243 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_different_abi_vlen.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_eight_128bit_vectors.c new file mode 100644 index 0000000..e017645 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_eight_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_five_256bit_vectors.c new file mode 100644 index 0000000..c36af06 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_five_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_four_256bit_vectors.c new file mode 100644 index 0000000..c2e65cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_four_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_nine_128bit_vectors.c new file mode 100644 index 0000000..ba015a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_two_registers.c new file mode 100644 index 0000000..a3a7cf9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_vector_array_struct.c new file mode 100644 index 0000000..66780fb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_vector_array_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 64 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_128bit_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_128bit_vector.h new file mode 100644 index 0000000..0732cf5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_128bit_vector.h @@ -0,0 +1,13 @@ +// Test: Two 128-bit vectors behavior under different ABI_VLEN + +#include "../vls-cc-common.h" + +int32x4_t VLS_CC(ABI_VLEN) test_128bit_vector(int32x4_t vec1, int32x4_t vec2) { + // Two 128-bit vectors: + // - ABI_VLEN=128: each uses 1 vector register (2 total) + // - ABI_VLEN=64: each uses 2 vector registers (4 total) + // - ABI_VLEN=32: each uses 4 vector registers (8 total) + int32x4_t result; + result = vec1 + vec2; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_256bit_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_256bit_vector.h new file mode 100644 index 0000000..18b99bf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_256bit_vector.h @@ -0,0 +1,14 @@ +// Test: Two 256-bit vectors behavior under different ABI_VLEN + +#include "../vls-cc-common.h" + +int32x8_t VLS_CC(ABI_VLEN) test_256bit_vector(int32x8_t vec1, int32x8_t vec2) { + // Two 256-bit vectors: + // - ABI_VLEN=256: each uses 1 vector register (2 total) + // - ABI_VLEN=128: each uses 2 vector registers (4 total) + // - ABI_VLEN=64: each uses 4 vector registers (8 total) + // - ABI_VLEN=32: each uses 8 vector registers (16 total) + int32x8_t result; + result = vec1 + vec2; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_32bit_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_32bit_vector.h new file mode 100644 index 0000000..e18b8e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_32bit_vector.h @@ -0,0 +1,13 @@ +// Test: Two 32-bit vectors (very small vectors) + +#include "../vls-cc-common.h" + +int16x2_t VLS_CC(ABI_VLEN) test_32bit_vector(int16x2_t vec1, int16x2_t vec2) { + // Two 32-bit vectors: + // - Each always uses 1 vector register regardless of ABI_VLEN + // - Uses even smaller portion when ABI_VLEN > 32 + int16x2_t result; + result[0] = vec1[0] + vec2[0]; + result[1] = vec1[1] + vec2[1]; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_64bit_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_64bit_vector.h new file mode 100644 index 0000000..dc3a2c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_64bit_vector.h @@ -0,0 +1,13 @@ +// Test: Two 64-bit vectors (always fit in one register each) + +#include "../vls-cc-common.h" + +int32x2_t VLS_CC(ABI_VLEN) test_64bit_vector(int32x2_t vec1, int32x2_t vec2) { + // Two 64-bit vectors: + // - Each always uses 1 vector register regardless of ABI_VLEN + // - Only uses portion of the register when ABI_VLEN > 64 + int32x2_t result; + result[0] = vec1[0] + vec2[0]; + result[1] = vec1[1] + vec2[1]; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_all_mixed.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_all_mixed.h new file mode 100644 index 0000000..6cc50b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_all_mixed.h @@ -0,0 +1,13 @@ +// Test: All three types mixed (int, float, vector) + +#include "../vls-cc-common.h" + +double VLS_CC(ABI_VLEN) test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) { + // int i -> a0 (integer register) + // float f -> fa0 (FP register) + // int32x4_t vec1 -> v8 (vector register) + // double d -> fa1 (FP register) + // float32x4_t vec2 -> v9 (vector register) + // int j -> a1 (integer register) + return i + f + vec1[0] + d + vec2[0] + j; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_call_mixed_function.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_call_mixed_function.h new file mode 100644 index 0000000..e5cd837 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_call_mixed_function.h @@ -0,0 +1,14 @@ +// Test: Function pointers with mixed signatures + +#include "../vls-cc-common.h" + +typedef int (*mixed_func_ptr_t)(int, int32x4_t, float) VLS_CC(ABI_VLEN); + +// Helper function to be called via function pointer +int VLS_CC(ABI_VLEN) helper_mixed_function(int i, int32x4_t v, float f) { + return i + v[0] + (int)f; +} + +int VLS_CC(ABI_VLEN) test_call_mixed_function(mixed_func_ptr_t func, int i, int32x4_t v, float f) { + return func(i, v, f); +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vector_elements.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vector_elements.h new file mode 100644 index 0000000..3ef700b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vector_elements.h @@ -0,0 +1,10 @@ +// Test: Vector types with different element types in same call + +#include "../vls-cc-common.h" + +int VLS_CC(ABI_VLEN) test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, + int32x4_t int_vec, int64x2_t long_vec) { + // All are 128-bit vectors but with different element types + // Should all use same vector register allocation rules + return byte_vec[0] + short_vec[0] + int_vec[0] + (int)long_vec[0]; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vectors_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vectors_struct.h new file mode 100644 index 0000000..b7c1e48 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vectors_struct.h @@ -0,0 +1,9 @@ +// Test: Struct with different sized vectors - uses hardware FP calling convention + +#include "../vls-cc-common.h" + +struct_different_vectors_t VLS_CC(ABI_VLEN) test_different_vectors_struct(struct_different_vectors_t s) { + // Contains int32x2_t (64 bits) and int32x4_t (128 bits) - different lengths + // Should use hardware floating-point calling convention, not vector registers + return s; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_width_vectors_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_width_vectors_struct.h new file mode 100644 index 0000000..a0b8e15 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_width_vectors_struct.h @@ -0,0 +1,27 @@ +// Test: Struct with two vectors of different widths but same total size +// int32x4_t (128 bits, 4 x 32-bit) and int16x8_t (128 bits, 8 x 16-bit) - both should be flattened + +#include "../vls-cc-common.h" + +typedef struct { + int32x4_t wide_vec; // 128-bit vector with 4 x 32-bit elements + int16x8_t narrow_vec; // 128-bit vector with 8 x 16-bit elements +} different_width_vectors_struct_t; + +different_width_vectors_struct_t VLS_CC(ABI_VLEN) test_different_width_vectors_struct(different_width_vectors_struct_t s) { + // Should be flattened and passed as two separate vector arguments + // wide_vec should use first vector register, narrow_vec should use second vector register + different_width_vectors_struct_t result; + + // Process wide vector: add 100 to each 32-bit element + for (int i = 0; i < 4; i++) { + result.wide_vec[i] = s.wide_vec[i] + 100; + } + + // Process narrow vector: add 10 to each 16-bit element + for (int i = 0; i < 8; i++) { + result.narrow_vec[i] = s.narrow_vec[i] + 10; + } + + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_equivalent_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_equivalent_struct.h new file mode 100644 index 0000000..859fc10 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_equivalent_struct.h @@ -0,0 +1,14 @@ +// Test: Compare struct vs union behavior + +#include "../vls-cc-common.h" + +// Struct equivalent to union (should use vector calling convention) +typedef struct { + int32x4_t vec; +} equivalent_struct_t; + +equivalent_struct_t VLS_CC(ABI_VLEN) test_equivalent_struct(equivalent_struct_t s) { + // This struct should use vector calling convention (flattened) + // Compare behavior with the union version + return s; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_four_registers.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_four_registers.h new file mode 100644 index 0000000..e53d417 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_four_registers.h @@ -0,0 +1,11 @@ +// Test: Two vectors passed in eight registers (<= 4 * ABI_VLEN bits each) +// int32x16_t (512 bits) should use 4 registers each when ABI_VLEN = 128 + +#include "../vls-cc-common.h" + +int32x16_t VLS_CC(ABI_VLEN) test_four_registers(int32x16_t vec1, int32x16_t vec2) { + // Add vectors element-wise + int32x16_t result; + result = vec1 + vec2; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_fp_vs_int_vectors.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_fp_vs_int_vectors.h new file mode 100644 index 0000000..649dc13 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_fp_vs_int_vectors.h @@ -0,0 +1,10 @@ +// Test: Floating-point vectors vs integer vectors + +#include "../vls-cc-common.h" + +float VLS_CC(ABI_VLEN) test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, + double64x2_t double_vec) { + // All vectors should use vector registers, regardless of element type + // Element type shouldn't affect register allocation for fixed-length vectors + return int_vec[0] + float_vec[0] + (float)double_vec[0]; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_large_vector_small_abi_vlen.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_large_vector_small_abi_vlen.h new file mode 100644 index 0000000..90627cf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_large_vector_small_abi_vlen.h @@ -0,0 +1,13 @@ +// Test: Two large vectors that might be passed by reference with small ABI_VLEN + +#include "../vls-cc-common.h" + +int32x16_t VLS_CC(ABI_VLEN) test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) { + // Two 512-bit vectors: + // - ABI_VLEN=128: each uses 4 registers (8 total, fits in available registers) + // - ABI_VLEN=64: each needs 8 registers (16 total, exceeds available, passed by reference) + // - ABI_VLEN=32: each needs 16 registers (32 total, far exceeds available, passed by reference) + int32x16_t result; + result = vec1 + vec2; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_args.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_args.h new file mode 100644 index 0000000..c6d91e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_args.h @@ -0,0 +1,8 @@ +// Test: Mixed scalar and vector arguments + +#include "../vls-cc-common.h" + +int VLS_CC(ABI_VLEN) test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) { + // scalars use integer/float registers, vectors use vector registers + return scalar1 + (int)scalar2 + vec1[0] + vec2[0]; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_float_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_float_vector.h new file mode 100644 index 0000000..03ca452 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_float_vector.h @@ -0,0 +1,10 @@ +// Test: Mixed floating-point scalars and vectors + +#include "../vls-cc-common.h" + +float VLS_CC(ABI_VLEN) test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) { + // Float scalars should use FP registers (fa0, fa1, ...) + // Vectors should use vector registers (v8, v9, ...) + // Different register classes should not interfere + return f1 + (float)d1 + vec[0] + vec2[0]; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_int_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_int_vector.h new file mode 100644 index 0000000..f379534 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_int_vector.h @@ -0,0 +1,10 @@ +// Test: Mixed integer scalars and vectors + +#include "../vls-cc-common.h" + +int VLS_CC(ABI_VLEN) test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) { + // Scalars should use integer registers (a0, a1, a2, ...) + // Vectors should use vector registers (v8, v9, ...) + // Should not interfere with each other's register allocation + return a + b + vec[0] + vec2[0]; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct.h new file mode 100644 index 0000000..fb289be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct.h @@ -0,0 +1,8 @@ +// Test: Struct with mixed vector and scalar - uses hardware FP calling convention + +#include "../vls-cc-common.h" + +struct_mixed_t VLS_CC(ABI_VLEN) test_mixed_struct(struct_mixed_t s) { + // Contains vector and scalar - should use hardware FP calling convention + return s; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct_advanced.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct_advanced.h new file mode 100644 index 0000000..5660a16 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct_advanced.h @@ -0,0 +1,15 @@ +// Test: Vector and scalar struct members (advanced mixed struct) + +#include "../vls-cc-common.h" + +typedef struct { + int scalar; + int32x4_t vector; + float fp_scalar; +} mixed_struct_advanced_t; + +mixed_struct_advanced_t VLS_CC(ABI_VLEN) test_mixed_struct_advanced(mixed_struct_advanced_t s) { + // Should use hardware FP calling convention due to mixed types + // Vector part will be treated according to standard struct rules + return s; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_vector_types_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_vector_types_struct.h new file mode 100644 index 0000000..d916423 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_vector_types_struct.h @@ -0,0 +1,23 @@ +// Test: Struct with two vectors of same width but different types +// int32x4_t (128 bits) and float32x4_t (128 bits) - both should be flattened + +#include "../vls-cc-common.h" + +typedef struct { + int32x4_t int_vec; // 128-bit integer vector + float32x4_t float_vec; // 128-bit float vector +} mixed_vector_types_struct_t; + +mixed_vector_types_struct_t VLS_CC(ABI_VLEN) test_mixed_vector_types_struct(mixed_vector_types_struct_t s) { + // Should be flattened and passed as two separate vector arguments + // int_vec should use first vector register, float_vec should use second vector register + mixed_vector_types_struct_t result; + + // Combine the vectors: add 10 to int elements, multiply float elements by 2.0 + for (int i = 0; i < 4; i++) { + result.int_vec[i] = s.int_vec[i] + 10; + result.float_vec[i] = s.float_vec[i] * 2.0f; + } + + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_unions.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_unions.h new file mode 100644 index 0000000..2205020 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_unions.h @@ -0,0 +1,14 @@ +// Test: Multiple union arguments + +#include "../vls-cc-common.h" + +union_vector_t VLS_CC(ABI_VLEN) test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) { + // All should use integer calling convention + // Should consume integer registers, not vector registers + union_vector_t result; + result.scalars[0] = u1.scalars[0] + u2.scalars[0] + u3.scalars[0]; + result.scalars[1] = u1.scalars[1] + u2.scalars[1] + u3.scalars[1]; + result.scalars[2] = u1.scalars[2] + u2.scalars[2] + u3.scalars[2]; + result.scalars[3] = u1.scalars[3] + u2.scalars[3] + u3.scalars[3]; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_vectors.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_vectors.h new file mode 100644 index 0000000..96c8009 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_vectors.h @@ -0,0 +1,12 @@ +// Test: Multiple vector arguments consuming available registers + +#include "../vls-cc-common.h" + +int32x4_t VLS_CC(ABI_VLEN) test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) { + // Each vector uses 1 register, total 3 registers + int32x4_t result = {v1[0] + v2[0] + v3[0], + v1[1] + v2[1] + v3[1], + v1[2] + v2[2] + v3[2], + v1[3] + v2[3] + v3[3]}; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_with_small_abi_vlen.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_with_small_abi_vlen.h new file mode 100644 index 0000000..39a957e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_with_small_abi_vlen.h @@ -0,0 +1,12 @@ +// Test: Multiple vectors that may exceed register count with small ABI_VLEN + +#include "../vls-cc-common.h" + +int32x4_t VLS_CC(ABI_VLEN) test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, + int32x4_t v3, int32x4_t v4) { + // With ABI_VLEN=32, each 128-bit vector needs 4 registers + // 4 vectors * 4 registers = 16 registers needed + // Will exceed available vector registers, some passed by reference + int32x4_t result = {v1[0] + v2[0], v1[1] + v3[1], v1[2] + v4[2], v1[3] + v2[3]}; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion.h new file mode 100644 index 0000000..6662185 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion.h @@ -0,0 +1,15 @@ +// Test: Vector register exhaustion - should fall back to reference passing + +#include "../vls-cc-common.h" + +int32x4_t VLS_CC(ABI_VLEN) test_register_exhaustion( + int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, + int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, + int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, + int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, + int32x4_t v17) { + // First 16 vectors (v1-v16) should use vector registers v8-v23 + // 17th vector (v17) should be passed by reference due to register exhaustion + int32x4_t result = {v1[0] + v17[0], v2[1] + v17[1], v3[2] + v17[2], v4[3] + v17[3]}; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion_mixed.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion_mixed.h new file mode 100644 index 0000000..3825584 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion_mixed.h @@ -0,0 +1,21 @@ +// Test: Large number of mixed arguments to test register exhaustion + +#include "../vls-cc-common.h" + +int VLS_CC(ABI_VLEN) test_register_exhaustion_mixed( + // Integer arguments (use a0-a7) + int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, + // FP arguments (use fa0-fa7) + float f1, float f2, float f3, float f4, float f5, float f6, float f7, float f8, float f9, + // Vector arguments (use v8-v23, 16 registers available) + int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, + int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, + int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, + int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, + int32x4_t v17 +) { + // i9, f9 should be passed via stack due to integer/FP register exhaustion + // v1-v16 should use vector registers v8-v23 + // v17 should be passed via stack/memory due to vector register exhaustion + return i1 + i9 + (int)f1 + (int)f9 + v1[0] + v17[0]; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_pressure_scenarios.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_pressure_scenarios.h new file mode 100644 index 0000000..e55c56b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_pressure_scenarios.h @@ -0,0 +1,15 @@ +// Test: Function demonstrating register pressure with different ABI_VLEN + +#include "../vls-cc-common.h" + +void VLS_CC(ABI_VLEN) test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, + int32x4_t medium1, int32x4_t medium2, + int32x8_t large1) { + // Different register consumption based on ABI_VLEN: + // ABI_VLEN=128: 2 * 1 + 2 * 1 + 1 * 2 = 6 registers + // ABI_VLEN=64: 2 * 1 + 2 * 2 + 1 * 4 = 10 registers (exceeds 8, some by reference) + // ABI_VLEN=32: 2 * 2 + 2 * 4 + 1 * 8 = 20 registers (many by reference) + + // Just use the parameters to avoid warnings + (void)small1; (void)small2; (void)medium1; (void)medium2; (void)large1; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_same_vectors_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_same_vectors_struct.h new file mode 100644 index 0000000..d5cd78d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_same_vectors_struct.h @@ -0,0 +1,10 @@ +// Test: Struct with two same-length vectors - should be passed as vector tuple + +#include "../vls-cc-common.h" + +struct_two_same_vectors_t VLS_CC(ABI_VLEN) test_same_vectors_struct(struct_two_same_vectors_t s) { + // Should be passed in vector registers like a vector tuple + // Both vectors are int32x4_t (128 bits each), total 256 bits + // Should use 2 vector registers when ABI_VLEN = 128 + return s; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_simple_union.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_simple_union.h new file mode 100644 index 0000000..09c57c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_simple_union.h @@ -0,0 +1,9 @@ +// Test: Simple union with vector - should use integer calling convention + +#include "../vls-cc-common.h" + +union_vector_t VLS_CC(ABI_VLEN) test_simple_union(union_vector_t u) { + // Union with fixed-length vector should always use integer calling convention + // Should NOT use vector registers, even though it contains a vector + return u; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_register.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_register.h new file mode 100644 index 0000000..b65a1e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_register.h @@ -0,0 +1,11 @@ +// Test: Two vectors passed in registers (<= ABI_VLEN bits each) +// int32x4_t (128 bits) should use 1 register per vector when ABI_VLEN >= 128 + +#include "../vls-cc-common.h" + +int32x4_t VLS_CC(ABI_VLEN) test_single_register(int32x4_t vec1, int32x4_t vec2) { + // Add vectors element-wise + int32x4_t result; + result = vec1 + vec2; + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_vector_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_vector_struct.h new file mode 100644 index 0000000..7d1d2a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_vector_struct.h @@ -0,0 +1,8 @@ +// Test: Struct with single vector - should be flattened + +#include "../vls-cc-common.h" + +struct_single_vector_t VLS_CC(ABI_VLEN) test_single_vector_struct(struct_single_vector_t s) { + // Should be flattened and passed as single vector argument + return s; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_different_abi_vlen.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_different_abi_vlen.h new file mode 100644 index 0000000..b0b388e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_different_abi_vlen.h @@ -0,0 +1,17 @@ +// Test: Struct behavior under different ABI_VLEN + +#include "../vls-cc-common.h" + +typedef struct { + int32x4_t vec1; + int32x4_t vec2; +} two_medium_vectors_t; + +two_medium_vectors_t VLS_CC(ABI_VLEN) test_struct_different_abi_vlen(two_medium_vectors_t s) { + // Struct with 2 * 128-bit vectors (256 bits total): + // - ABI_VLEN=256: fits in single "vector tuple" concept, uses 2 registers + // - ABI_VLEN=128: each vector uses 1 register, total 2 registers + // - ABI_VLEN=64: each vector uses 2 registers, total 4 registers + // - ABI_VLEN=32: each vector uses 4 registers, total 8 registers + return s; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_eight_128bit_vectors.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_eight_128bit_vectors.h new file mode 100644 index 0000000..78b9d50 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_eight_128bit_vectors.h @@ -0,0 +1,38 @@ +// Test: Struct with eight 128-bit vectors +// Each int32x4_t is 128 bits (4 x 32-bit elements) +// Total: 8 vectors * 128 bits = 1024 bits +// With ABI_VLEN=128: 8 vectors * 1 register each = 8 registers (fits in 16 available) + +#include "../vls-cc-common.h" + +typedef struct { + int32x4_t vec1; // 128-bit vector + int32x4_t vec2; // 128-bit vector + int32x4_t vec3; // 128-bit vector + int32x4_t vec4; // 128-bit vector + int32x4_t vec5; // 128-bit vector + int32x4_t vec6; // 128-bit vector + int32x4_t vec7; // 128-bit vector + int32x4_t vec8; // 128-bit vector +} eight_128bit_vectors_struct_t; + +eight_128bit_vectors_struct_t VLS_CC(ABI_VLEN) test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) { + // Should be flattened and passed as separate vector arguments + // With ABI_VLEN=128: vec1 uses v8, vec2 uses v9, ..., vec8 uses v15 + // Total uses 8 out of 16 available vector argument registers + eight_128bit_vectors_struct_t result; + + // Process each 128-bit vector: multiply by (index + 1) + for (int i = 0; i < 4; i++) { + result.vec1[i] = s.vec1[i] * 1; + result.vec2[i] = s.vec2[i] * 2; + result.vec3[i] = s.vec3[i] * 3; + result.vec4[i] = s.vec4[i] * 4; + result.vec5[i] = s.vec5[i] * 5; + result.vec6[i] = s.vec6[i] * 6; + result.vec7[i] = s.vec7[i] * 7; + result.vec8[i] = s.vec8[i] * 8; + } + + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_five_256bit_vectors.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_five_256bit_vectors.h new file mode 100644 index 0000000..190cafd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_five_256bit_vectors.h @@ -0,0 +1,33 @@ +// Test: Struct with five 256-bit vectors +// Each int32x8_t is 256 bits (8 x 32-bit elements) +// Total: 5 vectors * 256 bits = 1280 bits +// With ABI_VLEN=128: 5 vectors * 2 registers each = 10 registers (fits in 16 available) + +#include "../vls-cc-common.h" + +typedef struct { + int32x8_t vec1; // 256-bit vector + int32x8_t vec2; // 256-bit vector + int32x8_t vec3; // 256-bit vector + int32x8_t vec4; // 256-bit vector + int32x8_t vec5; // 256-bit vector +} five_256bit_vectors_struct_t; + +five_256bit_vectors_struct_t VLS_CC(ABI_VLEN) test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) { + // Should be flattened and passed as separate vector arguments + // With ABI_VLEN=128: vec1 uses v8+v9, vec2 uses v10+v11, vec3 uses v12+v13, + // vec4 uses v14+v15, vec5 uses v16+v17 + // Total uses 10 out of 16 available vector argument registers + five_256bit_vectors_struct_t result; + + // Process each 256-bit vector: add different values to each vector + for (int i = 0; i < 8; i++) { + result.vec1[i] = s.vec1[i] + 1000; + result.vec2[i] = s.vec2[i] + 2000; + result.vec3[i] = s.vec3[i] + 3000; + result.vec4[i] = s.vec4[i] + 4000; + result.vec5[i] = s.vec5[i] + 5000; + } + + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_four_256bit_vectors.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_four_256bit_vectors.h new file mode 100644 index 0000000..02e9cfe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_four_256bit_vectors.h @@ -0,0 +1,30 @@ +// Test: Struct with four 256-bit vectors +// Each int32x8_t is 256 bits (8 x 32-bit elements) +// Total: 4 vectors * 256 bits = 1024 bits +// With ABI_VLEN=128: 4 vectors * 2 registers each = 8 registers (fits in 16 available) + +#include "../vls-cc-common.h" + +typedef struct { + int32x8_t vec1; // 256-bit vector + int32x8_t vec2; // 256-bit vector + int32x8_t vec3; // 256-bit vector + int32x8_t vec4; // 256-bit vector +} four_256bit_vectors_struct_t; + +four_256bit_vectors_struct_t VLS_CC(ABI_VLEN) test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) { + // Should be flattened and passed as separate vector arguments + // With ABI_VLEN=128: vec1 uses v8+v9, vec2 uses v10+v11, vec3 uses v12+v13, vec4 uses v14+v15 + // With ABI_VLEN=256: vec1 uses v8, vec2 uses v9, vec3 uses v10, vec4 uses v11 + four_256bit_vectors_struct_t result; + + // Process each 256-bit vector: add 100 to first element, add 200 to second element, etc. + for (int i = 0; i < 8; i++) { + result.vec1[i] = s.vec1[i] + 100; + result.vec2[i] = s.vec2[i] + 200; + result.vec3[i] = s.vec3[i] + 300; + result.vec4[i] = s.vec4[i] + 400; + } + + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_nine_128bit_vectors.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_nine_128bit_vectors.h new file mode 100644 index 0000000..fe77bc8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_nine_128bit_vectors.h @@ -0,0 +1,40 @@ +// Test: Struct with nine 128-bit vectors +// Each int32x4_t is 128 bits (4 x 32-bit elements) +// Total: 9 vectors * 128 bits = 1152 bits +// With ABI_VLEN=128: 9 vectors * 1 register each = 9 registers (fits in 16 available) + +#include "../vls-cc-common.h" + +typedef struct { + int32x4_t vec1; // 128-bit vector + int32x4_t vec2; // 128-bit vector + int32x4_t vec3; // 128-bit vector + int32x4_t vec4; // 128-bit vector + int32x4_t vec5; // 128-bit vector + int32x4_t vec6; // 128-bit vector + int32x4_t vec7; // 128-bit vector + int32x4_t vec8; // 128-bit vector + int32x4_t vec9; // 128-bit vector +} nine_128bit_vectors_struct_t; + +nine_128bit_vectors_struct_t VLS_CC(ABI_VLEN) test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) { + // Should be flattened and passed as separate vector arguments + // With ABI_VLEN=128: vec1 uses v8, vec2 uses v9, ..., vec9 uses v16 + // Total uses 9 out of 16 available vector argument registers + nine_128bit_vectors_struct_t result; + + // Process each 128-bit vector: add vector index * 100 to each element + for (int i = 0; i < 4; i++) { + result.vec1[i] = s.vec1[i] + 100; + result.vec2[i] = s.vec2[i] + 200; + result.vec3[i] = s.vec3[i] + 300; + result.vec4[i] = s.vec4[i] + 400; + result.vec5[i] = s.vec5[i] + 500; + result.vec6[i] = s.vec6[i] + 600; + result.vec7[i] = s.vec7[i] + 700; + result.vec8[i] = s.vec8[i] + 800; + result.vec9[i] = s.vec9[i] + 900; + } + + return result; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_two_registers.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_two_registers.h new file mode 100644 index 0000000..b9fe523 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_two_registers.h @@ -0,0 +1,8 @@ +// Test: Vector passed in two registers (<= 2 * ABI_VLEN bits) +// int32x8_t (256 bits) should use 2 registers when ABI_VLEN = 128 + +#include "../vls-cc-common.h" + +int32x8_t VLS_CC(ABI_VLEN) test_two_registers(int32x8_t vec, int32x8_t vec2) { + return vec + vec2; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_vector_array_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_vector_array_struct.h new file mode 100644 index 0000000..77a84d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_vector_array_struct.h @@ -0,0 +1,9 @@ +// Test: Struct with vector array - should be passed as vector tuple + +#include "../vls-cc-common.h" + +struct_vector_array_t VLS_CC(ABI_VLEN) test_vector_array_struct(struct_vector_array_t s) { + // Array of 2 int32x4_t vectors, should be passed as vector tuple + // Total size: 256 bits, should use 2 vector registers + return s; +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/riscv-vls-cc.exp b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/riscv-vls-cc.exp new file mode 100644 index 0000000..68b4067 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/riscv-vls-cc.exp @@ -0,0 +1,63 @@ +# Copyright (C) 2025 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't a RISC-V target. +if ![istarget riscv*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# Initialize `dg'. +dg-init + +# Main loop. +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS + +# Test for specific XLEN and VLEN. +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-32-xlen-32/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-32-xlen-64/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-64-xlen-32/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-64-xlen-64/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-128-xlen-32/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-128-xlen-64/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-256-xlen-32/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-256-xlen-64/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-512-xlen-32/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-512-xlen-64/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_large_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_large_vector.c new file mode 100644 index 0000000..69a47ad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_large_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Large vector with ABI_VLEN=128 + +#include "vls-cc-common.h" + +int32x8_t __attribute__((riscv_vls_cc(128))) test_128_abi_vlen_large_vector(int32x8_t vec) { + // 256-bit vector with ABI_VLEN=128 -> uses 2 registers + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_medium_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_medium_vector.c new file mode 100644 index 0000000..3c179d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_medium_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Medium vector with ABI_VLEN=128 + +#include "vls-cc-common.h" + +int32x4_t __attribute__((riscv_vls_cc(128))) test_128_abi_vlen_medium_vector(int32x4_t vec) { + // 128-bit vector with ABI_VLEN=128 -> uses 1 register + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_large_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_large_vector.c new file mode 100644 index 0000000..ba0630d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_large_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Large vector with ABI_VLEN=256 + +#include "vls-cc-common.h" + +int32x8_t __attribute__((riscv_vls_cc(256))) test_256_abi_vlen_large_vector(int32x8_t vec) { + // 256-bit vector with ABI_VLEN=256 -> uses 1 register + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_very_large_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_very_large_vector.c new file mode 100644 index 0000000..503f9ce --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_very_large_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Very large vector with ABI_VLEN=256 + +#include "vls-cc-common.h" + +int32x16_t __attribute__((riscv_vls_cc(256))) test_256_abi_vlen_very_large_vector(int32x16_t vec) { + // 512-bit vector with ABI_VLEN=256 -> uses 2 registers + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ v8\)[[:space:]]+\(reg.*:V16SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_medium_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_medium_vector.c new file mode 100644 index 0000000..496b77c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_medium_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Medium vector with ABI_VLEN=32 + +#include "vls-cc-common.h" + +int32x4_t __attribute__((riscv_vls_cc(32))) test_32_abi_vlen_medium_vector(int32x4_t vec) { + // 128-bit vector with ABI_VLEN=32 -> uses 4 registers + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_small_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_small_vector.c new file mode 100644 index 0000000..1b44a09 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_small_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Small vector with ABI_VLEN=32 + +#include "vls-cc-common.h" + +int32x2_t __attribute__((riscv_vls_cc(32))) test_32_abi_vlen_small_vector(int32x2_t vec) { + // 64-bit vector with ABI_VLEN=32 -> uses 2 registers + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_medium_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_medium_vector.c new file mode 100644 index 0000000..c1f3673 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_medium_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Medium vector with ABI_VLEN=64 + +#include "vls-cc-common.h" + +int32x4_t __attribute__((riscv_vls_cc(64))) test_64_abi_vlen_medium_vector(int32x4_t vec) { + // 128-bit vector with ABI_VLEN=64 -> uses 2 registers + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_small_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_small_vector.c new file mode 100644 index 0000000..241e897 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_small_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Small vector with ABI_VLEN=64 + +#include "vls-cc-common.h" + +int32x2_t __attribute__((riscv_vls_cc(64))) test_64_abi_vlen_small_vector(int32x2_t vec) { + // 64-bit vector with ABI_VLEN=64 -> uses 1 register + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/vls-cc-common.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/vls-cc-common.h new file mode 100644 index 0000000..105f5a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/vls-cc-common.h @@ -0,0 +1,125 @@ +#ifndef VLS_CC_COMMON_H +#define VLS_CC_COMMON_H + +#include <stdint-gcc.h> + +// Check if ABI_VLEN is defined +#ifndef ABI_VLEN +#define ABI_VLEN 128 // Default fallback value +#endif + +// VLS Calling Convention attribute macro +#define VLS_CC(ABI_VLEN) \ + __attribute__((riscv_vls_cc(ABI_VLEN))) + +// Fixed-length vector type definitions following <basetype><width>x<num>_t naming convention +// These use GCC/Clang __attribute__((vector_size(N))) extension + +// 8-bit integer vectors +typedef int8_t int8x2_t __attribute__((vector_size(2))); +typedef int8_t int8x4_t __attribute__((vector_size(4))); +typedef int8_t int8x8_t __attribute__((vector_size(8))); +typedef int8_t int8x16_t __attribute__((vector_size(16))); +typedef int8_t int8x32_t __attribute__((vector_size(32))); +typedef int8_t int8x64_t __attribute__((vector_size(64))); + +typedef uint8_t uint8x2_t __attribute__((vector_size(2))); +typedef uint8_t uint8x4_t __attribute__((vector_size(4))); +typedef uint8_t uint8x8_t __attribute__((vector_size(8))); +typedef uint8_t uint8x16_t __attribute__((vector_size(16))); +typedef uint8_t uint8x32_t __attribute__((vector_size(32))); +typedef uint8_t uint8x64_t __attribute__((vector_size(64))); + +// 16-bit integer vectors +typedef int16_t int16x2_t __attribute__((vector_size(4))); +typedef int16_t int16x4_t __attribute__((vector_size(8))); +typedef int16_t int16x8_t __attribute__((vector_size(16))); +typedef int16_t int16x16_t __attribute__((vector_size(32))); +typedef int16_t int16x32_t __attribute__((vector_size(64))); + +typedef uint16_t uint16x2_t __attribute__((vector_size(4))); +typedef uint16_t uint16x4_t __attribute__((vector_size(8))); +typedef uint16_t uint16x8_t __attribute__((vector_size(16))); +typedef uint16_t uint16x16_t __attribute__((vector_size(32))); +typedef uint16_t uint16x32_t __attribute__((vector_size(64))); + +// 32-bit integer vectors +typedef int32_t int32x2_t __attribute__((vector_size(8))); +typedef int32_t int32x4_t __attribute__((vector_size(16))); +typedef int32_t int32x8_t __attribute__((vector_size(32))); +typedef int32_t int32x16_t __attribute__((vector_size(64))); + +typedef uint32_t uint32x2_t __attribute__((vector_size(8))); +typedef uint32_t uint32x4_t __attribute__((vector_size(16))); +typedef uint32_t uint32x8_t __attribute__((vector_size(32))); +typedef uint32_t uint32x16_t __attribute__((vector_size(64))); + +// 64-bit integer vectors +typedef int64_t int64x2_t __attribute__((vector_size(16))); +typedef int64_t int64x4_t __attribute__((vector_size(32))); +typedef int64_t int64x8_t __attribute__((vector_size(64))); + +typedef uint64_t uint64x2_t __attribute__((vector_size(16))); +typedef uint64_t uint64x4_t __attribute__((vector_size(32))); +typedef uint64_t uint64x8_t __attribute__((vector_size(64))); + +// Floating-point vectors (following the same pattern) +typedef float float32x2_t __attribute__((vector_size(8))); +typedef float float32x4_t __attribute__((vector_size(16))); +typedef float float32x8_t __attribute__((vector_size(32))); +typedef float float32x16_t __attribute__((vector_size(64))); + +typedef double double64x2_t __attribute__((vector_size(16))); +typedef double double64x4_t __attribute__((vector_size(32))); +typedef double double64x8_t __attribute__((vector_size(64))); + +// Test structures containing fixed-length vectors +typedef struct { + int32x4_t vec1; + int32x4_t vec2; +} struct_two_same_vectors_t; + +typedef struct { + int32x4_t vec; +} struct_single_vector_t; + +typedef struct { + int32x4_t vec_array[2]; +} struct_vector_array_t; + +typedef struct { + int32x2_t vec1; + int32x4_t vec2; // Different sizes +} struct_different_vectors_t; + +typedef struct { + int32x4_t vec; + int scalar; +} struct_mixed_t; + +// Union containing fixed-length vectors (always uses integer calling convention) +typedef union { + int32x4_t vec; + int32_t scalars[4]; +} union_vector_t; + +// Function pointer types for testing +typedef int32x4_t (*func_return_vector_t)(int32x4_t); +typedef void (*func_pass_vector_t)(int32x4_t); +typedef struct_single_vector_t (*func_return_struct_t)(struct_single_vector_t); + +// Test constants for initialization +#define INIT_INT32X4(a, b, c, d) (int32x4_t){a, b, c, d} +#define INIT_FLOAT32X4(a, b, c, d) (float32x4_t){a, b, c, d} +#define INIT_INT16X8(a, b, c, d, e, f, g, h) (int16x8_t){a, b, c, d, e, f, g, h} + +#ifdef SUPPORT_NON_POWER_OF_2_VEC +#define INIT_INT32X3(a, b, c) (int32x3_t){a, b, c} +#define INIT_FLOAT32X3(a, b, c) (float32x3_t){a, b, c} +#endif + +// Utility macros for vector operations testing +#define VEC_SIZE_BYTES(type) sizeof(type) +#define VEC_ELEMENT_COUNT(type, element_type) (sizeof(type) / sizeof(element_type)) + +#endif // VLS_CC_COMMON_H diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-01.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-01.c index f9f3222..9d8a772 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-01.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-01.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-Oz" "-Os" } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-O1" "-Oz" "-Os" } } */ int foo1(int rs1) { diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-02.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-02.c index 112c0fa..430d998 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-02.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-02.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gc_zbb -mabi=ilp32" } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-Oz" "-Os" } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-O1" "-Oz" "-Os" } } */ int foo1(int rs1) { diff --git a/gcc/testsuite/gcc.target/sh/pr67731.c b/gcc/testsuite/gcc.target/sh/pr67731.c new file mode 100644 index 0000000..43c1657 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr67731.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -m4 -ml" } */ + +typedef struct +{ + _Bool a : 1; + _Bool b : 1; + _Bool c : 1; + _Bool d : 1; + unsigned int e : 4; +} S; + +_Bool test_00 (S* s) +{ + return s->b | s->c; +} + +_Bool test_01 (S* s) +{ + return s->b | s->c | s->d; +} + +/* { dg-final { scan-assembler-times {\ttst} 2 } } */ +/* { dg-final { scan-assembler-times {\tnegc} 2 } } */ +/* { dg-final { scan-assembler-not {\tor} } } */ diff --git a/gcc/testsuite/gcc.target/xtensa/one_cmpl_abs.c b/gcc/testsuite/gcc.target/xtensa/one_cmpl_abs.c deleted file mode 100644 index 608f65f..0000000 --- a/gcc/testsuite/gcc.target/xtensa/one_cmpl_abs.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O1" } */ - -int one_cmpl_abs(int a) -{ - return a < 0 ? ~a : a; -} - -/* { dg-final { scan-assembler-not "bgez" } } */ |