diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
608 files changed, 16765 insertions, 515 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/cmpbr-1.c b/gcc/testsuite/gcc.target/aarch64/cmpbr-1.c new file mode 100644 index 0000000..39f1549 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cmpbr-1.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* PR target/121385 */ + +#pragma GCC target "+cmpbr" + +struct DWstruct { + long low, high; +}; +typedef union { + struct DWstruct s; + __int128 ll; +} DWunion; +__int128 f(__int128 u) { + if (u >> 64 == 0) + { + __int128 t = (__int128)(unsigned long )u * 2; + DWunion ww; + ww.ll = t; + ww.s.high -= 1; + if (ww.s.high >= 0) + return ww.ll; + } + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/cmpbr-2.c b/gcc/testsuite/gcc.target/aarch64/cmpbr-2.c new file mode 100644 index 0000000..2c2764f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cmpbr-2.c @@ -0,0 +1,110 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* PR target/121388 */ + +#pragma GCC target "+cmpbr" + +extern int a, b, s; +typedef struct { + unsigned long d[2]; +} g; +typedef struct { + long d[4]; +} h; +typedef struct { + unsigned long d[]; +} j; +typedef struct { + long d[]; +} k; +typedef union { + struct { + short l; + unsigned m; + } i; + long double f; +} n; +g o[] = {{}}; +const g aa[1]; +h ab, t; +h ac[1]; +long p, r, ae, af, ag, ah, aj, ak, al, an, ao, aq, ar, aw, ax, ba, bb, bc, bd; +unsigned long q, am, ay, w; +g ad; +unsigned ai, ap, at, au, av, az; +short as, v, be; +long double u; +double f() { + long bf; + g c; + unsigned long bg; + int e, bh; + j x; + if (q << 61 == 3ull << 61) { + if (q & 58) { + return u; + } + as = 8; + return a; + } + e = c.d[1] = q & ((1ull << 49) - 1); + bg = p; + if (101086242752 < c.d[1] || + (101086242752 == c.d[1] && 4003012203950112767 < p)) + c.d[1] = p; + if (c.d[1] && p == 0) { + n bi; + bi.i.l = be; + return bi.f; + } + s = c.d[1] == 0 ? p ?: p : __builtin_clzll(c.d[1]); + s == 0 ? c.d[1] : s >= 64 ? c.d[1] : (c.d[1] = s, bg = 0); + if (e >= 3) { + if (a) { + n bi; + bi.i.m = 0; + return bi.f; + } + return ar; + } + if (e <= -4985) + e = 4985; + ad = (aa + 5)[e]; + bh = s; + if (r && (bg = 0)) + t = ab; + t = ac[e]; + k bj, bk; + ao = bg; + az = bg; + al = az; + ay = aw = bg >> 2; + b = ay + (aq > 2) < bg * ap; + ay = az; + bd = av = w; + ah = bb; + bj.d[4] = am; + an = c.d[1] >> an; + ax = bg * az; + aj = t.d[1]; + az = w = ax; + bb = az; + ag = aj; + long bl = af = w + az < w; + au = aw; + am = au < w || w < ak + am; + bk.d[3] = bl + az; + ai = a < aj; + at = aj + b < ai; + x.d[3] = ba; + bc = bk.d[3] + bc + bj.d[4]; + bf = ae; + if (x.d[3] || o[bf & 1].d[0]) { + if (bf == 0) + ; + else if (bf == 3 && bh) + if ((a & 3 && x.d[3] < 3ull << 62) || (q && x.d[3])) + b = 6; + } + return a; +} diff --git a/gcc/testsuite/gcc.target/aarch64/cmpbr-3.c b/gcc/testsuite/gcc.target/aarch64/cmpbr-3.c new file mode 100644 index 0000000..a4f12de --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cmpbr-3.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2" } */ + +#pragma GCC target "+cmpbr" + +long aarch64_fallback_frame_state_tpidr2_0; +unsigned short aarch64_fallback_frame_state_tpidr2_1, aarch64_fallback_frame_state_za_ctx_0; +void aarch64_fallback_frame_state_za_buffer() +{ + long num_slices = aarch64_fallback_frame_state_tpidr2_1; + if (aarch64_fallback_frame_state_tpidr2_1 > aarch64_fallback_frame_state_za_ctx_0) + num_slices = aarch64_fallback_frame_state_za_ctx_0; + __builtin_memcpy((void *)aarch64_fallback_frame_state_tpidr2_0, + aarch64_fallback_frame_state_za_buffer, num_slices); +} diff --git a/gcc/testsuite/gcc.target/aarch64/cmpbr.c b/gcc/testsuite/gcc.target/aarch64/cmpbr.c index a86af9d..23f462f 100644 --- a/gcc/testsuite/gcc.target/aarch64/cmpbr.c +++ b/gcc/testsuite/gcc.target/aarch64/cmpbr.c @@ -1,6 +1,5 @@ // Test that the instructions added by FEAT_CMPBR are emitted // { dg-do compile } -// { dg-do-if assemble { target aarch64_asm_cmpbr_ok } } // { dg-options "-march=armv9.5-a+cmpbr -O2" } // { dg-final { check-function-bodies "**" "*/" "" { target *-*-* } {\.L[0-9]+} } } @@ -121,7 +120,7 @@ FAR_BRANCH(u64, 42); /* ** u8_x0_eq_x1: -** cbbeq w1, w0, .L([0-9]+) +** cbbeq (?:w1, w0|w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -129,7 +128,7 @@ FAR_BRANCH(u64, 42); /* ** u8_x0_ne_x1: -** cbbne w1, w0, .L([0-9]+) +** cbbne (?:w1, w0|w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -137,7 +136,7 @@ FAR_BRANCH(u64, 42); /* ** u8_x0_ult_x1: -** cbbhi w1, w0, .L([0-9]+) +** (?:cbbhi w1, w0|cbblo w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -145,7 +144,7 @@ FAR_BRANCH(u64, 42); /* ** u8_x0_ule_x1: -** cbbhs w1, w0, .L([0-9]+) +** (?:cbbhs w1, w0|cbbls w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -153,7 +152,7 @@ FAR_BRANCH(u64, 42); /* ** u8_x0_ugt_x1: -** cbblo w1, w0, .L([0-9]+) +** (?:cbblo w1, w0|cbbhi w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -161,7 +160,7 @@ FAR_BRANCH(u64, 42); /* ** u8_x0_uge_x1: -** cbbls w1, w0, .L([0-9]+) +** (?:cbbls w1, w0|cbbhs w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -169,7 +168,7 @@ FAR_BRANCH(u64, 42); /* ** i8_x0_slt_x1: -** cbbgt w1, w0, .L([0-9]+) +** (?:cbbgt w1, w0|cbblt w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -177,7 +176,7 @@ FAR_BRANCH(u64, 42); /* ** i8_x0_sle_x1: -** cbbge w1, w0, .L([0-9]+) +** (?:cbbge w1, w0|cbble w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -185,7 +184,7 @@ FAR_BRANCH(u64, 42); /* ** i8_x0_sgt_x1: -** cbblt w1, w0, .L([0-9]+) +** (?:cbblt w1, w0|cbbgt w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -193,7 +192,7 @@ FAR_BRANCH(u64, 42); /* ** i8_x0_sge_x1: -** cbble w1, w0, .L([0-9]+) +** (?:cbble w1, w0|cbbge w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -201,7 +200,7 @@ FAR_BRANCH(u64, 42); /* ** u16_x0_eq_x1: -** cbheq w1, w0, .L([0-9]+) +** cbheq (?:w1, w0|w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -209,7 +208,7 @@ FAR_BRANCH(u64, 42); /* ** u16_x0_ne_x1: -** cbhne w0|w1, w1|w0, .L([0-9]+) +** cbhne (?:w1, w0|w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -217,7 +216,7 @@ FAR_BRANCH(u64, 42); /* ** u16_x0_ult_x1: -** cbhhi w1, w0, .L([0-9]+) +** (?:cbhhi w1, w0|cbhlo w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -225,7 +224,7 @@ FAR_BRANCH(u64, 42); /* ** u16_x0_ule_x1: -** cbhhs w1, w0, .L([0-9]+) +** (?:cbhhs w1, w0|cbhls w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -233,7 +232,7 @@ FAR_BRANCH(u64, 42); /* ** u16_x0_ugt_x1: -** cbhlo w1, w0, .L([0-9]+) +** (?:cbhlo w1, w0|cbhhi w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -241,7 +240,7 @@ FAR_BRANCH(u64, 42); /* ** u16_x0_uge_x1: -** cbhls w1, w0, .L([0-9]+) +** (?:cbhls w1, w0|cbhhs w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -249,7 +248,7 @@ FAR_BRANCH(u64, 42); /* ** i16_x0_slt_x1: -** cbhgt w1, w0, .L([0-9]+) +** (?:cbhgt w1, w0|cbhlt w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -257,7 +256,7 @@ FAR_BRANCH(u64, 42); /* ** i16_x0_sle_x1: -** cbhge w1, w0, .L([0-9]+) +** (?:cbhge w1, w0|cbhle w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -265,7 +264,7 @@ FAR_BRANCH(u64, 42); /* ** i16_x0_sgt_x1: -** cbhlt w1, w0, .L([0-9]+) +** (?:cbhlt w1, w0|cbhgt w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -273,7 +272,7 @@ FAR_BRANCH(u64, 42); /* ** i16_x0_sge_x1: -** cbhle w1, w0, .L([0-9]+) +** (?:cbhle w1, w0|cbhge w0, w1), .L([0-9]+) ** b not_taken ** .L\1: ** b taken @@ -1274,7 +1273,7 @@ FAR_BRANCH(u64, 42); */ /* -** u32_x0_ult_64: +** u32_x0_ult_64: { xfail *-*-* } ** cbhi w0, 63, .L([0-9]+) ** b taken ** .L\1: @@ -1309,7 +1308,7 @@ FAR_BRANCH(u64, 42); */ /* -** i32_x0_slt_64: +** i32_x0_slt_64: { xfail *-*-* } ** cbgt w0, 63, .L([0-9]+) ** b taken ** .L\1: @@ -1362,7 +1361,7 @@ FAR_BRANCH(u64, 42); */ /* -** u64_x0_ult_64: +** u64_x0_ult_64: { xfail *-*-* } ** cbhi x0, 63, .L([0-9]+) ** b taken ** .L\1: @@ -1397,7 +1396,7 @@ FAR_BRANCH(u64, 42); */ /* -** i64_x0_slt_64: +** i64_x0_slt_64: { xfail *-*-* } ** cbgt x0, 63, .L([0-9]+) ** b taken ** .L\1: diff --git a/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-3.c b/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-3.c index e2391555..7a76b14 100644 --- a/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-3.c +++ b/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-3.c @@ -7,7 +7,7 @@ void run (void (*)()); ** bar.0: ** ... ** hint 40 // chkfeat x16 -** tbnz w16, 0, (\.L[0-9]+) +** cbnz x16, (\.L[0-9]+) ** ... ** mrs (x[0-9]+), s3_3_c2_c5_1 // gcspr_el0 ** subs x[0-9]+, x[0-9]+, \2 diff --git a/gcc/testsuite/gcc.target/aarch64/ifcvt_multiple_sets_rewire.c b/gcc/testsuite/gcc.target/aarch64/ifcvt_multiple_sets_rewire.c index 448425f..2f28756 100644 --- a/gcc/testsuite/gcc.target/aarch64/ifcvt_multiple_sets_rewire.c +++ b/gcc/testsuite/gcc.target/aarch64/ifcvt_multiple_sets_rewire.c @@ -14,7 +14,5 @@ void cond1(int cond, int x, int y, int z) sink2(x, y); } -/* { dg-final { scan-assembler-times "csel\tw0, w0, w1" 1 } } */ -/* { dg-final { scan-assembler-times "csel\tw1, w3, w2" 1 } } */ - +/* { dg-final { scan-assembler-times "csel" 2 } } */ /* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_convert_multiple_sets" 1 "ce1" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-0.c b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-0.c new file mode 100644 index 0000000..e544b04f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-0.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-require-effective-target mmap } */ +/* { dg-options "-Wno-experimental-fmv-target" } */ + +#include <stdint.h> + +typedef struct { + uint64_t size; +} ifunc_arg_t; + +#include "ifunc-resolver.in" diff --git a/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-1.c b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-1.c new file mode 100644 index 0000000..be70687 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-1.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-require-effective-target mmap } */ +/* { dg-options "-Wno-experimental-fmv-target" } */ + +#include <stdint.h> + +typedef struct { + uint64_t size; + uint64_t hwcap; +} ifunc_arg_t; + +#include "ifunc-resolver.in" diff --git a/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-2.c b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-2.c new file mode 100644 index 0000000..bf594d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-2.c @@ -0,0 +1,14 @@ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-require-effective-target mmap } */ +/* { dg-options "-Wno-experimental-fmv-target" } */ + +#include <stdint.h> + +typedef struct { + uint64_t size; + uint64_t hwcap; + uint64_t hwcap2; +} ifunc_arg_t; + +#include "ifunc-resolver.in" diff --git a/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-3.c b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-3.c new file mode 100644 index 0000000..f16d01b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-3.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-require-effective-target mmap } */ +/* { dg-options "-Wno-experimental-fmv-target" } */ + +#include <stdint.h> + +typedef struct { + uint64_t size; + uint64_t hwcap; + uint64_t hwcap2; + uint64_t hwcap3; +} ifunc_arg_t; + +#include "ifunc-resolver.in" diff --git a/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-4.c b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-4.c new file mode 100644 index 0000000..1b4ccbd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver-4.c @@ -0,0 +1,16 @@ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-require-effective-target mmap } */ +/* { dg-options "-Wno-experimental-fmv-target" } */ + +#include <stdint.h> + +typedef struct { + uint64_t size; + uint64_t hwcap; + uint64_t hwcap2; + uint64_t hwcap3; + uint64_t hwcap4; +} ifunc_arg_t; + +#include "ifunc-resolver.in" diff --git a/gcc/testsuite/gcc.target/aarch64/ifunc-resolver.in b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver.in new file mode 100644 index 0000000..ada0b33 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ifunc-resolver.in @@ -0,0 +1,48 @@ +#include <unistd.h> +#include <string.h> +#include <sys/mman.h> + +/* Allocate memory buffer of size LEN with a protected page + following right after the buffer end so that any memory + accesses past the end of the buffer would trigger SEGFAUL. */ +void *allocate_mem (size_t len) +{ + size_t pagesize = sysconf (_SC_PAGESIZE); + char *m = mmap (NULL, pagesize * 2, + PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, + -1, 0); + mprotect (m + pagesize, pagesize, PROT_NONE); + m = m + pagesize - len; + memset(m, 0, len); + return m; +} + +int impl () +{ + return 0; +} + +#ifndef _IFUNC_ARG_HWCAP +#define _IFUNC_ARG_HWCAP (1ULL << 62) +#endif + +void +__init_cpu_features_resolver (unsigned long hwcap, const void *arg); + +static void * +fun_resolver (uint64_t a0, const uint64_t *a1) +{ + ifunc_arg_t *arg = allocate_mem (sizeof (ifunc_arg_t)); + arg->size = sizeof (ifunc_arg_t); + /* Call this function with synthetic ifunc_arg_t arg. */ + __init_cpu_features_resolver (_IFUNC_ARG_HWCAP, arg); + return (void *)(uintptr_t)impl; +} + +int fun (void) __attribute__ ((ifunc ("fun_resolver"))); + +int main (int argc, char *argv[]) +{ + return fun (); +} diff --git a/gcc/testsuite/gcc.target/aarch64/pr120986-1.c b/gcc/testsuite/gcc.target/aarch64/pr120986-1.c new file mode 100644 index 0000000..e3bc56c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr120986-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8.2-a+sve2+fp8dot2" } */ +#include <arm_sve.h> + +/* This triggered an ICE with an unrecognizable insn due to incorrect gating of + the insn in the backend. */ +svfloat16_t foo(svfloat16_t a, svmfloat8_t b, svmfloat8_t c, unsigned long fpm) +{ + return svdot_lane_fpm (a, b, c, 0, fpm); +} diff --git a/gcc/testsuite/gcc.target/aarch64/pr121253.c b/gcc/testsuite/gcc.target/aarch64/pr121253.c new file mode 100644 index 0000000..37de605 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr121253.c @@ -0,0 +1,16 @@ +/* { dg-options "-O" } */ + +struct s128 { + long a, b; +}; + +struct s128 foo(void) { + struct s128 ret; + asm("mov %0, #0 \n\t" + "mov %R0, #0 \n\t" + "mov x0, #12345" + : "=r" (ret) : : "x0"); + return ret; +} + +/* { dg-final { scan-assembler-not {mov x0, #0} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/pr121290.c b/gcc/testsuite/gcc.target/aarch64/pr121290.c new file mode 100644 index 0000000..05aa4a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr121290.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O3 -mcpu=neoverse-v2 -fdump-tree-vect-all -std=c99" } */ + +void +f (int *restrict x, int *restrict y, int *restrict z, int n) +{ + for (int i = 0; i < 4; ++i) + { + int res = 0; + for (int j = 0; j < 100; ++j) + res += y[j] * z[i]; + x[i] = res; + } +} + +/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ +/* { dg-final { scan-tree-dump-not "OUTER LOOP VECTORIZED" "vect" } } */ +/* { dg-final { scan-tree-dump "low throughput of per iteration due to splats" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/pr121300.c b/gcc/testsuite/gcc.target/aarch64/pr121300.c new file mode 100644 index 0000000..5f2cd9a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr121300.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-S -O3 -march=armv9-a+sme2" } */ + +#include <arm_sme.h> + +svfloat16x2_t test (svfloat16x2_t zd, svfloat16x2_t zm) __arm_streaming +{ + return svamin_f16_x2 (zd, zm); // { dg-error "ACLE function .svamin_f16_x2. requires ISA extension .faminmax." } +} diff --git a/gcc/testsuite/gcc.target/aarch64/pr66462.c b/gcc/testsuite/gcc.target/aarch64/pr66462.c new file mode 100644 index 0000000..9ebd48e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr66462.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fsignaling-nans -fno-inline" } */ +/* { dg-require-effective-target fenv_exceptions } */ + +#include <fenv.h> + +static void t_inff (float x, bool res) +{ + if (__builtin_isinff (x) != res) + __builtin_abort (); + if (__builtin_isinff (-x) != res) + __builtin_abort (); + if (fetestexcept (FE_INVALID)) + __builtin_abort (); +} + +static void t_inf (double x, bool res) +{ + if (__builtin_isinf (x) != res) + __builtin_abort (); + if (__builtin_isinf (-x) != res) + __builtin_abort (); + if (fetestexcept (FE_INVALID)) + __builtin_abort (); +} + +int +main () +{ + feclearexcept (FE_INVALID); + + t_inff (0.0f, 0); + t_inff (1.0f, 0); + t_inff (__builtin_inff (), 1); + t_inff (__builtin_nansf (""), 0); + t_inff (__builtin_nanf (""), 0); + + t_inf (0.0, 0); + t_inf (1.0, 0); + t_inf (__builtin_inf (), 1); + t_inf (__builtin_nans (""), 0); + t_inf (__builtin_nan (""), 0); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_1.c b/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_1.c index acd2e11..8fc1569 100644 --- a/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_1.c +++ b/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_1.c @@ -4,24 +4,24 @@ /* ** uadd: -** dup v([0-9]+).8b, w1 -** dup v([0-9]+).8b, w0 +** dup v([0-9]+).8b, w[01] +** dup v([0-9]+).8b, w[01] ** uqadd b([0-9]+), (?:b\2, b\1|b\1, b\2) ** umov w0, v\3.b\[0\] ** ret */ /* ** uadd2: -** dup v([0-9]+).8b, w1 -** dup v([0-9]+).8b, w0 +** dup v([0-9]+).8b, w[01] +** dup v([0-9]+).8b, w[01] ** uqadd b([0-9]+), (?:b\2, b\1|b\1, b\2) ** umov w0, v\3.b\[0\] ** ret */ /* ** usub: { xfail *-*-* } -** dup v([0-9]+).8b, w1 -** dup v([0-9]+).8b, w0 +** dup v([0-9]+).8b, w[01] +** dup v([0-9]+).8b, w[01] ** uqsub b([0-9]+), b\1, b\2 ** umov w0, v\3.b\[0\] ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_2.c b/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_2.c index 86c88f8..dd0fefa 100644 --- a/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_2.c +++ b/gcc/testsuite/gcc.target/aarch64/saturating_arithmetic_2.c @@ -4,16 +4,16 @@ /* ** uadd: -** dup v([0-9]+).4h, w1 -** dup v([0-9]+).4h, w0 +** dup v([0-9]+).4h, w[01] +** dup v([0-9]+).4h, w[01] ** uqadd h([0-9]+), (?:h\2, h\1|h\1, h\2) ** umov w0, v\3.h\[0\] ** ret */ /* ** uadd2: -** dup v([0-9]+).4h, w1 -** dup v([0-9]+).4h, w0 +** dup v([0-9]+).4h, w[01] +** dup v([0-9]+).4h, w[01] ** uqadd h([0-9]+), (?:h\2, h\1|h\1, h\2) ** umov w0, v\3.h\[0\] ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c index 98922aa..3a63da7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c @@ -1,5 +1,5 @@ // { dg-options "-O -fomit-frame-pointer -fno-optimize-sibling-calls -funwind-tables" } -// { dg-final { check-function-bodies "**" "" } } +// { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {\t\.inst} } } void ns_callee (); void s_callee () [[arm::streaming]]; @@ -218,7 +218,7 @@ sc_caller_x1 (int *ptr, int a) [[arm::streaming_compatible]] ** bl ns_callee_stack ** ldr x16, \[x29, #?16\] ** tbz x16, 0, .* -** smstart sm +** .inst 0xd503437f // smstart sm ** ... */ void diff --git a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11.c b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11.c index ee6f987..c72d03f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11.c @@ -1,5 +1,6 @@ // { dg-options "-O -fomit-frame-pointer -fno-optimize-sibling-calls -funwind-tables -mtrack-speculation" } -// { dg-final { check-function-bodies "**" "" } } +// { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {\t\.inst} } } + void ns_callee (); void s_callee () [[arm::streaming]]; @@ -196,7 +197,7 @@ sc_caller_x1 (int *ptr, int a) [[arm::streaming_compatible]] ** tst x16, #?1 ** beq [^\n]* ** csel x15, x15, xzr, ne -** smstart sm +** .inst 0xd503437f // smstart sm ** ... */ void diff --git a/gcc/testsuite/gcc.target/aarch64/sme/pr121028.c b/gcc/testsuite/gcc.target/aarch64/sme/pr121028.c new file mode 100644 index 0000000..a6aa119 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme/pr121028.c @@ -0,0 +1,46 @@ +// PR121028 +// { dg-do assemble { target aarch64_asm_sme_ok } } +// { dg-options "-O --save-temps" } +// { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {\t\.inst} } } + +void ns_callee (); + +/* +** sc_caller_sme: +** ... +** mrs x16, svcr +** str x16, \[x29, #?16\] +** ldr x16, \[x29, #?16\] +** tbz x16, 0, .* +** smstop sm +** bl ns_callee +** ldr x16, \[x29, #?16\] +** tbz x16, 0, .* +** smstart sm +** ... +*/ +void sc_caller_sme() __arm_streaming_compatible +{ + ns_callee (); +} + +#pragma GCC target "+nosme" + +/* +** sc_caller_nosme: +** ... +** bl __arm_sme_state +** str x0, \[x29, #?16\] +** ldr x16, \[x29, #?16\] +** tbz x16, 0, .* +** .inst 0xd503427f // smstop sm +** bl ns_callee +** ldr x16, \[x29, #?16\] +** tbz x16, 0, .* +** .inst 0xd503437f // smstart sm +** ... +*/ +void sc_caller_nosme() __arm_streaming_compatible +{ + ns_callee (); +} diff --git a/gcc/testsuite/gcc.target/aarch64/sme/pr121414_1.c b/gcc/testsuite/gcc.target/aarch64/sme/pr121414_1.c new file mode 100644 index 0000000..ad8600f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme/pr121414_1.c @@ -0,0 +1,27 @@ +#pragma GCC target "+sme2" + +void f1() __arm_streaming_compatible {} +void f2() __arm_streaming {} +void f3() __arm_in("za") {} +void f4() __arm_out("za") {} +void f5() __arm_inout("za") {} +void f6() __arm_in("zt0") {} +void f7() __arm_out("zt0") {} +void f8() __arm_inout("zt0") {} + +__arm_locally_streaming void g1() {} +__arm_new("za") void g2() {} +__arm_new("zt0") void g3() {} + +/* { dg-final { scan-assembler {\t\.variant_pcs\tf1\n} } } */ +/* { dg-final { scan-assembler {\t\.variant_pcs\tf2\n} } } */ +/* { dg-final { scan-assembler {\t\.variant_pcs\tf3\n} } } */ +/* { dg-final { scan-assembler {\t\.variant_pcs\tf4\n} } } */ +/* { dg-final { scan-assembler {\t\.variant_pcs\tf5\n} } } */ +/* { dg-final { scan-assembler {\t\.variant_pcs\tf6\n} } } */ +/* { dg-final { scan-assembler {\t\.variant_pcs\tf7\n} } } */ +/* { dg-final { scan-assembler {\t\.variant_pcs\tf8\n} } } */ + +/* { dg-final { scan-assembler-not {\t\.variant_pcs\tg1\n} } } */ +/* { dg-final { scan-assembler-not {\t\.variant_pcs\tg2\n} } } */ +/* { dg-final { scan-assembler-not {\t\.variant_pcs\tg3\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x2.c index 90b5438..b9fd96a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x2.c +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x2.c @@ -1,3 +1,5 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sme2_acle.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x4.c index d168ad7..70e2697 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x4.c +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f16_x4.c @@ -1,3 +1,5 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sme2_acle.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x2.c index 618d50b9..cf57d1b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x2.c +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x2.c @@ -1,3 +1,5 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sme2_acle.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x4.c index 981e78c..10d9175 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x4.c +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f32_x4.c @@ -1,3 +1,5 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sme2_acle.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x2.c index e93a409..b7918ab 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x2.c +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x2.c @@ -1,3 +1,5 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sme2_acle.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x4.c index 2db629e..153a37a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x4.c +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amax_f64_x4.c @@ -1,3 +1,5 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sme2_acle.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x2.c index 74604e1..bd6e13b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x2.c +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x2.c @@ -1,3 +1,5 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sme2_acle.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x4.c index bc3779b..9f71b1f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x4.c +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f16_x4.c @@ -1,3 +1,5 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sme2_acle.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x2.c index 43e3075..aaa6a2e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x2.c +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x2.c @@ -1,3 +1,5 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sme2_acle.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x4.c index 6bd20f8f..34c1098 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x4.c +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f32_x4.c @@ -1,3 +1,5 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sme2_acle.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x2.c index 3bbef3f..e4138e0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x2.c +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x2.c @@ -1,3 +1,5 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sme2_acle.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x4.c index 6f4c9b7..8fbabe7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x4.c +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/amin_f64_x4.c @@ -1,3 +1,5 @@ +/* { dg-do assemble { target { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } */ +/* { dg-do compile { target { ! { aarch64_asm_sme2_ok && aarch64_asm_faminmax_ok } } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sme2_acle.h" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/acge_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/acge_1.c new file mode 100644 index 0000000..37428a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/acge_1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** facge p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svacge (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** facge p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svacge (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** facge p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svacge (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** facge p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svacge (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** facge p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svacge (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** facge p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svacge (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** facge p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svacge (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/acgt_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/acgt_1.c new file mode 100644 index 0000000..5829369 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/acgt_1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** facgt p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svacgt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** facgt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svacgt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** facgt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svacgt (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** facgt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svacgt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** facgt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svacgt (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** facgt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svacgt (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** facgt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svacgt (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/acle_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/acle_1.c new file mode 100644 index 0000000..bd5200e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/acle_1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** facle p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svacle (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** facle p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svacle (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** facle p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svacle (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** facle p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svacle (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** facle p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svacle (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** facle p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svacle (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** facle p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svacle (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/aclt_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/aclt_1.c new file mode 100644 index 0000000..876aba9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/aclt_1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** faclt p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svaclt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** faclt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svaclt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** faclt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svaclt (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** faclt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svaclt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** faclt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svaclt (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** faclt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svaclt (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** faclt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svaclt (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_1.c index dd8f6c4..d6aabc8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_1.c @@ -18,5 +18,57 @@ test2 (svbool_t pg, svint8_t x, svint64_t y, int *any) return svptest_any (pg, res); } -/* { dg-final { scan-assembler-times {\tcmpeq\t} 2 } } */ +void +test3 (svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpeq_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svint8_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpeq_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpeq_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpeq_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint32_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpeq_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint32_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpeq_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpeq\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ /* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_2.c index 028d375..df98d27 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_2.c @@ -33,6 +33,108 @@ test4 (svbool_t pg, svint8_t x, int *any) return svptest_any (pg, res); } -/* { dg-final { scan-assembler-times {\tcmpeq\t} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\t[^\n]*, #10} 2 } } */ +void +test5 (svint16_t x, svint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpeq (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpeq (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpeq (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpeq (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svint32_t x, svint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpeq (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpeq (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpeq (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpeq (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svint64_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpeq (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpeq (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpeq (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpeq (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpeq\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\t[^\n]*, #10} 8 } } */ /* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_4.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_4.c new file mode 100644 index 0000000..8e4b931 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_4.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpeq p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpeq (pg, x, y), p0); +} + +/* +** test2: +** cmpeq p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpeq (pg, x, y), p0); +} + +/* +** test3: +** cmpeq p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpeq (pg, x, y), pg); +} + +/* +** test4: +** cmpeq p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test4 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpeq (pg, x, 10), p0); +} + +/* +** test5: +** cmpeq p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test5 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpeq (pg, x, 10), p0); +} + +/* +** test6: +** cmpeq p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test6 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpeq (pg, x, 10), pg); +} + +/* +** test7: +** cmpeq p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpeq (pg, x, y), p0); +} + +/* +** test8: +** cmpeq p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpeq (pg, x, 10), p0); +} + +/* +** test9: +** cmpeq p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpeq (pg, x, y), p0); +} + +/* +** test10: +** cmpeq p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpeq (pg, x, 10), p0); +} + +/* +** test11: +** cmpeq p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpeq (pg, x, y), p0); +} + +/* +** test12: +** cmpeq p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpeq (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_5.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_5.c new file mode 100644 index 0000000..2958bc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_5.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpeq p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svint16_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpeq_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmpeq p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpeq_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmpeq p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpeq_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_6.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_6.c new file mode 100644 index 0000000..9233de9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_6.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** fcmeq p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svcmpeq (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** fcmeq p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpeq (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** fcmeq p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpeq (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** fcmeq p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpeq (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** fcmeq p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpeq (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** fcmeq p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpeq (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** fcmeq p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpeq (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_1.c new file mode 100644 index 0000000..f6bb3c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_1.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint8_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpge (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint8_t y, int *any) +{ + svbool_t res = svcmpge (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svbool_t pg, svint8_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpge (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svbool_t pg, svint8_t x, int *any) +{ + svbool_t res = svcmpge (pg, x, 10); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svint32_t x, svint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svint64_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpge (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpge (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpge (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpge (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpge\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmpge\t[^\n]*, #10} 8 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_2.c new file mode 100644 index 0000000..fc92291 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_2.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svuint8_t x, svuint8_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpge (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svuint8_t x, svuint8_t y, int *any) +{ + svbool_t res = svcmpge (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svbool_t pg, svuint8_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpge (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svbool_t pg, svuint8_t x, int *any) +{ + svbool_t res = svcmpge (pg, x, 10); + return svptest_any (pg, res); +} + +void +test5 (svuint16_t x, svuint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svuint16_t x, svuint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svuint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svuint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svuint32_t x, svuint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svuint32_t x, svuint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svuint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svuint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svuint64_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpge (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svuint64_t x, svuint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpge (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svuint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpge (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svuint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpge (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmphs\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmphs\t[^\n]*, #10} 8 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_3.c new file mode 100644 index 0000000..6d50df5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_3.c @@ -0,0 +1,169 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpge p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, y), p0); +} + +/* +** test2: +** cmpge p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpge (pg, x, y), p0); +} + +/* +** test3: +** cmpge p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpge (pg, x, y), pg); +} + +/* +** test4: +** ( +** cmpge p0\.b, p0/z, z0\.b, #10 +** | +** cmpgt p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test4 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, 10), p0); +} + +/* +** test5: +** ( +** cmpge p0\.b, p0/z, z0\.b, #10 +** | +** cmpgt p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test5 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpge (pg, x, 10), p0); +} + +/* +** test6: +** ( +** cmpge p0\.b, p0/z, z0\.b, #10 +** | +** cmpgt p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test6 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpge (pg, x, 10), pg); +} + +/* +** test7: +** cmpge p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, y), p0); +} + +/* +** test8: +** cmpge p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpge (pg, x, 10), p0); +} + +/* +** test9: +** cmpge p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, y), p0); +} + +/* +** test10: +** cmpge p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpge (pg, x, 10), p0); +} + +/* +** test11: +** cmpge p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, y), p0); +} + +/* +** test12: +** cmpge p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpge (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_4.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_4.c new file mode 100644 index 0000000..2430e80 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_4.c @@ -0,0 +1,169 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmphs p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, y), p0); +} + +/* +** test2: +** cmphs p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpge (pg, x, y), p0); +} + +/* +** test3: +** cmphs p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpge (pg, x, y), pg); +} + +/* +** test4: +** ( +** cmphs p0\.b, p0/z, z0\.b, #10 +** | +** cmphi p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test4 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, 10), p0); +} + +/* +** test5: +** ( +** cmphs p0\.b, p0/z, z0\.b, #10 +** | +** cmphi p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test5 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpge (pg, x, 10), p0); +} + +/* +** test6: +** ( +** cmphs p0\.b, p0/z, z0\.b, #10 +** | +** cmphi p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test6 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpge (pg, x, 10), pg); +} + +/* +** test7: +** cmphs p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svuint16_t x, svuint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, y), p0); +} + +/* +** test8: +** cmphs p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svuint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpge (pg, x, 10), p0); +} + +/* +** test9: +** cmphs p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svuint32_t x, svuint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, y), p0); +} + +/* +** test10: +** cmphs p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svuint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpge (pg, x, 10), p0); +} + +/* +** test11: +** cmphs p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svuint64_t x, svuint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, y), p0); +} + +/* +** test12: +** cmphs p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svuint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpge (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_5.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_5.c new file mode 100644 index 0000000..f4fa758 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_5.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpge_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint64_t y, int *any) +{ + svbool_t res = svcmpge_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpge_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svint8_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpge_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint32_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint32_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpge\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_6.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_6.c new file mode 100644 index 0000000..979db4c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_6.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svuint8_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpge_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svuint8_t x, svuint64_t y, int *any) +{ + svbool_t res = svcmpge_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svuint8_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpge_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svuint8_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpge_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svuint16_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svuint16_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svuint32_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svuint32_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmphs\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_7.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_7.c new file mode 100644 index 0000000..d6abab0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_7.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpge p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svint16_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmpge p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmpge p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_8.c new file mode 100644 index 0000000..70be917 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_8.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmphs p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svuint16_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmphs p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svuint32_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmphs p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svuint32_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_9.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_9.c new file mode 100644 index 0000000..0d4140e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_9.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** fcmge p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** fcmge p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** fcmge p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** fcmge p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** fcmge p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpge (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** fcmge p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** fcmge p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpge (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_1.c new file mode 100644 index 0000000..6c28d6f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_1.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint8_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpgt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint8_t y, int *any) +{ + svbool_t res = svcmpgt (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svbool_t pg, svint8_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpgt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svbool_t pg, svint8_t x, int *any) +{ + svbool_t res = svcmpgt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svint32_t x, svint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svint64_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpgt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpgt (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpgt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpgt (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpgt\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\t[^\n]*, #10} 8 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_2.c new file mode 100644 index 0000000..2160484 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_2.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svuint8_t x, svuint8_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpgt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svuint8_t x, svuint8_t y, int *any) +{ + svbool_t res = svcmpgt (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svbool_t pg, svuint8_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpgt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svbool_t pg, svuint8_t x, int *any) +{ + svbool_t res = svcmpgt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test5 (svuint16_t x, svuint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svuint16_t x, svuint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svuint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svuint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svuint32_t x, svuint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svuint32_t x, svuint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svuint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svuint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svuint64_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpgt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svuint64_t x, svuint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpgt (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svuint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpgt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svuint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpgt (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmphi\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\t[^\n]*, #10} 8 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_3.c new file mode 100644 index 0000000..cc48b7e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_3.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpgt p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, y), p0); +} + +/* +** test2: +** cmpgt p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpgt (pg, x, y), p0); +} + +/* +** test3: +** cmpgt p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpgt (pg, x, y), pg); +} + +/* +** test4: +** cmpgt p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test4 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, 10), p0); +} + +/* +** test5: +** cmpgt p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test5 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpgt (pg, x, 10), p0); +} + +/* +** test6: +** cmpgt p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test6 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpgt (pg, x, 10), pg); +} + +/* +** test7: +** cmpgt p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, y), p0); +} + +/* +** test8: +** cmpgt p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpgt (pg, x, 10), p0); +} + +/* +** test9: +** cmpgt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, y), p0); +} + +/* +** test10: +** cmpgt p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpgt (pg, x, 10), p0); +} + +/* +** test11: +** cmpgt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, y), p0); +} + +/* +** test12: +** cmpgt p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpgt (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_4.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_4.c new file mode 100644 index 0000000..bd49fe8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_4.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmphi p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, y), p0); +} + +/* +** test2: +** cmphi p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpgt (pg, x, y), p0); +} + +/* +** test3: +** cmphi p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpgt (pg, x, y), pg); +} + +/* +** test4: +** cmphi p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test4 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, 10), p0); +} + +/* +** test5: +** cmphi p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test5 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpgt (pg, x, 10), p0); +} + +/* +** test6: +** cmphi p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test6 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpgt (pg, x, 10), pg); +} + +/* +** test7: +** cmphi p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svuint16_t x, svuint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, y), p0); +} + +/* +** test8: +** cmphi p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svuint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpgt (pg, x, 10), p0); +} + +/* +** test9: +** cmphi p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svuint32_t x, svuint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, y), p0); +} + +/* +** test10: +** cmphi p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svuint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpgt (pg, x, 10), p0); +} + +/* +** test11: +** cmphi p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svuint64_t x, svuint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, y), p0); +} + +/* +** test12: +** cmphi p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svuint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpgt (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_5.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_5.c new file mode 100644 index 0000000..f9f4c7d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_5.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpgt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint64_t y, int *any) +{ + svbool_t res = svcmpgt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpgt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svint8_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpgt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint32_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint32_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpgt\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_6.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_6.c new file mode 100644 index 0000000..6df15b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_6.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svuint8_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpgt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svuint8_t x, svuint64_t y, int *any) +{ + svbool_t res = svcmpgt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svuint8_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpgt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svuint8_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpgt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svuint16_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svuint16_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svuint32_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svuint32_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmphi\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_7.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_7.c new file mode 100644 index 0000000..0656b29 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_7.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpgt p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svint16_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmpgt p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmpgt p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_8.c new file mode 100644 index 0000000..b0a9ac8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_8.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmphi p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svuint16_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmphi p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svuint32_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmphi p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svuint32_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_9.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_9.c new file mode 100644 index 0000000..dcd84f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_9.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** fcmgt p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** fcmgt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** fcmgt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** fcmgt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** fcmgt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpgt (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** fcmgt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** fcmgt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpgt (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_1.c new file mode 100644 index 0000000..f2d7d2b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_1.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint8_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmple (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint8_t y, int *any) +{ + svbool_t res = svcmple (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svbool_t pg, svint8_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svcmple (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svbool_t pg, svint8_t x, int *any) +{ + svbool_t res = svcmple (pg, x, 10); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svint32_t x, svint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svint64_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmple (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmple (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmple (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmple (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmple\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmple\t[^\n]*, #10} 8 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_2.c new file mode 100644 index 0000000..9d13d7a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_2.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svuint8_t x, svuint8_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmple (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svuint8_t x, svuint8_t y, int *any) +{ + svbool_t res = svcmple (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svbool_t pg, svuint8_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svcmple (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svbool_t pg, svuint8_t x, int *any) +{ + svbool_t res = svcmple (pg, x, 10); + return svptest_any (pg, res); +} + +void +test5 (svuint16_t x, svuint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svuint16_t x, svuint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svuint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svuint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svuint32_t x, svuint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svuint32_t x, svuint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svuint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svuint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svuint64_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmple (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svuint64_t x, svuint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmple (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svuint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmple (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svuint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmple (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpls\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\t[^\n]*, #10} 8 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_3.c new file mode 100644 index 0000000..7a9326c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_3.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmple p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, y), p0); +} + +/* +** test2: +** cmple p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmple (pg, x, y), p0); +} + +/* +** test3: +** cmple p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmple (pg, x, y), pg); +} + +/* +** test4: +** cmple p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test4 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, 10), p0); +} + +/* +** test5: +** cmple p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test5 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmple (pg, x, 10), p0); +} + +/* +** test6: +** cmple p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test6 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmple (pg, x, 10), pg); +} + +/* +** test7: +** cmple p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, y), p0); +} + +/* +** test8: +** cmple p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmple (pg, x, 10), p0); +} + +/* +** test9: +** cmple p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, y), p0); +} + +/* +** test10: +** cmple p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmple (pg, x, 10), p0); +} + +/* +** test11: +** cmple p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, y), p0); +} + +/* +** test12: +** cmple p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmple (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_4.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_4.c new file mode 100644 index 0000000..aca4385 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_4.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpls p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, y), p0); +} + +/* +** test2: +** cmpls p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmple (pg, x, y), p0); +} + +/* +** test3: +** cmpls p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmple (pg, x, y), pg); +} + +/* +** test4: +** cmpls p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test4 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, 10), p0); +} + +/* +** test5: +** cmpls p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test5 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmple (pg, x, 10), p0); +} + +/* +** test6: +** cmpls p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test6 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmple (pg, x, 10), pg); +} + +/* +** test7: +** cmpls p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svuint16_t x, svuint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, y), p0); +} + +/* +** test8: +** cmpls p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svuint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmple (pg, x, 10), p0); +} + +/* +** test9: +** cmpls p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svuint32_t x, svuint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, y), p0); +} + +/* +** test10: +** cmpls p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svuint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmple (pg, x, 10), p0); +} + +/* +** test11: +** cmpls p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svuint64_t x, svuint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, y), p0); +} + +/* +** test12: +** cmpls p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svuint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmple (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_5.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_5.c new file mode 100644 index 0000000..1caf496 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_5.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmple_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint64_t y, int *any) +{ + svbool_t res = svcmple_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmple_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svint8_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmple_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint32_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint32_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmple\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_6.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_6.c new file mode 100644 index 0000000..ae85e89 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_6.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svuint8_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmple_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svuint8_t x, svuint64_t y, int *any) +{ + svbool_t res = svcmple_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svuint8_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmple_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svuint8_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmple_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svuint16_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svuint16_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svuint32_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svuint32_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpls\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_7.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_7.c new file mode 100644 index 0000000..3f3ea53 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_7.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmple p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svint16_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmple_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmple p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmple_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmple p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmple_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_8.c new file mode 100644 index 0000000..01281ca --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_8.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpls p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svuint16_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmple_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmpls p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svuint32_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmple_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmpls p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svuint32_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmple_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_9.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_9.c new file mode 100644 index 0000000..8d008b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_9.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** fcmle p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svcmple (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** fcmle p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmple (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** fcmle p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmple (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** fcmle p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmple (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** fcmle p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmple (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** fcmle p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmple (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** fcmle p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmple (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_1.c new file mode 100644 index 0000000..a15bb4a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_1.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint8_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmplt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint8_t y, int *any) +{ + svbool_t res = svcmplt (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svbool_t pg, svint8_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svcmplt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svbool_t pg, svint8_t x, int *any) +{ + svbool_t res = svcmplt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svint32_t x, svint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svint64_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmplt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmplt (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmplt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmplt (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmplt\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmplt\t[^\n]*, #10} 8 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_2.c new file mode 100644 index 0000000..43c53a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_2.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svuint8_t x, svuint8_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmplt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svuint8_t x, svuint8_t y, int *any) +{ + svbool_t res = svcmplt (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svbool_t pg, svuint8_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svcmplt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svbool_t pg, svuint8_t x, int *any) +{ + svbool_t res = svcmplt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test5 (svuint16_t x, svuint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svuint16_t x, svuint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svuint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svuint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svuint32_t x, svuint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svuint32_t x, svuint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svuint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svuint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svuint64_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmplt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svuint64_t x, svuint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmplt (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svuint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmplt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svuint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmplt (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmplo\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmplo\t[^\n]*, #10} 8 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_3.c new file mode 100644 index 0000000..bddbbeb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_3.c @@ -0,0 +1,169 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmplt p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, y), p0); +} + +/* +** test2: +** cmplt p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmplt (pg, x, y), p0); +} + +/* +** test3: +** cmplt p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmplt (pg, x, y), pg); +} + +/* +** test4: +** ( +** cmplt p0\.b, p0/z, z0\.b, #10 +** | +** cmple p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test4 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, 10), p0); +} + +/* +** test5: +** ( +** cmplt p0\.b, p0/z, z0\.b, #10 +** | +** cmple p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test5 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmplt (pg, x, 10), p0); +} + +/* +** test6: +** ( +** cmplt p0\.b, p0/z, z0\.b, #10 +** | +** cmple p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test6 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmplt (pg, x, 10), pg); +} + +/* +** test7: +** cmplt p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, y), p0); +} + +/* +** test8: +** cmplt p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmplt (pg, x, 10), p0); +} + +/* +** test9: +** cmplt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, y), p0); +} + +/* +** test10: +** cmplt p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmplt (pg, x, 10), p0); +} + +/* +** test11: +** cmplt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, y), p0); +} + +/* +** test12: +** cmplt p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmplt (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_4.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_4.c new file mode 100644 index 0000000..b71c8e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_4.c @@ -0,0 +1,169 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmplo p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, y), p0); +} + +/* +** test2: +** cmplo p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmplt (pg, x, y), p0); +} + +/* +** test3: +** cmplo p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmplt (pg, x, y), pg); +} + +/* +** test4: +** ( +** cmplo p0\.b, p0/z, z0\.b, #10 +** | +** cmpls p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test4 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, 10), p0); +} + +/* +** test5: +** ( +** cmplo p0\.b, p0/z, z0\.b, #10 +** | +** cmpls p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test5 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmplt (pg, x, 10), p0); +} + +/* +** test6: +** ( +** cmplo p0\.b, p0/z, z0\.b, #10 +** | +** cmpls p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test6 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmplt (pg, x, 10), pg); +} + +/* +** test7: +** cmplo p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svuint16_t x, svuint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, y), p0); +} + +/* +** test8: +** cmplo p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svuint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmplt (pg, x, 10), p0); +} + +/* +** test9: +** cmplo p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svuint32_t x, svuint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, y), p0); +} + +/* +** test10: +** cmplo p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svuint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmplt (pg, x, 10), p0); +} + +/* +** test11: +** cmplo p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svuint64_t x, svuint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, y), p0); +} + +/* +** test12: +** cmplo p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svuint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmplt (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_5.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_5.c new file mode 100644 index 0000000..6885e4d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_5.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmplt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint64_t y, int *any) +{ + svbool_t res = svcmplt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmplt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svint8_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmplt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint32_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint32_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmplt\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_6.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_6.c new file mode 100644 index 0000000..e9be9e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_6.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svuint8_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmplt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svuint8_t x, svuint64_t y, int *any) +{ + svbool_t res = svcmplt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svuint8_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmplt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svuint8_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmplt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svuint16_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svuint16_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svuint32_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svuint32_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmplo\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_7.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_7.c new file mode 100644 index 0000000..a4de6ab --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_7.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmplt p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svint16_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmplt p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmplt p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_8.c new file mode 100644 index 0000000..0a095eb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_8.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmplo p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svuint16_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmplo p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svuint32_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmplo p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svuint32_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_9.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_9.c new file mode 100644 index 0000000..4f4b7b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_9.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** fcmlt p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** fcmlt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** fcmlt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** fcmlt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** fcmlt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmplt (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** fcmlt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** fcmlt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmplt (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_1.c new file mode 100644 index 0000000..61f7718 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_1.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint8_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpne (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint8_t y, int *any) +{ + svbool_t res = svcmpne (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svbool_t pg, svint8_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpne (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svbool_t pg, svint8_t x, int *any) +{ + svbool_t res = svcmpne (pg, x, 10); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpne (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpne (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpne (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpne (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svint32_t x, svint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpne (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpne (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpne (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpne (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svint64_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpne (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpne (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpne (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpne (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpne\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\t[^\n]*, #10} 8 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_2.c new file mode 100644 index 0000000..53cedb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_2.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpne p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpne (pg, x, y), p0); +} + +/* +** test2: +** cmpne p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpne (pg, x, y), p0); +} + +/* +** test3: +** cmpne p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpne (pg, x, y), pg); +} + +/* +** test4: +** cmpne p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test4 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpne (pg, x, 10), p0); +} + +/* +** test5: +** cmpne p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test5 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpne (pg, x, 10), p0); +} + +/* +** test6: +** cmpne p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test6 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpne (pg, x, 10), pg); +} + +/* +** test7: +** cmpne p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpne (pg, x, y), p0); +} + +/* +** test8: +** cmpne p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpne (pg, x, 10), p0); +} + +/* +** test9: +** cmpne p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpne (pg, x, y), p0); +} + +/* +** test10: +** cmpne p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpne (pg, x, 10), p0); +} + +/* +** test11: +** cmpne p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpne (pg, x, y), p0); +} + +/* +** test12: +** cmpne p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpne (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_3.c new file mode 100644 index 0000000..c5c3936 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_3.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpne_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint64_t y, int *any) +{ + svbool_t res = svcmpne_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpne_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svint8_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpne_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpne_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpne_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint32_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpne_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint32_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpne_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpne\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_4.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_4.c new file mode 100644 index 0000000..595e024 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_4.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpne p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svint16_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpne_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmpne p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpne_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmpne p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpne_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_5.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_5.c new file mode 100644 index 0000000..94fecd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_5.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** fcmne p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svcmpne (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** fcmne p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpne (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** fcmne p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpne (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** fcmne p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpne (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** fcmne p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpne (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** fcmne p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpne (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** fcmne p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpne (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpuo_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpuo_1.c new file mode 100644 index 0000000..4b124b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpuo_1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** fcmuo p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svcmpuo (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** fcmuo p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpuo (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** fcmuo p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpuo (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** fcmuo p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpuo (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** fcmuo p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpuo (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** fcmuo p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpuo (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** fcmuo p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpuo (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cops.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cops.c index f0dc9a9..1201ca0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cops.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cops.c @@ -212,22 +212,22 @@ type init4 = svld1_ ## su ## sz (cmp ## sz, mem); \ \ type res_init1 = func_ ## type ## _init1 (); \ - svbool_t cmp = svcmpne_ ## su ## sz (all_true, init1, res_init1); \ + svbool_t cmp = svcmpne_ ## su ## sz (cmp ## sz, init1, res_init1); \ if (svptest_any (all_true, cmp)) \ __builtin_abort (); \ \ type res_init2 = func_ ## type ## _init2 (); \ - cmp = svcmpne_ ## su ## sz (all_true, init2, res_init2); \ + cmp = svcmpne_ ## su ## sz (cmp ## sz, init2, res_init2); \ if (svptest_any (all_true, cmp)) \ __builtin_abort (); \ \ type res_init3 = func_ ## type ## _init3 (); \ - cmp = svcmpne_ ## su ## sz (all_true, init3, res_init3); \ + cmp = svcmpne_ ## su ## sz (cmp ## sz, init3, res_init3); \ if (svptest_any (all_true, cmp)) \ __builtin_abort (); \ \ type res_init4 = func_ ## type ## _init4 (); \ - cmp = svcmpne_ ## su ## sz (all_true, init4, res_init4); \ + cmp = svcmpne_ ## su ## sz (cmp ## sz, init4, res_init4); \ if (svptest_any (all_true, cmp)) \ __builtin_abort (); \ } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dup_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dup_1.c new file mode 100644 index 0000000..c3c4e2d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dup_1.c @@ -0,0 +1,47 @@ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +svbool_t +test1 (int x) +{ + return svand_z (svptrue_b16 (), svdup_b16 (x), svptrue_b16 ()); +} + +svbool_t +test2 (int x) +{ + return svand_z (svptrue_b8 (), svdup_b32 (x), svptrue_b16 ()); +} + +svbool_t +test3 (int x) +{ + return svand_z (svptrue_b32 (), svdup_b32 (x), svptrue_b16 ()); +} + +svbool_t +test4 (int x) +{ + return svand_z (svptrue_b32 (), svdup_b32 (x), svptrue_b32 ()); +} + +svbool_t +test5 (int x) +{ + return svand_z (svptrue_b8 (), svdup_b64 (x), svptrue_b32 ()); +} + +svbool_t +test6 (int x) +{ + return svand_z (svptrue_b16 (), svdup_b64 (x), svptrue_b8 ()); +} + +svbool_t +test7 (int x) +{ + return svand_z (svptrue_b16 (), svdup_b64 (x), svptrue_b64 ()); +} + +/* { dg-final { scan-assembler-not {\tand\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_13.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_13.c new file mode 100644 index 0000000..6d702b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_13.c @@ -0,0 +1,45 @@ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +svbool_t +test1 (int x0, int x1) +{ + return svand_z (svptrue_b8 (), svdupq_b64 (x0, x1), svptrue_b16 ()); +} + +svbool_t +test2 (int x0, int x1, int x2, int x3) +{ + return svand_z (svptrue_b8 (), svdupq_b32 (x0, x1, x2, x3), svptrue_b16 ()); +} + +svbool_t +test3 (int x0, int x1, int x2, int x3) +{ + return svand_z (svptrue_b32 (), svdupq_b32 (x0, x1, x2, x3), svptrue_b16 ()); +} + +svbool_t +test4 (int x0, int x1, int x2, int x3) +{ + return svand_z (svptrue_b32 (), svdupq_b32 (x0, x1, x2, x3), svptrue_b32 ()); +} + +svbool_t +test5 (int x0, int x1, int x2, int x3) +{ + return svand_z (svptrue_b8 (), + svdupq_b16 (x0, x1, x2, x3, x2, x0, x1, x3), + svptrue_b32 ()); +} + +svbool_t +test6 (int x0, int x1, int x2, int x3) +{ + return svand_z (svptrue_b64 (), + svdupq_b16 (x0, x1, x2, x3, x2, x0, x1, x3), + svptrue_b16 ()); +} + +/* { dg-final { scan-assembler-not {\tand\tp} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_lane_9.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_lane_9.c new file mode 100644 index 0000000..e3f352b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_lane_9.c @@ -0,0 +1,8 @@ +/* { dg-options "-O2 -mbig-endian" } */ + +#pragma GCC aarch64 "arm_sve.h" + +svint32_t f(svint32_t x) { return svdupq_lane (x, 17); } +void g(svint32_t *a, svint32_t *b) { *a = svdupq_lane (*b, 17); } + +/* { dg-final { scan-assembler-not {\trevw\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_2.c new file mode 100644 index 0000000..9b3daaa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_2.c @@ -0,0 +1,96 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** ... +** ptrue (p[0-3])\.h, all +** ... +** trn1 p0\.h, p[0-3]\.h, \1\.h +** ret +*/ +svbool_t +test1 () +{ + return svtrn1_b16 (svptrue_b8 (), svptrue_b16 ()); +} + +/* +** test2: +** ... +** ptrue (p[0-3])\.h, all +** ... +** trn1 p0\.h, \1\.h, p[0-3]\.h +** ret +*/ +svbool_t +test2 () +{ + return svtrn1_b16 (svptrue_b16 (), svptrue_b8 ()); +} + +/* +** test3: +** ... +** ptrue (p[0-3])\.s, all +** ... +** trn1 p0\.s, p[0-3]\.s, \1\.s +** ret +*/ +svbool_t +test3 () +{ + return svtrn1_b32 (svptrue_b8 (), svptrue_b32 ()); +} + +/* +** test4: +** ... +** ptrue (p[0-3])\.s, all +** ... +** trn1 p0\.s, \1\.s, p[0-3]\.s +** ret +*/ +svbool_t +test4 () +{ + return svtrn1_b32 (svptrue_b32 (), svptrue_b8 ()); +} + +/* +** test5: +** ... +** ptrue (p[0-3])\.d, all +** ... +** trn1 p0\.d, p[0-3]\.d, \1\.d +** ret +*/ +svbool_t +test5 () +{ + return svtrn1_b64 (svptrue_b8 (), svptrue_b64 ()); +} + +/* +** test6: +** ... +** ptrue (p[0-3])\.d, all +** ... +** trn1 p0\.d, \1\.d, p[0-3]\.d +** ret +*/ +svbool_t +test6 () +{ + return svtrn1_b64 (svptrue_b64 (), svptrue_b8 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_3.c new file mode 100644 index 0000000..678c541 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_3.c @@ -0,0 +1,96 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** ... +** ptrue (p[0-3])\.h, all +** ... +** trn2 p0\.h, p[0-3]\.h, \1\.h +** ret +*/ +svbool_t +test1 () +{ + return svtrn2_b16 (svptrue_b8 (), svptrue_b16 ()); +} + +/* +** test2: +** ... +** ptrue (p[0-3])\.h, all +** ... +** trn2 p0\.h, \1\.h, p[0-3]\.h +** ret +*/ +svbool_t +test2 () +{ + return svtrn2_b16 (svptrue_b16 (), svptrue_b8 ()); +} + +/* +** test3: +** ... +** ptrue (p[0-3])\.s, all +** ... +** trn2 p0\.s, p[0-3]\.s, \1\.s +** ret +*/ +svbool_t +test3 () +{ + return svtrn2_b32 (svptrue_b8 (), svptrue_b32 ()); +} + +/* +** test4: +** ... +** ptrue (p[0-3])\.s, all +** ... +** trn2 p0\.s, \1\.s, p[0-3]\.s +** ret +*/ +svbool_t +test4 () +{ + return svtrn2_b32 (svptrue_b32 (), svptrue_b8 ()); +} + +/* +** test5: +** ... +** ptrue (p[0-3])\.d, all +** ... +** trn2 p0\.d, p[0-3]\.d, \1\.d +** ret +*/ +svbool_t +test5 () +{ + return svtrn2_b64 (svptrue_b8 (), svptrue_b64 ()); +} + +/* +** test6: +** ... +** ptrue (p[0-3])\.d, all +** ... +** trn2 p0\.d, \1\.d, p[0-3]\.d +** ret +*/ +svbool_t +test6 () +{ + return svtrn2_b64 (svptrue_b64 (), svptrue_b8 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_4.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_4.c new file mode 100644 index 0000000..28c6018 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_4.c @@ -0,0 +1,96 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** ... +** ptrue (p[0-3])\.h, all +** ... +** zip1 p0\.h, p[0-3]\.h, \1\.h +** ret +*/ +svbool_t +test1 () +{ + return svzip1_b16 (svptrue_b8 (), svptrue_b16 ()); +} + +/* +** test2: +** ... +** ptrue (p[0-3])\.h, all +** ... +** zip1 p0\.h, \1\.h, p[0-3]\.h +** ret +*/ +svbool_t +test2 () +{ + return svzip1_b16 (svptrue_b16 (), svptrue_b8 ()); +} + +/* +** test3: +** ... +** ptrue (p[0-3])\.s, all +** ... +** zip1 p0\.s, p[0-3]\.s, \1\.s +** ret +*/ +svbool_t +test3 () +{ + return svzip1_b32 (svptrue_b8 (), svptrue_b32 ()); +} + +/* +** test4: +** ... +** ptrue (p[0-3])\.s, all +** ... +** zip1 p0\.s, \1\.s, p[0-3]\.s +** ret +*/ +svbool_t +test4 () +{ + return svzip1_b32 (svptrue_b32 (), svptrue_b8 ()); +} + +/* +** test5: +** ... +** ptrue (p[0-3])\.d, all +** ... +** zip1 p0\.d, p[0-3]\.d, \1\.d +** ret +*/ +svbool_t +test5 () +{ + return svzip1_b64 (svptrue_b8 (), svptrue_b64 ()); +} + +/* +** test6: +** ... +** ptrue (p[0-3])\.d, all +** ... +** zip1 p0\.d, \1\.d, p[0-3]\.d +** ret +*/ +svbool_t +test6 () +{ + return svzip1_b64 (svptrue_b64 (), svptrue_b8 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_5.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_5.c new file mode 100644 index 0000000..a8aec2b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_5.c @@ -0,0 +1,96 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** ... +** ptrue (p[0-3])\.h, all +** ... +** zip2 p0\.h, p[0-3]\.h, \1\.h +** ret +*/ +svbool_t +test1 () +{ + return svzip2_b16 (svptrue_b8 (), svptrue_b16 ()); +} + +/* +** test2: +** ... +** ptrue (p[0-3])\.h, all +** ... +** zip2 p0\.h, \1\.h, p[0-3]\.h +** ret +*/ +svbool_t +test2 () +{ + return svzip2_b16 (svptrue_b16 (), svptrue_b8 ()); +} + +/* +** test3: +** ... +** ptrue (p[0-3])\.s, all +** ... +** zip2 p0\.s, p[0-3]\.s, \1\.s +** ret +*/ +svbool_t +test3 () +{ + return svzip2_b32 (svptrue_b8 (), svptrue_b32 ()); +} + +/* +** test4: +** ... +** ptrue (p[0-3])\.s, all +** ... +** zip2 p0\.s, \1\.s, p[0-3]\.s +** ret +*/ +svbool_t +test4 () +{ + return svzip2_b32 (svptrue_b32 (), svptrue_b8 ()); +} + +/* +** test5: +** ... +** ptrue (p[0-3])\.d, all +** ... +** zip2 p0\.d, p[0-3]\.d, \1\.d +** ret +*/ +svbool_t +test5 () +{ + return svzip2_b64 (svptrue_b8 (), svptrue_b64 ()); +} + +/* +** test6: +** ... +** ptrue (p[0-3])\.d, all +** ... +** zip2 p0\.d, \1\.d, p[0-3]\.d +** ret +*/ +svbool_t +test6 () +{ + return svzip2_b64 (svptrue_b64 (), svptrue_b8 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_6.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_6.c new file mode 100644 index 0000000..3405004 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_6.c @@ -0,0 +1,96 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** ... +** ptrue (p[0-3])\.h, all +** ... +** uzp1 p0\.h, p[0-3]\.h, \1\.h +** ret +*/ +svbool_t +test1 () +{ + return svuzp1_b16 (svptrue_b8 (), svptrue_b16 ()); +} + +/* +** test2: +** ... +** ptrue (p[0-3])\.h, all +** ... +** uzp1 p0\.h, \1\.h, p[0-3]\.h +** ret +*/ +svbool_t +test2 () +{ + return svuzp1_b16 (svptrue_b16 (), svptrue_b8 ()); +} + +/* +** test3: +** ... +** ptrue (p[0-3])\.s, all +** ... +** uzp1 p0\.s, p[0-3]\.s, \1\.s +** ret +*/ +svbool_t +test3 () +{ + return svuzp1_b32 (svptrue_b8 (), svptrue_b32 ()); +} + +/* +** test4: +** ... +** ptrue (p[0-3])\.s, all +** ... +** uzp1 p0\.s, \1\.s, p[0-3]\.s +** ret +*/ +svbool_t +test4 () +{ + return svuzp1_b32 (svptrue_b32 (), svptrue_b8 ()); +} + +/* +** test5: +** ... +** ptrue (p[0-3])\.d, all +** ... +** uzp1 p0\.d, p[0-3]\.d, \1\.d +** ret +*/ +svbool_t +test5 () +{ + return svuzp1_b64 (svptrue_b8 (), svptrue_b64 ()); +} + +/* +** test6: +** ... +** ptrue (p[0-3])\.d, all +** ... +** uzp1 p0\.d, \1\.d, p[0-3]\.d +** ret +*/ +svbool_t +test6 () +{ + return svuzp1_b64 (svptrue_b64 (), svptrue_b8 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_7.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_7.c new file mode 100644 index 0000000..1758d00 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_7.c @@ -0,0 +1,96 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** ... +** ptrue (p[0-3])\.h, all +** ... +** uzp2 p0\.h, p[0-3]\.h, \1\.h +** ret +*/ +svbool_t +test1 () +{ + return svuzp2_b16 (svptrue_b8 (), svptrue_b16 ()); +} + +/* +** test2: +** ... +** ptrue (p[0-3])\.h, all +** ... +** uzp2 p0\.h, \1\.h, p[0-3]\.h +** ret +*/ +svbool_t +test2 () +{ + return svuzp2_b16 (svptrue_b16 (), svptrue_b8 ()); +} + +/* +** test3: +** ... +** ptrue (p[0-3])\.s, all +** ... +** uzp2 p0\.s, p[0-3]\.s, \1\.s +** ret +*/ +svbool_t +test3 () +{ + return svuzp2_b32 (svptrue_b8 (), svptrue_b32 ()); +} + +/* +** test4: +** ... +** ptrue (p[0-3])\.s, all +** ... +** uzp2 p0\.s, \1\.s, p[0-3]\.s +** ret +*/ +svbool_t +test4 () +{ + return svuzp2_b32 (svptrue_b32 (), svptrue_b8 ()); +} + +/* +** test5: +** ... +** ptrue (p[0-3])\.d, all +** ... +** uzp2 p0\.d, p[0-3]\.d, \1\.d +** ret +*/ +svbool_t +test5 () +{ + return svuzp2_b64 (svptrue_b8 (), svptrue_b64 ()); +} + +/* +** test6: +** ... +** ptrue (p[0-3])\.d, all +** ... +** uzp2 p0\.d, \1\.d, p[0-3]\.d +** ret +*/ +svbool_t +test6 () +{ + return svuzp2_b64 (svptrue_b64 (), svptrue_b8 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pnext_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pnext_3.c new file mode 100644 index 0000000..d9c0090 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pnext_3.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** pnext p0\.h, p1, p0\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svbool_t prev) +{ + return svand_z (svptrue_b8 (), + svpnext_b16 (prev, pg), + svptrue_b16 ()); +} + +/* +** test2: +** pnext p0\.h, p1, p0\.h +** ret +*/ +svbool_t +test2 (svbool_t pg, svbool_t prev) +{ + return svand_z (svptrue_b16 (), + svpnext_b16 (prev, pg), + svptrue_b8 ()); +} + +/* +** test3: +** pnext p0\.h, p1, p0\.h +** ret +*/ +svbool_t +test3 (svbool_t pg, svbool_t prev) +{ + return svand_z (svptrue_b16 (), + svpnext_b16 (prev, pg), + svptrue_b16 ()); +} + +/* +** test4: +** pnext p0\.s, p1, p0\.s +** ret +*/ +svbool_t +test4 (svbool_t pg, svbool_t prev) +{ + return svand_z (svptrue_b32 (), + svpnext_b32 (prev, pg), + svptrue_b8 ()); +} + +/* +** test5: +** pnext p0\.s, p1, p0\.s +** ret +*/ +svbool_t +test5 (svbool_t pg, svbool_t prev) +{ + return svand_z (svptrue_b16 (), + svpnext_b32 (prev, pg), + svptrue_b8 ()); +} + +/* +** test6: +** pnext p0\.s, p1, p0\.s +** ret +*/ +svbool_t +test6 (svbool_t pg, svbool_t prev) +{ + return svand_z (svptrue_b8 (), + svpnext_b32 (prev, pg), + svptrue_b32 ()); +} + +/* +** test7: +** pnext p0\.d, p1, p0\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svbool_t prev) +{ + return svand_z (svptrue_b16 (), + svpnext_b64 (prev, pg), + svptrue_b8 ()); +} + +/* +** test8: +** pnext p0\.d, p1, p0\.d +** ret +*/ +svbool_t +test8 (svbool_t pg, svbool_t prev) +{ + return svand_z (svptrue_b32 (), + svpnext_b64 (prev, pg), + svptrue_b8 ()); +} + +/* +** test9: +** pnext p0\.d, p1, p0\.d +** ret +*/ +svbool_t +test9 (svbool_t pg, svbool_t prev) +{ + return svand_z (svptrue_b8 (), + svpnext_b64 (prev, pg), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr120718.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr120718.c new file mode 100644 index 0000000..9ca0938 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr120718.c @@ -0,0 +1,12 @@ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> +typedef int __attribute__((vector_size(8))) v2si; +typedef struct { int x; int y; } A; +void bar(A a); +void foo() +{ + A a; + *(v2si *)&a = (v2si){0, (int)svcntd_pat(SV_ALL)}; + bar(a); +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr121118_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr121118_1.c new file mode 100644 index 0000000..b59a972 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr121118_1.c @@ -0,0 +1,16 @@ +/* { dg-options "-O2 -msve-vector-bits=512" } */ + +typedef __SVBool_t fixed_bool __attribute__((arm_sve_vector_bits(512))); + +#define TEST_CONST(NAME, CONST) \ + fixed_bool \ + NAME () \ + { \ + union { unsigned long long i; fixed_bool pg; } u = { CONST }; \ + return u.pg; \ + } + +TEST_CONST (test1, 0x02aaaaaaaa) +TEST_CONST (test2, 0x0155555557) +TEST_CONST (test3, 0x0013333333333333ULL) +TEST_CONST (test4, 0x0011111111111113ULL) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/rev_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/rev_2.c new file mode 100644 index 0000000..3dc4eb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/rev_2.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +svbool_t test1() +{ + return svrev_b16 (svptrue_b16 ()); +} + +svbool_t test2() +{ + return svrev_b32 (svptrue_b32 ()); +} + +svbool_t test3() +{ + return svrev_b64 (svptrue_b64 ()); +} + +/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.h} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.b} } } */ +/* { dg-final { scan-assembler {\trev\tp0\.h} } } */ +/* { dg-final { scan-assembler {\trev\tp0\.s} } } */ +/* { dg-final { scan-assembler {\trev\tp0\.d} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/unpkhi_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/unpkhi_1.c new file mode 100644 index 0000000..9c7b4bc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/unpkhi_1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +svbool_t +test1 (svbool_t p) +{ + return svand_z (svptrue_b8 (), svunpkhi (p), svptrue_b16 ()); +} + +svbool_t +test2 (svbool_t p) +{ + return svand_z (svptrue_b16 (), svunpkhi (p), svptrue_b8 ()); +} + +svbool_t +test3 (svbool_t p) +{ + return svand_z (svptrue_b16 (), svunpkhi (p), svptrue_b16 ()); +} + +/* { dg-final { scan-assembler-not {\tand\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/unpklo_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/unpklo_1.c new file mode 100644 index 0000000..f072a2f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/unpklo_1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +svbool_t +test1 (svbool_t p) +{ + return svand_z (svptrue_b8 (), svunpklo (p), svptrue_b16 ()); +} + +svbool_t +test2 (svbool_t p) +{ + return svand_z (svptrue_b16 (), svunpklo (p), svptrue_b8 ()); +} + +svbool_t +test3 (svbool_t p) +{ + return svand_z (svptrue_b16 (), svunpklo (p), svptrue_b16 ()); +} + +/* { dg-final { scan-assembler-not {\tand\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_13.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_13.c new file mode 100644 index 0000000..cf50dc1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_13.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** whilele p0\.h, w0, w1 +** ret +*/ +svbool_t +test1 (int32_t x, int32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilele_b16 (x, y), + svptrue_b16 ()); +} + +/* +** test2: +** whilele p0\.h, x0, x1 +** ret +*/ +svbool_t +test2 (int64_t x, int64_t y) +{ + return svand_z (svptrue_b16 (), + svwhilele_b16 (x, y), + svptrue_b16 ()); +} + +/* +** test3: +** whilels p0\.s, w0, w1 +** ret +*/ +svbool_t +test3 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilele_b32 (x, y), + svptrue_b16 ()); +} + +/* +** test4: +** whilels p0\.s, x0, x1 +** ret +*/ +svbool_t +test4 (uint64_t x, uint64_t y) +{ + return svand_z (svptrue_b8 (), + svwhilele_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test5: +** whilele p0\.s, w0, w1 +** ret +*/ +svbool_t +test5 (int32_t x, int32_t y) +{ + return svand_z (svptrue_b16 (), + svwhilele_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test6: +** whilels p0\.s, w0, w1 +** ret +*/ +svbool_t +test6 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b32 (), + svwhilele_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test7: +** whilels p0\.d, w0, w1 +** ret +*/ +svbool_t +test7 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilele_b64 (x, y), + svptrue_b64 ()); +} + +/* +** test8: +** whilele p0\.d, x0, x1 +** ret +*/ +svbool_t +test8 (int64_t x, int64_t y) +{ + return svand_z (svptrue_b16 (), + svwhilele_b64 (x, y), + svptrue_b32 ()); +} + +/* +** test9: +** whilels p0\.d, x0, x1 +** ret +*/ +svbool_t +test9 (uint64_t x, uint64_t y) +{ + return svand_z (svptrue_b64 (), + svwhilele_b64 (x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_6.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_6.c new file mode 100644 index 0000000..27bf0c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_6.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** whilelt p0\.h, w0, w1 +** ret +*/ +svbool_t +test1 (int32_t x, int32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilelt_b16 (x, y), + svptrue_b16 ()); +} + +/* +** test2: +** whilelt p0\.h, x0, x1 +** ret +*/ +svbool_t +test2 (int64_t x, int64_t y) +{ + return svand_z (svptrue_b16 (), + svwhilelt_b16 (x, y), + svptrue_b16 ()); +} + +/* +** test3: +** whilelo p0\.s, w0, w1 +** ret +*/ +svbool_t +test3 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilelt_b32 (x, y), + svptrue_b16 ()); +} + +/* +** test4: +** whilelo p0\.s, x0, x1 +** ret +*/ +svbool_t +test4 (uint64_t x, uint64_t y) +{ + return svand_z (svptrue_b8 (), + svwhilelt_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test5: +** whilelt p0\.s, w0, w1 +** ret +*/ +svbool_t +test5 (int32_t x, int32_t y) +{ + return svand_z (svptrue_b16 (), + svwhilelt_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test6: +** whilelo p0\.s, w0, w1 +** ret +*/ +svbool_t +test6 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b32 (), + svwhilelt_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test7: +** whilelo p0\.d, w0, w1 +** ret +*/ +svbool_t +test7 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilelt_b64 (x, y), + svptrue_b64 ()); +} + +/* +** test8: +** whilelt p0\.d, x0, x1 +** ret +*/ +svbool_t +test8 (int64_t x, int64_t y) +{ + return svand_z (svptrue_b16 (), + svwhilelt_b64 (x, y), + svptrue_b32 ()); +} + +/* +** test9: +** whilelo p0\.d, x0, x1 +** ret +*/ +svbool_t +test9 (uint64_t x, uint64_t y) +{ + return svand_z (svptrue_b64 (), + svwhilelt_b64 (x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_11.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_11.c new file mode 100644 index 0000000..feb7ee7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_11.c @@ -0,0 +1,20 @@ +/* Peeling for alignment with masking in VLA modes. */ +/* { dg-do compile } */ +/* { dg-options "-Ofast -msve-vector-bits=scalable --param aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */ + +#define START 3 +#define END 510 + +int __attribute__((noipa)) +foo (int *a) { + for (signed int i = START; i < END; ++i) { + if (a[i] != 0) + return i; + } + return -1; +} + +/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ +/* { dg-final { scan-tree-dump "pfa_iv_offset" "vect" } } */ +/* { dg-final { scan-tree-dump "Alignment of access forced using peeling" "vect" } } */ +/* { dg-final { scan-assembler {\tnot\tp[0-7]\.b, p[0-7]/z, p.*\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_11_run.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_11_run.c new file mode 100644 index 0000000..b4c267f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_11_run.c @@ -0,0 +1,27 @@ +/* Peeling for alignment with masking in VLA modes. */ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-Ofast -msve-vector-bits=scalable --param aarch64-autovec-preference=sve-only" } */ + +#include "peel_ind_11.c" +#include <stdio.h> +#include <stdlib.h> + +#define N 512 + +int __attribute__ ((optimize (1))) +main (void) +{ + for (int k = 5; k < 30; k++) { + int *a = (int *) malloc (sizeof(int) * N); + + /* Set only one non-zero element for test. */ + for (int i = 5; i < 30; i++) + a[i] = (i == k ? 1 : 0); + + int res = foo (a); + asm volatile (""); + if (res != k) { + __builtin_abort (); + } + } +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_12.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_12.c new file mode 100644 index 0000000..260482a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_12.c @@ -0,0 +1,21 @@ +/* Peeling for alignment with masking together with versioning in VLA modes. */ +/* { dg-do compile } */ +/* { dg-options "-Ofast -msve-vector-bits=scalable --param aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */ + +#define START 5 +#define END 509 + +int __attribute__((noipa)) +foo (int *restrict a, int * restrict b) { + for (signed int i = START; i < END; ++i) { + if (a[i] != b[i]) + return i; + } + return -1; +} + +/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ +/* { dg-final { scan-tree-dump "pfa_iv_offset" "vect" } } */ +/* { dg-final { scan-tree-dump "Both peeling and versioning will be applied" "vect" } } */ +/* { dg-final { scan-assembler {\tnot\tp[0-7]\.b, p[0-7]/z, p.*\n} } } */ +/* { dg-final { scan-assembler {\teor\t.*\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_12_run.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_12_run.c new file mode 100644 index 0000000..ba978fe --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_12_run.c @@ -0,0 +1,29 @@ +/* Peeling for alignment with masking together with versioning in VLA modes. */ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-Ofast -msve-vector-bits=scalable --param aarch64-autovec-preference=sve-only" } */ + +#include "peel_ind_12.c" +#include <stdio.h> +#include <stdlib.h> + +#define N 512 + +int __attribute__ ((optimize (1))) +main (void) { + for (int k = 5; k < 50; k++) { + int *a = (int *) malloc (sizeof(int) * N); + int *b = (int *) malloc (sizeof(int) * N); + + /* Set only one place of different values for test. */ + for (int i = 5; i < 50; i++) { + a[i] = (i == k ? 1 : 0); + b[i] = 0; + } + + int res = foo (a, b); + asm volatile (""); + if (res != k) { + __builtin_abort (); + } + } +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_13.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_13.c new file mode 100644 index 0000000..730e33e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_13.c @@ -0,0 +1,24 @@ +/* Known inbounds DR in VLA modes. */ +/* { dg-do compile } */ +/* { dg-options "-Ofast -msve-vector-bits=scalable --param aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */ + +#define N 512 +#define START 5 +#define END 509 + +int x[N] __attribute__((aligned(32))); + +int __attribute__((noipa)) +foo (void) +{ + for (signed int i = START; i < END; ++i) + { + if (x[i] == 0) + return i; + } + return -1; +} + +/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ +/* { dg-final { scan-tree-dump-not "pfa_iv_offset" "vect" } } */ +/* { dg-final { scan-tree-dump-not "Alignment of access forced using peeling" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_13_run.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_13_run.c new file mode 100644 index 0000000..83352a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_13_run.c @@ -0,0 +1,15 @@ +/* Known inbounds DR in VLA modes. */ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-Ofast -msve-vector-bits=scalable --param aarch64-autovec-preference=sve-only" } */ + +#include "peel_ind_13.c" + +int __attribute__ ((optimize (1))) +main (void) +{ + int res = foo (); + asm volatile (""); + if (res != START) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr119156_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pr119156_1.c new file mode 100644 index 0000000..35a5668 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr119156_1.c @@ -0,0 +1,15 @@ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void inner_loop_029(double *restrict input, int64_t *restrict scale, + double *restrict output, int64_t size) { + svbool_t p; + int64_t i = 0; + while (p = svwhilelt_b64(i, size), svptest_first(svptrue_b64(), p)) { + svst1(p, output+i, svld1(p, input+i)); + i += svcntd(); + } +} + +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_1.c index 38dfdd4..e777f03 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mcpu=neoverse-n2" } */ +/* { dg-options "-O2 -mcpu=neoverse-n2 -fdisable-rtl-combine" } */ /* { dg-final { check-function-bodies "**" "" } } */ #pragma GCC target "+sve" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_2.c b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_2.c index 45363cc..41182e1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mcpu=neoverse-v2" } */ +/* { dg-options "-O2 -mcpu=neoverse-v2 -fdisable-rtl-combine" } */ /* { dg-final { check-function-bodies "**" "" } } */ #pragma GCC target "+sve" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_3.c b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_3.c index c50a581..04a9023 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mcpu=neoverse-v1" } */ +/* { dg-options "-O2 -mcpu=neoverse-v1 -fdisable-rtl-combine" } */ /* { dg-final { check-function-bodies "**" "" } } */ #pragma GCC target "+sve" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmax_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmax_2.c new file mode 100644 index 0000000..f84ded5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmax_2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_builtin_fmax_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 14 } } */ +/* { dg-final { scan-assembler-times {\tand} 21 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmin_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmin_2.c new file mode 100644 index 0000000..bceddf9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmin_2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_builtin_fmin_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 14 } } */ +/* { dg-final { scan-assembler-times {\tand} 21 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fadd_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fadd_2.c new file mode 100644 index 0000000..e59864b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fadd_2.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_fadd_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 11 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 22 } } */ +/* { dg-final { scan-assembler-times {\tand} 33 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 19 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 19 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 19 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 5 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 10 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fdiv_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fdiv_2.c new file mode 100644 index 0000000..1ca3dbf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fdiv_2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_fdiv_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 6 } } */ +/* { dg-final { scan-assembler-times {\tand} 9 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 7 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfdivr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfdiv\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfdivr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfdiv\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmaxnm_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmaxnm_2.c new file mode 100644 index 0000000..282f3ed --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmaxnm_2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-signed-zeros -ffinite-math-only" } */ + +#include "unpacked_cond_fmaxnm_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 14 } } */ +/* { dg-final { scan-assembler-times {\tand} 21 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fminnm_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fminnm_2.c new file mode 100644 index 0000000..8226a6f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fminnm_2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-signed-zeros -ffinite-math-only" } */ + +#include "unpacked_cond_fminnm_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 14 } } */ +/* { dg-final { scan-assembler-times {\tand} 21 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmla_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmla_1.c new file mode 100644 index 0000000..cae9242 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmla_1.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define FMLA(SUFF) __builtin_fma##SUFF (a[i], b[i], c[i]) +#define FMLS(SUFF) __builtin_fma##SUFF (a[i], -b[i], c[i]) +#define FNMLA(SUFF) -FMLA (SUFF) +#define FNMLS(SUFF) -FMLS (SUFF) + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0) + +TEST_ALL (FMLA (f16), _Float16, uint64_t, 32) + +TEST_ALL (FMLA (f16), _Float16, uint32_t, 64) + +TEST_ALL (FMLA (f32), float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 12 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmad\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmad\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmla_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmla_2.c new file mode 100644 index 0000000..72e04a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmla_2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_fmla_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 8 } } */ +/* { dg-final { scan-assembler-times {\tand} 12 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 12 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmad\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmad\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmls_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmls_1.c new file mode 100644 index 0000000..db0f818 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmls_1.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define FMLA(SUFF) __builtin_fma##SUFF (a[i], b[i], c[i]) +#define FMLS(SUFF) __builtin_fma##SUFF (a[i], -b[i], c[i]) +#define FNMLA(SUFF) -FMLA (SUFF) +#define FNMLS(SUFF) -FMLS (SUFF) + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0) + +TEST_ALL (FMLS (f16), _Float16, uint64_t, 32) + +TEST_ALL (FMLS (f16), _Float16, uint32_t, 64) + +TEST_ALL (FMLS (f32), float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 12 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmsb\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmsb\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmls_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmls_2.c new file mode 100644 index 0000000..3012052 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmls_2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_fmls_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 8 } } */ +/* { dg-final { scan-assembler-times {\tand} 12 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 12 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmsb\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmsb\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmul_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmul_2.c new file mode 100644 index 0000000..21713f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmul_2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_fmul_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 5 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 10 } } */ +/* { dg-final { scan-assembler-times {\tand} 15 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 10 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 10 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 10 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmla_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmla_1.c new file mode 100644 index 0000000..07bab63 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmla_1.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define FMLA(SUFF) __builtin_fma##SUFF (a[i], b[i], c[i]) +#define FMLS(SUFF) __builtin_fma##SUFF (a[i], -b[i], c[i]) +#define FNMLA(SUFF) -FMLA (SUFF) +#define FNMLS(SUFF) -FMLS (SUFF) + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0) + +TEST_ALL (FNMLA (f16), _Float16, uint64_t, 32) + +TEST_ALL (FNMLA (f16), _Float16, uint32_t, 64) + +TEST_ALL (FNMLA (f32), float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 12 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfnmla\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfnmad\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfnmad\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfnmla\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmla_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmla_2.c new file mode 100644 index 0000000..daef4e49 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmla_2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_fnmla_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 8 } } */ +/* { dg-final { scan-assembler-times {\tand} 12 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 12 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfnmad\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfnmla\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfnmad\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfnmla\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmls_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmls_1.c new file mode 100644 index 0000000..5526378 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmls_1.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define FMLA(SUFF) __builtin_fma##SUFF (a[i], b[i], c[i]) +#define FMLS(SUFF) __builtin_fma##SUFF (a[i], -b[i], c[i]) +#define FNMLA(SUFF) -FMLA (SUFF) +#define FNMLS(SUFF) -FMLS (SUFF) + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0) + +TEST_ALL (FNMLS (f16), _Float16, uint64_t, 32) + +TEST_ALL (FNMLS (f16), _Float16, uint32_t, 64) + +TEST_ALL (FNMLS (f32), float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 12 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfnmsb\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfnmls\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfnmsb\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfnmls\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmls_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmls_2.c new file mode 100644 index 0000000..8a8f348 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fnmls_2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_fnmls_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 8 } } */ +/* { dg-final { scan-assembler-times {\tand} 12 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 12 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 12 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfnmsb\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfnmls\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfnmsb\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfnmls\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fsubr_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fsubr_2.c new file mode 100644 index 0000000..cd7a0e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fsubr_2.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include "unpacked_cond_fsubr_1.c" + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 14 } } */ +/* { dg-final { scan-assembler-times {\tand} 21 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmla_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmla_1.c new file mode 100644 index 0000000..312bccc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmla_1.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define FMLA(SUFF) __builtin_fma##SUFF (a[i], b[i], c[i]) +#define FMLS(SUFF) __builtin_fma##SUFF (a[i], -b[i], c[i]) +#define FNMLA(SUFF) -FMLA (SUFF) +#define FNMLS(SUFF) -FMLS (SUFF) + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE0 *__restrict d) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN > d[i]) \ + out[i] = 3; \ + } + +TEST_FN (FMLA (f16), _Float16, uint64_t, 32) + +TEST_FN (FMLA (f16), _Float16, uint32_t, 64) + +TEST_FN (FMLA (f32), float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\t(fmla|fmad)\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\t(fmla|fmad)\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmla_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmla_2.c new file mode 100644 index 0000000..ca3f94d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmla_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_fmla_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\t(fmla|fmad)\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\t(fmla|fmad)\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmls_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmls_1.c new file mode 100644 index 0000000..f7cbfb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmls_1.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define FMLA(SUFF) __builtin_fma##SUFF (a[i], b[i], c[i]) +#define FMLS(SUFF) __builtin_fma##SUFF (a[i], -b[i], c[i]) +#define FNMLA(SUFF) -FMLA (SUFF) +#define FNMLS(SUFF) -FMLS (SUFF) + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE0 *__restrict d) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN > d[i]) \ + out[i] = 3; \ + } + +TEST_FN (FMLS (f16), _Float16, uint64_t, 32) + +TEST_FN (FMLS (f16), _Float16, uint32_t, 64) + +TEST_FN (FMLS (f32), float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\t(fmls|fmsb)\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\t(fmls|fmsb)\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmls_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmls_2.c new file mode 100644 index 0000000..387dbec --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmls_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_fmls_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\t(fmls|fmsb)\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\t(fmls|fmsb)\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmla_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmla_1.c new file mode 100644 index 0000000..bf13ff5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmla_1.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define FMLA(SUFF) __builtin_fma##SUFF (a[i], b[i], c[i]) +#define FMLS(SUFF) __builtin_fma##SUFF (a[i], -b[i], c[i]) +#define FNMLA(SUFF) -FMLA (SUFF) +#define FNMLS(SUFF) -FMLS (SUFF) + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE0 *__restrict d) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN > d[i]) \ + out[i] = 3; \ + } + +TEST_FN (FNMLA (f16), _Float16, uint64_t, 32) + +TEST_FN (FNMLA (f16), _Float16, uint32_t, 64) + +TEST_FN (FNMLA (f32), float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\t(fnmla|fnmad)\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\t(fnmla|fnmad)\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmla_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmla_2.c new file mode 100644 index 0000000..64130ba --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmla_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_fnmla_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\t(fnmla|fnmad)\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\t(fnmla|fnmad)\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmls_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmls_1.c new file mode 100644 index 0000000..399920a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmls_1.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define FMLA(SUFF) __builtin_fma##SUFF (a[i], b[i], c[i]) +#define FMLS(SUFF) __builtin_fma##SUFF (a[i], -b[i], c[i]) +#define FNMLA(SUFF) -FMLA (SUFF) +#define FNMLS(SUFF) -FMLS (SUFF) + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE0 *__restrict d) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN > d[i]) \ + out[i] = 3; \ + } + +TEST_FN (FNMLS (f16), _Float16, uint64_t, 32) + +TEST_FN (FNMLS (f16), _Float16, uint32_t, 64) + +TEST_FN (FNMLS (f32), float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\t(fnmls|fnmsb)\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\t(fnmls|fnmsb)\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmls_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmls_2.c new file mode 100644 index 0000000..59fb7f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fnmls_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_fnmls_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\t(fnmls|fnmsb)\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\t(fnmls|fnmsb)\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/match_4.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/match_4.c new file mode 100644 index 0000000..57f625b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/match_4.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +svbool_t +test1 (svbool_t pg, svint16_t x, svint16_t y) +{ + return svand_z (svptrue_b8 (), + svmatch (pg, x, y), + svptrue_b16 ()); +} + +svbool_t +test2 (svbool_t pg, svint16_t x, svint16_t y) +{ + return svand_z (svptrue_b16 (), + svmatch (pg, x, y), + svptrue_b8 ()); +} + +svbool_t +test3 (svbool_t pg, svint16_t x, svint16_t y) +{ + return svand_z (svptrue_b16 (), + svmatch (pg, x, y), + svptrue_b16 ()); +} + +/* { dg-final { scan-assembler-not {\tand\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/nmatch_1.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/nmatch_1.c new file mode 100644 index 0000000..a3b1e2d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/nmatch_1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +svbool_t +test1 (svbool_t pg, svint16_t x, svint16_t y) +{ + return svand_z (svptrue_b8 (), + svnmatch (pg, x, y), + svptrue_b16 ()); +} + +svbool_t +test2 (svbool_t pg, svint16_t x, svint16_t y) +{ + return svand_z (svptrue_b16 (), + svnmatch (pg, x, y), + svptrue_b8 ()); +} + +svbool_t +test3 (svbool_t pg, svint16_t x, svint16_t y) +{ + return svand_z (svptrue_b16 (), + svnmatch (pg, x, y), + svptrue_b16 ()); +} + +/* { dg-final { scan-assembler-not {\tand\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilege_1.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilege_1.c new file mode 100644 index 0000000..07b56a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilege_1.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** whilege p0\.h, w0, w1 +** ret +*/ +svbool_t +test1 (int32_t x, int32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilege_b16 (x, y), + svptrue_b16 ()); +} + +/* +** test2: +** whilege p0\.h, x0, x1 +** ret +*/ +svbool_t +test2 (int64_t x, int64_t y) +{ + return svand_z (svptrue_b16 (), + svwhilege_b16 (x, y), + svptrue_b16 ()); +} + +/* +** test3: +** whilehs p0\.s, w0, w1 +** ret +*/ +svbool_t +test3 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilege_b32 (x, y), + svptrue_b16 ()); +} + +/* +** test4: +** whilehs p0\.s, x0, x1 +** ret +*/ +svbool_t +test4 (uint64_t x, uint64_t y) +{ + return svand_z (svptrue_b8 (), + svwhilege_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test5: +** whilege p0\.s, w0, w1 +** ret +*/ +svbool_t +test5 (int32_t x, int32_t y) +{ + return svand_z (svptrue_b16 (), + svwhilege_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test6: +** whilehs p0\.s, w0, w1 +** ret +*/ +svbool_t +test6 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b32 (), + svwhilege_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test7: +** whilehs p0\.d, w0, w1 +** ret +*/ +svbool_t +test7 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilege_b64 (x, y), + svptrue_b64 ()); +} + +/* +** test8: +** whilege p0\.d, x0, x1 +** ret +*/ +svbool_t +test8 (int64_t x, int64_t y) +{ + return svand_z (svptrue_b16 (), + svwhilege_b64 (x, y), + svptrue_b32 ()); +} + +/* +** test9: +** whilehs p0\.d, x0, x1 +** ret +*/ +svbool_t +test9 (uint64_t x, uint64_t y) +{ + return svand_z (svptrue_b64 (), + svwhilege_b64 (x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilegt_1.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilegt_1.c new file mode 100644 index 0000000..df707c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilegt_1.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** whilegt p0\.h, w0, w1 +** ret +*/ +svbool_t +test1 (int32_t x, int32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilegt_b16 (x, y), + svptrue_b16 ()); +} + +/* +** test2: +** whilegt p0\.h, x0, x1 +** ret +*/ +svbool_t +test2 (int64_t x, int64_t y) +{ + return svand_z (svptrue_b16 (), + svwhilegt_b16 (x, y), + svptrue_b16 ()); +} + +/* +** test3: +** whilehi p0\.s, w0, w1 +** ret +*/ +svbool_t +test3 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilegt_b32 (x, y), + svptrue_b16 ()); +} + +/* +** test4: +** whilehi p0\.s, x0, x1 +** ret +*/ +svbool_t +test4 (uint64_t x, uint64_t y) +{ + return svand_z (svptrue_b8 (), + svwhilegt_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test5: +** whilegt p0\.s, w0, w1 +** ret +*/ +svbool_t +test5 (int32_t x, int32_t y) +{ + return svand_z (svptrue_b16 (), + svwhilegt_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test6: +** whilehi p0\.s, w0, w1 +** ret +*/ +svbool_t +test6 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b32 (), + svwhilegt_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test7: +** whilehi p0\.d, w0, w1 +** ret +*/ +svbool_t +test7 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilegt_b64 (x, y), + svptrue_b64 ()); +} + +/* +** test8: +** whilegt p0\.d, x0, x1 +** ret +*/ +svbool_t +test8 (int64_t x, int64_t y) +{ + return svand_z (svptrue_b16 (), + svwhilegt_b64 (x, y), + svptrue_b32 ()); +} + +/* +** test9: +** whilehi p0\.d, x0, x1 +** ret +*/ +svbool_t +test9 (uint64_t x, uint64_t y) +{ + return svand_z (svptrue_b64 (), + svwhilegt_b64 (x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilerw_5.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilerw_5.c new file mode 100644 index 0000000..0c24199 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilerw_5.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** whilerw p0\.h, x0, x1 +** ret +*/ +svbool_t +test1 (int16_t *x, int16_t *y) +{ + return svand_z (svptrue_b8 (), + svwhilerw (x, y), + svptrue_b16 ()); +} + +/* +** test2: +** whilerw p0\.h, x0, x1 +** ret +*/ +svbool_t +test2 (uint16_t *x, uint16_t *y) +{ + return svand_z (svptrue_b16 (), + svwhilerw (x, y), + svptrue_b16 ()); +} + +/* +** test3: +** whilerw p0\.s, x0, x1 +** ret +*/ +svbool_t +test3 (int32_t *x, int32_t *y) +{ + return svand_z (svptrue_b8 (), + svwhilerw (x, y), + svptrue_b16 ()); +} + +/* +** test4: +** whilerw p0\.s, x0, x1 +** ret +*/ +svbool_t +test4 (uint32_t *x, uint32_t *y) +{ + return svand_z (svptrue_b8 (), + svwhilerw (x, y), + svptrue_b32 ()); +} + +/* +** test5: +** whilerw p0\.s, x0, x1 +** ret +*/ +svbool_t +test5 (float32_t *x, float32_t *y) +{ + return svand_z (svptrue_b16 (), + svwhilerw (x, y), + svptrue_b32 ()); +} + +/* +** test6: +** whilerw p0\.s, x0, x1 +** ret +*/ +svbool_t +test6 (int32_t *x, int32_t *y) +{ + return svand_z (svptrue_b32 (), + svwhilerw (x, y), + svptrue_b32 ()); +} + +/* +** test7: +** whilerw p0\.d, x0, x1 +** ret +*/ +svbool_t +test7 (int64_t *x, int64_t *y) +{ + return svand_z (svptrue_b8 (), + svwhilerw (x, y), + svptrue_b64 ()); +} + +/* +** test8: +** whilerw p0\.d, x0, x1 +** ret +*/ +svbool_t +test8 (uint64_t *x, uint64_t *y) +{ + return svand_z (svptrue_b16 (), + svwhilerw (x, y), + svptrue_b32 ()); +} + +/* +** test9: +** whilerw p0\.d, x0, x1 +** ret +*/ +svbool_t +test9 (float64_t *x, float64_t *y) +{ + return svand_z (svptrue_b64 (), + svwhilerw (x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilewr_5.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilewr_5.c new file mode 100644 index 0000000..38db9af --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilewr_5.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** whilewr p0\.h, x0, x1 +** ret +*/ +svbool_t +test1 (int16_t *x, int16_t *y) +{ + return svand_z (svptrue_b8 (), + svwhilewr (x, y), + svptrue_b16 ()); +} + +/* +** test2: +** whilewr p0\.h, x0, x1 +** ret +*/ +svbool_t +test2 (uint16_t *x, uint16_t *y) +{ + return svand_z (svptrue_b16 (), + svwhilewr (x, y), + svptrue_b16 ()); +} + +/* +** test3: +** whilewr p0\.s, x0, x1 +** ret +*/ +svbool_t +test3 (int32_t *x, int32_t *y) +{ + return svand_z (svptrue_b8 (), + svwhilewr (x, y), + svptrue_b16 ()); +} + +/* +** test4: +** whilewr p0\.s, x0, x1 +** ret +*/ +svbool_t +test4 (uint32_t *x, uint32_t *y) +{ + return svand_z (svptrue_b8 (), + svwhilewr (x, y), + svptrue_b32 ()); +} + +/* +** test5: +** whilewr p0\.s, x0, x1 +** ret +*/ +svbool_t +test5 (float32_t *x, float32_t *y) +{ + return svand_z (svptrue_b16 (), + svwhilewr (x, y), + svptrue_b32 ()); +} + +/* +** test6: +** whilewr p0\.s, x0, x1 +** ret +*/ +svbool_t +test6 (int32_t *x, int32_t *y) +{ + return svand_z (svptrue_b32 (), + svwhilewr (x, y), + svptrue_b32 ()); +} + +/* +** test7: +** whilewr p0\.d, x0, x1 +** ret +*/ +svbool_t +test7 (int64_t *x, int64_t *y) +{ + return svand_z (svptrue_b8 (), + svwhilewr (x, y), + svptrue_b64 ()); +} + +/* +** test8: +** whilewr p0\.d, x0, x1 +** ret +*/ +svbool_t +test8 (uint64_t *x, uint64_t *y) +{ + return svand_z (svptrue_b16 (), + svwhilewr (x, y), + svptrue_b32 ()); +} + +/* +** test9: +** whilewr p0\.d, x0, x1 +** ret +*/ +svbool_t +test9 (float64_t *x, float64_t *y) +{ + return svand_z (svptrue_b64 (), + svwhilewr (x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/torture/pr120986-2.c b/gcc/testsuite/gcc.target/aarch64/torture/pr120986-2.c new file mode 100644 index 0000000..1218dea --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/torture/pr120986-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8.2-a+sve2+fp8dot2" } */ +#include <arm_sve.h> +svfloat16_t foo(svfloat16_t a, svmfloat8_t b, svmfloat8_t c) +{ + return svdot_lane_fpm (a, b, c, 0, 0); +} diff --git a/gcc/testsuite/gcc.target/aarch64/vect-pr121754.c b/gcc/testsuite/gcc.target/aarch64/vect-pr121754.c new file mode 100644 index 0000000..8b6a757 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-pr121754.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -mcpu=neoverse-v2" } */ + +float a; +void +fn1 (int b) +{ + for (; b < 10; b++) + { + a = 01.; + for (int c = 0; c < 2000; c++) + a *= 0.99; + } +} diff --git a/gcc/testsuite/gcc.target/aarch64/vld2-1.c b/gcc/testsuite/gcc.target/aarch64/vld2-1.c index 8a26767..0a5b97b 100644 --- a/gcc/testsuite/gcc.target/aarch64/vld2-1.c +++ b/gcc/testsuite/gcc.target/aarch64/vld2-1.c @@ -42,4 +42,5 @@ void func3(float32x2x2_t *p, const float *p1, const float *p2) *p = vld2_lane_f32(p2, v, 1); } -/* { dg-final { scan-tree-dump-times "after previous" 3 "forwprop1" } } */ +/* 2 copy props for each function */ +/* { dg-final { scan-tree-dump-times "after previous" 6 "forwprop1" } } */ diff --git a/gcc/testsuite/gcc.target/arm/acle/mcrr.c b/gcc/testsuite/gcc.target/arm/acle/mcrr.c index 468dd96..5081f71 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mcrr.c +++ b/gcc/testsuite/gcc.target/arm/acle/mcrr.c @@ -3,6 +3,7 @@ /* { dg-do assemble } */ /* { dg-options "-save-temps" } */ /* { dg-require-effective-target arm_coproc3_ok } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ #include "arm_acle.h" #if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ @@ -15,6 +16,22 @@ void test_mcrr (uint64_t a) a += 77; __arm_mcrr (10, 5, a, 3); } +/* +** test_mcrr: +** ... +** add.*#77 +** ... +** mcrr p10, #5, r[0-9]+, r[0-9]+, CR3 +** ... +*/ -/* { dg-final { scan-assembler "add\[^\n\]*#77\n" } } */ -/* { dg-final { scan-assembler "mcrr\tp10, #5, r\[r0-9\]*, r\[r0-9\]*, CR3\n" } } */ +void test_mcrr_pr121464 (uint64_t a) +{ + __arm_mcrr (7, 11, a, 0); +} +/* +** test_mcrr_pr121464: +** ... +** mcrr p7, #11, r[0-9]+, r[0-9]+, CR0 +** ... +*/ diff --git a/gcc/testsuite/gcc.target/arm/acle/mcrr2.c b/gcc/testsuite/gcc.target/arm/acle/mcrr2.c index 1173ad0..a0f93cc 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mcrr2.c +++ b/gcc/testsuite/gcc.target/arm/acle/mcrr2.c @@ -3,6 +3,7 @@ /* { dg-do assemble } */ /* { dg-options "-save-temps" } */ /* { dg-require-effective-target arm_coproc4_ok } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ #include "arm_acle.h" #if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ @@ -15,6 +16,25 @@ void test_mcrr2 (uint64_t a) a += 77; __arm_mcrr2 (10, 5, a, 3); } +/* +** test_mcrr2: +** ... +** add.*#77 +** ... +** mcrr2 p10, #5, r[0-9]+, r[0-9]+, CR3 +** ... +*/ -/* { dg-final { scan-assembler "add\[^\n\]*#77\n" } } */ -/* { dg-final { scan-assembler "mcrr2\tp10, #5, r\[r0-9\]*, r\[r0-9\]*, CR3\n" } } */ +void test_mcrr2_pr121464 (void) +{ + __arm_mcrr2 (3, 12, 49, 4); +} + +/* +** test_mcrr2_pr121464: +** ... +** mov.*#49 +** ... +** mcrr2 p3, #12, r[0-9]+, r[0-9]+, CR4 +** ... +*/ diff --git a/gcc/testsuite/gcc.target/arm/acle/mrrc.c b/gcc/testsuite/gcc.target/arm/acle/mrrc.c index c004660..54e542b 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mrrc.c +++ b/gcc/testsuite/gcc.target/arm/acle/mrrc.c @@ -3,6 +3,7 @@ /* { dg-do assemble } */ /* { dg-options "-save-temps" } */ /* { dg-require-effective-target arm_coproc3_ok } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ #include "arm_acle.h" #if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ @@ -15,4 +16,21 @@ uint64_t test_mrrc (void) return __arm_mrrc (10, 5, 3); } -/* { dg-final { scan-assembler "mrrc\tp10, #5, r\[r0-9\]*, r\[r0-9\]*, CR3\n" } } */ +/* +** test_mrrc: +** ... +** mrrc p10, #5, r[0-9]+, r[0-9]+, CR3 +** ... +*/ + +uint64_t test_mrrc_pr121464 (void) +{ + return __arm_mrrc (15, 9, 7); +} + +/* +** test_mrrc_pr121464: +** ... +** mrrc p15, #9, r[0-9]+, r[0-9]+, CR7 +** ... +*/ diff --git a/gcc/testsuite/gcc.target/arm/acle/mrrc2.c b/gcc/testsuite/gcc.target/arm/acle/mrrc2.c index b5d56da..8d8937a 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mrrc2.c +++ b/gcc/testsuite/gcc.target/arm/acle/mrrc2.c @@ -3,6 +3,7 @@ /* { dg-do assemble } */ /* { dg-options "-save-temps" } */ /* { dg-require-effective-target arm_coproc4_ok } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ #include "arm_acle.h" #if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ @@ -14,5 +15,20 @@ uint64_t test_mrrc2 (void) { return __arm_mrrc2 (10, 5, 3); } +/* +** test_mrrc2: +** ... +** mrrc2 p10, #5, r[0-9]+, r[0-9]+, CR3 +** ... +*/ -/* { dg-final { scan-assembler "mrrc2\tp10, #5, r\[r0-9\]*, r\[r0-9\]*, CR3\n" } } */ +uint64_t test_mrrc2_pr121464 (void) +{ + return __arm_mrrc2 (0, 15, 10); +} +/* +** test_mrrc2_pr121464: +** ... +** mrrc2 p0, #15, r[0-9]+, r[0-9]+, CR10 +** ... +*/ diff --git a/gcc/testsuite/gcc.target/arm/bics_3.c b/gcc/testsuite/gcc.target/arm/bics_3.c index 4d69389..deea15f 100644 --- a/gcc/testsuite/gcc.target/arm/bics_3.c +++ b/gcc/testsuite/gcc.target/arm/bics_3.c @@ -2,11 +2,14 @@ /* { dg-options "-O2 --save-temps -fno-inline" } */ /* { dg-require-effective-target arm32 } */ +volatile int three = 3; + +/* The following need a BICS, rather than BIC+CMP. */ int bics_si_test (int a, int b) { if ((a & ~b) >= 0) - return 3; + return three; else return 0; } @@ -15,6 +18,25 @@ int bics_si_test2 (int a, int b) { if ((a & ~ (b << 2)) >= 0) + return three; + else + return 0; +} + +/* The following no-longer need a BICS and conditional execution. */ +int +bics_si_test3 (int a, int b) +{ + if ((a & ~b) >= 0) + return 3; + else + return 0; +} + +int +bics_si_test4 (int a, int b) +{ + if ((a & ~ (b << 2)) >= 0) return 3; else return 0; @@ -30,8 +52,15 @@ main (void) __builtin_abort (); if (bics_si_test2 (c, b) != 3) __builtin_abort (); + if (bics_si_test3 (a, b) != 3) + __builtin_abort (); + if (bics_si_test4 (c, b) != 3) + __builtin_abort (); return 0; } /* { dg-final { scan-assembler-times "bics\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" 2 } } */ /* { dg-final { scan-assembler-times "bics\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+, .sl #2" 1 } } */ +/* { dg-final { scan-assembler-times "bic\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler-times "bic\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+, .sl #2" 1 } } */ +/* { dg-final { scan-assembler-not "cmp\tr\[0-9]+, #0" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c b/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c index db7d975..eb8a358 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c +++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-mcmse -fdump-rtl-final-slim" } */ +/* Make sure FPCXT is not enabled. */ +/* { dg-options "-mcmse -fdump-rtl-final -march=armv8-m.main+fp" } */ typedef void (*f)(int) __attribute__((cmse_nonsecure_call)); @@ -8,5 +9,5 @@ void bar(f func, int a) func(a); } -/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r4:SI\\\]\\\]" "final" { target { ! arm_v8_1m_mve_ok } } } } */ -/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r\[0-7\]:SI\\\]\\\]" "final" { target { arm_v8_1m_mve_ok } } } } */ +/* { dg-final { scan-rtl-dump "call \\\(mem:SI \\\(reg:SI 4 r4" "final" } } */ +/* { dg-final { scan-rtl-dump "UNSPEC_NONSECURE_MEM" "final" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-19.c b/gcc/testsuite/gcc.target/arm/cmse/cmse-19.c new file mode 100644 index 0000000..ae075c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-19.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* This is a duplicate of cmse-18.c, targetting arm_v8_1m_mve, to make sure + FPCXT is enabled. */ +/* { dg-options "-mcmse -fdump-rtl-final -march=armv8.1-m.main+mve" } */ + +typedef void (*f)(int) __attribute__((cmse_nonsecure_call)); + +void bar(f func, int a) +{ + func(a); +} + +/* { dg-final { scan-rtl-dump "call \\\(mem:SI \\\(reg/f:SI \[0-7] r\[0-7\]" "final" } } */ +/* { dg-final { scan-rtl-dump "UNSPEC_NONSECURE_MEM" "final" } } */ diff --git a/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c b/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c index d9f95a1..8a1a293 100644 --- a/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c +++ b/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c @@ -1,26 +1,21 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_thumb2_ok } */ -/* { dg-options "-O2 -mthumb" } */ +/* { dg-options "-O2 -mthumb -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ /* ** foo: -** movs (r[0-9]+), #8 ** ( -** subs \1, \1, #1 -** ands \1, \1, #255 +** movs (r[0-9]+), #8 ** and r0, r1, r0, lsr #1 -** bne .L[0-9]+ -** bx lr -** | ** subs \1, \1, #1 -** and r0, r1, r0, lsr #1 ** ands \1, \1, #255 ** bne .L[0-9]+ ** bx lr ** | ** push {lr} -** dls lr, \1 +** movs (r[0-9]+), #8 +** dls lr, \2 ** and r0, r1, r0, lsr #1 ** le lr, .L[0-9]+ ** pop {pc} diff --git a/gcc/testsuite/gcc.target/avr/torture/pr118591-1.c b/gcc/testsuite/gcc.target/avr/torture/pr118591-1.c index 814f041..6f54c63 100644 --- a/gcc/testsuite/gcc.target/avr/torture/pr118591-1.c +++ b/gcc/testsuite/gcc.target/avr/torture/pr118591-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { ! avr_tiny } } } */ -/* { dg-additional-options "-std=c99 -mlra" } */ +/* { dg-additional-options "-std=c99" } */ __attribute__((noipa)) void func2 (long long a1, long long a2, long b) diff --git a/gcc/testsuite/gcc.target/avr/torture/pr118591-2.c b/gcc/testsuite/gcc.target/avr/torture/pr118591-2.c index 83d3606..222af09 100644 --- a/gcc/testsuite/gcc.target/avr/torture/pr118591-2.c +++ b/gcc/testsuite/gcc.target/avr/torture/pr118591-2.c @@ -1,6 +1,6 @@ /* Test case failed on avrtiny. */ /* { dg-do run } */ -/* { dg-additional-options "-std=c99 -mlra" } */ +/* { dg-additional-options "-std=c99" } */ __attribute__((noipa)) void func2 (long a, long b) diff --git a/gcc/testsuite/gcc.target/i386/20020224-1.c b/gcc/testsuite/gcc.target/i386/20020224-1.c index 2905719..769332b 100644 --- a/gcc/testsuite/gcc.target/i386/20020224-1.c +++ b/gcc/testsuite/gcc.target/i386/20020224-1.c @@ -4,6 +4,7 @@ while callee was actually not poping it up (as the hidden argument was passed in register). */ /* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ /* { dg-options "-O2 -fomit-frame-pointer" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/apx-1.c b/gcc/testsuite/gcc.target/i386/apx-1.c index 4e580ec..b118928 100644 --- a/gcc/testsuite/gcc.target/i386/apx-1.c +++ b/gcc/testsuite/gcc.target/i386/apx-1.c @@ -3,6 +3,6 @@ /* { dg-error "'-mapxf' is not supported for 32-bit code" "" { target ia32 } 0 } */ void -apx_hanlder () +apx_handler () { } diff --git a/gcc/testsuite/gcc.target/i386/asm-hard-reg-2.c b/gcc/testsuite/gcc.target/i386/asm-hard-reg-2.c index b35cf53..756f6f8 100644 --- a/gcc/testsuite/gcc.target/i386/asm-hard-reg-2.c +++ b/gcc/testsuite/gcc.target/i386/asm-hard-reg-2.c @@ -8,7 +8,7 @@ test (void) #ifdef __x86_64__ int z __attribute__ ((mode (TI))); #else - long z; + long long z; #endif __asm__ __volatile__ ("" : "=A" (z), "={rbx}" (y)); diff --git a/gcc/testsuite/gcc.target/i386/attributes-error.c b/gcc/testsuite/gcc.target/i386/attributes-error.c index 405eda5..5d1c77d 100644 --- a/gcc/testsuite/gcc.target/i386/attributes-error.c +++ b/gcc/testsuite/gcc.target/i386/attributes-error.c @@ -1,12 +1,40 @@ +/* { dg-options "-msse2" } */ /* { dg-do compile } */ /* { dg-require-effective-target ia32 } */ -void foo1(int i, int j) __attribute__((fastcall, cdecl)); /* { dg-error "not compatible" } */ -void foo2(int i, int j) __attribute__((fastcall, stdcall)); /* { dg-error "not compatible" } */ +void foo1(int i, int j) __attribute__((cdecl, regparm(2))); +void foo2(int i, int j) __attribute__((stdcall, regparm(2))); void foo3(int i, int j) __attribute__((fastcall, regparm(2))); /* { dg-error "not compatible" } */ -void foo4(int i, int j) __attribute__((stdcall, cdecl)); /* { dg-error "not compatible" } */ -void foo5(int i, int j) __attribute__((stdcall, fastcall)); /* { dg-error "not compatible" } */ -void foo6(int i, int j) __attribute__((cdecl, fastcall)); /* { dg-error "not compatible" } */ -void foo7(int i, int j) __attribute__((cdecl, stdcall)); /* { dg-error "not compatible" } */ -void foo8(int i, int j) __attribute__((regparm(2), fastcall)); /* { dg-error "not compatible" } */ +void foo4(int i, int j) __attribute__((thiscall, regparm(2))); /* { dg-error "not compatible" } */ +void foo5(int i, int j) __attribute__((sseregparm, regparm(2))); + +void foo6(int i, int j) __attribute__((stdcall, fastcall)); /* { dg-error "not compatible" } */ +void foo7(int i, int j) __attribute__((regparm(2), fastcall)); /* { dg-error "not compatible" } */ +void foo8(int i, int j) __attribute__((cdecl, fastcall)); /* { dg-error "not compatible" } */ +void foo9(int i, int j) __attribute__((thiscall, fastcall)); /* { dg-error "not compatible" } */ +void foo10(int i, int j) __attribute__((sseregparm, fastcall)); + +void foo11(int i, int j) __attribute__((cdecl, stdcall)); /* { dg-error "not compatible" } */ +void foo12(int i, int j) __attribute__((fastcall, stdcall)); /* { dg-error "not compatible" } */ +void foo13(int i, int j) __attribute__((thiscall, stdcall)); /* { dg-error "not compatible" } */ +void foo14(int i, int j) __attribute__((regparm(2), stdcall)); +void foo15(int i, int j) __attribute__((sseregparm, stdcall)); + +void foo16(int i, int j) __attribute__((stdcall, cdecl)); /* { dg-error "not compatible" } */ +void foo17(int i, int j) __attribute__((fastcall, cdecl)); /* { dg-error "not compatible" } */ +void foo18(int i, int j) __attribute__((thiscall, cdecl)); /* { dg-error "not compatible" } */ +void foo19(int i, int j) __attribute__((regparm(2), cdecl)); +void foo20(int i, int j) __attribute__((sseregparm, cdecl)); + +void foo21(int i, int j) __attribute__((stdcall, thiscall)); /* { dg-error "not compatible" } */ +void foo22(int i, int j) __attribute__((fastcall, thiscall)); /* { dg-error "not compatible" } */ +void foo23(int i, int j) __attribute__((cdecl, thiscall)); /* { dg-error "not compatible" } */ +void foo24(int i, int j) __attribute__((regparm(2), thiscall)); /* { dg-error "not compatible" } */ +void foo25(int i, int j) __attribute__((sseregparm, thiscall)); + +void foo26(int i, int j) __attribute__((cdecl, sseregparm)); +void foo27(int i, int j) __attribute__((fastcall, sseregparm)); +void foo28(int i, int j) __attribute__((stdcall, sseregparm)); +void foo29(int i, int j) __attribute__((thiscall, sseregparm)); +void foo30(int i, int j) __attribute__((regparm(2), sseregparm)); diff --git a/gcc/testsuite/gcc.target/i386/attributes-ignore.c b/gcc/testsuite/gcc.target/i386/attributes-ignore.c new file mode 100644 index 0000000..93a3770 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/attributes-ignore.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target { ! ia32 } } } */ + +void foo1(int i, int j) __attribute__((regparm(0))); /* { dg-warning "ignored" } */ +void foo2(int i, int j) __attribute__((stdcall)); /* { dg-warning "ignored" } */ +void foo3(int i, int j) __attribute__((fastcall)); /* { dg-warning "ignored" } */ +void foo4(int i, int j) __attribute__((cdecl)); /* { dg-warning "ignored" } */ +void foo5(int i, int j) __attribute__((thiscall)); /* { dg-warning "ignored" } */ +void foo6(int i, int j) __attribute__((sseregparm)); /* { dg-warning "ignored" } */ diff --git a/gcc/testsuite/gcc.target/i386/memcpy-strategy-14.c b/gcc/testsuite/gcc.target/i386/memcpy-strategy-14.c new file mode 100644 index 0000000..44cd652 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memcpy-strategy-14.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -mno-avx -msse2 -mtune=generic -minline-all-stringops -mstringop-strategy=vector_loop" } */ +/* { dg-final { scan-assembler-times "movaps" 8 } } */ + +char a[2048]; +char b[2048]; +void t (void) +{ + __builtin_memcpy (a, b, 2048); +} diff --git a/gcc/testsuite/gcc.target/i386/memcpy-strategy-15.c b/gcc/testsuite/gcc.target/i386/memcpy-strategy-15.c new file mode 100644 index 0000000..ea8e4be --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memcpy-strategy-15.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -mno-avx -msse2 -mtune=generic -minline-all-stringops -mstringop-strategy=vector_loop" } */ +/* { dg-final { scan-assembler-times "movups" 8 } } */ + +char *a; +char *b; +void t (void) +{ + __builtin_memcpy (a, b, 2048); +} diff --git a/gcc/testsuite/gcc.target/i386/memset-strategy-10.c b/gcc/testsuite/gcc.target/i386/memset-strategy-10.c new file mode 100644 index 0000000..b4a93a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-strategy-10.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -march=x86-64 -mstringop-strategy=vector_loop -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** xorps %xmm0, %xmm0 +** xorl %eax, %eax +** movq %rax, 48\(%(e|r)di\) +** movups %xmm0, \(%(e|r)di\) +** movups %xmm0, 16\(%(e|r)di\) +** movups %xmm0, 32\(%(e|r)di\) +** ret +**... +*/ + +void +foo (char *a) +{ + __builtin_memset (a, 0, 56); +} diff --git a/gcc/testsuite/gcc.target/i386/memset-strategy-11.c b/gcc/testsuite/gcc.target/i386/memset-strategy-11.c new file mode 100644 index 0000000..851c6fa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-strategy-11.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -mno-avx -msse2 -mtune=generic -minline-all-stringops -mstringop-strategy=vector_loop" } */ +/* { dg-final { scan-assembler-times "movaps" 4 } } */ + +char a[2048]; +void t (void) +{ + __builtin_memset (a, 0, 2048); +} diff --git a/gcc/testsuite/gcc.target/i386/memset-strategy-12.c b/gcc/testsuite/gcc.target/i386/memset-strategy-12.c new file mode 100644 index 0000000..06cac03 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-strategy-12.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -mno-sse -mstringop-strategy=vector_loop" } */ + +void +foo (char *a) +{ + __builtin_memset (a, 0, 56); +} diff --git a/gcc/testsuite/gcc.target/i386/memset-strategy-13.c b/gcc/testsuite/gcc.target/i386/memset-strategy-13.c new file mode 100644 index 0000000..be67610 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-strategy-13.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -mno-sse -mstringop-strategy=unrolled_loop -fasynchronous-unwind-tables -fdwarf2-cfi-asm" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +** .cfi_startproc +** xorl %eax, %eax +** movq %rax, \(%(e|r)di\) +** movq %rax, 8\(%(e|r)di\) +** movq %rax, 16\(%(e|r)di\) +** movq %rax, 24\(%(e|r)di\) +** movq %rax, 32\(%(e|r)di\) +** movq %rax, 40\(%(e|r)di\) +** movq %rax, 48\(%(e|r)di\) +** ret +**... +*/ + +void +foo (char *a) +{ + __builtin_memset (a, 0, 56); +} diff --git a/gcc/testsuite/gcc.target/i386/memset-strategy-14.c b/gcc/testsuite/gcc.target/i386/memset-strategy-14.c new file mode 100644 index 0000000..144235e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-strategy-14.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -march=x86-64 -mstringop-strategy=vector_loop" } */ + +void +foo (char *a, int c) +{ + __builtin_memset (a, c, 56); +} diff --git a/gcc/testsuite/gcc.target/i386/memset-strategy-15.c b/gcc/testsuite/gcc.target/i386/memset-strategy-15.c new file mode 100644 index 0000000..66f9fa6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-strategy-15.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -mno-avx -msse2 -mtune=generic -mstringop-strategy=vector_loop" } */ +/* { dg-final { scan-assembler-times "movups" 4} } */ + +char *a; +void t (void) +{ + __builtin_memset (a, 0, 2048); +} diff --git a/gcc/testsuite/gcc.target/i386/memset-strategy-16.c b/gcc/testsuite/gcc.target/i386/memset-strategy-16.c new file mode 100644 index 0000000..a8d60e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-strategy-16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mstringop-strategy=rep_4byte" } */ + +extern unsigned x[]; +void +foo (void) +{ + __builtin_memset(x, 0, 847); +} diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-19a.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-19a.c index 12f35cf..3ba578d 100644 --- a/gcc/testsuite/gcc.target/i386/no-callee-saved-19a.c +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-19a.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { *-*-linux* && lp64 } } } */ -/* { dg-options "-O2 -fno-pic -mtune=generic -msse2 -mno-apxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ +/* { dg-options "-O2 -fno-pic -mtune=generic -msse2 -mno-avx -mno-mmx -mno-80387 -mno-apxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-19b.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-19b.c index c9343a6..dc38936 100644 --- a/gcc/testsuite/gcc.target/i386/no-callee-saved-19b.c +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-19b.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { *-*-linux* && maybe_x32 } } } */ -/* { dg-options "-O2 -mx32 -fno-pic -mtune=generic -msse2 -mno-apxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ +/* { dg-options "-O2 -mx32 -fno-pic -mtune=generic -msse2 -mno-avx -mno-mmx -mno-80387 -mno-apxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-19c.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-19c.c index 05aca9f..e7f247b 100644 --- a/gcc/testsuite/gcc.target/i386/no-callee-saved-19c.c +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-19c.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { *-*-linux* && ia32 } } } */ -/* { dg-options "-O2 -fno-pic -mtune=generic -msse2 -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ +/* { dg-options "-O2 -fno-pic -mtune=generic -msse2 -mno-avx -mno-mmx -mno-80387 -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-19d.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-19d.c index b3caa3d..4657e17 100644 --- a/gcc/testsuite/gcc.target/i386/no-callee-saved-19d.c +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-19d.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { *-*-linux* && lp64 } } } */ -/* { dg-options "-O2 -fno-pic -mtune=generic -msse2 -mapxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ +/* { dg-options "-O2 -fno-pic -mtune=generic -msse2 -mno-avx -mno-mmx -mno-80387 -mapxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/no-callee-saved-19e.c b/gcc/testsuite/gcc.target/i386/no-callee-saved-19e.c index 3fcb41f..8e0bbe8 100644 --- a/gcc/testsuite/gcc.target/i386/no-callee-saved-19e.c +++ b/gcc/testsuite/gcc.target/i386/no-callee-saved-19e.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { *-*-linux* && maybe_x32 } } } */ -/* { dg-options "-O2 -mx32 -fno-pic -mtune=generic -msse2 -mapxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ +/* { dg-options "-O2 -mx32 -fno-pic -mtune=generic -msse2 -mno-avx -mno-mmx -mno-80387 -mapxf -mtune-ctrl=prologue_using_move,epilogue_using_move" } */ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ /* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */ diff --git a/gcc/testsuite/gcc.target/i386/noplt-gd-1.c b/gcc/testsuite/gcc.target/i386/noplt-gd-1.c index 5d5b531..7eac70a 100644 --- a/gcc/testsuite/gcc.target/i386/noplt-gd-1.c +++ b/gcc/testsuite/gcc.target/i386/noplt-gd-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { *-*-linux* && tls_get_addr_via_got } } } */ -/* { dg-options "-fpic -fno-plt" } */ +/* { dg-options "-fpic -fno-plt -mtls-dialect=gnu" } */ extern __thread int gd; diff --git a/gcc/testsuite/gcc.target/i386/noplt-ld-1.c b/gcc/testsuite/gcc.target/i386/noplt-ld-1.c index 8769830..12dcb7a 100644 --- a/gcc/testsuite/gcc.target/i386/noplt-ld-1.c +++ b/gcc/testsuite/gcc.target/i386/noplt-ld-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { *-*-linux* && tls_get_addr_via_got } } } */ -/* { dg-options "-fpic -fno-plt" } */ +/* { dg-options "-fpic -fno-plt -mtls-dialect=gnu" } */ static __thread int ld; diff --git a/gcc/testsuite/gcc.target/i386/pr103785.c b/gcc/testsuite/gcc.target/i386/pr103785.c index 5503b96..49d6c56 100644 --- a/gcc/testsuite/gcc.target/i386/pr103785.c +++ b/gcc/testsuite/gcc.target/i386/pr103785.c @@ -11,7 +11,10 @@ struct wrapper_t struct wrapper_t **table; -__attribute__ ((weak, regparm (2))) +#ifndef __x86_64__ +__attribute__ ((regparm (2))) +#endif +__attribute__ ((weak)) void update (long k, long e) { diff --git a/gcc/testsuite/gcc.target/i386/pr119795.c b/gcc/testsuite/gcc.target/i386/pr119795.c new file mode 100644 index 0000000..03c91cc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr119795.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-options "-O -fschedule-insns -favoid-store-forwarding" } */ + +unsigned a, b, c; + +void +foo (_BitInt(2) b2, unsigned _BitInt(255) by, unsigned _BitInt(5) b5, + unsigned _BitInt(256) *ret) +{ + unsigned _BitInt(255) bx = b2; + by += 0x80000000000000000000000000000000wb; + __builtin_memmove (&b, &c, 3); + unsigned d = b; + unsigned e = __builtin_stdc_rotate_right (0x1uwb % b5, a); + unsigned _BitInt(256) r = by + bx + d + e; + *ret = r; +} + +int +main () +{ + unsigned _BitInt(256) x; + foo (0, -1, 2, &x); + if (x != 0x80000000000000000000000000000000wb) + __builtin_abort(); +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/i386/pr120427-5.c b/gcc/testsuite/gcc.target/i386/pr120427-5.c new file mode 100644 index 0000000..7199aef --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120427-5.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-Oz" } */ + +long long +func1 (void) +{ + return -1; +} +/* { dg-final { scan-assembler-times "pushq\[ \\t\]+\\\$-1" 1 } } */ +/* { dg-final { scan-assembler-times "popq\[ \\t\]+%rax" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr120941-1.c b/gcc/testsuite/gcc.target/i386/pr120941-1.c new file mode 100644 index 0000000..b4fc6ac --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr120941-1.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast -march=x86-64-v3" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } {^\t?\.} } } */ + +/* +**bar: +**.LFB[0-9]+: +**... +** vbroadcastsd .LC4\(%rip\), %ymm2 +** leal 2\(%rbx\), %eax +** vbroadcastsd .LC2\(%rip\), %ymm4 +** negl %eax +**... +*/ + +extern void foo (int); + +enum { N_CELL_ENTRIES1 = 2 } +typedef LBM_Grid1[64]; +enum { N_CELL_ENTRIES2 = 2 } +typedef LBM_Grid2[64]; +LBM_Grid1 grid1; +LBM_Grid2 grid2; +extern int n; + +void +LBM_handleInOutFlow() +{ + int i, j; + for (; i; i += 2) + { + for (j = 0; j < n; j++) + { + grid1[i] = 1.0 / 36.0 * i; + grid2[i] = 1.0 / 36.0 * i; + } + } +} + +int main_t; +void +bar (void) +{ + for (; main_t; main_t++) { + LBM_handleInOutFlow(); + foo (main_t); + } +} diff --git a/gcc/testsuite/gcc.target/i386/pr121208-1a.c b/gcc/testsuite/gcc.target/i386/pr121208-1a.c new file mode 100644 index 0000000..f799bc8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121208-1a.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fPIC -mno-avx -mno-mmx -mno-80387 -mtls-dialect=gnu" } */ + +extern __thread int bar; +extern void func (void); + +__attribute__((no_caller_saved_registers)) +void +foo (int error) +{ + bar = 1; /* { dg-error -mtls-dialect=gnu2 } */ + if (error == 0) + func (); + bar = 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr121208-1b.c b/gcc/testsuite/gcc.target/i386/pr121208-1b.c new file mode 100644 index 0000000..ba37abc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121208-1b.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fPIC -mno-avx -mno-mmx -mno-80387 -mtls-dialect=gnu2" } */ + +#include "pr121208-1a.c" diff --git a/gcc/testsuite/gcc.target/i386/pr121208-2a.c b/gcc/testsuite/gcc.target/i386/pr121208-2a.c new file mode 100644 index 0000000..c1891ae --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121208-2a.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fPIC -mtls-dialect=gnu" } */ + +typedef unsigned int uword_t __attribute__ ((mode (__word__))); +extern __thread int bar; +extern void func (void); + +__attribute__((target("general-regs-only"))) +__attribute__((interrupt)) +void +foo (void *frame, uword_t error) +{ + bar = 1; /* { dg-error -mtls-dialect=gnu2 } */ + if (error == 0) + func (); + bar = 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr121208-2b.c b/gcc/testsuite/gcc.target/i386/pr121208-2b.c new file mode 100644 index 0000000..269b120 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121208-2b.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fPIC -mtls-dialect=gnu2" } */ + +#include "pr121208-2a.c" diff --git a/gcc/testsuite/gcc.target/i386/pr121208-3a.c b/gcc/testsuite/gcc.target/i386/pr121208-3a.c new file mode 100644 index 0000000..26fe687 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121208-3a.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fPIC -mtls-dialect=gnu" } */ + +typedef unsigned int uword_t __attribute__ ((mode (__word__))); +extern __thread int bar; +extern void func (void); + +__attribute__((target("general-regs-only"))) +__attribute__((interrupt)) +void +foo (void *frame) +{ + bar = 1; /* { dg-error -mtls-dialect=gnu2 } */ + if (frame == 0) + func (); + bar = 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr121208-3b.c b/gcc/testsuite/gcc.target/i386/pr121208-3b.c new file mode 100644 index 0000000..b672d75 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121208-3b.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fPIC -mtls-dialect=gnu2" } */ + +#include "pr121208-3a.c" diff --git a/gcc/testsuite/gcc.target/i386/pr121274.c b/gcc/testsuite/gcc.target/i386/pr121274.c new file mode 100644 index 0000000..16760cf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121274.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-march=x86-64-v4 -O2" } */ +/* { dg-final { scan-assembler-not "vpextrq" } } */ +/* { dg-final { scan-assembler-not "vpinsrq" } } */ + +typedef int v16si __attribute__((vector_size(64))); +typedef int v4si __attribute__((vector_size(16))); + +v4si f(v16si x) +{ + return __builtin_shufflevector(x, x, 0, 1, 2, 3); +} + +v4si g(v16si x) +{ +return __builtin_shufflevector(x, x, 4, 5, 6, 7); +} + +v4si f1(__int128 *x) +{ + __int128 t = *x; + asm("":"+x"(t)); + return (v4si)t; +} diff --git a/gcc/testsuite/gcc.target/i386/pr121303.c b/gcc/testsuite/gcc.target/i386/pr121303.c new file mode 100644 index 0000000..7900bce --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121303.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -favoid-store-forwarding" } */ + +typedef struct { + bool is_ssa; +} nir_src; + +nir_src nir_src_init; + +typedef struct { + nir_src src; + char swizzle[6]; +} nir_alu_src; + +void nir_src_bit_size(nir_src); + +void nir_lower_fb_read_instr() { + { + nir_alu_src alu_src = {nir_src_init}, src = alu_src; + nir_src_bit_size(src.src); + } + { + nir_alu_src alu_src = {nir_src_init}, src = alu_src; + nir_src_bit_size(src.src); + } +} diff --git a/gcc/testsuite/gcc.target/i386/pr121410.c b/gcc/testsuite/gcc.target/i386/pr121410.c new file mode 100644 index 0000000..04bab91 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121410.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -mavx512f -mstore-max=128" } */ + +extern unsigned _BitInt(3719) a; +extern _BitInt(465) g; +void +foo(void) +{ + _BitInt(465) b = a >> 1860; + g = b + b; +} diff --git a/gcc/testsuite/gcc.target/i386/pr121497.c b/gcc/testsuite/gcc.target/i386/pr121497.c new file mode 100644 index 0000000..ce55f95 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121497.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -msse2 -w" } */ + +extern void a(int *); +int q; +void b(int c, int d, int e, int f, int g, int h) { + int t[] = {c, d, e, f, g, h}; + a(t); +} +int main() { + int k[2], i = 0, *p(); + if (q) { + for (; (int)p + i < 2; i++) + k[i] = -1294967296; + b(k[0] + 7, k[0] + 9, k[0] + 6, k[0] + 9, k[0] + 9, k[0] + 6); + } + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr121540-1.c b/gcc/testsuite/gcc.target/i386/pr121540-1.c new file mode 100644 index 0000000..dee9c27 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121540-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64" } */ + +void + __attribute__ ((no_caller_saved_registers)) +fn (void) +{ /* { dg-message "sorry, unimplemented: MMX/3Dnow instructions aren't allowed" } */ +} diff --git a/gcc/testsuite/gcc.target/i386/pr121540-2.c b/gcc/testsuite/gcc.target/i386/pr121540-2.c new file mode 100644 index 0000000..15a3f40 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121540-2.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -mno-mmx" } */ + +void + __attribute__ ((no_caller_saved_registers)) +fn (void) +{ /* { dg-message "sorry, unimplemented: 80387 instructions aren't allowed" } */ +} diff --git a/gcc/testsuite/gcc.target/i386/pr121541-1a.c b/gcc/testsuite/gcc.target/i386/pr121541-1a.c new file mode 100644 index 0000000..83884a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121541-1a.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=x86-64" } */ + +extern long double d; + +__attribute__ ((target("no-80387"))) +void +func1 (void) +{ + d *= 3; /* { dg-error "x87 register return with x87 disabled" } */ +} diff --git a/gcc/testsuite/gcc.target/i386/pr121541-1b.c b/gcc/testsuite/gcc.target/i386/pr121541-1b.c new file mode 100644 index 0000000..f440b14 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121541-1b.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target ia32 } } */ +/* { dg-options "-O2" } */ + +#include "pr121541-1a.c" + +/* { dg-final { scan-assembler "call\[\\t \]+_?__mulxf3" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121541-2.c b/gcc/testsuite/gcc.target/i386/pr121541-2.c new file mode 100644 index 0000000..281341e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121541-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-80387" } */ + +extern long double d; + +__attribute__ ((target("80387"))) +void +func1 (void) +{ + d *= 3; +} diff --git a/gcc/testsuite/gcc.target/i386/pr121541-3.c b/gcc/testsuite/gcc.target/i386/pr121541-3.c new file mode 100644 index 0000000..380fab2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121541-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mgeneral-regs-only" } */ + +extern long double d; + +__attribute__ ((target("80387"))) +void +func1 (void) +{ + d *= 3; +} diff --git a/gcc/testsuite/gcc.target/i386/pr121541-4.c b/gcc/testsuite/gcc.target/i386/pr121541-4.c new file mode 100644 index 0000000..1f4381a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121541-4.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +extern long double d; + +__attribute__ ((target("general-regs-only","80387"))) +void +func1 (void) +{ + d *= 3; +} diff --git a/gcc/testsuite/gcc.target/i386/pr121541-5a.c b/gcc/testsuite/gcc.target/i386/pr121541-5a.c new file mode 100644 index 0000000..e6137e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121541-5a.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=x86-64" } */ + +extern long double d; + +__attribute__ ((target("80387","general-regs-only"))) +void +func1 (void) +{ + d *= 3; /* { dg-error "x87 register return with x87 disabled" } */ +} diff --git a/gcc/testsuite/gcc.target/i386/pr121541-5b.c b/gcc/testsuite/gcc.target/i386/pr121541-5b.c new file mode 100644 index 0000000..b61a7fe --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121541-5b.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target ia32 } } */ +/* { dg-options "-O2" } */ + +#include "pr121541-5a.c" + +/* { dg-final { scan-assembler "call\[\\t \]+_?__mulxf3" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121572-1a.c b/gcc/testsuite/gcc.target/i386/pr121572-1a.c new file mode 100644 index 0000000..270d8ff --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121572-1a.c @@ -0,0 +1,41 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O0 -fpic -fplt -mtls-dialect=gnu" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */ + +/* +**bug: +**.LFB[0-9]+: +**... +** leaq tv_cache@tlsld\(%rip\), %rdi +** call __tls_get_addr@PLT +** movl \$-1, %edi +** mov[l|q] %[e|r]ax, %[e|r]bx +** call val@PLT +**... +*/ + +extern __thread int tv_cache __attribute__ ((visibility ("hidden"))); +extern void use_cache (int); +extern int val (int v); + +__attribute__ ((optimize (2))) +void +bug (void) +{ + int compared = val (-1); + + if (compared == 0 || (compared > 0 && val (2) == 0)) + { + __builtin_trap (); + } + + if (compared < 0) + { + use_cache (tv_cache); + return; + } + + use_cache (tv_cache); + __builtin_trap (); +} diff --git a/gcc/testsuite/gcc.target/i386/pr121572-1b.c b/gcc/testsuite/gcc.target/i386/pr121572-1b.c new file mode 100644 index 0000000..8a60891 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121572-1b.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O0 -fpic -fplt -mtls-dialect=gnu2" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */ + +/* +**bug: +**.LFB[0-9]+: +**... +** lea[l|q] tv_cache@TLSDESC\(%rip\), %[e|r]ax +** movl \$-1, %edi +** call \*tv_cache@TLSCALL\(%[e|r]ax\) +** mov[l|q] %[e|r]ax, %[e|r]bx +** call val@PLT +**... +*/ + +#include "pr121572-1a.c" diff --git a/gcc/testsuite/gcc.target/i386/pr121572-2a.c b/gcc/testsuite/gcc.target/i386/pr121572-2a.c new file mode 100644 index 0000000..38b2546 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121572-2a.c @@ -0,0 +1,39 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -fplt -mtls-dialect=gnu" } */ + +typedef enum +{ + MPFR_RNDN +} mpfr_rnd_t; +typedef int mpfr_t[1]; +long __gmpfr_emin, mpfr_agm_expo_0; +_Thread_local long __gmpfr_emax; +int mpfr_agm_compare, mpfr_agm___trans_tmp_1; +mpfr_t mpfr_agm_u; +void mpfr_mul (int *, int, int, mpfr_rnd_t); +int +mpfr_agm (int op1) +{ + int op2 = 0; + if (__builtin_expect (mpfr_agm_compare == 0, 0)) + return 0; + if (mpfr_agm_compare > 0) + { + int t = op1; + op2 = t; + } + mpfr_agm_expo_0 = __gmpfr_emax; + for (;;) + { + retry: + mpfr_mul (mpfr_agm_u, op1, op2, MPFR_RNDN); + if (0) + goto retry; + if (__builtin_expect (mpfr_agm___trans_tmp_1, 1)) + break; + } + __gmpfr_emin = __gmpfr_emax; + return 0; +} + +/* { dg-final { scan-assembler-times "call\[ \t\]__tls_get_addr@PLT" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121572-2b.c b/gcc/testsuite/gcc.target/i386/pr121572-2b.c new file mode 100644 index 0000000..33d7002 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121572-2b.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -fplt -mtls-dialect=gnu2" } */ + +#include "pr121572-2a.c" + +/* { dg-final { scan-assembler-times "call\[ \t\]\\*__gmpfr_emax@TLSCALL\\(%(?:r|e)ax\\)" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121607-1a.c b/gcc/testsuite/gcc.target/i386/pr121607-1a.c new file mode 100644 index 0000000..4c04706 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121607-1a.c @@ -0,0 +1,59 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -fplt -mtls-dialect=gnu -fno-semantic-interposition -fstack-protector" } */ + +typedef enum +{ + bfd_error_invalid_error_code +} bfd_error_type; +thread_local bfd_error_type bfd_error; +int aout_16_write_syms___trans_tmp_1; +short aout_16_write_syms_g_0_0; +void xvec_0 (long, void *); + +typedef struct +{ + int output_section; +} asection; + +void bfd_asymbol_section (); + +struct pdp11_external_nlist +{ + char e_desc[2]; + char e_type[1]; + char e_ovly[10]; +} translate_to_native_sym_flags (struct pdp11_external_nlist *sym_pointer) +{ + asection *sec; + sym_pointer->e_type[0] &= 5; + bfd_asymbol_section (); + if (sec == 0) + { + bfd_error_type error_tag; + bfd_error = error_tag; + } + if (sec->output_section) + { + bfd_error_type error_tag; + bfd_error = error_tag; + } +} + +bool +aout_16_write_syms (void *abfd) +{ + for (; aout_16_write_syms___trans_tmp_1;) + { + struct pdp11_external_nlist nsp; + if (abfd) + { + xvec_0 (aout_16_write_syms_g_0_0, nsp.e_desc); + nsp.e_ovly[0] = 0; + } + else + nsp.e_type[0] = 0; + translate_to_native_sym_flags (&nsp); + } +} + +/* { dg-final { scan-assembler-times "call\[ \t\]__tls_get_addr@PLT" 2 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121607-1b.c b/gcc/testsuite/gcc.target/i386/pr121607-1b.c new file mode 100644 index 0000000..3663067 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121607-1b.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -fplt -mtls-dialect=gnu2 -fno-semantic-interposition -fstack-protector" } */ + +#include "pr121607-1a.c" + +/* { dg-final { scan-assembler-times "call\[ \t\]\\*bfd_error@TLSCALL\\(%(?:r|e)ax\\)" 2 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121635-1a.c b/gcc/testsuite/gcc.target/i386/pr121635-1a.c new file mode 100644 index 0000000..4db7def --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121635-1a.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -fplt -mtls-dialect=gnu" } */ + +extern int get_cordz_mean_interval (); +extern thread_local long cordz_next_sample, kIntervalIfDisabled; +extern bool cordz_should_profile_slow (void); +inline bool +cordz_should_profile (void) +{ + return cordz_should_profile_slow (); +} +bool +cordz_should_profile_slow (void) +{ + int mean_interval = get_cordz_mean_interval (); + if (mean_interval) + cordz_next_sample = kIntervalIfDisabled; + return cordz_next_sample || cordz_should_profile (); +} + +/* { dg-final { scan-assembler-times "call\[ \t\]__tls_get_addr@PLT" 2 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121635-1b.c b/gcc/testsuite/gcc.target/i386/pr121635-1b.c new file mode 100644 index 0000000..4095fb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121635-1b.c @@ -0,0 +1,7 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -fplt -mtls-dialect=gnu2" } */ + +#include "pr121635-1a.c" + +/* { dg-final { scan-assembler-times "call\[ \t\]\\*cordz_next_sample@TLSCALL\\(%(?:r|e)ax\\)" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "call\[ \t\]\\*kIntervalIfDisabled@TLSCALL\\(%(?:r|e)ax\\)" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121658.c b/gcc/testsuite/gcc.target/i386/pr121658.c new file mode 100644 index 0000000..0437316 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121658.c @@ -0,0 +1,11 @@ +/* PR target/121658 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -mgfni" } */ + +__attribute__((__vector_size__(64))) unsigned char v; + +void +foo (void) +{ + v = (v << 7) | (v >> 1); +} diff --git a/gcc/testsuite/gcc.target/i386/pr121668-1a.c b/gcc/testsuite/gcc.target/i386/pr121668-1a.c new file mode 100644 index 0000000..eb55308 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121668-1a.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-Og -g -fpic -fplt -mtls-dialect=gnu" } */ + +typedef int caml_domain_state; +thread_local caml_domain_state caml_state; +void +caml_empty_mark_stack () +{ + while (caml_state) + caml_state = 0; +} + +/* { dg-final { scan-assembler-times "call\[ \t\]__tls_get_addr@PLT" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121668-1b.c b/gcc/testsuite/gcc.target/i386/pr121668-1b.c new file mode 100644 index 0000000..54a2775 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121668-1b.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-Og -g -fpic -fplt -mtls-dialect=gnu2" } */ + +#include "pr121668-1a.c" + +/* { dg-final { scan-assembler-times "call\[ \t\]\\*caml_state@TLSCALL\\(%(?:r|e)ax\\)" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121694-1a.c b/gcc/testsuite/gcc.target/i386/pr121694-1a.c new file mode 100644 index 0000000..af9c657 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121694-1a.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-Og -fpic -fplt -mtls-dialect=gnu" } */ + +extern void func1 (long *); +extern int func2 (void); +extern void func3 (void); +static __thread long foo; +static __thread long bar; +long +func (void) +{ + func1 (&foo); + func1 (&bar); + if (func2 ()) + func3 (); + return foo + bar; +} + +/* { dg-final { scan-assembler-times "call\[ \t\]__tls_get_addr@PLT" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121694-1b.c b/gcc/testsuite/gcc.target/i386/pr121694-1b.c new file mode 100644 index 0000000..76ebbf7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121694-1b.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-Og -fpic -fplt -mtls-dialect=gnu2" } */ + +#include "pr121694-1a.c" + +/* { dg-final { scan-assembler-times "call\[ \t\]\\*_TLS_MODULE_BASE_@TLSCALL\\(%(?:r|e)ax\\)" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121699.c b/gcc/testsuite/gcc.target/i386/pr121699.c new file mode 100644 index 0000000..80c1404 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121699.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=znver4 -O3" } */ + +typedef struct +{ + int u32; +} nir_const_value; + +nir_const_value *evaluate_prmt_nv__dst_val; + +int evaluate_prmt_nv__src_0, evaluate_prmt_nv_src; + +void +evaluate_prmt_nv (unsigned num_components) +{ + for (unsigned _i = 0; _i < num_components; _i++) + { + char x = evaluate_prmt_nv_src; + if (evaluate_prmt_nv__src_0) + x = x >> 7; + evaluate_prmt_nv__dst_val[_i].u32 = x; + } +} diff --git a/gcc/testsuite/gcc.target/i386/pr121725-1a.c b/gcc/testsuite/gcc.target/i386/pr121725-1a.c new file mode 100644 index 0000000..d0a498c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121725-1a.c @@ -0,0 +1,41 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O3 -fpic -fplt -mtls-dialect=gnu" } */ + +typedef enum +{ + bfd_error_invalid_error_code +} bfd_error_type; +static thread_local bfd_error_type bfd_error; +extern int sections; +extern void *bfd_alloc_ret; +extern int bfd_alloc___o; +extern long bfd_alloc_size; + +extern void _objalloc_alloc (int *, long); + +bfd_error_type +bfd_get_error () +{ + return bfd_error; +} + +bool +s7_bfd_score_elf_late_size_sections () +{ + for (; sections;) + { + if (bfd_alloc_size) + { + bfd_error_type error_tag; + bfd_error = error_tag; + } + _objalloc_alloc (&bfd_alloc___o, 0); + if (bfd_alloc_ret) + { + bfd_error_type error_tag; + bfd_error = error_tag; + } + } +} + +/* { dg-final { scan-assembler-times "call\[ \t\]__tls_get_addr@PLT" 2 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121725-1b.c b/gcc/testsuite/gcc.target/i386/pr121725-1b.c new file mode 100644 index 0000000..0b97a8a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121725-1b.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O3 -fpic -fplt -mtls-dialect=gnu2" } */ + +#include "pr121725-1a.c" + +/* { dg-final { scan-assembler-times "call\[ \t\]\\*bfd_error@TLSCALL\\(%(?:r|e)ax\\)" 2 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr15184-2.c b/gcc/testsuite/gcc.target/i386/pr15184-2.c index cb8201f..dd50c42 100644 --- a/gcc/testsuite/gcc.target/i386/pr15184-2.c +++ b/gcc/testsuite/gcc.target/i386/pr15184-2.c @@ -1,4 +1,4 @@ -/* PR 15184 second two tests +/* PR 15184 second two tests */ /* { dg-do compile { target ia32 } } */ /* { dg-options "-O2 -march=pentiumpro" } */ /* { dg-additional-options "-fno-PIE" { target ia32 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr36533.c b/gcc/testsuite/gcc.target/i386/pr36533.c index 8d71ece..8699d26 100644 --- a/gcc/testsuite/gcc.target/i386/pr36533.c +++ b/gcc/testsuite/gcc.target/i386/pr36533.c @@ -55,14 +55,22 @@ typedef struct S1 *s18; } S7; -__attribute__((regparm (3), noinline)) int +#ifndef __x86_64__ +__attribute__((regparm (3))) +#endif +__attribute__((noinline)) +int fn1 (const char *x, void *y, S1 *z) { asm volatile ("" : : : "memory"); return *x + (y != 0); } -__attribute__((regparm (3), noinline)) int +#ifndef __x86_64__ +__attribute__((regparm (3))) +#endif +__attribute__((noinline)) +int fn2 (const char *x, int y, S2 *z) { asm volatile ("" : : : "memory"); @@ -84,7 +92,11 @@ fn3 (S3 *p) return (S3 *) ((char *) p + fn4 (p->s9)); } -__attribute__((regparm (3), noinline)) int +#ifndef __x86_64__ +__attribute__((regparm (3))) +#endif +__attribute__((noinline)) +int fn5 (void) { asm volatile ("" : : : "memory"); @@ -116,7 +128,11 @@ fn6 (S3 *w, int x, S2 *y, S4 *z) return a; } -__attribute__((regparm (3), noinline)) unsigned int +#ifndef __x86_64__ +__attribute__((regparm (3))) +#endif +__attribute__((noinline)) +unsigned int test (void *u, S6 *v, S1 **w, S7 *x, S2 *y, S1 *z) { unsigned b = v->s17->s16; diff --git a/gcc/testsuite/gcc.target/i386/pr44130.c b/gcc/testsuite/gcc.target/i386/pr44130.c index 2ad7409..6269dc8 100644 --- a/gcc/testsuite/gcc.target/i386/pr44130.c +++ b/gcc/testsuite/gcc.target/i386/pr44130.c @@ -21,6 +21,8 @@ void testf (void) xxxxx[5] = __builtin_copysignf (-0.0, Yf[5]); xxxxx[6] = __builtin_copysignf (__builtin_inff (), Yf[6]); xxxxx[7] = __builtin_copysignf (-__builtin_nanf (""), Yf[7]); + + asm("":"=m"(xxxxx)); for (i = 0; i < 8; ++i) if (__builtin_memcmp (xxxxx+i, Zf+i, sizeof(float)) != 0) abort (); diff --git a/gcc/testsuite/gcc.target/i386/pr59099.c b/gcc/testsuite/gcc.target/i386/pr59099.c index cf4a8da..21dfbc2 100644 --- a/gcc/testsuite/gcc.target/i386/pr59099.c +++ b/gcc/testsuite/gcc.target/i386/pr59099.c @@ -13,10 +13,17 @@ struct s }; -void* f (struct s *, struct s *) __attribute__ ((noinline, regparm(1))); +void* f (struct s *, struct s *) +#ifndef __x86_64__ +__attribute__ ((regparm(1))) +#endif +__attribute__ ((noinline)) +; void* +#ifndef __x86_64__ __attribute__ ((regparm(1))) +#endif f (struct s *p, struct s *p2) { void *gp, *gp1; diff --git a/gcc/testsuite/gcc.target/i386/pr81501-10a.c b/gcc/testsuite/gcc.target/i386/pr81501-10a.c new file mode 100644 index 0000000..438abf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81501-10a.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -mtls-dialect=gnu" } */ + +static __thread int foo = 30; + +int * +test1 (void) +{ + __builtin_printf ("foo: %d\n", foo); + return &foo; +} diff --git a/gcc/testsuite/gcc.target/i386/pr81501-10b.c b/gcc/testsuite/gcc.target/i386/pr81501-10b.c new file mode 100644 index 0000000..4cd1da8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81501-10b.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -fplt -mtls-dialect=gnu2" } */ + +#include "pr81501-10a.c" diff --git a/gcc/testsuite/gcc.target/i386/pr81501-1a.c b/gcc/testsuite/gcc.target/i386/pr81501-1a.c new file mode 100644 index 0000000..30b4642 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81501-1a.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -fplt -mtls-dialect=gnu" } */ + +void a(long *); +int b(void); +void c(void); +static __thread long e; +long +d(void) +{ + a(&e); + if (b()) + c(); + return e; +} + +/* { dg-final { scan-assembler-times "call\[ \t\]__tls_get_addr@PLT" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81501-1b.c b/gcc/testsuite/gcc.target/i386/pr81501-1b.c new file mode 100644 index 0000000..de25f22 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81501-1b.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -fplt -mtls-dialect=gnu2" } */ + +#include "pr81501-1a.c" + +/* { dg-final { scan-assembler-times "call\[ \t\]\\*e@TLSCALL\\(%(?:r|e)ax\\)" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81501-2a.c b/gcc/testsuite/gcc.target/i386/pr81501-2a.c new file mode 100644 index 0000000..a06302a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81501-2a.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -fplt -mtls-dialect=gnu" } */ + +void a(long *); +int b(void); +void c(void); +extern __thread long e; +long +d(void) +{ + a(&e); + if (b()) + c(); + return e; +} + +/* { dg-final { scan-assembler-times "call\[ \t\]__tls_get_addr@PLT" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81501-2b.c b/gcc/testsuite/gcc.target/i386/pr81501-2b.c new file mode 100644 index 0000000..4afb742 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81501-2b.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -fplt -mtls-dialect=gnu2" } */ + +#include "pr81501-2a.c" + +/* { dg-final { scan-assembler-times "call\[ \t\]\\*e@TLSCALL\\(%(?:r|e)ax\\)" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81501-3.c b/gcc/testsuite/gcc.target/i386/pr81501-3.c new file mode 100644 index 0000000..d422063 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81501-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -fplt -mtls-dialect=gnu2" } */ + +static __thread int local1; +int * +get_local1 (void) +{ + return &local1; +} diff --git a/gcc/testsuite/gcc.target/i386/pr81501-4a.c b/gcc/testsuite/gcc.target/i386/pr81501-4a.c new file mode 100644 index 0000000..0c655e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81501-4a.c @@ -0,0 +1,51 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -march=x86-64 -fpic -fplt -mtls-dialect=gnu" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */ + +/* +**in_dso: +**.LFB[0-9]+: +**... +** movl %edi, %.* +**... +** mov(l|q) %(e|r)si, %.* +**... +** call __tls_get_addr@PLT +**... +*/ + +__thread int foo; + +extern void bar1 (int *, int *); +extern void bar2 (int); +extern void bar3 (const char *); + +int +in_dso (int n, int *caller_foop) +{ + int *foop; + int result = 0; + + bar3 ("foo"); /* Make sure PLT is used before macros. */ + asm ("" ::: "memory"); + + foop = &foo; + + if (caller_foop != (void *) 0 && foop != caller_foop) + { + bar1 (caller_foop, foop); + result = 1; + } + else if (*foop != n) + { + bar2 (n); + result = 1; + } + + *foop = 16; + + return result; +} + +/* { dg-final { scan-assembler-times "call\[ \t\]__tls_get_addr@PLT" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81501-4b.c b/gcc/testsuite/gcc.target/i386/pr81501-4b.c new file mode 100644 index 0000000..5d35712 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81501-4b.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -fplt -mtls-dialect=gnu2" } */ + +#include "pr81501-4a.c" + +/* { dg-final { scan-assembler-times "call\[ \t\]\\*\*foo@TLSCALL\\(%(?:r|e)ax\\)" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81501-5.c b/gcc/testsuite/gcc.target/i386/pr81501-5.c new file mode 100644 index 0000000..7f666e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81501-5.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -fplt -mtls-dialect=gnu" } */ + +extern __thread int __bid_IDEC_glbflags; +extern long __bid64qq_div_bid_y_0_1; +extern void get_BID64(int *); +void +__bid64qq_div(void) +{ + if (__bid64qq_div_bid_y_0_1) + __bid_IDEC_glbflags |= 1; + get_BID64(&__bid_IDEC_glbflags); +} diff --git a/gcc/testsuite/gcc.target/i386/pr81501-6a.c b/gcc/testsuite/gcc.target/i386/pr81501-6a.c new file mode 100644 index 0000000..db8acf8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81501-6a.c @@ -0,0 +1,67 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -march=x86-64 -fpic -fplt -mtls-dialect=gnu" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */ + +/* +**in_dso: +**.LFB[0-9]+: +**... +** mov(l|q) %(e|r)dx, %.* +**... +** movl %edi, %.* +**... +** mov(l|q) %(e|r)si, %.* +**... +** call __tls_get_addr@PLT +**... +*/ + +__thread int foo; +__thread int bar; + +extern void fun1 (int *, int *); +extern void fun2 (int); +extern void fun3 (const char *); + +int +in_dso (int n, int *caller_foop, int *caller_barp) +{ + int *foop; + int *barp; + int result = 0; + + fun3 ("foo"); /* Make sure PLT is used before macros. */ + asm ("" ::: "memory"); + + foop = &foo; + barp = &bar; + + if (caller_foop != (void *) 0 && foop != caller_foop) + { + fun1 (caller_foop, foop); + result = 1; + if (caller_barp != (void *) 0 && barp != caller_barp) + { + fun1 (caller_barp, barp); + result = 2; + } + else if (*barp != n) + { + fun2 (n); + result = 3; + } + } + else if (*foop != n) + { + fun2 (n); + result = 4; + } + + *barp = 16; + *foop = 16; + + return result; +} + +/* { dg-final { scan-assembler-times "call\[ \t\]__tls_get_addr@PLT" 2 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81501-6b.c b/gcc/testsuite/gcc.target/i386/pr81501-6b.c new file mode 100644 index 0000000..0b71f0a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81501-6b.c @@ -0,0 +1,28 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -march=x86-64 -fpic -fplt -mtls-dialect=gnu2" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */ + +/* +**in_dso: +**.LFB[0-9]+: +**... +** lea(l|q) bar@TLSDESC\(%rip\), %(e|r)ax +** mov(l|q) %(e|r)si, %.* +**... +** mov(l|q) %(e|r)dx, %.* +**... +** movl %edi, %.* +**... +** call \*bar@TLSCALL\(%(e|r)ax\) +**... +** lea(l|q) foo@TLSDESC\(%rip\), %(e|r)ax +**... +** call \*foo@TLSCALL\(%(e|r)ax\) +**... +*/ + +#include "pr81501-6a.c" + +/* { dg-final { scan-assembler-times "call\[ \t\]\\*foo@TLSCALL\\(%(?:r|e)ax\\)" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "call\[ \t\]\\*bar@TLSCALL\\(%(?:r|e)ax\\)" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81501-7.c b/gcc/testsuite/gcc.target/i386/pr81501-7.c new file mode 100644 index 0000000..b2fe5d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81501-7.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpic -fplt -mtls-dialect=gnu" } */ + +extern int __bid_IDEC_glbround, __bid64qqq_fma_save_fpsf; +extern __thread int __bid_IDEC_glbflags; +typedef struct { + long w[2]; +} UINT128; +extern long __bid64qqq_fma_res_0_1; +extern void bid128_ext_fma(UINT128, UINT128); +void +__bid64qqq_fma(UINT128 y, UINT128 z) +{ + __bid_IDEC_glbflags = 0; + bid128_ext_fma(y, z); + if (__bid_IDEC_glbround || __bid64qqq_fma_res_0_1) + __bid_IDEC_glbflags |= __bid64qqq_fma_save_fpsf; +} + +/* { dg-final { scan-assembler-times "call\[ \t\]__tls_get_addr@PLT" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81501-8a.c b/gcc/testsuite/gcc.target/i386/pr81501-8a.c new file mode 100644 index 0000000..7e14ef5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81501-8a.c @@ -0,0 +1,82 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -march=x86-64 -fpic -fplt -mtls-dialect=gnu" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */ + +/* +**in_dso: +**.LFB[0-9]+: +**... +** mov(l|q) %(e|r)dx, %.* +**... +** movl %edi, %.* +**... +** mov(l|q) %(e|r)si, %.* +**... +** testb %al, %al +**... +** call __tls_get_addr@PLT +**... +*/ + +#include <stdarg.h> + +__thread int foo; +__thread int bar; + +extern void fun1 (int *, int *); +extern void fun2 (int); +extern void fun3 (const char *); + +int +in_dso (int n, int *caller_foop, int *caller_barp, ...) +{ + int *foop; + int *barp; + int result; + va_list ap; + double d; + + va_start (ap, caller_barp); + + result = 0; + + fun3 ("foo"); /* Make sure PLT is used before macros. */ + asm ("" ::: "memory"); + + foop = &foo; + barp = &bar; + + if (caller_foop != (void *) 0 && foop != caller_foop) + { + fun1 (caller_foop, foop); + result = 1; + if (caller_barp != (void *) 0 && barp != caller_barp) + { + fun1 (caller_barp, barp); + result = 2; + } + else if (*barp != n) + { + fun2 (n); + result = 3; + } + } + else if (*foop != n) + { + fun2 (n); + result = 4; + } + + *barp = 16; + *foop = 16; + + d = va_arg (ap, double); + if (d != 1234.0) + result = 10; + va_end (ap); + + return result; +} + +/* { dg-final { scan-assembler-times "call\[ \t\]__tls_get_addr@PLT" 2 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81501-8b.c b/gcc/testsuite/gcc.target/i386/pr81501-8b.c new file mode 100644 index 0000000..778b2fb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81501-8b.c @@ -0,0 +1,31 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -march=x86-64 -fpic -fplt -mtls-dialect=gnu2" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */ + +/* +**in_dso: +**.LFB[0-9]+: +**... +** mov(l|q) %(e|r)si, %.* +**... +** mov(l|q) %(e|r)dx, %.* +**... +** movl %edi, %.* +**... +** testb %al, %al +**... +** lea(l|q) bar@TLSDESC\(%rip\), %(e|r)ax +**... +** call \*bar@TLSCALL\(%(e|r)ax\) +**... +** lea(l|q) foo@TLSDESC\(%rip\), %(e|r)ax +**... +** call \*foo@TLSCALL\(%(e|r)ax\) +**... +*/ + +#include "pr81501-8a.c" + +/* { dg-final { scan-assembler-times "call\[ \t\]\\*foo@TLSCALL\\(%(?:r|e)ax\\)" 1 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "call\[ \t\]\\*bar@TLSCALL\\(%(?:r|e)ax\\)" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81501-9a.c b/gcc/testsuite/gcc.target/i386/pr81501-9a.c new file mode 100644 index 0000000..66a2768 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81501-9a.c @@ -0,0 +1,39 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -march=x86-64-v4 -fpic -fplt -mtls-dialect=gnu" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */ + +/* +**foo: +**.LFB[0-9]+: +**... +** vpbroadcastb %edi, %zmm0 +**... +** call __tls_get_addr@PLT +**... +*/ + +#include <immintrin.h> + +extern __m512i sinkz; +extern __m256i sinky; +extern __m128i sinkx; +extern void func1 (long *); +extern int func2 (void); +extern void func3 (void); +static __thread long var; + +long +foo (char c) +{ + func1 (&var); + if (func2 ()) + func3 (); + sinkx = _mm_set1_epi8 (c); + sinkz = _mm512_set1_epi8 (c); + sinky = _mm256_set1_epi8 (c); + return var; +} + +/* { dg-final { scan-assembler-times "vpbroadcastb" 1 } } */ +/* { dg-final { scan-assembler-times "call\[ \t\]__tls_get_addr@PLT" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81501-9b.c b/gcc/testsuite/gcc.target/i386/pr81501-9b.c new file mode 100644 index 0000000..711b177 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81501-9b.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -march=x86-64-v4 -fpic -fplt -mtls-dialect=gnu2" } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ +/* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */ +/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */ + +/* +**foo: +**.LFB[0-9]+: +**... +** vpbroadcastb %edi, %zmm0 +**... +** lea(l|q) var@TLSDESC\(%rip\), %(e|r)ax +**... +** call \*var@TLSCALL\(%(e|r)ax\) +**... +*/ + +#include "pr81501-9a.c" + +/* { dg-final { scan-assembler-times "vpbroadcastb" 1 } } */ +/* { dg-final { scan-assembler-times "call\[ \t\]\\*var@TLSCALL\\(%(?:r|e)ax\\)" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr90579.c b/gcc/testsuite/gcc.target/i386/pr90579.c index ab48a44..e8c6bad3 100644 --- a/gcc/testsuite/gcc.target/i386/pr90579.c +++ b/gcc/testsuite/gcc.target/i386/pr90579.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -mavx2 -mfpmath=sse" } */ +/* { dg-options "-O3 -mavx2 -mfpmath=sse -fno-pie" } */ extern double r[6]; extern double a[]; @@ -16,8 +16,5 @@ loop (int k, double x) return t; } -/* Verify we end up with scalar loads from r for the final sum. */ -/* { dg-final { scan-assembler "vaddsd\tr\\\+40" } } */ -/* { dg-final { scan-assembler "vaddsd\tr\\\+32" } } */ -/* { dg-final { scan-assembler "vaddsd\tr\\\+24" } } */ -/* { dg-final { scan-assembler "vaddsd\tr\\\+16" } } */ +/* Verify we end up with no loads from r. */ +/* { dg-final { scan-assembler-not "v\[ma\]\[^\t \]+\tr" } } */ diff --git a/gcc/testsuite/gcc.target/i386/shift-gf2p8affine-1.c b/gcc/testsuite/gcc.target/i386/shift-gf2p8affine-1.c new file mode 100644 index 0000000..cb576eb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/shift-gf2p8affine-1.c @@ -0,0 +1,64 @@ +/* { dg-do compile } */ +/* { dg-options "-mgfni -mavx512vl -mavx512bw -mavx512f -O3 -march=x86-64 -mtune=generic" } */ +/* { dg-final { scan-assembler-times "vgf2p8affineqb" 14 } } */ + +#ifndef N +#define N 5 +#endif + +void +ubyteshiftl (unsigned char *a, int len) +{ + int i; + for (i = 0; i < len; i++) + a[i] <<= N; +} + +void +ubyteshiftr (unsigned char *a, int len) +{ + int i; + for (i = 0; i < len; i++) + a[i] >>= N; +} + +void +ubyteshiftl_mask (unsigned char *a, int len) +{ + int i; + for (i = 0; i < len; i++) + if (a[i] & 1) + a[i] <<= N; +} + +void +sbyteshiftl (signed char *a, int len) +{ + int i; + for (i = 0; i < len; i++) + a[i] <<= N; +} + +void +sbyteshiftr (signed char *a, int len) +{ + int i; + for (i = 0; i < len; i++) + a[i] >>= N; +} + +void +ubyteror (unsigned char *a, int len) +{ + int i; + for (i = 0; i < len; i++) + a[i] = a[i] << N | a[i] >> (8 - N); +} + +void +ubyterol (unsigned char *a, int len) +{ + int i; + for (i = 0; i < len; i++) + a[i] = a[i] >> N | a[i] << (8 - N); +} diff --git a/gcc/testsuite/gcc.target/i386/shift-gf2p8affine-2.c b/gcc/testsuite/gcc.target/i386/shift-gf2p8affine-2.c new file mode 100644 index 0000000..c46af84 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/shift-gf2p8affine-2.c @@ -0,0 +1,196 @@ +/* { dg-do run } */ +/* { dg-options "-mgfni -mavx512vl -mavx512bw -mavx512f -O3 -Wno-shift-count-negative -march=x86-64 -mtune=generic" } */ + +#include <string.h> + +#ifndef N1 +#define N1 5 +#endif + +#ifndef N2 +#define N2 3 +#endif + +#ifndef N3 +#define N3 1 +#endif + +#ifndef N4 +#define N4 7 +#endif + +#ifndef N5 +#define N5 -3 +#endif + +#ifndef FILLER +#define FILLER 0xab +#endif + +#define FUNC(N) \ + void ubyteshiftl##N(unsigned char *a, int len) \ + { \ + int i; \ + for (i = 0; i < len; i++) \ + a[i] <<= N; \ + } \ + \ + void ubyteshiftr##N(unsigned char *a, int len) \ + { \ + int i; \ + for (i = 0; i < len; i++) \ + a[i] >>= N; \ + } \ + \ + void ubyteshiftl_mask##N(unsigned char *a, int len) \ + { \ + int i; \ + for (i = 0; i < len; i++) \ + if (a[i] & 1) \ + a[i] <<= N; \ + } \ + \ + void sbyteshiftl##N(signed char *a, int len) \ + { \ + int i; \ + for (i = 0; i < len; i++) \ + a[i] <<= N; \ + } \ + \ + void sbyteshiftr##N(signed char *a, int len) \ + { \ + int i; \ + for (i = 0; i < len; i++) \ + a[i] >>= N; \ + } \ + \ + void ubyteror##N(unsigned char *a, int len) \ + { \ + int i; \ + for (i = 0; i < len; i++) \ + a[i] = a[i] << N | a[i] >> (8-N); \ + } \ + \ + void ubyterol##N(unsigned char *a, int len) \ + { \ + int i; \ + for (i = 0; i < len; i++) \ + a[i] = a[i] >> N | a[i] << (8-N); \ + } \ + void ubyteshiftl##N##ref(unsigned char *a, int len) \ + { \ + int i; \ + _Pragma("GCC novector") \ + for (i = 0; i < len; i++) \ + a[i] <<= N; \ + } \ + \ + void ubyteshiftr##N##ref(unsigned char *a, int len) \ + { \ + int i; \ + _Pragma("GCC novector") \ + for (i = 0; i < len; i++) \ + a[i] >>= N; \ + } \ + \ + void ubyteshiftl_mask##N##ref(unsigned char *a, int len) \ + { \ + int i; \ + _Pragma("GCC novector") \ + for (i = 0; i < len; i++) \ + if (a[i] & 1) \ + a[i] <<= N; \ + } \ + \ + void sbyteshiftl##N##ref(signed char *a, int len) \ + { \ + int i; \ + _Pragma("GCC novector") \ + for (i = 0; i < len; i++) \ + a[i] <<= N; \ + } \ + \ + void sbyteshiftr##N##ref(signed char *a, int len) \ + { \ + int i; \ + _Pragma("GCC novector") \ + for (i = 0; i < len; i++) \ + a[i] >>= N; \ + } \ + \ + void ubyteror##N##ref(unsigned char *a, int len) \ + { \ + int i; \ + _Pragma("GCC novector") \ + for (i = 0; i < len; i++) \ + a[i] = a[i] << N | a[i] >> (8-N); \ + } \ + \ + void ubyterol##N##ref(unsigned char *a, int len) \ + { \ + int i; \ + _Pragma("GCC novector") \ + for (i = 0; i < len; i++) \ + a[i] = a[i] >> N | a[i] << (8-N); \ + } + +FUNC (N1) +FUNC (N2) +FUNC (N3) +FUNC (N4) +FUNC (N5) + +#define TEST(N, func) \ + memset (array, filler, len); \ + func##N (array, len); \ + memset (array2, filler, len); \ + func##N##ref (array2, len); \ + if (memcmp (array, array2, len)) __builtin_abort () + +int main () +{ + __builtin_cpu_init (); + if (!__builtin_cpu_supports ("gfni")) + return 0; + + const unsigned long len = 256; + char array[len], array2[len]; + unsigned char filler = FILLER; + + TEST (N1, ubyteshiftl); + TEST (N1, ubyteshiftl_mask); + TEST (N1, sbyteshiftl); + TEST (N1, sbyteshiftr); + TEST (N1, ubyteror); + TEST (N1, ubyterol); + + TEST (N2, ubyteshiftl); + TEST (N2, ubyteshiftl_mask); + TEST (N2, sbyteshiftl); + TEST (N2, sbyteshiftr); + TEST (N2, ubyteror); + TEST (N2, ubyterol); + + TEST (N3, ubyteshiftl); + TEST (N3, ubyteshiftl_mask); + TEST (N3, sbyteshiftl); + TEST (N3, sbyteshiftr); + TEST (N3, ubyteror); + TEST (N3, ubyterol); + + TEST (N4, ubyteshiftl); + TEST (N4, ubyteshiftl_mask); + TEST (N4, sbyteshiftl); + TEST (N4, sbyteshiftr); + TEST (N4, ubyteror); + TEST (N4, ubyterol); + + TEST (N5, ubyteshiftl); + TEST (N5, ubyteshiftl_mask); + TEST (N5, sbyteshiftl); + TEST (N5, sbyteshiftr); + TEST (N5, ubyteror); + TEST (N5, ubyterol); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/shift-gf2p8affine-3.c b/gcc/testsuite/gcc.target/i386/shift-gf2p8affine-3.c new file mode 100644 index 0000000..2099f4e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/shift-gf2p8affine-3.c @@ -0,0 +1,85 @@ +/* { dg-do compile } */ +/* { dg-options "-mgfni -mavx512bw -mavx512f -O3 -march=x86-64 -mtune=generic" } */ +/* { dg-final { scan-assembler-times "vgf2p8affineqb" 12 } } */ + +/* Based on a test case from Andrew Pinski */ + +#ifndef N +#define N 5 +#endif + +void +ubyteshiftl (unsigned char *restrict a, unsigned char *restrict b, unsigned char *restrict c, int len) +{ + int i; + for (i = 0; i < len; i++) + { + a[i] = c[i] ? (a[i] | b[i]) << N : a[i]; + a[i] = (!c[i]) ? (a[i] ^ b[i]) << N : a[i]; + } +} + +void +ubyteshiftr (unsigned char *restrict a, unsigned char *restrict b, unsigned char *restrict c, int len) +{ + int i; + for (i = 0; i < len; i++) + { + a[i] = c[i] ? (a[i] | b[i]) >> N : a[i]; + a[i] = (!c[i]) ? (a[i] ^ b[i]) >> N : a[i]; + } +} + +void +sbyteshiftl (signed char *restrict a, signed char *restrict b, signed char *restrict c, int len) +{ + int i; + for (i = 0; i < len; i++) + { + a[i] = c[i] ? (a[i] | b[i]) << N : a[i]; + a[i] = (!c[i]) ? (a[i] ^ b[i]) << N : a[i]; + } +} + +void +sbyteshiftr (signed char *restrict a, signed char *restrict b, signed char *restrict c, int len) +{ + int i; + for (i = 0; i < len; i++) + { + a[i] = c[i] ? (a[i] | b[i]) >> N : a[i]; + a[i] = (!c[i]) ? (a[i] ^ b[i]) >> N : a[i]; + } +} + +static inline unsigned char rol8(unsigned char v, int c) +{ + return (v >> c) | (v << (8-c)); +} + +static inline unsigned char ror8(unsigned char v, int c) +{ + return (v << c) | (v >> (8-c)); +} + +void +ubyterol (unsigned char *restrict a, unsigned char *restrict b, unsigned char *restrict c, int len) +{ + int i; + for (i = 0; i < len; i++) + { + a[i] = c[i] ? rol8(a[i] | b[i], N) : a[i]; + a[i] = (!c[i]) ? rol8(a[i] ^ b[i], N) : a[i]; + } +} + +void +ubyteror (unsigned char *restrict a, unsigned char *restrict b, unsigned char *restrict c, int len) +{ + int i; + for (i = 0; i < len; i++) + { + a[i] = c[i] ? ror8(a[i] | b[i], N) : a[i]; + a[i] = (!c[i]) ? ror8(a[i] ^ b[i], N) : a[i]; + } +} diff --git a/gcc/testsuite/gcc.target/i386/shift-gf2p8affine-5.c b/gcc/testsuite/gcc.target/i386/shift-gf2p8affine-5.c new file mode 100644 index 0000000..b8489a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/shift-gf2p8affine-5.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-mgfni -mavx -O3 -Wno-shift-count-negative -march=x86-64 -mtune=generic" } */ +/* { dg-final { scan-assembler-times "vgf2p8affineqb" 31 } } */ + +#include "shift-gf2p8affine-2.c" diff --git a/gcc/testsuite/gcc.target/i386/shift-gf2p8affine-6.c b/gcc/testsuite/gcc.target/i386/shift-gf2p8affine-6.c new file mode 100644 index 0000000..bf8d341 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/shift-gf2p8affine-6.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-mgfni -O3 -Wno-shift-count-negative -march=x86-64 -mtune=generic" } */ +/* { dg-final { scan-assembler-times "vgf2p8affineqb" 0 } } */ + +#include "shift-gf2p8affine-2.c" diff --git a/gcc/testsuite/gcc.target/i386/shift-gf2p8affine-7.c b/gcc/testsuite/gcc.target/i386/shift-gf2p8affine-7.c new file mode 100644 index 0000000..8e93bb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/shift-gf2p8affine-7.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-mgfni -mavx512vl -mavx512bw -mavx512f -O3 -Wno-shift-count-negative -mtune=generic -march=x86-64" } */ +/* { dg-final { scan-assembler-times "vgf2p8affineqb" 53 } } */ + +#include "shift-gf2p8affine-2.c" diff --git a/gcc/testsuite/gcc.target/i386/shift-v16qi-4.c b/gcc/testsuite/gcc.target/i386/shift-v16qi-4.c new file mode 100644 index 0000000..edc2b21 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/shift-v16qi-4.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-mgfni -mavx512vl -mavx512bw -mavx512f -O2" } */ +/* { dg-final { scan-assembler-times "vpcmpgtb" 1 } } */ + +typedef char v16qi __attribute__((vector_size(16))); + +v16qi +foo (v16qi a) +{ + return a >> 7; +} diff --git a/gcc/testsuite/gcc.target/i386/sibcall-8.c b/gcc/testsuite/gcc.target/i386/sibcall-8.c index 3ab3809..29ebfe5 100644 --- a/gcc/testsuite/gcc.target/i386/sibcall-8.c +++ b/gcc/testsuite/gcc.target/i386/sibcall-8.c @@ -1,23 +1,29 @@ /* { dg-do run } */ /* { dg-options "-O2" } */ +#ifndef __x86_64__ +#define REGPARM __attribute__((regparm(1))) +#else +#define REGPARM +#endif + extern void abort (void); -static int __attribute__((regparm(1))) +static int REGPARM bar(void *arg) { return arg != bar; } -static int __attribute__((noinline,noclone,regparm(1))) -foo(int (__attribute__((regparm(1))) **bar)(void*)) +static int __attribute__((noinline,noclone)) REGPARM +foo(int (REGPARM **bar)(void*)) { return (*bar)(*bar); } int main() { - int (__attribute__((regparm(1))) *p)(void*) = bar; + int (REGPARM *p)(void*) = bar; if (foo(&p)) abort(); return 0; diff --git a/gcc/testsuite/gcc.target/i386/sw-1.c b/gcc/testsuite/gcc.target/i386/sw-1.c index 14db3ce..025f0e1 100644 --- a/gcc/testsuite/gcc.target/i386/sw-1.c +++ b/gcc/testsuite/gcc.target/i386/sw-1.c @@ -7,7 +7,10 @@ int c; int x[2000]; -__attribute__((regparm(1))) void foo (int a, int b) +#ifndef __x86_64__ +__attribute__((regparm(1))) +#endif +void foo (int a, int b) { int t[200]; if (a == 0 || c == 0) diff --git a/gcc/testsuite/gcc.target/i386/uintr-2.c b/gcc/testsuite/gcc.target/i386/uintr-2.c index 0a83c66..a0d2514 100644 --- a/gcc/testsuite/gcc.target/i386/uintr-2.c +++ b/gcc/testsuite/gcc.target/i386/uintr-2.c @@ -15,6 +15,6 @@ foo (void *frame, uword_t uirrv) void __attribute__((interrupt)) -UINTR_hanlder (struct __uintr_frame *frame, uword_t uirrv) +UINTR_handler (struct __uintr_frame *frame, uword_t uirrv) { } diff --git a/gcc/testsuite/gcc.target/i386/uintr-5.c b/gcc/testsuite/gcc.target/i386/uintr-5.c index 49cb2ec..7c7c12f 100644 --- a/gcc/testsuite/gcc.target/i386/uintr-5.c +++ b/gcc/testsuite/gcc.target/i386/uintr-5.c @@ -7,6 +7,6 @@ typedef unsigned int uword_t __attribute__ ((mode (__word__))); void -UINTR_hanlder (struct __uintr_frame *frame, uword_t uirrv) +UINTR_handler (struct __uintr_frame *frame, uword_t uirrv) { } diff --git a/gcc/testsuite/gcc.target/i386/vect-pragma-target-1.c b/gcc/testsuite/gcc.target/i386/vect-pragma-target-1.c index f5e71e4..58ff7f0 100644 --- a/gcc/testsuite/gcc.target/i386/vect-pragma-target-1.c +++ b/gcc/testsuite/gcc.target/i386/vect-pragma-target-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { i?86-*-* x86_64-*-* } } } */ -/* { dg-options "-O0" } */ +/* { dg-options "-O0 -mno-sse3 -mtune=generic" } */ /* { dg-final { scan-assembler-times "paddd.+xmm\[0-9]+" 1 } } */ /* { dg-final { scan-assembler-times "vfmadd132ps.+ymm\[0-9]+" 1 } } */ /* { dg-final { scan-assembler-times "vpaddw.+zmm\[0-9]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-pragma-target-2.c b/gcc/testsuite/gcc.target/i386/vect-pragma-target-2.c index 3496804..f6dbd54 100644 --- a/gcc/testsuite/gcc.target/i386/vect-pragma-target-2.c +++ b/gcc/testsuite/gcc.target/i386/vect-pragma-target-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { i?86-*-* x86_64-*-* } } } */ -/* { dg-options "-O0" } */ +/* { dg-options "-O0 -mno-sse3 -mtune=generic" } */ /* { dg-final { scan-assembler-times "paddd.+xmm\[0-9]+" 1 } } */ /* { dg-final { scan-assembler-times "vfmadd132ps.+ymm\[0-9]+" 1 } } */ /* { dg-final { scan-assembler-times "vpaddw.+zmm\[0-9]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect_unroll-1.c b/gcc/testsuite/gcc.target/i386/vect_unroll-1.c new file mode 100644 index 0000000..2e294d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect_unroll-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64-v3 -Ofast" } */ +/* { dg-final { scan-assembler-times {(?n)vfmadd[1-3]*ps[^\n]*ymm} 4 } } */ + +float +foo (float* a, float* b, int n) +{ + float sum = 0; + for (int i = 0; i != n; i++) + sum += a[i] * b[i]; + return sum; +} diff --git a/gcc/testsuite/gcc.target/i386/vect_unroll-2.c b/gcc/testsuite/gcc.target/i386/vect_unroll-2.c new file mode 100644 index 0000000..069f7d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect_unroll-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64-v3 -Ofast" } */ +/* { dg-final { scan-assembler-times {(?n)vfnmadd[1-3]*ps[^\n]*ymm} 4 } } */ + +float +foo (float* a, float* b, int n) +{ + float sum = 0; + for (int i = 0; i != n; i++) + sum -= a[i] * b[i]; + return sum; +} diff --git a/gcc/testsuite/gcc.target/i386/vect_unroll-3.c b/gcc/testsuite/gcc.target/i386/vect_unroll-3.c new file mode 100644 index 0000000..6860c2f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect_unroll-3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mavxvnni -O3" } */ +/* { dg-final { scan-assembler-times {(?n)vpdpbusd[^\n]*ymm} 4 } } */ + +int +foo (unsigned char* a, char* b, int n) +{ + int sum = 0; + for (int i = 0; i != n; i++) + sum += a[i] * b[i]; + return sum; +} diff --git a/gcc/testsuite/gcc.target/i386/vect_unroll-4.c b/gcc/testsuite/gcc.target/i386/vect_unroll-4.c new file mode 100644 index 0000000..01d8af6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect_unroll-4.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64-v3 -O3 -mno-avxvnni" } */ +/* { dg-final { scan-assembler-times {(?n)vpmaddwd[^\n]*ymm} 4 } } */ + +int +foo (unsigned char* a, char* b, int n) +{ + int sum = 0; + for (int i = 0; i != n; i++) + sum += a[i] * b[i]; + return sum; +} diff --git a/gcc/testsuite/gcc.target/i386/vect_unroll-5.c b/gcc/testsuite/gcc.target/i386/vect_unroll-5.c new file mode 100644 index 0000000..c6375b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect_unroll-5.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64-v3 -Ofast -mgather" } */ +/* { dg-final { scan-assembler-times {(?n)vfmadd[1-3]*ps[^\n]*ymm} 1 } } */ + +float +foo (float* a, int* b, float* c, int n) +{ + float sum = 0; + for (int i = 0; i != n; i++) + sum += a[b[i]] *c[i]; + return sum; +} + diff --git a/gcc/testsuite/gcc.target/i386/vect_unroll-6.c b/gcc/testsuite/gcc.target/i386/vect_unroll-6.c new file mode 100644 index 0000000..b64c2fb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect_unroll-6.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64-v3 -Ofast" } */ +/* { dg-final { scan-assembler-times {(?n)vfmadd[1-3]*ps[^\n]*ymm} 4 } } */ + +float +foo (float* a, float* b, int n) +{ + float sum = 0; + for (int i = 0; i != n; i++) + sum = __builtin_fma (a[i], b[i], sum); + return sum; +} diff --git a/gcc/testsuite/gcc.target/loongarch/bitint-alignments.c b/gcc/testsuite/gcc.target/loongarch/bitint-alignments.c new file mode 100644 index 0000000..8592279 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/bitint-alignments.c @@ -0,0 +1,58 @@ +/* { dg-do run { target bitint } } */ +/* { dg-additional-options "-std=c23" } */ + +static long unsigned int +calc_alignof (int n) +{ + if (n > 64) + return alignof(__int128_t); + if (n > 32) + return alignof(long long); + if (n > 16) + return alignof(int); + if (n > 8) + return alignof(short); + else + return alignof(char); +} + +#define CHECK_ALIGNMENT(N) \ + if (alignof(_BitInt(N)) != calc_alignof(N)) \ + __builtin_abort (); + +int main (void) +{ + CHECK_ALIGNMENT(2); + CHECK_ALIGNMENT(3); + CHECK_ALIGNMENT(7); + CHECK_ALIGNMENT(8); + CHECK_ALIGNMENT(9); + CHECK_ALIGNMENT(13); + CHECK_ALIGNMENT(15); + CHECK_ALIGNMENT(16); + CHECK_ALIGNMENT(17); + CHECK_ALIGNMENT(24); + CHECK_ALIGNMENT(31); + CHECK_ALIGNMENT(32); + CHECK_ALIGNMENT(33); + CHECK_ALIGNMENT(42); + CHECK_ALIGNMENT(53); + CHECK_ALIGNMENT(63); + CHECK_ALIGNMENT(64); + CHECK_ALIGNMENT(65); + CHECK_ALIGNMENT(79); + CHECK_ALIGNMENT(96); + CHECK_ALIGNMENT(113); + CHECK_ALIGNMENT(127); + CHECK_ALIGNMENT(128); + CHECK_ALIGNMENT(129); + CHECK_ALIGNMENT(153); + CHECK_ALIGNMENT(255); + CHECK_ALIGNMENT(256); + CHECK_ALIGNMENT(257); + CHECK_ALIGNMENT(353); + CHECK_ALIGNMENT(512); + CHECK_ALIGNMENT(620); + CHECK_ALIGNMENT(1024); + CHECK_ALIGNMENT(30000); +} diff --git a/gcc/testsuite/gcc.target/loongarch/bitint-args.c b/gcc/testsuite/gcc.target/loongarch/bitint-args.c new file mode 100644 index 0000000..ceba1fb --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/bitint-args.c @@ -0,0 +1,81 @@ +/* { dg-do compile { target bitint } } */ +/* { dg-additional-options "-std=c23 -O -fno-stack-clash-protection -g" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#define CHECK_ARG(N) \ +void f##N(_BitInt(N) *ptr, _BitInt(N) y) \ +{ \ + *ptr = y; \ +} + + +CHECK_ARG(2) +/* +** f2: +** st.b \$r5,\$r4,0 +** jr \$r1 +*/ +CHECK_ARG(8) +/* +** f8: +** st.b \$r5,\$r4,0 +** jr \$r1 +*/ +CHECK_ARG(9) +/* +** f9: +** st.h \$r5,\$r4,0 +** jr \$r1 +*/ +CHECK_ARG(16) +/* +** f16: +** st.h \$r5,\$r4,0 +** jr \$r1 +*/ +CHECK_ARG(19) +/* +** f19: +** stptr.w \$r5,\$r4,0 +** jr \$r1 +*/ +CHECK_ARG(32) +/* +** f32: +** stptr.w \$r5,\$r4,0 +** jr \$r1 +*/ +CHECK_ARG(42) +/* +** f42: +** stptr.d \$r5,\$r4,0 +** jr \$r1 +*/ +CHECK_ARG(64) +/* +** f64: +** stptr.d \$r5,\$r4,0 +** jr \$r1 +*/ +CHECK_ARG(65) +/* +** f65: +** stptr.d \$r5,\$r4,0 +** st.d \$r6,\$r4,8 +** jr \$r1 +*/ +CHECK_ARG(127) +/* +** f127: +** stptr.d \$r5,\$r4,0 +** st.d \$r6,\$r4,8 +** jr \$r1 +*/ + +CHECK_ARG(128) +/* +** f128: +** stptr.d \$r5,\$r4,0 +** st.d \$r6,\$r4,8 +** jr \$r1 +*/ diff --git a/gcc/testsuite/gcc.target/loongarch/bitint-sizes.c b/gcc/testsuite/gcc.target/loongarch/bitint-sizes.c new file mode 100644 index 0000000..7272f98 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/bitint-sizes.c @@ -0,0 +1,60 @@ +/* { dg-do run { target bitint } } */ +/* { dg-additional-options "-std=c23" } */ + +static long unsigned int +calc_size (int n) +{ + if (n > 128) + return ((n - 1)/128 + 1) * sizeof(__int128_t); + if (n > 64) + return sizeof(__int128_t); + if (n > 32) + return sizeof(long long); + if (n > 16) + return sizeof(int); + if (n > 8) + return sizeof(short); + else + return sizeof(char); +} + +#define CHECK_SIZE(N) \ + if (sizeof(_BitInt(N)) != calc_size(N)) \ + __builtin_abort (); + +int main (void) +{ + CHECK_SIZE(2); + CHECK_SIZE(3); + CHECK_SIZE(7); + CHECK_SIZE(8); + CHECK_SIZE(9); + CHECK_SIZE(13); + CHECK_SIZE(15); + CHECK_SIZE(16); + CHECK_SIZE(17); + CHECK_SIZE(24); + CHECK_SIZE(31); + CHECK_SIZE(32); + CHECK_SIZE(33); + CHECK_SIZE(42); + CHECK_SIZE(53); + CHECK_SIZE(63); + CHECK_SIZE(64); + CHECK_SIZE(65); + CHECK_SIZE(79); + CHECK_SIZE(96); + CHECK_SIZE(113); + CHECK_SIZE(127); + CHECK_SIZE(128); + CHECK_SIZE(129); + CHECK_SIZE(153); + CHECK_SIZE(255); + CHECK_SIZE(256); + CHECK_SIZE(257); + CHECK_SIZE(353); + CHECK_SIZE(512); + CHECK_SIZE(620); + CHECK_SIZE(1024); + CHECK_SIZE(30000); +} diff --git a/gcc/testsuite/gcc.target/loongarch/pr121542.c b/gcc/testsuite/gcc.target/loongarch/pr121542.c new file mode 100644 index 0000000..51a5e3c --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/pr121542.c @@ -0,0 +1,54 @@ +/* { dg-do compile } */ +/* { dg-options "-mrecip=all -mfrecipe -mabi=lp64d -march=loongarch64 -mfpu=64 -msimd=lasx -Ofast" } */ + +typedef long unsigned int STRLEN; +typedef struct sv SV; +struct sv +{ + void *sv_any; + unsigned int sv_refcnt; + unsigned int sv_flags; +}; +typedef struct xpv XPV; +struct xpv +{ + char *xpv_pv; + STRLEN xpv_cur; + STRLEN xpv_len; +}; +typedef unsigned long UV; +extern char *PL_bufend; +extern char *d; +SV *Perl_newSV (STRLEN len); + +char * +S_scan_const (char *start) +{ + register char *send = PL_bufend; + SV *sv = Perl_newSV (send - start); + register char *s = start; + UV uv; + + while (s < send) + { + if (!(((UV)(uv)) < 0x80)) + { + int hicount = 0; + unsigned char *c; + for (c = (unsigned char *)((XPV *)(sv)->sv_any)->xpv_pv; + c < (unsigned char *)d; c++) + { + if (!(((UV)(*c)) < 0x80)) + { + hicount++; + } + } + d += hicount; + *d++ = (char)uv; + } + + s++; + } + + return s; +} diff --git a/gcc/testsuite/gcc.target/loongarch/pr121634.c b/gcc/testsuite/gcc.target/loongarch/pr121634.c new file mode 100644 index 0000000..325173a --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/pr121634.c @@ -0,0 +1,15 @@ +/* PR target/121634: ICE in highway-1.3.0 testsuite */ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=la464 -mabi=lp64d" } */ + +typedef short v8i16 __attribute__ ((vector_size (16))); +typedef int v4i32 __attribute__ ((vector_size (16))); +typedef long __m128i __attribute__ ((__vector_size__ (16))); +__m128i x, y; + +__m128i +WidenMulPairwiseAdd (__m128i a, __m128i b) +{ + y = (__m128i)__builtin_lsx_vmaddwod_w_h ((v4i32)x, (v8i16){}, (v8i16){}); + return y; +} diff --git a/gcc/testsuite/gcc.target/mips/call-clobbered-1.c b/gcc/testsuite/gcc.target/mips/call-clobbered-1.c index 8880ad1..2e05213 100644 --- a/gcc/testsuite/gcc.target/mips/call-clobbered-1.c +++ b/gcc/testsuite/gcc.target/mips/call-clobbered-1.c @@ -1,6 +1,6 @@ /* Check that we handle call-clobbered FPRs correctly. */ /* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ -/* { dg-options "isa>=2 -mabi=32 -mfpxx -mhard-float -ffixed-f0 -ffixed-f1 -ffixed-f2 -ffixed-f3 -ffixed-f4 -ffixed-f5 -ffixed-f6 -ffixed-f7 -ffixed-f8 -ffixed-f9 -ffixed-f10 -ffixed-f11 -ffixed-f12 -ffixed-f13 -ffixed-f14 -ffixed-f15 -ffixed-f16 -ffixed-f17 -ffixed-f18 -ffixed-f19" } */ +/* { dg-options "(HAS_LDC) -mabi=32 -mfpxx -mhard-float -ffixed-f0 -ffixed-f1 -ffixed-f2 -ffixed-f3 -ffixed-f4 -ffixed-f5 -ffixed-f6 -ffixed-f7 -ffixed-f8 -ffixed-f9 -ffixed-f10 -ffixed-f11 -ffixed-f12 -ffixed-f13 -ffixed-f14 -ffixed-f15 -ffixed-f16 -ffixed-f17 -ffixed-f18 -ffixed-f19" } */ void bar (void); double a; diff --git a/gcc/testsuite/gcc.target/mips/call-clobbered-2.c b/gcc/testsuite/gcc.target/mips/call-clobbered-2.c index 5f9a472..86be445 100644 --- a/gcc/testsuite/gcc.target/mips/call-clobbered-2.c +++ b/gcc/testsuite/gcc.target/mips/call-clobbered-2.c @@ -4,7 +4,8 @@ void bar (void); float a; -float + +NOMIPS16 float foo () { float b = a + 1.0f; diff --git a/gcc/testsuite/gcc.target/mips/call-clobbered-3.c b/gcc/testsuite/gcc.target/mips/call-clobbered-3.c index 3a9e8d8..cca94bd 100644 --- a/gcc/testsuite/gcc.target/mips/call-clobbered-3.c +++ b/gcc/testsuite/gcc.target/mips/call-clobbered-3.c @@ -4,7 +4,7 @@ void bar (void); float a; -float +NOMIPS16 float foo () { float b = a + 1.0f; diff --git a/gcc/testsuite/gcc.target/mips/call-clobbered-5.c b/gcc/testsuite/gcc.target/mips/call-clobbered-5.c index c7cd7ca..b9ca587 100644 --- a/gcc/testsuite/gcc.target/mips/call-clobbered-5.c +++ b/gcc/testsuite/gcc.target/mips/call-clobbered-5.c @@ -4,7 +4,7 @@ void bar (void); float a; -float +NOMIPS16 float foo () { float b = a + 1.0f; diff --git a/gcc/testsuite/gcc.target/mips/ds-schedule-2.c b/gcc/testsuite/gcc.target/mips/ds-schedule-2.c index 6c5de5d..3cb3c59 100644 --- a/gcc/testsuite/gcc.target/mips/ds-schedule-2.c +++ b/gcc/testsuite/gcc.target/mips/ds-schedule-2.c @@ -1,4 +1,4 @@ -/* { dg-options "-mcompact-branches=never -mno-abicalls -G4" } */ +/* { dg-options "-mcompact-branches=never -mno-mips16 -mno-abicalls -G4" } */ /* { dg-skip-if "code quality test" { *-*-* } { "-O0" "-O1" "-Os" } { "" } } */ /* { dg-final { scan-assembler "beq.*\n\tlw" } } */ /* { dg-final { scan-assembler-times "\\(foo\\)" 2 } } */ @@ -19,7 +19,7 @@ int foo; extern void t (int, int, int*); -void +NOMIPS16 void f (struct list **ptr) { if (gr) diff --git a/gcc/testsuite/gcc.target/mips/insn-casesi.c b/gcc/testsuite/gcc.target/mips/insn-casesi.c index 2b4c9f2..03d1307 100644 --- a/gcc/testsuite/gcc.target/mips/insn-casesi.c +++ b/gcc/testsuite/gcc.target/mips/insn-casesi.c @@ -1,7 +1,7 @@ /* { dg-do run } */ -/* { dg-options "-mips16 -mcode-readable=yes" } */ +/* { dg-options "(-mips16) -mabi=32 -mcode-readable=yes" } */ -int __attribute__ ((noinline)) +MIPS16 int __attribute__ ((noinline)) frob (int i) { switch (i) @@ -22,7 +22,7 @@ frob (int i) return i; } -int +MIPS16 int main (int argc, char **argv) { asm ("" : "+r" (argc)); diff --git a/gcc/testsuite/gcc.target/mips/insn-tablejump.c b/gcc/testsuite/gcc.target/mips/insn-tablejump.c index ecba154..271108a 100644 --- a/gcc/testsuite/gcc.target/mips/insn-tablejump.c +++ b/gcc/testsuite/gcc.target/mips/insn-tablejump.c @@ -1,7 +1,7 @@ /* { dg-do run } */ -/* { dg-options "-mmicromips" } */ +/* { dg-options "(-mmicromips) -mabi=32" } */ -int __attribute__ ((noinline)) +MICROMIPS int __attribute__ ((noinline)) frob (int i) { switch (i) @@ -22,7 +22,7 @@ frob (int i) return i; } -int +MICROMIPS int main (int argc, char **argv) { asm ("" : "+r" (argc)); diff --git a/gcc/testsuite/gcc.target/mips/interrupt_handler-bug-1.c b/gcc/testsuite/gcc.target/mips/interrupt_handler-bug-1.c index 083e152..d8412f1 100644 --- a/gcc/testsuite/gcc.target/mips/interrupt_handler-bug-1.c +++ b/gcc/testsuite/gcc.target/mips/interrupt_handler-bug-1.c @@ -2,7 +2,7 @@ int foo; int bar; -void __attribute__ ((interrupt)) +NOMIPS16 void __attribute__ ((interrupt)) isr (void) { if (!foo) diff --git a/gcc/testsuite/gcc.target/mips/movdf-1.c b/gcc/testsuite/gcc.target/mips/movdf-1.c index f0267d0..5fe6180 100644 --- a/gcc/testsuite/gcc.target/mips/movdf-1.c +++ b/gcc/testsuite/gcc.target/mips/movdf-1.c @@ -4,7 +4,7 @@ void bar (void); -double +NOMIPS16 double foo (int x, double a) { return a; diff --git a/gcc/testsuite/gcc.target/mips/movdf-2.c b/gcc/testsuite/gcc.target/mips/movdf-2.c index 175b61c..0e52c9f 100644 --- a/gcc/testsuite/gcc.target/mips/movdf-2.c +++ b/gcc/testsuite/gcc.target/mips/movdf-2.c @@ -4,7 +4,7 @@ void bar (void); -double +NOMIPS16 double foo (int x, double a) { return a; diff --git a/gcc/testsuite/gcc.target/mips/movdf-3.c b/gcc/testsuite/gcc.target/mips/movdf-3.c index 5db52c9..f1dd2ab 100644 --- a/gcc/testsuite/gcc.target/mips/movdf-3.c +++ b/gcc/testsuite/gcc.target/mips/movdf-3.c @@ -4,7 +4,7 @@ void bar (void); -double +NOMIPS16 double foo (int x, double a) { return a; diff --git a/gcc/testsuite/gcc.target/mips/msa-builtins.c b/gcc/testsuite/gcc.target/mips/msa-builtins.c index 6a146b3..932cc8d 100644 --- a/gcc/testsuite/gcc.target/mips/msa-builtins.c +++ b/gcc/testsuite/gcc.target/mips/msa-builtins.c @@ -1,6 +1,6 @@ /* Test builtins for MIPS MSA ASE instructions */ /* { dg-do compile } */ -/* { dg-options "-mfp64 -mhard-float -mmsa" } */ +/* { dg-options "-mno-mips16 -mfp64 -mhard-float -mmsa" } */ /* { dg-final { scan-assembler-times "msa_addv_b:.*addv\\.b.*msa_addv_b" 1 } } */ /* { dg-final { scan-assembler-times "msa_addv_h:.*addv\\.h.*msa_addv_h" 1 } } */ @@ -641,182 +641,182 @@ #define FN(NAME, T) FN_EVAL (NAME, T) /* MSA Arithmetic builtins. */ -#define ADDV(T) NOMIPS16 T FN (addv, T ## _DF) (T i, T j) { return BUILTIN (addv, T ## _DF) (i, j); } -#define ADDVI(T) NOMIPS16 T FN (addvi, T ## _DF) (T i) { return BUILTIN (addvi, T ## _DF) (i, U5MAX); } -#define ADD_A(T) NOMIPS16 T FN (add_a, T ## _DF) (T i, T j) { return BUILTIN (add_a, T ## _DF) (i, j); } -#define ADDS_A(T) NOMIPS16 T FN (adds_a, T ## _DF) (T i, T j) { return BUILTIN (adds_a, T ## _DF) (i, j); } -#define ADDS_S(T) NOMIPS16 T FN (adds_s, T ## _DF) (T i, T j) { return BUILTIN (adds_s, T ## _DF) (i, j); } -#define ADDS_U(T) NOMIPS16 T FN (adds_u, T ## _DF) (T i, T j) { return BUILTIN (adds_u, T ## _DF) (i, j); } -#define HADD_S(T) NOMIPS16 T ## _DBL FN (hadd_s, T ## _DDF) (T i, T j) { return BUILTIN (hadd_s, T ## _DDF) (i, j); } -#define HADD_U(T) NOMIPS16 T ## _DBL FN (hadd_u, T ## _DDF) (T i, T j) { return BUILTIN (hadd_u, T ## _DDF) (i, j); } -#define ASUB_S(T) NOMIPS16 T FN (asub_s, T ## _DF) (T i, T j) { return BUILTIN (asub_s, T ## _DF) (i, j); } -#define ASUB_U(T) NOMIPS16 T FN (asub_u, T ## _DF) (T i, T j) { return BUILTIN (asub_u, T ## _DF) (i, j); } -#define AVE_S(T) NOMIPS16 T FN (ave_s, T ## _DF) (T i, T j) { return BUILTIN (ave_s, T ## _DF) (i, j); } -#define AVE_U(T) NOMIPS16 T FN (ave_u, T ## _DF) (T i, T j) { return BUILTIN (ave_u, T ## _DF) (i, j); } -#define AVER_S(T) NOMIPS16 T FN (aver_s, T ## _DF) (T i, T j) { return BUILTIN (aver_s, T ## _DF) (i, j); } -#define AVER_U(T) NOMIPS16 T FN (aver_u, T ## _DF) (T i, T j) { return BUILTIN (aver_u, T ## _DF) (i, j); } -#define DOTP_S(T) NOMIPS16 T ## _DBL FN (dotp_s, T ## _DDF) (T i, T j) { return BUILTIN (dotp_s, T ## _DDF) (i, j); } -#define DOTP_U(T) NOMIPS16 T ## _DBL FN (dotp_u, T ## _DDF) (T i, T j) { return BUILTIN (dotp_u, T ## _DDF) (i, j); } -#define DPADD_S(T) NOMIPS16 T ## _DBL FN (dpadd_s, T ## _DDF) (T ## _DBL i, T j, T k) { return BUILTIN (dpadd_s, T ## _DDF) (i, j, k); } -#define DPADD_U(T) NOMIPS16 T ## _DBL FN (dpadd_u, T ## _DDF) (T ## _DBL i, T j, T k) { return BUILTIN (dpadd_u, T ## _DDF) (i, j, k); } -#define DPSUB_S(T) NOMIPS16 T ## _DBL FN (dpsub_s, T ## _DDF) (T ## _DBL i, T j, T k) { return BUILTIN (dpsub_s, T ## _DDF) (i, j, k); } -#define DPSUB_U(T) NOMIPS16 T ## _SDBL FN (dpsub_u, T ## _DDF) (T ## _SDBL i, T j, T k) { return BUILTIN (dpsub_u, T ## _DDF) (i, j, k); } -#define DIV_S(T) NOMIPS16 T FN (div_s, T ## _DF) (T i, T j) { return BUILTIN (div_s, T ## _DF) (i, j); } -#define DIV_U(T) NOMIPS16 T FN (div_u, T ## _DF) (T i, T j) { return BUILTIN (div_u, T ## _DF) (i, j); } -#define MADDV(T) NOMIPS16 T FN (maddv, T ## _DF) (T i, T j, T k) { return BUILTIN (maddv, T ## _DF) (i, j, k); } -#define MAX_A(T) NOMIPS16 T FN (max_a, T ## _DF) (T i, T j) { return BUILTIN (max_a, T ## _DF) (i, j); } -#define MIN_A(T) NOMIPS16 T FN (min_a, T ## _DF) (T i, T j) { return BUILTIN (min_a, T ## _DF) (i, j); } -#define MAX_S(T) NOMIPS16 T FN (max_s, T ## _DF) (T i, T j) { return BUILTIN (max_s, T ## _DF) (i, j); } -#define MAXI_S(T) NOMIPS16 T FN (maxi_s, T ## _DF) (T i) { return BUILTIN (maxi_s, T ## _DF) (i, S5MAX); } -#define MAX_U(T) NOMIPS16 T FN (max_u, T ## _DF) (T i, T j) { return BUILTIN (max_u, T ## _DF) (i, j); } -#define MAXI_U(T) NOMIPS16 T FN (maxi_u, T ## _DF) (T i) { return BUILTIN (maxi_u, T ## _DF) (i, S5MAX); } -#define MIN_S(T) NOMIPS16 T FN (min_s, T ## _DF) (T i, T j) { return BUILTIN (min_s, T ## _DF) (i, j); } -#define MINI_S(T) NOMIPS16 T FN (mini_s, T ## _DF) (T i) { return BUILTIN (mini_s, T ## _DF) (i, S5MAX); } -#define MIN_U(T) NOMIPS16 T FN (min_u, T ## _DF) (T i, T j) { return BUILTIN (min_u, T ## _DF) (i, j); } -#define MINI_U(T) NOMIPS16 T FN (mini_u, T ## _DF) (T i) { return BUILTIN (mini_u, T ## _DF) (i, S5MAX); } -#define MSUBV(T) NOMIPS16 T FN (msubv, T ## _DF) (T i, T j, T k) { return BUILTIN (msubv, T ## _DF) (i, j, k); } -#define MULV(T) NOMIPS16 T FN (mulv, T ## _DF) (T i, T j) { return BUILTIN (mulv, T ## _DF) (i, j); } -#define MOD_S(T) NOMIPS16 T FN (mod_s, T ## _DF) (T i, T j) { return BUILTIN (mod_s, T ## _DF) (i, j); } -#define MOD_U(T) NOMIPS16 T FN (mod_u, T ## _DF) (T i, T j) { return BUILTIN (mod_u, T ## _DF) (i, j); } -#define SAT_S(T) NOMIPS16 T FN (sat_s, T ## _DF) (T i) { return BUILTIN (sat_s, T ## _DF) (i, 7); } -#define SAT_U(T) NOMIPS16 T FN (sat_u, T ## _DF) (T i) { return BUILTIN (sat_u, T ## _DF) (i, 7); } -#define SUBS_S(T) NOMIPS16 T FN (subs_s, T ## _DF) (T i, T j) { return BUILTIN (subs_s, T ## _DF) (i, j); } -#define SUBS_U(T) NOMIPS16 T FN (subs_u, T ## _DF) (T i, T j) { return BUILTIN (subs_u, T ## _DF) (i, j); } -#define HSUB_S(T) NOMIPS16 T ## _DBL FN (hsub_s, T ## _DDF) (T i, T j) { return BUILTIN (hsub_s, T ## _DDF) (i, j); } -#define HSUB_U(T) NOMIPS16 T ## _SDBL FN (hsub_u, T ## _DDF) (T i, T j) { return BUILTIN (hsub_u, T ## _DDF) (i, j); } -#define SUBSUU_S(T) NOMIPS16 T ## _S FN (subsuu_s, T ## _DF) (T i, T j) { return BUILTIN (subsuu_s, T ## _DF) (i, j); } -#define SUBSUS_U(T) NOMIPS16 T FN (subsus_u, T ## _DF) (T i, T ## _S j) { return BUILTIN (subsus_u, T ## _DF) (i, j); } -#define SUBV(T) NOMIPS16 T FN (subv, T ## _DF) (T i, T j) { return BUILTIN (subv, T ## _DF) (i, j); } -#define SUBVI(T) NOMIPS16 T FN (subvi, T ## _DF) (T i) { return BUILTIN (subvi, T ## _DF) (i, U5MAX); } +#define ADDV(T) T FN (addv, T ## _DF) (T i, T j) { return BUILTIN (addv, T ## _DF) (i, j); } +#define ADDVI(T) T FN (addvi, T ## _DF) (T i) { return BUILTIN (addvi, T ## _DF) (i, U5MAX); } +#define ADD_A(T) T FN (add_a, T ## _DF) (T i, T j) { return BUILTIN (add_a, T ## _DF) (i, j); } +#define ADDS_A(T) T FN (adds_a, T ## _DF) (T i, T j) { return BUILTIN (adds_a, T ## _DF) (i, j); } +#define ADDS_S(T) T FN (adds_s, T ## _DF) (T i, T j) { return BUILTIN (adds_s, T ## _DF) (i, j); } +#define ADDS_U(T) T FN (adds_u, T ## _DF) (T i, T j) { return BUILTIN (adds_u, T ## _DF) (i, j); } +#define HADD_S(T) T ## _DBL FN (hadd_s, T ## _DDF) (T i, T j) { return BUILTIN (hadd_s, T ## _DDF) (i, j); } +#define HADD_U(T) T ## _DBL FN (hadd_u, T ## _DDF) (T i, T j) { return BUILTIN (hadd_u, T ## _DDF) (i, j); } +#define ASUB_S(T) T FN (asub_s, T ## _DF) (T i, T j) { return BUILTIN (asub_s, T ## _DF) (i, j); } +#define ASUB_U(T) T FN (asub_u, T ## _DF) (T i, T j) { return BUILTIN (asub_u, T ## _DF) (i, j); } +#define AVE_S(T) T FN (ave_s, T ## _DF) (T i, T j) { return BUILTIN (ave_s, T ## _DF) (i, j); } +#define AVE_U(T) T FN (ave_u, T ## _DF) (T i, T j) { return BUILTIN (ave_u, T ## _DF) (i, j); } +#define AVER_S(T) T FN (aver_s, T ## _DF) (T i, T j) { return BUILTIN (aver_s, T ## _DF) (i, j); } +#define AVER_U(T) T FN (aver_u, T ## _DF) (T i, T j) { return BUILTIN (aver_u, T ## _DF) (i, j); } +#define DOTP_S(T) T ## _DBL FN (dotp_s, T ## _DDF) (T i, T j) { return BUILTIN (dotp_s, T ## _DDF) (i, j); } +#define DOTP_U(T) T ## _DBL FN (dotp_u, T ## _DDF) (T i, T j) { return BUILTIN (dotp_u, T ## _DDF) (i, j); } +#define DPADD_S(T) T ## _DBL FN (dpadd_s, T ## _DDF) (T ## _DBL i, T j, T k) { return BUILTIN (dpadd_s, T ## _DDF) (i, j, k); } +#define DPADD_U(T) T ## _DBL FN (dpadd_u, T ## _DDF) (T ## _DBL i, T j, T k) { return BUILTIN (dpadd_u, T ## _DDF) (i, j, k); } +#define DPSUB_S(T) T ## _DBL FN (dpsub_s, T ## _DDF) (T ## _DBL i, T j, T k) { return BUILTIN (dpsub_s, T ## _DDF) (i, j, k); } +#define DPSUB_U(T) T ## _SDBL FN (dpsub_u, T ## _DDF) (T ## _SDBL i, T j, T k) { return BUILTIN (dpsub_u, T ## _DDF) (i, j, k); } +#define DIV_S(T) T FN (div_s, T ## _DF) (T i, T j) { return BUILTIN (div_s, T ## _DF) (i, j); } +#define DIV_U(T) T FN (div_u, T ## _DF) (T i, T j) { return BUILTIN (div_u, T ## _DF) (i, j); } +#define MADDV(T) T FN (maddv, T ## _DF) (T i, T j, T k) { return BUILTIN (maddv, T ## _DF) (i, j, k); } +#define MAX_A(T) T FN (max_a, T ## _DF) (T i, T j) { return BUILTIN (max_a, T ## _DF) (i, j); } +#define MIN_A(T) T FN (min_a, T ## _DF) (T i, T j) { return BUILTIN (min_a, T ## _DF) (i, j); } +#define MAX_S(T) T FN (max_s, T ## _DF) (T i, T j) { return BUILTIN (max_s, T ## _DF) (i, j); } +#define MAXI_S(T) T FN (maxi_s, T ## _DF) (T i) { return BUILTIN (maxi_s, T ## _DF) (i, S5MAX); } +#define MAX_U(T) T FN (max_u, T ## _DF) (T i, T j) { return BUILTIN (max_u, T ## _DF) (i, j); } +#define MAXI_U(T) T FN (maxi_u, T ## _DF) (T i) { return BUILTIN (maxi_u, T ## _DF) (i, S5MAX); } +#define MIN_S(T) T FN (min_s, T ## _DF) (T i, T j) { return BUILTIN (min_s, T ## _DF) (i, j); } +#define MINI_S(T) T FN (mini_s, T ## _DF) (T i) { return BUILTIN (mini_s, T ## _DF) (i, S5MAX); } +#define MIN_U(T) T FN (min_u, T ## _DF) (T i, T j) { return BUILTIN (min_u, T ## _DF) (i, j); } +#define MINI_U(T) T FN (mini_u, T ## _DF) (T i) { return BUILTIN (mini_u, T ## _DF) (i, S5MAX); } +#define MSUBV(T) T FN (msubv, T ## _DF) (T i, T j, T k) { return BUILTIN (msubv, T ## _DF) (i, j, k); } +#define MULV(T) T FN (mulv, T ## _DF) (T i, T j) { return BUILTIN (mulv, T ## _DF) (i, j); } +#define MOD_S(T) T FN (mod_s, T ## _DF) (T i, T j) { return BUILTIN (mod_s, T ## _DF) (i, j); } +#define MOD_U(T) T FN (mod_u, T ## _DF) (T i, T j) { return BUILTIN (mod_u, T ## _DF) (i, j); } +#define SAT_S(T) T FN (sat_s, T ## _DF) (T i) { return BUILTIN (sat_s, T ## _DF) (i, 7); } +#define SAT_U(T) T FN (sat_u, T ## _DF) (T i) { return BUILTIN (sat_u, T ## _DF) (i, 7); } +#define SUBS_S(T) T FN (subs_s, T ## _DF) (T i, T j) { return BUILTIN (subs_s, T ## _DF) (i, j); } +#define SUBS_U(T) T FN (subs_u, T ## _DF) (T i, T j) { return BUILTIN (subs_u, T ## _DF) (i, j); } +#define HSUB_S(T) T ## _DBL FN (hsub_s, T ## _DDF) (T i, T j) { return BUILTIN (hsub_s, T ## _DDF) (i, j); } +#define HSUB_U(T) T ## _SDBL FN (hsub_u, T ## _DDF) (T i, T j) { return BUILTIN (hsub_u, T ## _DDF) (i, j); } +#define SUBSUU_S(T) T ## _S FN (subsuu_s, T ## _DF) (T i, T j) { return BUILTIN (subsuu_s, T ## _DF) (i, j); } +#define SUBSUS_U(T) T FN (subsus_u, T ## _DF) (T i, T ## _S j) { return BUILTIN (subsus_u, T ## _DF) (i, j); } +#define SUBV(T) T FN (subv, T ## _DF) (T i, T j) { return BUILTIN (subv, T ## _DF) (i, j); } +#define SUBVI(T) T FN (subvi, T ## _DF) (T i) { return BUILTIN (subvi, T ## _DF) (i, U5MAX); } /* MSA Bitwise builtins. */ -#define AND(T) NOMIPS16 T FN (and, v) (T i, T j) { return BUILTIN (and, v) (i, j); } -#define ANDI(T) NOMIPS16 T FN (andi, T ## _DF) (T i) { return BUILTIN (andi, T ## _DF) (i, 252); } -#define BCLR(T) NOMIPS16 T FN (bclr, T ## _DF) (T i, T j) { return BUILTIN (bclr, T ## _DF) (i, j); } -#define BCLRI(T) NOMIPS16 T FN (bclri, T ## _DF) (T i) { return BUILTIN (bclri, T ## _DF) (i, 0); } -#define BINSL(T) NOMIPS16 T FN (binsl, T ## _DF) (T i, T j, T k) { return BUILTIN (binsl, T ## _DF) (i, j, k); } -#define BINSLI(T) NOMIPS16 T FN (binsli, T ## _DF) (T i, T j) { return BUILTIN (binsli, T ## _DF) (i, j, 0); } -#define BINSR(T) NOMIPS16 T FN (binsr, T ## _DF) (T i, T j, T k) { return BUILTIN (binsr, T ## _DF) (i, j, k); } -#define BINSRI(T) NOMIPS16 T FN (binsri, T ## _DF) (T i, T j) { return BUILTIN (binsri, T ## _DF) (i, j, 0); } -#define BMNZ(T) NOMIPS16 T FN (bmnz, v) (T i, T j, T k) { return BUILTIN (bmnz, v) (i, j, k); } -#define BMNZI(T) NOMIPS16 T FN (bmnzi, T ## _DF) (T i, T j) { return BUILTIN (bmnzi, T ## _DF) (i, j, 254); } -#define BMZ(T) NOMIPS16 T FN (bmz, v) (T i, T j, T k) { return BUILTIN (bmz, v) (i, j, k); } -#define BMZI(T) NOMIPS16 T FN (bmzi, T ## _DF) (T i, T j) { return BUILTIN (bmzi, T ## _DF) (i, j, 254); } -#define BNEG(T) NOMIPS16 T FN (bneg, T ## _DF) (T i, T j) { return BUILTIN (bneg, T ## _DF) (i, j); } -#define BNEGI(T) NOMIPS16 T FN (bnegi, T ## _DF) (T i) { return BUILTIN (bnegi, T ## _DF) (i, 0); } -#define BSEL(T) NOMIPS16 T FN (bsel, v) (T i, T j, T k) { return BUILTIN (bsel, v) (i, j, k); } -#define BSELI(T) NOMIPS16 T FN (bseli, T ## _DF) (T i, T j) { return BUILTIN (bseli, T ## _DF) (i, j, U8MAX-1); } -#define BSET(T) NOMIPS16 T FN (bset, T ## _DF) (T i, T j) { return BUILTIN (bset, T ## _DF) (i, j); } -#define BSETI(T) NOMIPS16 T FN (bseti, T ## _DF) (T i) { return BUILTIN (bseti, T ## _DF) (i, 0); } -#define NLOC(T) NOMIPS16 T FN (nloc, T ## _DF) (T i) { return BUILTIN (nloc, T ## _DF) (i); } -#define NLZC(T) NOMIPS16 T FN (nlzc, T ## _DF) (T i) { return BUILTIN (nlzc, T ## _DF) (i); } -#define NOR(T) NOMIPS16 T FN (nor, v) (T i, T j) { return BUILTIN (nor, v) (i, j); } -#define NORI(T) NOMIPS16 T FN (nori, T ## _DF) (T i) { return BUILTIN (nori, T ## _DF) (i, 254); } -#define PCNT(T) NOMIPS16 T FN (pcnt, T ## _DF) (T i) { return BUILTIN (pcnt, T ## _DF) (i); } -#define OR(T) NOMIPS16 T FN (or, v) (T i, T j) { return BUILTIN (or, v) (i, j); } -#define ORI(T) NOMIPS16 T FN (ori, T ## _DF) (T i) { return BUILTIN (ori, T ## _DF) (i, 252); } -#define XOR(T) NOMIPS16 T FN (xor, v) (T i, T j) { return BUILTIN (xor, v) (i, j); } -#define XORI(T) NOMIPS16 T FN (xori, T ## _DF) (T i) { return BUILTIN (xori, T ## _DF) (i, 254); } -#define SLL(T) NOMIPS16 T FN (sll, T ## _DF) (T i, T j) { return BUILTIN (sll, T ## _DF) (i, j); } -#define SLLI(T) NOMIPS16 T FN (slli, T ## _DF) (T i) { return BUILTIN (slli, T ## _DF) (i, 1); } -#define SRA(T) NOMIPS16 T FN (sra, T ## _DF) (T i, T j) { return BUILTIN (sra, T ## _DF) (i, j); } -#define SRAI(T) NOMIPS16 T FN (srai, T ## _DF) (T i) { return BUILTIN (srai, T ## _DF) (i, 1); } -#define SRAR(T) NOMIPS16 T FN (srar, T ## _DF) (T i, T j) { return BUILTIN (srar, T ## _DF) (i, j); } -#define SRARI(T) NOMIPS16 T FN (srari, T ## _DF) (T i) { return BUILTIN (srari, T ## _DF) (i, 0); } -#define SRL(T) NOMIPS16 T FN (srl, T ## _DF) (T i, T j) { return BUILTIN (srl, T ## _DF) (i, j); } -#define SRLI(T) NOMIPS16 T FN (srli, T ## _DF) (T i) { return BUILTIN (srli, T ## _DF) (i, 1); } -#define SRLR(T) NOMIPS16 T FN (srlr, T ## _DF) (T i, T j) { return BUILTIN (srlr, T ## _DF) (i, j); } -#define SRLRI(T) NOMIPS16 T FN (srlri, T ## _DF) (T i) { return BUILTIN (srlri, T ## _DF) (i, 0); } +#define AND(T) T FN (and, v) (T i, T j) { return BUILTIN (and, v) (i, j); } +#define ANDI(T) T FN (andi, T ## _DF) (T i) { return BUILTIN (andi, T ## _DF) (i, 252); } +#define BCLR(T) T FN (bclr, T ## _DF) (T i, T j) { return BUILTIN (bclr, T ## _DF) (i, j); } +#define BCLRI(T) T FN (bclri, T ## _DF) (T i) { return BUILTIN (bclri, T ## _DF) (i, 0); } +#define BINSL(T) T FN (binsl, T ## _DF) (T i, T j, T k) { return BUILTIN (binsl, T ## _DF) (i, j, k); } +#define BINSLI(T) T FN (binsli, T ## _DF) (T i, T j) { return BUILTIN (binsli, T ## _DF) (i, j, 0); } +#define BINSR(T) T FN (binsr, T ## _DF) (T i, T j, T k) { return BUILTIN (binsr, T ## _DF) (i, j, k); } +#define BINSRI(T) T FN (binsri, T ## _DF) (T i, T j) { return BUILTIN (binsri, T ## _DF) (i, j, 0); } +#define BMNZ(T) T FN (bmnz, v) (T i, T j, T k) { return BUILTIN (bmnz, v) (i, j, k); } +#define BMNZI(T) T FN (bmnzi, T ## _DF) (T i, T j) { return BUILTIN (bmnzi, T ## _DF) (i, j, 254); } +#define BMZ(T) T FN (bmz, v) (T i, T j, T k) { return BUILTIN (bmz, v) (i, j, k); } +#define BMZI(T) T FN (bmzi, T ## _DF) (T i, T j) { return BUILTIN (bmzi, T ## _DF) (i, j, 254); } +#define BNEG(T) T FN (bneg, T ## _DF) (T i, T j) { return BUILTIN (bneg, T ## _DF) (i, j); } +#define BNEGI(T) T FN (bnegi, T ## _DF) (T i) { return BUILTIN (bnegi, T ## _DF) (i, 0); } +#define BSEL(T) T FN (bsel, v) (T i, T j, T k) { return BUILTIN (bsel, v) (i, j, k); } +#define BSELI(T) T FN (bseli, T ## _DF) (T i, T j) { return BUILTIN (bseli, T ## _DF) (i, j, U8MAX-1); } +#define BSET(T) T FN (bset, T ## _DF) (T i, T j) { return BUILTIN (bset, T ## _DF) (i, j); } +#define BSETI(T) T FN (bseti, T ## _DF) (T i) { return BUILTIN (bseti, T ## _DF) (i, 0); } +#define NLOC(T) T FN (nloc, T ## _DF) (T i) { return BUILTIN (nloc, T ## _DF) (i); } +#define NLZC(T) T FN (nlzc, T ## _DF) (T i) { return BUILTIN (nlzc, T ## _DF) (i); } +#define NOR(T) T FN (nor, v) (T i, T j) { return BUILTIN (nor, v) (i, j); } +#define NORI(T) T FN (nori, T ## _DF) (T i) { return BUILTIN (nori, T ## _DF) (i, 254); } +#define PCNT(T) T FN (pcnt, T ## _DF) (T i) { return BUILTIN (pcnt, T ## _DF) (i); } +#define OR(T) T FN (or, v) (T i, T j) { return BUILTIN (or, v) (i, j); } +#define ORI(T) T FN (ori, T ## _DF) (T i) { return BUILTIN (ori, T ## _DF) (i, 252); } +#define XOR(T) T FN (xor, v) (T i, T j) { return BUILTIN (xor, v) (i, j); } +#define XORI(T) T FN (xori, T ## _DF) (T i) { return BUILTIN (xori, T ## _DF) (i, 254); } +#define SLL(T) T FN (sll, T ## _DF) (T i, T j) { return BUILTIN (sll, T ## _DF) (i, j); } +#define SLLI(T) T FN (slli, T ## _DF) (T i) { return BUILTIN (slli, T ## _DF) (i, 1); } +#define SRA(T) T FN (sra, T ## _DF) (T i, T j) { return BUILTIN (sra, T ## _DF) (i, j); } +#define SRAI(T) T FN (srai, T ## _DF) (T i) { return BUILTIN (srai, T ## _DF) (i, 1); } +#define SRAR(T) T FN (srar, T ## _DF) (T i, T j) { return BUILTIN (srar, T ## _DF) (i, j); } +#define SRARI(T) T FN (srari, T ## _DF) (T i) { return BUILTIN (srari, T ## _DF) (i, 0); } +#define SRL(T) T FN (srl, T ## _DF) (T i, T j) { return BUILTIN (srl, T ## _DF) (i, j); } +#define SRLI(T) T FN (srli, T ## _DF) (T i) { return BUILTIN (srli, T ## _DF) (i, 1); } +#define SRLR(T) T FN (srlr, T ## _DF) (T i, T j) { return BUILTIN (srlr, T ## _DF) (i, j); } +#define SRLRI(T) T FN (srlri, T ## _DF) (T i) { return BUILTIN (srlri, T ## _DF) (i, 0); } /* MSA Floating-Point Arithmetic builtins. */ -#define FADD(T) NOMIPS16 T FN (fadd, T ## _DF) (T i, T j) { return BUILTIN (fadd, T ## _DF) (i, j); } -#define FDIV(T) NOMIPS16 T FN (fdiv, T ## _DF) (T i, T j) { return BUILTIN (fdiv, T ## _DF) (i, j); } -#define FEXP2(T) NOMIPS16 T FN (fexp2, T ## _DF) (T i, T ## _FEXP2 j) { return BUILTIN (fexp2, T ## _DF) (i, j); } -#define FLOG2(T) NOMIPS16 T FN (flog2, T ## _DF) (T i) { return BUILTIN (flog2, T ## _DF) (i); } -#define FMADD(T) NOMIPS16 T FN (fmadd, T ## _DF) (T i, T j, T k) { return BUILTIN (fmadd, T ## _DF) (i, j, k); } -#define FMSUB(T) NOMIPS16 T FN (fmsub, T ## _DF) (T i, T j, T k) { return BUILTIN (fmsub, T ## _DF) (i, j, k); } -#define FMAX(T) NOMIPS16 T FN (fmax, T ## _DF) (T i, T j) { return BUILTIN (fmax, T ## _DF) (i, j); } -#define FMIN(T) NOMIPS16 T FN (fmin, T ## _DF) (T i, T j) { return BUILTIN (fmin, T ## _DF) (i, j); } -#define FMAX_A(T) NOMIPS16 T FN (fmax_a, T ## _DF) (T i, T j) { return BUILTIN (fmax_a, T ## _DF) (i, j); } -#define FMIN_A(T) NOMIPS16 T FN (fmin_a, T ## _DF) (T i, T j) { return BUILTIN (fmin_a, T ## _DF) (i, j); } -#define FMUL(T) NOMIPS16 T FN (fmul, T ## _DF) (T i, T j) { return BUILTIN (fmul, T ## _DF) (i, j); } -#define FRCP(T) NOMIPS16 T FN (frcp, T ## _DF) (T i) { return BUILTIN (frcp, T ## _DF) (i); } -#define FRINT(T) NOMIPS16 T FN (frint, T ## _DF) (T i) { return BUILTIN (frint, T ## _DF) (i); } -#define FRSQRT(T) NOMIPS16 T FN (frsqrt, T ## _DF) (T i) { return BUILTIN (frsqrt, T ## _DF) (i); } -#define FSQRT(T) NOMIPS16 T FN (fsqrt, T ## _DF) (T i) { return BUILTIN (fsqrt, T ## _DF) (i); } -#define FSUB(T) NOMIPS16 T FN (fsub, T ## _DF) (T i, T j) { return BUILTIN (fsub, T ## _DF) (i, j); } +#define FADD(T) T FN (fadd, T ## _DF) (T i, T j) { return BUILTIN (fadd, T ## _DF) (i, j); } +#define FDIV(T) T FN (fdiv, T ## _DF) (T i, T j) { return BUILTIN (fdiv, T ## _DF) (i, j); } +#define FEXP2(T) T FN (fexp2, T ## _DF) (T i, T ## _FEXP2 j) { return BUILTIN (fexp2, T ## _DF) (i, j); } +#define FLOG2(T) T FN (flog2, T ## _DF) (T i) { return BUILTIN (flog2, T ## _DF) (i); } +#define FMADD(T) T FN (fmadd, T ## _DF) (T i, T j, T k) { return BUILTIN (fmadd, T ## _DF) (i, j, k); } +#define FMSUB(T) T FN (fmsub, T ## _DF) (T i, T j, T k) { return BUILTIN (fmsub, T ## _DF) (i, j, k); } +#define FMAX(T) T FN (fmax, T ## _DF) (T i, T j) { return BUILTIN (fmax, T ## _DF) (i, j); } +#define FMIN(T) T FN (fmin, T ## _DF) (T i, T j) { return BUILTIN (fmin, T ## _DF) (i, j); } +#define FMAX_A(T) T FN (fmax_a, T ## _DF) (T i, T j) { return BUILTIN (fmax_a, T ## _DF) (i, j); } +#define FMIN_A(T) T FN (fmin_a, T ## _DF) (T i, T j) { return BUILTIN (fmin_a, T ## _DF) (i, j); } +#define FMUL(T) T FN (fmul, T ## _DF) (T i, T j) { return BUILTIN (fmul, T ## _DF) (i, j); } +#define FRCP(T) T FN (frcp, T ## _DF) (T i) { return BUILTIN (frcp, T ## _DF) (i); } +#define FRINT(T) T FN (frint, T ## _DF) (T i) { return BUILTIN (frint, T ## _DF) (i); } +#define FRSQRT(T) T FN (frsqrt, T ## _DF) (T i) { return BUILTIN (frsqrt, T ## _DF) (i); } +#define FSQRT(T) T FN (fsqrt, T ## _DF) (T i) { return BUILTIN (fsqrt, T ## _DF) (i); } +#define FSUB(T) T FN (fsub, T ## _DF) (T i, T j) { return BUILTIN (fsub, T ## _DF) (i, j); } /* MSA Floating-Point Compare builtins. */ -#define FCLASS(T) NOMIPS16 T ## _FRES FN (fclass, T ## _DF) (T i) { return BUILTIN (fclass, T ## _DF) (i); } -#define FCAF(T) NOMIPS16 T ## _FRES FN (fcaf, T ## _DF) (T i, T j) { return BUILTIN (fcaf, T ## _DF) (i, j); } -#define FCUN(T) NOMIPS16 T ## _FRES FN (fcun, T ## _DF) (T i, T j) { return BUILTIN (fcun, T ## _DF) (i, j); } -#define FCOR(T) NOMIPS16 T ## _FRES FN (fcor, T ## _DF) (T i, T j) { return BUILTIN (fcor, T ## _DF) (i, j); } -#define FCEQ(T) NOMIPS16 T ## _FRES FN (fceq, T ## _DF) (T i, T j) { return BUILTIN (fceq, T ## _DF) (i, j); } -#define FCUNE(T) NOMIPS16 T ## _FRES FN (fcune, T ## _DF) (T i, T j) { return BUILTIN (fcune, T ## _DF) (i, j); } -#define FCUEQ(T) NOMIPS16 T ## _FRES FN (fcueq, T ## _DF) (T i, T j) { return BUILTIN (fcueq, T ## _DF) (i, j); } -#define FCNE(T) NOMIPS16 T ## _FRES FN (fcne, T ## _DF) (T i, T j) { return BUILTIN (fcne, T ## _DF) (i, j); } -#define FCLT(T) NOMIPS16 T ## _FRES FN (fclt, T ## _DF) (T i, T j) { return BUILTIN (fclt, T ## _DF) (i, j); } -#define FCULT(T) NOMIPS16 T ## _FRES FN (fcult, T ## _DF) (T i, T j) { return BUILTIN (fcult, T ## _DF) (i, j); } -#define FCLE(T) NOMIPS16 T ## _FRES FN (fcle, T ## _DF) (T i, T j) { return BUILTIN (fcle, T ## _DF) (i, j); } -#define FCULE(T) NOMIPS16 T ## _FRES FN (fcule, T ## _DF) (T i, T j) { return BUILTIN (fcule, T ## _DF) (i, j); } -#define FSAF(T) NOMIPS16 T ## _FRES FN (fsaf, T ## _DF) (T i, T j) { return BUILTIN (fsaf, T ## _DF) (i, j); } -#define FSUN(T) NOMIPS16 T ## _FRES FN (fsun, T ## _DF) (T i, T j) { return BUILTIN (fsun, T ## _DF) (i, j); } -#define FSOR(T) NOMIPS16 T ## _FRES FN (fsor, T ## _DF) (T i, T j) { return BUILTIN (fsor, T ## _DF) (i, j); } -#define FSEQ(T) NOMIPS16 T ## _FRES FN (fseq, T ## _DF) (T i, T j) { return BUILTIN (fseq, T ## _DF) (i, j); } -#define FSUNE(T) NOMIPS16 T ## _FRES FN (fsune, T ## _DF) (T i, T j) { return BUILTIN (fsune, T ## _DF) (i, j); } -#define FSUEQ(T) NOMIPS16 T ## _FRES FN (fsueq, T ## _DF) (T i, T j) { return BUILTIN (fsueq, T ## _DF) (i, j); } -#define FSNE(T) NOMIPS16 T ## _FRES FN (fsne, T ## _DF) (T i, T j) { return BUILTIN (fsne, T ## _DF) (i, j); } -#define FSLT(T) NOMIPS16 T ## _FRES FN (fslt, T ## _DF) (T i, T j) { return BUILTIN (fslt, T ## _DF) (i, j); } -#define FSULT(T) NOMIPS16 T ## _FRES FN (fsult, T ## _DF) (T i, T j) { return BUILTIN (fsult, T ## _DF) (i, j); } -#define FSLE(T) NOMIPS16 T ## _FRES FN (fsle, T ## _DF) (T i, T j) { return BUILTIN (fsle, T ## _DF) (i, j); } -#define FSULE(T) NOMIPS16 T ## _FRES FN (fsule, T ## _DF) (T i, T j) { return BUILTIN (fsule, T ## _DF) (i, j); } +#define FCLASS(T) T ## _FRES FN (fclass, T ## _DF) (T i) { return BUILTIN (fclass, T ## _DF) (i); } +#define FCAF(T) T ## _FRES FN (fcaf, T ## _DF) (T i, T j) { return BUILTIN (fcaf, T ## _DF) (i, j); } +#define FCUN(T) T ## _FRES FN (fcun, T ## _DF) (T i, T j) { return BUILTIN (fcun, T ## _DF) (i, j); } +#define FCOR(T) T ## _FRES FN (fcor, T ## _DF) (T i, T j) { return BUILTIN (fcor, T ## _DF) (i, j); } +#define FCEQ(T) T ## _FRES FN (fceq, T ## _DF) (T i, T j) { return BUILTIN (fceq, T ## _DF) (i, j); } +#define FCUNE(T) T ## _FRES FN (fcune, T ## _DF) (T i, T j) { return BUILTIN (fcune, T ## _DF) (i, j); } +#define FCUEQ(T) T ## _FRES FN (fcueq, T ## _DF) (T i, T j) { return BUILTIN (fcueq, T ## _DF) (i, j); } +#define FCNE(T) T ## _FRES FN (fcne, T ## _DF) (T i, T j) { return BUILTIN (fcne, T ## _DF) (i, j); } +#define FCLT(T) T ## _FRES FN (fclt, T ## _DF) (T i, T j) { return BUILTIN (fclt, T ## _DF) (i, j); } +#define FCULT(T) T ## _FRES FN (fcult, T ## _DF) (T i, T j) { return BUILTIN (fcult, T ## _DF) (i, j); } +#define FCLE(T) T ## _FRES FN (fcle, T ## _DF) (T i, T j) { return BUILTIN (fcle, T ## _DF) (i, j); } +#define FCULE(T) T ## _FRES FN (fcule, T ## _DF) (T i, T j) { return BUILTIN (fcule, T ## _DF) (i, j); } +#define FSAF(T) T ## _FRES FN (fsaf, T ## _DF) (T i, T j) { return BUILTIN (fsaf, T ## _DF) (i, j); } +#define FSUN(T) T ## _FRES FN (fsun, T ## _DF) (T i, T j) { return BUILTIN (fsun, T ## _DF) (i, j); } +#define FSOR(T) T ## _FRES FN (fsor, T ## _DF) (T i, T j) { return BUILTIN (fsor, T ## _DF) (i, j); } +#define FSEQ(T) T ## _FRES FN (fseq, T ## _DF) (T i, T j) { return BUILTIN (fseq, T ## _DF) (i, j); } +#define FSUNE(T) T ## _FRES FN (fsune, T ## _DF) (T i, T j) { return BUILTIN (fsune, T ## _DF) (i, j); } +#define FSUEQ(T) T ## _FRES FN (fsueq, T ## _DF) (T i, T j) { return BUILTIN (fsueq, T ## _DF) (i, j); } +#define FSNE(T) T ## _FRES FN (fsne, T ## _DF) (T i, T j) { return BUILTIN (fsne, T ## _DF) (i, j); } +#define FSLT(T) T ## _FRES FN (fslt, T ## _DF) (T i, T j) { return BUILTIN (fslt, T ## _DF) (i, j); } +#define FSULT(T) T ## _FRES FN (fsult, T ## _DF) (T i, T j) { return BUILTIN (fsult, T ## _DF) (i, j); } +#define FSLE(T) T ## _FRES FN (fsle, T ## _DF) (T i, T j) { return BUILTIN (fsle, T ## _DF) (i, j); } +#define FSULE(T) T ## _FRES FN (fsule, T ## _DF) (T i, T j) { return BUILTIN (fsule, T ## _DF) (i, j); } /* MSA Floating-Point Conversion builtins. */ -#define FEXUPL(T) NOMIPS16 T FN (fexupl, T ## _DF) (T ## _FCNV i) { return BUILTIN (fexupl, T ## _DF) (i); } -#define FEXUPR(T) NOMIPS16 T FN (fexupr, T ## _DF) (T ## _FCNV i) { return BUILTIN (fexupr, T ## _DF) (i); } -#define FEXDO(T) NOMIPS16 T ## _FCNV FN (fexdo, T ## _HDF) (T i, T j) { return BUILTIN (fexdo, T ## _HDF) (i, j); } -#define FFINT_S(T) NOMIPS16 T FN (ffint_s, T ## _DF) (T ## _FSINT i) { return BUILTIN (ffint_s, T ## _DF) (i); } -#define FFINT_U(T) NOMIPS16 T FN (ffint_u, T ## _DF) (T ## _FUINT i) { return BUILTIN (ffint_u, T ## _DF) (i); } -#define FFQL(T) NOMIPS16 T FN (ffql, T ## _DF) (T ## _FFP i) { return BUILTIN (ffql, T ## _DF) (i); } -#define FFQR(T) NOMIPS16 T FN (ffqr, T ## _DF) (T ## _FFP i) { return BUILTIN (ffqr, T ## _DF) (i); } -#define FTINT_S(T) NOMIPS16 T ## _FSINT FN (ftint_s, T ## _DF) (T i) { return BUILTIN (ftint_s, T ## _DF) (i); } -#define FTINT_U(T) NOMIPS16 T ## _FUINT FN (ftint_u, T ## _DF) (T i) { return BUILTIN (ftint_u, T ## _DF) (i); } -#define FTRUNC_S(T) NOMIPS16 T ## _FSINT FN (ftrunc_s, T ## _DF) (T i) { return BUILTIN (ftrunc_s, T ## _DF) (i); } -#define FTRUNC_U(T) NOMIPS16 T ## _FUINT FN (ftrunc_u, T ## _DF) (T i) { return BUILTIN (ftrunc_u, T ## _DF) (i); } -#define FTQ(T) NOMIPS16 T ## _FFP FN (ftq, T ## _HDF) (T i, T j) { return BUILTIN (ftq, T ## _HDF) (i, j); } +#define FEXUPL(T) T FN (fexupl, T ## _DF) (T ## _FCNV i) { return BUILTIN (fexupl, T ## _DF) (i); } +#define FEXUPR(T) T FN (fexupr, T ## _DF) (T ## _FCNV i) { return BUILTIN (fexupr, T ## _DF) (i); } +#define FEXDO(T) T ## _FCNV FN (fexdo, T ## _HDF) (T i, T j) { return BUILTIN (fexdo, T ## _HDF) (i, j); } +#define FFINT_S(T) T FN (ffint_s, T ## _DF) (T ## _FSINT i) { return BUILTIN (ffint_s, T ## _DF) (i); } +#define FFINT_U(T) T FN (ffint_u, T ## _DF) (T ## _FUINT i) { return BUILTIN (ffint_u, T ## _DF) (i); } +#define FFQL(T) T FN (ffql, T ## _DF) (T ## _FFP i) { return BUILTIN (ffql, T ## _DF) (i); } +#define FFQR(T) T FN (ffqr, T ## _DF) (T ## _FFP i) { return BUILTIN (ffqr, T ## _DF) (i); } +#define FTINT_S(T) T ## _FSINT FN (ftint_s, T ## _DF) (T i) { return BUILTIN (ftint_s, T ## _DF) (i); } +#define FTINT_U(T) T ## _FUINT FN (ftint_u, T ## _DF) (T i) { return BUILTIN (ftint_u, T ## _DF) (i); } +#define FTRUNC_S(T) T ## _FSINT FN (ftrunc_s, T ## _DF) (T i) { return BUILTIN (ftrunc_s, T ## _DF) (i); } +#define FTRUNC_U(T) T ## _FUINT FN (ftrunc_u, T ## _DF) (T i) { return BUILTIN (ftrunc_u, T ## _DF) (i); } +#define FTQ(T) T ## _FFP FN (ftq, T ## _HDF) (T i, T j) { return BUILTIN (ftq, T ## _HDF) (i, j); } /* MSA Fixed-Point Multiplication builtins. */ -#define MADD_Q(T) NOMIPS16 T ## _FFP FN (madd_q, T ## _HDF) (T ## _FFP i, T ## _FFP j, T ## _FFP k) { return BUILTIN (madd_q, T ## _HDF) (i, j, k); } -#define MADDR_Q(T) NOMIPS16 T ## _FFP FN (maddr_q, T ## _HDF) (T ## _FFP i, T ## _FFP j, T ## _FFP k) { return BUILTIN (maddr_q, T ## _HDF) (i, j, k); } -#define MSUB_Q(T) NOMIPS16 T ## _FFP FN (msub_q, T ## _HDF) (T ## _FFP i, T ## _FFP j, T ## _FFP k) { return BUILTIN (msub_q, T ## _HDF) (i, j, k); } -#define MSUBR_Q(T) NOMIPS16 T ## _FFP FN (msubr_q, T ## _HDF) (T ## _FFP i, T ## _FFP j, T ## _FFP k) { return BUILTIN (msubr_q, T ## _HDF) (i, j, k); } -#define MUL_Q(T) NOMIPS16 T ## _FFP FN (mul_q, T ## _HDF) (T ## _FFP i, T ## _FFP j) { return BUILTIN (mul_q, T ## _HDF) (i, j); } -#define MULR_Q(T) NOMIPS16 T ## _FFP FN (mulr_q, T ## _HDF) (T ## _FFP i, T ## _FFP j) { return BUILTIN (mulr_q, T ## _HDF) (i, j); } +#define MADD_Q(T) T ## _FFP FN (madd_q, T ## _HDF) (T ## _FFP i, T ## _FFP j, T ## _FFP k) { return BUILTIN (madd_q, T ## _HDF) (i, j, k); } +#define MADDR_Q(T) T ## _FFP FN (maddr_q, T ## _HDF) (T ## _FFP i, T ## _FFP j, T ## _FFP k) { return BUILTIN (maddr_q, T ## _HDF) (i, j, k); } +#define MSUB_Q(T) T ## _FFP FN (msub_q, T ## _HDF) (T ## _FFP i, T ## _FFP j, T ## _FFP k) { return BUILTIN (msub_q, T ## _HDF) (i, j, k); } +#define MSUBR_Q(T) T ## _FFP FN (msubr_q, T ## _HDF) (T ## _FFP i, T ## _FFP j, T ## _FFP k) { return BUILTIN (msubr_q, T ## _HDF) (i, j, k); } +#define MUL_Q(T) T ## _FFP FN (mul_q, T ## _HDF) (T ## _FFP i, T ## _FFP j) { return BUILTIN (mul_q, T ## _HDF) (i, j); } +#define MULR_Q(T) T ## _FFP FN (mulr_q, T ## _HDF) (T ## _FFP i, T ## _FFP j) { return BUILTIN (mulr_q, T ## _HDF) (i, j); } /* MSA Compare builtins. */ -#define CEQ(T) NOMIPS16 T FN (ceq, T ## _DF) (T i, T j) { return BUILTIN (ceq, T ## _DF) (i, j); } -#define CEQI(T) NOMIPS16 T FN (ceqi, T ## _DF) (T i) { return BUILTIN (ceqi, T ## _DF) (i, 0); } -#define CLE_S(T) NOMIPS16 T FN (cle_s, T ## _DF) (T i, T j) { return BUILTIN (cle_s, T ## _DF) (i, j); } -#define CLEI_S(T) NOMIPS16 T FN (clei_s, T ## _DF) (T i) { return BUILTIN (clei_s, T ## _DF) (i, 0); } -#define CLE_U(T) NOMIPS16 T ## _CMP FN (cle_u, T ## _DF) (T i, T j) { return BUILTIN (cle_u, T ## _DF) (i, j); } -#define CLEI_U(T) NOMIPS16 T ## _CMP FN (clei_u, T ## _DF) (T i) { return BUILTIN (clei_u, T ## _DF) (i, 10); } -#define CLT_S(T) NOMIPS16 T FN (clt_s, T ## _DF) (T i, T j) { return BUILTIN (clt_s, T ## _DF) (i, j); } -#define CLTI_S(T) NOMIPS16 T FN (clti_s, T ## _DF) (T i) { return BUILTIN (clti_s, T ## _DF) (i, 0); } -#define CLT_U(T) NOMIPS16 T ## _CMP FN (clt_u, T ## _DF) (T i, T j) { return BUILTIN (clt_u, T ## _DF) (i, j); } -#define CLTI_U(T) NOMIPS16 T ## _CMP FN (clti_u, T ## _DF) (T i) { return BUILTIN (clti_u, T ## _DF) (i, 0); } +#define CEQ(T) T FN (ceq, T ## _DF) (T i, T j) { return BUILTIN (ceq, T ## _DF) (i, j); } +#define CEQI(T) T FN (ceqi, T ## _DF) (T i) { return BUILTIN (ceqi, T ## _DF) (i, 0); } +#define CLE_S(T) T FN (cle_s, T ## _DF) (T i, T j) { return BUILTIN (cle_s, T ## _DF) (i, j); } +#define CLEI_S(T) T FN (clei_s, T ## _DF) (T i) { return BUILTIN (clei_s, T ## _DF) (i, 0); } +#define CLE_U(T) T ## _CMP FN (cle_u, T ## _DF) (T i, T j) { return BUILTIN (cle_u, T ## _DF) (i, j); } +#define CLEI_U(T) T ## _CMP FN (clei_u, T ## _DF) (T i) { return BUILTIN (clei_u, T ## _DF) (i, 10); } +#define CLT_S(T) T FN (clt_s, T ## _DF) (T i, T j) { return BUILTIN (clt_s, T ## _DF) (i, j); } +#define CLTI_S(T) T FN (clti_s, T ## _DF) (T i) { return BUILTIN (clti_s, T ## _DF) (i, 0); } +#define CLT_U(T) T ## _CMP FN (clt_u, T ## _DF) (T i, T j) { return BUILTIN (clt_u, T ## _DF) (i, j); } +#define CLTI_U(T) T ## _CMP FN (clti_u, T ## _DF) (T i) { return BUILTIN (clti_u, T ## _DF) (i, 0); } /* MSA Branch builtins. */ -#define BNZV(T) NOMIPS16 int FN (bnz, v) (T i) { return BUILTIN (bnz, v) (i); } -#define BZV(T) NOMIPS16 int FN (bz, v) (T i) { return BUILTIN (bz, v) (i); } -#define BNZ(T) NOMIPS16 int FN (bnz, T ## _DF) (T i) { return BUILTIN (bnz, T ## _DF) (i); } -#define BZ(T) NOMIPS16 int FN (bz, T ## _DF) (T i) { return BUILTIN (bz, T ## _DF) (i); } +#define BNZV(T) int FN (bnz, v) (T i) { return BUILTIN (bnz, v) (i); } +#define BZV(T) int FN (bz, v) (T i) { return BUILTIN (bz, v) (i); } +#define BNZ(T) int FN (bnz, T ## _DF) (T i) { return BUILTIN (bnz, T ## _DF) (i); } +#define BZ(T) int FN (bz, T ## _DF) (T i) { return BUILTIN (bz, T ## _DF) (i); } /* MSA Load/Store and Move builtins. */ #define CFCMSA() int msa_cfcmsa () { return __builtin_msa_cfcmsa(0x1f); } #define CTCMSA() void msa_ctcmsa (int i) { return __builtin_msa_ctcmsa(0x1f, i); } #define LD(T) T FN (ld, T ## _DF) (char *i) { return BUILTIN (ld, T ## _DF) (i, 0); } #define LDI(T) T FN (ldi, T ## _DF) () { return BUILTIN (ldi, T ## _DF) (123); } -#define MOVE(T) NOMIPS16 T FN (move, v) (T i) { return BUILTIN (move, v) (i); } +#define MOVE(T) T FN (move, v) (T i) { return BUILTIN (move, v) (i); } #define SPLAT(T) T FN (splat, T ## _DF) (T i, int j) { return BUILTIN (splat, T ## _DF) (i, j); } #define SPLATI(T) T FN (splati, T ## _DF) (T i) { return BUILTIN (splati, T ## _DF) (i, 1); } #define FILL(T) T FN (fill, T ## _DF) (int i) { return BUILTIN (fill, T ## _DF) (i); } @@ -829,16 +829,16 @@ #define ST(T) void FN (st, T ## _DF) (T i, char *j) { BUILTIN (st, T ## _DF) (i, j, -64); } /* MSA Element Permute builtins. */ -#define ILVEV(T) NOMIPS16 T FN (ilvev, T ## _DF) (T i, T j) { return BUILTIN (ilvev, T ## _DF) (i, j); } -#define ILVOD(T) NOMIPS16 T FN (ilvod, T ## _DF) (T i, T j) { return BUILTIN (ilvod, T ## _DF) (i, j); } -#define ILVL(T) NOMIPS16 T FN (ilvl, T ## _DF) (T i, T j) { return BUILTIN (ilvl, T ## _DF) (i, j); } -#define ILVR(T) NOMIPS16 T FN (ilvr, T ## _DF) (T i, T j) { return BUILTIN (ilvr, T ## _DF) (i, j); } -#define PCKEV(T) NOMIPS16 T FN (pckev, T ## _DF) (T i, T j) { return BUILTIN (pckev, T ## _DF) (i, j); } -#define PCKOD(T) NOMIPS16 T FN (pckod, T ## _DF) (T i, T j) { return BUILTIN (pckod, T ## _DF) (i, j); } -#define SHF(T) NOMIPS16 T FN (shf, T ## _DF) (T i) { return BUILTIN (shf, T ## _DF) (i, 127); } -#define SLD(T) NOMIPS16 T FN (sld, T ## _DF) (T i, T j, int k) { return BUILTIN (sld, T ## _DF) (i, j, k); } -#define SLDI(T) NOMIPS16 T FN (sldi, T ## _DF) (T i, T j) { return BUILTIN (sldi, T ## _DF) (i, j, 1); } -#define VSHF(T) NOMIPS16 T FN (vshf, T ## _DF) (T i, T j, T k) { return BUILTIN (vshf, T ## _DF) (i, j, k); } +#define ILVEV(T) T FN (ilvev, T ## _DF) (T i, T j) { return BUILTIN (ilvev, T ## _DF) (i, j); } +#define ILVOD(T) T FN (ilvod, T ## _DF) (T i, T j) { return BUILTIN (ilvod, T ## _DF) (i, j); } +#define ILVL(T) T FN (ilvl, T ## _DF) (T i, T j) { return BUILTIN (ilvl, T ## _DF) (i, j); } +#define ILVR(T) T FN (ilvr, T ## _DF) (T i, T j) { return BUILTIN (ilvr, T ## _DF) (i, j); } +#define PCKEV(T) T FN (pckev, T ## _DF) (T i, T j) { return BUILTIN (pckev, T ## _DF) (i, j); } +#define PCKOD(T) T FN (pckod, T ## _DF) (T i, T j) { return BUILTIN (pckod, T ## _DF) (i, j); } +#define SHF(T) T FN (shf, T ## _DF) (T i) { return BUILTIN (shf, T ## _DF) (i, 127); } +#define SLD(T) T FN (sld, T ## _DF) (T i, T j, int k) { return BUILTIN (sld, T ## _DF) (i, j, k); } +#define SLDI(T) T FN (sldi, T ## _DF) (T i, T j) { return BUILTIN (sldi, T ## _DF) (i, j, 1); } +#define VSHF(T) T FN (vshf, T ## _DF) (T i, T j, T k) { return BUILTIN (vshf, T ## _DF) (i, j, k); } /* GCC builtins that generate MSA instructions. */ #define SHUFFLE1_S(T) T FN (gcc_1_s_vshf, T ## _DF) (T i, T mask) { return __builtin_shuffle (i, mask); } diff --git a/gcc/testsuite/gcc.target/mips/msa.c b/gcc/testsuite/gcc.target/mips/msa.c index 62d0606..8647b6d 100644 --- a/gcc/testsuite/gcc.target/mips/msa.c +++ b/gcc/testsuite/gcc.target/mips/msa.c @@ -1,6 +1,6 @@ /* Test MIPS MSA ASE instructions */ /* { dg-do compile } */ -/* { dg-options "-mfp64 -mhard-float -mmsa -fexpensive-optimizations -fcommon" } */ +/* { dg-options "-mno-mips16 -mfp64 -mhard-float -mmsa -fexpensive-optimizations -fcommon" } */ /* { dg-skip-if "madd and msub need combine" { *-*-* } { "-O0" } { "" } } */ /* { dg-final { scan-assembler-times "\t.comm\tv16i8_\\d+,16,16" 3 } } */ @@ -485,11 +485,11 @@ float imm_f = 37.0; #define DECLARE(TYPE) TYPE TYPE ## _0, TYPE ## _1, TYPE ## _2; -#define RETURN(TYPE) NOMIPS16 TYPE test0_ ## TYPE () { return TYPE ## _0; } -#define ASSIGN(TYPE) NOMIPS16 void test1_ ## TYPE (TYPE i) { TYPE ## _1 = i; } -#define ADD(TYPE) NOMIPS16 TYPE test2_ ## TYPE (TYPE i, TYPE j) { return i + j; } -#define SUB(TYPE) NOMIPS16 TYPE test3_ ## TYPE (TYPE i, TYPE j) { return i - j; } -#define MUL(TYPE) NOMIPS16 TYPE test4_ ## TYPE (TYPE i, TYPE j) { return i * j; } +#define RETURN(TYPE) TYPE test0_ ## TYPE () { return TYPE ## _0; } +#define ASSIGN(TYPE) void test1_ ## TYPE (TYPE i) { TYPE ## _1 = i; } +#define ADD(TYPE) TYPE test2_ ## TYPE (TYPE i, TYPE j) { return i + j; } +#define SUB(TYPE) TYPE test3_ ## TYPE (TYPE i, TYPE j) { return i - j; } +#define MUL(TYPE) TYPE test4_ ## TYPE (TYPE i, TYPE j) { return i * j; } #define DIV(TYPE) TYPE test5_ ## TYPE (TYPE i, TYPE j) { return i / j; } #define MOD(TYPE) TYPE test6_ ## TYPE (TYPE i, TYPE j) { return i % j; } #define MINUS(TYPE) TYPE test7_ ## TYPE (TYPE i) { return -i; } diff --git a/gcc/testsuite/gcc.target/mips/near-far-1.c b/gcc/testsuite/gcc.target/mips/near-far-1.c index 356f7ad..9d3f29d 100644 --- a/gcc/testsuite/gcc.target/mips/near-far-1.c +++ b/gcc/testsuite/gcc.target/mips/near-far-1.c @@ -16,8 +16,8 @@ int test () + normal_func ()); } -/* { dg-final { scan-assembler-not "\tjal\tlong_call_func\n" } } */ -/* { dg-final { scan-assembler-not "\tjal\tfar_func\n" } } */ -/* { dg-final { scan-assembler "\t(jal(|s)|balc)\tshort_call_func\n" } } */ -/* { dg-final { scan-assembler "\t(jal(|s)|balc)\tnear_func\n" } } */ -/* { dg-final { scan-assembler-not "\tjal\tnormal_func\n" } } */ +/* { dg-final { scan-assembler-not "\t(jals?|balc)\tlong_call_func\n" } } */ +/* { dg-final { scan-assembler-not "\t(jals?|balc)\tfar_func\n" } } */ +/* { dg-final { scan-assembler "\t(jals?|balc)\tshort_call_func\n" } } */ +/* { dg-final { scan-assembler "\t(jals?|balc)\tnear_func\n" } } */ +/* { dg-final { scan-assembler-not "\t(jals?|balc)\tnormal_func\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/near-far-2.c b/gcc/testsuite/gcc.target/mips/near-far-2.c index 2e8dbb1..ed9757c 100644 --- a/gcc/testsuite/gcc.target/mips/near-far-2.c +++ b/gcc/testsuite/gcc.target/mips/near-far-2.c @@ -16,8 +16,8 @@ int test () + normal_func ()); } -/* { dg-final { scan-assembler-not "\tjal(|s)\tlong_call_func\n" } } */ -/* { dg-final { scan-assembler-not "\tjal(|s)\tfar_func\n" } } */ -/* { dg-final { scan-assembler "\t(jal(|s)|balc)\tshort_call_func\n" } } */ -/* { dg-final { scan-assembler "\t(jal(|s)|balc)\tnear_func\n" } } */ -/* { dg-final { scan-assembler "\t(jal(|s)|balc)\tnormal_func\n" } } */ +/* { dg-final { scan-assembler-not "\t(jals?|balc)\tlong_call_func\n" } } */ +/* { dg-final { scan-assembler-not "\t(jals?|balc)\tfar_func\n" } } */ +/* { dg-final { scan-assembler "\t(jals?|balc)\tshort_call_func\n" } } */ +/* { dg-final { scan-assembler "\t(jals?|balc)\tnear_func\n" } } */ +/* { dg-final { scan-assembler "\t(jals?|balc)\tnormal_func\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/near-far-3.c b/gcc/testsuite/gcc.target/mips/near-far-3.c index 19e1b3a..d4ad3e7 100644 --- a/gcc/testsuite/gcc.target/mips/near-far-3.c +++ b/gcc/testsuite/gcc.target/mips/near-far-3.c @@ -13,8 +13,8 @@ NOMIPS16 int test3 () { return near_func (); } NOMIPS16 int test4 () { return normal_func (); } NOMIPS16 int test5 () { return short_call_func (); } -/* { dg-final { scan-assembler-not "\tj\tlong_call_func\n" } } */ -/* { dg-final { scan-assembler-not "\tj\tfar_func\n" } } */ -/* { dg-final { scan-assembler "\t(j(|al|als)|b(|al)c)\tnear_func\n" } } */ -/* { dg-final { scan-assembler-not "\tj\tnormal_func\n" } } */ -/* { dg-final { scan-assembler "\t(j(|al|als)|b(|al)c)\tshort_call_func\n" } } */ +/* { dg-final { scan-assembler-not "\t((j(|al|als))|b(|al)c)\tlong_call_func\n" } } */ +/* { dg-final { scan-assembler-not "\t((j(|al|als))|b(|al)c)\tfar_func\n" } } */ +/* { dg-final { scan-assembler "\t((j(|al|als))|b(|al)c)\tnear_func\n" } } */ +/* { dg-final { scan-assembler-not "\t((j(|al|als))|b(|al)c)\tnormal_func\n" } } */ +/* { dg-final { scan-assembler "\t((j(|al|als))|b(|al)c)\tshort_call_func\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/near-far-4.c b/gcc/testsuite/gcc.target/mips/near-far-4.c index ac7d727..37baad9 100644 --- a/gcc/testsuite/gcc.target/mips/near-far-4.c +++ b/gcc/testsuite/gcc.target/mips/near-far-4.c @@ -13,8 +13,8 @@ NOMIPS16 int test3 () { return near_func (); } NOMIPS16 int test4 () { return normal_func (); } NOMIPS16 int test5 () { return short_call_func (); } -/* { dg-final { scan-assembler-not "\tj\tlong_call_func\n" } } */ -/* { dg-final { scan-assembler-not "\tj\tfar_func\n" } } */ -/* { dg-final { scan-assembler "\t(j(|al|als)|b(|al)c)\tnear_func\n" } } */ -/* { dg-final { scan-assembler "\t(j(|al|als)|b(|al)c)\tnormal_func\n" } } */ -/* { dg-final { scan-assembler "\t(j(|al|als)|b(|al)c)\tshort_call_func\n" } } */ +/* { dg-final { scan-assembler-not "\t((j(|al|als))|b(|al)c)\tlong_call_func\n" } } */ +/* { dg-final { scan-assembler-not "\t((j(|al|als))|b(|al)c)\tfar_func\n" } } */ +/* { dg-final { scan-assembler "\t((j(|al|als))|b(|al)c)\tnear_func\n" } } */ +/* { dg-final { scan-assembler "\t((j(|al|als))|b(|al)c)\tnormal_func\n" } } */ +/* { dg-final { scan-assembler "\t((j(|al|als))|b(|al)c)\tshort_call_func\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/tls-1.c b/gcc/testsuite/gcc.target/mips/tls-1.c new file mode 100644 index 0000000..38f6a5e --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/tls-1.c @@ -0,0 +1,10 @@ +/* { dg-options "-mgp32" } */ + +extern __thread int x __attribute__ ((tls_model ("initial-exec"))); + +long long +foo (long long y) +{ + x = 0; + return y; +} diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_100.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_100.c new file mode 100644 index 0000000..e759a11 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_100.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_100 -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_100a.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_100a.c new file mode 100644 index 0000000..153ed1e --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_100a.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_100a -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_100f.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_100f.c new file mode 100644 index 0000000..9bb9127 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_100f.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_100f -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_101.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_101.c new file mode 100644 index 0000000..06b3ceb --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_101.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_101 -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_101a.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_101a.c new file mode 100644 index 0000000..0cca3f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_101a.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_101a -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_101f.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_101f.c new file mode 100644 index 0000000..9548be5 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_101f.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_101f -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_103.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_103.c new file mode 100644 index 0000000..5731249 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_103.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_103 -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_103a.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_103a.c new file mode 100644 index 0000000..aea501e --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_103a.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_103a -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_103f.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_103f.c new file mode 100644 index 0000000..59d8987 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_103f.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_103f -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_120.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_120.c new file mode 100644 index 0000000..d28a671 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_120.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_120 -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_120a.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_120a.c new file mode 100644 index 0000000..613dd65 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_120a.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_120a -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_120f.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_120f.c new file mode 100644 index 0000000..1b23350 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_120f.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_120f -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_121.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_121.c new file mode 100644 index 0000000..240332b --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_121.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_121 -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_121a.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_121a.c new file mode 100644 index 0000000..1e7fb70 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_121a.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_121a -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/nvptx/march-map=sm_121f.c b/gcc/testsuite/gcc.target/nvptx/march-map=sm_121f.c new file mode 100644 index 0000000..2cbec51 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/march-map=sm_121f.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options {-march-map=sm_121f -mptx=_} } */ +/* { dg-additional-options -save-temps } */ +/* { dg-final { scan-assembler-times {(?n)^ \.version 7\.8$} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)^ \.target sm_89$} 1 } } */ + +#if __PTX_ISA_VERSION_MAJOR__ != 7 +#error wrong value for __PTX_ISA_VERSION_MAJOR__ +#endif + +#if __PTX_ISA_VERSION_MINOR__ != 8 +#error wrong value for __PTX_ISA_VERSION_MINOR__ +#endif + +#if __PTX_SM__ != 890 +#error wrong value for __PTX_SM__ +#endif + +int dummy; diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c index 3ceae15..12d1e8b 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c @@ -21,7 +21,7 @@ int main() { /* Returns a vector with each element containing the parity of the low-order bit of each of the bytes in that element. Note results are always - returned in an unsinged type, per the ABI spec. */ + returned in an unsigned type, per the ABI spec. */ vsia = (vector int) {0x10101010, 0x10101011, 0x10101111, 0x10111111}; vsiexpt = (vector unsigned int){0x0, 0x1, 0x0, 0x1}; diff --git a/gcc/testsuite/gcc.target/riscv/add-synthesis-1.c b/gcc/testsuite/gcc.target/riscv/add-synthesis-1.c new file mode 100644 index 0000000..247096c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/add-synthesis-1.c @@ -0,0 +1,40 @@ +/* { dg-options "-march=rv32gcb -mabi=ilp32d" { target { rv32 } } } */ +/* { dg-options "-march=rv64gcb -mabi=lp64d" { target { rv64 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + + + +#if __riscv_xlen == 64 +#define TYPE long +#else +#define TYPE int +#endif + +#define T(C) TYPE foo_##C (TYPE x) { return x + C; } +#define TM(C) TYPE foo_M##C (TYPE x) { return x + -C; } + +/* These cases were selected because they all can be synthesized + at expansion time without synthesizing the constant directly. + + That makes the assembler scan testing simpler. I've verified + by hand that cases that should synthesize the constant do in + fact still generate code that way. */ +T (2050) +T (4094) +T (4100) +T (8200) + +TM (2049) +TM (4096) +TM (4100) +TM (8200) + +#if __riscv_xlen == 64 +TM (0x200000000) +#endif + +/* We have 4/5 tests which should use shNadd insns and 4 + which used paired addi insns. */ +/* { dg-final { scan-assembler-times "sh.add\t" 4 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "sh.add\t" 5 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "addi\t" 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/add-synthesis-2.c b/gcc/testsuite/gcc.target/riscv/add-synthesis-2.c new file mode 100644 index 0000000..a047615 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/add-synthesis-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target rv64 } } */ +/* { dg-options "-march=rv64gcb -mabi=lp64d" { target { rv64 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + + + +#define T(C) int foo_##C (int x) { return x + C; } +#define TM(C) int foo_M##C (int x) { return x + -C; } + +/* These cases were selected because they all can be synthesized + at expansion time without synthesizing the constant directly. + + That makes the assembler scan testing simpler. I've verified + by hand that cases that should synthesize the constant do in + fact still generate code that way. */ +T (2050) +T (4094) + +TM (2049) +TM (4096) + +/* We have 4/5 tests which should use shNadd insns and 4 + which used paired addi insns. */ +/* { dg-final { scan-assembler-times "addiw\t" 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo/pr121213.c b/gcc/testsuite/gcc.target/riscv/amo/pr121213.c new file mode 100644 index 0000000..3b2d694 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo/pr121213.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc -mabi=lp64" { target { rv64 } } } */ +/* { dg-options "-O2 -march=rv32gc -mabi=ilp32" { target { rv32 } } } */ + +void test0(unsigned long* lock) { + while (!__atomic_exchange_n(lock, 0, __ATOMIC_ACQUIRE)); +} + + +void test1(unsigned* lock) { + while (!__atomic_exchange_n(lock, 0, __ATOMIC_ACQUIRE)); +} + +/* { dg-final { scan-assembler-not "\tli" } } */ +/* { dg-final { scan-assembler-times "\tamoswap...aq\t\[axt\]\[0-9\],zero," 2 } } */ +/* { dg-final { scan-assembler-not "\tsext" { xfail *-*-* } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/arch-25.c b/gcc/testsuite/gcc.target/riscv/arch-25.c index 9201883..ca4d0ee 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-25.c +++ b/gcc/testsuite/gcc.target/riscv/arch-25.c @@ -1,5 +1,4 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64i_zcf -mabi=lp64" } */ int foo() {} -/* { dg-error "'-march=rv64i_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv64ic_zca_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64.*zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-ss-2.c b/gcc/testsuite/gcc.target/riscv/arch-ss-2.c index f1d7724..457063b 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-ss-2.c +++ b/gcc/testsuite/gcc.target/riscv/arch-ss-2.c @@ -3,13 +3,8 @@ int foo() { } -/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': ssnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': smnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': smmpm extension supports in rv64 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': sspm extension supports in rv64 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': supm extension supports in rv64 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': ssnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': smnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': smmpm extension supports in rv64 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': sspm extension supports in rv64 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': supm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32.\*ssnpm.*': ssnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32.\*smnpm.*': smnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32.\*smmpm.*': smmpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32.\*sspm.*': sspm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32.\*supm.*': supm extension supports in rv64 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-1.c b/gcc/testsuite/gcc.target/riscv/arch-unset-1.c new file mode 100644 index 0000000..971b936 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-unset-1.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i -march=unset -mcpu=sifive-x280 -mabi=lp64 -misa-spec=20191213" } */ +int foo() +{ +} + +/* { dg-final { scan-assembler "\.attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-2.c b/gcc/testsuite/gcc.target/riscv/arch-unset-2.c new file mode 100644 index 0000000..9840658 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-unset-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i -march=unset -mcpu=sifive-x280 -march=rv64i -mabi=lp64 -misa-spec=20191213" } */ +int foo() +{ +} + +/* { dg-final { scan-assembler "\.attribute arch, \"rv64i2p1\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-3.c b/gcc/testsuite/gcc.target/riscv/arch-unset-3.c new file mode 100644 index 0000000..5ddc224 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-unset-3.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i -march=unset -mcpu=sifive-x280 -march=rv64i -march=unset -mabi=lp64 -misa-spec=20191213" } */ +int foo() +{ +} + +/* { dg-final { scan-assembler "\.attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-4.c b/gcc/testsuite/gcc.target/riscv/arch-unset-4.c new file mode 100644 index 0000000..c16821d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-unset-4.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i -march=unset -mcpu=sifive-x280 -march=unset -march=rv64i -march=unset -march=rv64i -mabi=lp64 -misa-spec=20191213" } */ +int foo() +{ +} + +/* { dg-final { scan-assembler "\.attribute arch, \"rv64i2p1\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-5.c b/gcc/testsuite/gcc.target/riscv/arch-unset-5.c new file mode 100644 index 0000000..368c129 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-unset-5.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i -march=unset -mabi=lp64 -misa-spec=20191213" } */ +int foo() +{ +} + +/* { dg-error "At least one valid -mcpu option must be given after -march=unset" "" { target { "riscv*-*-*" } } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c b/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c index 5d6185d..585395e 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c +++ b/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c @@ -3,5 +3,4 @@ int foo() { } -/* { dg-error "'-march=rv64gc_zilsd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv64imafdc_zicsr_zifencei_zilsd_zmmul_zaamo_zalrsc_zca_zcd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64g.*zilsd.*': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-zilsd-3.c b/gcc/testsuite/gcc.target/riscv/arch-zilsd-3.c index 3cda120..3328599 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-zilsd-3.c +++ b/gcc/testsuite/gcc.target/riscv/arch-zilsd-3.c @@ -3,7 +3,5 @@ int foo() { } -/* { dg-error "'-march=rv64gc_zclsd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv64gc_zclsd': zclsd extension supports in rv32 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv64imafdc_zicsr_zifencei_zilsd_zmmul_zaamo_zalrsc_zca_zcd_zclsd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv64imafdc_zicsr_zifencei_zilsd_zmmul_zaamo_zalrsc_zca_zcd_zclsd': zclsd extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64.*zclsd.*': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64.*zclsd.*': zclsd extension supports in rv32 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c index bb9e310..c96d0b5 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c @@ -4,7 +4,7 @@ /* XuanTie C908v => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_ zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_sstc_svinval_svnapot_svpbmt_xtheadba_ xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_ -xtheadmemidx_xtheadmempair_xtheadsync_xtheadvdot */ +xtheadmemidx_xtheadmempair_xtheadsync */ #if !((__riscv_xlen == 64) \ && !defined(__riscv_32e) \ @@ -39,8 +39,7 @@ xtheadmemidx_xtheadmempair_xtheadsync_xtheadvdot */ && defined(__riscv_xtheadmac) \ && defined(__riscv_xtheadmemidx) \ && defined(__riscv_xtheadmempair) \ - && defined(__riscv_xtheadsync) \ - && defined (__riscv__xtheadvdot)) + && defined(__riscv_xtheadsync)) #error "unexpected arch" #endif diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c index 1f21d07..806949e 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ /* { dg-options "-mcpu=xt-c920v2" { target { rv64 } } } */ -/* XuanTie C920v2 => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_zbs_zvfbfmin_zvfbfwma_zvfh_sscofpmf_sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadsync_xtheadvdot */ +/* XuanTie C920v2 => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_zbs_zvfbfmin_zvfbfwma_zvfh_sscofpmf_sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadsync */ #if !((__riscv_xlen == 64) \ && !defined(__riscv_32e) \ @@ -45,8 +45,7 @@ && defined(__riscv_xtheadcmo) \ && defined(__riscv_xtheadcondmov) \ && defined(__riscv_xtheadfmemidx) \ - && defined(__riscv_xtheadsync) \ - && defined(__riscv_xtheadvdot)) + && defined(__riscv_xtheadsync)) #error "unexpected arch" #endif diff --git a/gcc/testsuite/gcc.target/riscv/mipsprefetch.c b/gcc/testsuite/gcc.target/riscv/mipsprefetch.c new file mode 100644 index 0000000..b58aa0f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mipsprefetch.c @@ -0,0 +1,31 @@ +/* pic used here to prevent the assembler to emit .nopic directive. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv32imafd_xmipscbop -fpic" { target { rv32 } } } */ +/* { dg-options "-march=rv64imafd_xmipscbop -fpic -mabi=lp64d" { target { rv64 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + + +void prefetch_read(char *a) +{ + __builtin_prefetch (&a[3], 0, 0); +} + +void prefetch_write(char *a) +{ + __builtin_prefetch (&a[1], 1, 0); +} + +void prefetch_read_out_range_offset(char *a) +{ + __builtin_prefetch (&a[512], 0, 1); +} + +void prefetch_write_out_range_offset(char *a) +{ + __builtin_prefetch (&a[1024], 1, 1); +} + +/* { dg-final { scan-assembler-times "mips.pref\t8,0\\(\[a-x0-9\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "mips.pref\t8,3\\(\[a-x0-9\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "nop" 2 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/nozicond-2.c b/gcc/testsuite/gcc.target/riscv/nozicond-2.c index f705253..588d41a 100644 --- a/gcc/testsuite/gcc.target/riscv/nozicond-2.c +++ b/gcc/testsuite/gcc.target/riscv/nozicond-2.c @@ -9,7 +9,7 @@ long foo2 (long c) { return c >= 0 ? -1 : 1; } /* We don't support 4->3 splitters, so this fails. We could perhaps try to catch it in the expander as a special case rather than waiting for combine. */ -/* { dg-final { scan-assembler-times {srai\t} 2 { xfail *-*-* } } } */ -/* { dg-final { scan-assembler-times {ori\t} 2 { xfail *-*-* } } } */ -/* { dg-final { scan-assembler-times {not\t} 2 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {srai\t} 2 } } */ +/* { dg-final { scan-assembler-times {ori\t} 2 } } */ +/* { dg-final { scan-assembler-times {not\t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr116085.c b/gcc/testsuite/gcc.target/riscv/pr116085.c index 998d82bd..880f835 100644 --- a/gcc/testsuite/gcc.target/riscv/pr116085.c +++ b/gcc/testsuite/gcc.target/riscv/pr116085.c @@ -1,5 +1,4 @@ -/* { dg-do run } */ -/* { dg-require-effective-target rv64 } */ +/* { dg-do run { target { rv64 && riscv_b_ok } } } */ /* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-ext-dce" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/riscv/pr117690.c b/gcc/testsuite/gcc.target/riscv/pr117690.c index 9c06ab4..d0784a1 100644 --- a/gcc/testsuite/gcc.target/riscv/pr117690.c +++ b/gcc/testsuite/gcc.target/riscv/pr117690.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv64*-*-* } } } */ +/* { dg-do run { target { rv64 && riscv_b_ok } } } */ /* { dg-options "-march=rv64gc_zba_zbb -mabi=lp64d" } */ #define myconst 0x4fffaffb0fffefffUL; diff --git a/gcc/testsuite/gcc.target/riscv/pr119275.c b/gcc/testsuite/gcc.target/riscv/pr119275.c new file mode 100644 index 0000000..02a1a7b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr119275.c @@ -0,0 +1,26 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-march=rv64gv -mabi=lp64d -mrvv-vector-bits=zvl" { target { rv64 } } } */ + +__int128 h, j; +int y; +double d; +void *p; +char *q; +char x; +long u; + +char *bar(int, int); + +typedef __attribute__((__vector_size__ (2))) char V; + +void +foo(V v) +{ + x += *bar (0, 0); + for(;;) { + __builtin_strcat (p, 7 + q); + d += __builtin_stdc_rotate_left ( + (unsigned __int128) u | h << *__builtin_strcat (p, 7 + q), j); + u += (long) __builtin_memmove (&y, &v, 2); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/pr120333.c b/gcc/testsuite/gcc.target/riscv/pr120333.c index 17b376f..3417d22 100644 --- a/gcc/testsuite/gcc.target/riscv/pr120333.c +++ b/gcc/testsuite/gcc.target/riscv/pr120333.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { rv64 } } } */ +/* { dg-do run { target { rv64 && riscv_b_ok } } } */ /* { dg-additional-options "-march=rv64gcb -std=gnu23" } */ __attribute__ ((noipa)) _Bool diff --git a/gcc/testsuite/gcc.target/riscv/pr120553-1.c b/gcc/testsuite/gcc.target/riscv/pr120553-1.c new file mode 100644 index 0000000..95ff1d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120553-1.c @@ -0,0 +1,90 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb_zicond -mbranch-cost=3 -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb_zicond -mbranch-cost=3 -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define ONE 1U +#define TYPE int +#else +#define ONE 1ULL +#define TYPE long +#endif + +#define T1(N) TYPE test1_##N (TYPE c) { return c < 0 ? -ONE : (ONE << N); } \ + TYPE test2_##N (TYPE c) { return c >= 0 ? (ONE << N) : -ONE; } \ + +T1(0) +T1(1) +T1(2) +T1(3) +T1(4) +T1(5) +T1(6) +T1(7) +T1(8) +T1(9) +T1(10) +T1(11) +T1(12) +T1(13) +T1(14) +T1(15) +T1(16) +T1(17) +T1(18) +T1(19) +T1(20) +T1(21) +T1(22) +T1(23) +T1(24) +T1(25) +T1(26) +T1(27) +T1(28) +T1(29) +T1(30) +T1(31) +#if __riscv_xlen == 64 +T1(32) +T1(33) +T1(34) +T1(35) +T1(36) +T1(37) +T1(38) +T1(39) +T1(40) +T1(41) +T1(42) +T1(43) +T1(44) +T1(45) +T1(46) +T1(47) +T1(48) +T1(49) +T1(50) +T1(51) +T1(52) +T1(53) +T1(54) +T1(55) +T1(56) +T1(57) +T1(58) +T1(59) +T1(60) +T1(61) +T1(62) +T1(63) +#endif + +/* { dg-final { scan-assembler-times "\\t(srai)" 128 { target rv64 } } } */ +/* { dg-final { scan-assembler-times "\\t(ori|bset)" 128 { target rv64 } } } */ + +/* { dg-final { scan-assembler-times "\\t(srai)" 64 { target rv32 } } } */ +/* { dg-final { scan-assembler-times "\\t(ori|bset)" 64 { target rv32 } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/pr120553-2.c b/gcc/testsuite/gcc.target/riscv/pr120553-2.c new file mode 100644 index 0000000..1501f86 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120553-2.c @@ -0,0 +1,90 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb_zicond -mbranch-cost=3 -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb_zicond -mbranch-cost=3 -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define ONE 1U +#define TYPE int +#else +#define ONE 1ULL +#define TYPE long +#endif + +#define T1(N) TYPE test1_##N (TYPE c) { return c >= 0 ? -ONE : (ONE << N); } \ + TYPE test2_##N (TYPE c) { return c < 0 ? (ONE << N) : -ONE; } \ + +T1(0) +T1(1) +T1(2) +T1(3) +T1(4) +T1(5) +T1(6) +T1(7) +T1(8) +T1(9) +T1(10) +T1(11) +T1(12) +T1(13) +T1(14) +T1(15) +T1(16) +T1(17) +T1(18) +T1(19) +T1(20) +T1(21) +T1(22) +T1(23) +T1(24) +T1(25) +T1(26) +T1(27) +T1(28) +T1(29) +T1(30) +T1(31) +#if __riscv_xlen == 64 +T1(32) +T1(33) +T1(34) +T1(35) +T1(36) +T1(37) +T1(38) +T1(39) +T1(40) +T1(41) +T1(42) +T1(43) +T1(44) +T1(45) +T1(46) +T1(47) +T1(48) +T1(49) +T1(50) +T1(51) +T1(52) +T1(53) +T1(54) +T1(55) +T1(56) +T1(57) +T1(58) +T1(59) +T1(60) +T1(61) +T1(62) +T1(63) +#endif + +/* { dg-final { scan-assembler-times "\\t(srai)" 128 { target rv64 } } } */ +/* { dg-final { scan-assembler-times "\\t(orn|ori|bset)" 128 { target rv64 } } } */ + +/* { dg-final { scan-assembler-times "\\t(srai)" 64 { target rv32 } } } */ +/* { dg-final { scan-assembler-times "\\t(orn|ori|bset)" 64 { target rv32 } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/pr120553-3.c b/gcc/testsuite/gcc.target/riscv/pr120553-3.c new file mode 100644 index 0000000..09ec714 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120553-3.c @@ -0,0 +1,90 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb_zicond -mbranch-cost=3 -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb_zicond -mbranch-cost=3 -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define ONE 1U +#define TYPE int +#else +#define ONE 1ULL +#define TYPE long +#endif + +#define T1(N) TYPE test1_##N (TYPE c) { return c < 0 ? -ONE : 0xff; } \ + TYPE test2_##N (TYPE c) { return c >= 0 ? 0xff : -ONE; } \ + +T1(0) +T1(1) +T1(2) +T1(3) +T1(4) +T1(5) +T1(6) +T1(7) +T1(8) +T1(9) +T1(10) +T1(11) +T1(12) +T1(13) +T1(14) +T1(15) +T1(16) +T1(17) +T1(18) +T1(19) +T1(20) +T1(21) +T1(22) +T1(23) +T1(24) +T1(25) +T1(26) +T1(27) +T1(28) +T1(29) +T1(30) +T1(31) +#if __riscv_xlen == 64 +T1(32) +T1(33) +T1(34) +T1(35) +T1(36) +T1(37) +T1(38) +T1(39) +T1(40) +T1(41) +T1(42) +T1(43) +T1(44) +T1(45) +T1(46) +T1(47) +T1(48) +T1(49) +T1(50) +T1(51) +T1(52) +T1(53) +T1(54) +T1(55) +T1(56) +T1(57) +T1(58) +T1(59) +T1(60) +T1(61) +T1(62) +T1(63) +#endif + +/* { dg-final { scan-assembler-times "\\t(srai)" 128 { target rv64 } } } */ +/* { dg-final { scan-assembler-times "\\t(ori|bset)" 128 { target rv64 } } } */ + +/* { dg-final { scan-assembler-times "\\t(srai)" 64 { target rv32 } } } */ +/* { dg-final { scan-assembler-times "\\t(ori|bset)" 64 { target rv32 } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/pr120553-4.c b/gcc/testsuite/gcc.target/riscv/pr120553-4.c new file mode 100644 index 0000000..bc8c1b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120553-4.c @@ -0,0 +1,90 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb_zicond -mbranch-cost=3 -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb_zicond -mbranch-cost=3 -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define ONE 1U +#define TYPE int +#else +#define ONE 1ULL +#define TYPE long +#endif + +#define T1(N) TYPE test1_##N (TYPE c) { return c < 0 ? -ONE : 0x7ff; } \ + TYPE test2_##N (TYPE c) { return c >= 0 ? 0x7ff : -ONE; } \ + +T1(0) +T1(1) +T1(2) +T1(3) +T1(4) +T1(5) +T1(6) +T1(7) +T1(8) +T1(9) +T1(10) +T1(11) +T1(12) +T1(13) +T1(14) +T1(15) +T1(16) +T1(17) +T1(18) +T1(19) +T1(20) +T1(21) +T1(22) +T1(23) +T1(24) +T1(25) +T1(26) +T1(27) +T1(28) +T1(29) +T1(30) +T1(31) +#if __riscv_xlen == 64 +T1(32) +T1(33) +T1(34) +T1(35) +T1(36) +T1(37) +T1(38) +T1(39) +T1(40) +T1(41) +T1(42) +T1(43) +T1(44) +T1(45) +T1(46) +T1(47) +T1(48) +T1(49) +T1(50) +T1(51) +T1(52) +T1(53) +T1(54) +T1(55) +T1(56) +T1(57) +T1(58) +T1(59) +T1(60) +T1(61) +T1(62) +T1(63) +#endif + +/* { dg-final { scan-assembler-times "\\t(srai)" 128 { target rv64 } } } */ +/* { dg-final { scan-assembler-times "\\t(ori|bset)" 128 { target rv64 } } } */ + +/* { dg-final { scan-assembler-times "\\t(srai)" 64 { target rv32 } } } */ +/* { dg-final { scan-assembler-times "\\t(ori|bset)" 64 { target rv32 } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/pr120553-5.c b/gcc/testsuite/gcc.target/riscv/pr120553-5.c new file mode 100644 index 0000000..1e48330 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120553-5.c @@ -0,0 +1,91 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb_zicond -mbranch-cost=3 -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb_zicond -mbranch-cost=3 -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define ONE 1U +#define TYPE int +#else +#define ONE 1ULL +#define TYPE long +#endif + +#define T1(N) TYPE test1_##N (TYPE c) { return c < 0 ? ~(ONE << N) : 0; } \ + TYPE test2_##N (TYPE c) { return c >= 0 ? 0 : ~(ONE << N); } \ + +T1(0) +T1(1) +T1(2) +T1(3) +T1(4) +T1(5) +T1(6) +T1(7) +T1(8) +T1(9) +T1(10) +T1(11) +T1(12) +T1(13) +T1(14) +T1(15) +T1(16) +T1(17) +T1(18) +T1(19) +T1(20) +T1(21) +T1(22) +T1(23) +T1(24) +T1(25) +T1(26) +T1(27) +T1(28) +T1(29) +T1(30) +T1(31) +#if __riscv_xlen == 64 +T1(32) +T1(33) +T1(34) +T1(35) +T1(36) +T1(37) +T1(38) +T1(39) +T1(40) +T1(41) +T1(42) +T1(43) +T1(44) +T1(45) +T1(46) +T1(47) +T1(48) +T1(49) +T1(50) +T1(51) +T1(52) +T1(53) +T1(54) +T1(55) +T1(56) +T1(57) +T1(58) +T1(59) +T1(60) +T1(61) +T1(62) +T1(63) +#endif + +/* The MSB case isn't handled the way we want. */ +/* { dg-final { scan-assembler-times "\\t(srai)" 126 { target rv64 } } } */ +/* { dg-final { scan-assembler-times "\\t(slli|andi|bclr)" 126 { target rv64 } } } */ + +/* { dg-final { scan-assembler-times "\\t(srai)" 62 { target rv32 } } } */ +/* { dg-final { scan-assembler-times "\\t(slli|andi|bclr)" 62 { target rv32 } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/pr120553-6.c b/gcc/testsuite/gcc.target/riscv/pr120553-6.c new file mode 100644 index 0000000..6c409af --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120553-6.c @@ -0,0 +1,91 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb_zicond -mbranch-cost=3 -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb_zicond -mbranch-cost=3 -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define ONE 1U +#define TYPE int +#else +#define ONE 1ULL +#define TYPE long +#endif + +#define T1(N) TYPE test1_##N (TYPE c) { return c >= 0 ? ~(ONE << N) : 0; } \ + TYPE test2_##N (TYPE c) { return c < 0 ? 0 : ~(ONE << N); } \ + +T1(0) +T1(1) +T1(2) +T1(3) +T1(4) +T1(5) +T1(6) +T1(7) +T1(8) +T1(9) +T1(10) +T1(11) +T1(12) +T1(13) +T1(14) +T1(15) +T1(16) +T1(17) +T1(18) +T1(19) +T1(20) +T1(21) +T1(22) +T1(23) +T1(24) +T1(25) +T1(26) +T1(27) +T1(28) +T1(29) +T1(30) +T1(31) +#if __riscv_xlen == 64 +T1(32) +T1(33) +T1(34) +T1(35) +T1(36) +T1(37) +T1(38) +T1(39) +T1(40) +T1(41) +T1(42) +T1(43) +T1(44) +T1(45) +T1(46) +T1(47) +T1(48) +T1(49) +T1(50) +T1(51) +T1(52) +T1(53) +T1(54) +T1(55) +T1(56) +T1(57) +T1(58) +T1(59) +T1(60) +T1(61) +T1(62) +T1(63) +#endif + +/* Not working for the high bit case yet. */ +/* { dg-final { scan-assembler-times "\\t(srai)" 126 { target rv64 } } } */ +/* { dg-final { scan-assembler-times "\\t(andn|andi|bclr)" 126 { target rv64 } } } */ + +/* { dg-final { scan-assembler-times "\\t(srai)" 62 { target rv32 } } } */ +/* { dg-final { scan-assembler-times "\\t(andn|andi|bclr)" 62 { target rv32 } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/pr120553-7.c b/gcc/testsuite/gcc.target/riscv/pr120553-7.c new file mode 100644 index 0000000..27953f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120553-7.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb_zicond -mbranch-cost=3 -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb_zicond -mbranch-cost=3 -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define TYPE int +#else +#define TYPE long +#endif + +#define T1(N) TYPE test1_##N (TYPE c) { return c < 0 ? ~0xff : 0; } \ + TYPE test2_##N (TYPE c) { return c >= 0 ? 0 : ~0xff; } \ + +T1(0) + +/* { dg-final { scan-assembler-times "\\t(srai)" 2 } } */ +/* { dg-final { scan-assembler-times "\\t(slli|andi|bclr)" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr120553-8.c b/gcc/testsuite/gcc.target/riscv/pr120553-8.c new file mode 100644 index 0000000..90bec45 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120553-8.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb_zicond -mbranch-cost=3 -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb_zicond -mbranch-cost=3 -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define TYPE int +#else +#define TYPE long +#endif + +#define T1(N) TYPE test1_##N (TYPE c) { return c < 0 ? ~0x7ff : 0; } \ + TYPE test2_##N (TYPE c) { return c >= 0 ? 0 : ~0x7ff; } \ + +T1(0) + +/* { dg-final { scan-assembler-times "\\t(srai)" 2 } } */ +/* { dg-final { scan-assembler-times "\\t(slli|andi|bclr)" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr121113.c b/gcc/testsuite/gcc.target/riscv/pr121113.c new file mode 100644 index 0000000..091fa82 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr121113.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c23 -mcpu=xiangshan-kunminghu" } */ + +_Float16 f, g; +void foo() { f /= g; } diff --git a/gcc/testsuite/gcc.target/riscv/pr121160.c b/gcc/testsuite/gcc.target/riscv/pr121160.c new file mode 100644 index 0000000..93cca8a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr121160.c @@ -0,0 +1,60 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -ffast-math -O2" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32d -ffast-math -O2" { target { rv32 } } } */ + + +typedef long int ssize_t; +typedef float MagickRealType; +typedef unsigned short Quantum; +typedef unsigned long long MagickSizeType; +typedef struct _PixelPacket +{ + Quantum blue, green, red, opacity; +} PixelPacket; +static inline Quantum +ClampToQuantum (const MagickRealType value) +{ + if (value <= 0.0f) + return ((Quantum) 0); + if (value >= (MagickRealType) ((Quantum) 65535)) + return (((Quantum) 65535)); + return ((Quantum) (value + 0.5f)); +} + +static inline float +HalfToSinglePrecision (const unsigned short half) +{ + typedef union _SinglePrecision + { + unsigned int fixed_point; + float single_precision; + } SinglePrecision; + register unsigned int exponent, significand, sign_bit; + SinglePrecision map; + unsigned int value; + if (significand == 0) + value = sign_bit << 31; + else + { + while ((significand & 0x00000400) == 0) + { + significand <<= 1; + } + value = (sign_bit << 31) | (exponent << 23) | (significand << 13); + } + map.fixed_point = value; + return (map.single_precision); +} + +void +ImportBlueQuantum (const MagickSizeType number_pixels, + PixelPacket *restrict q) +{ + register ssize_t x; + unsigned short pixel; + { + for (x = 0; x < (ssize_t) number_pixels; x++) + q->blue = ClampToQuantum (HalfToSinglePrecision (pixel)); + } +} + diff --git a/gcc/testsuite/gcc.target/riscv/pr121531.c b/gcc/testsuite/gcc.target/riscv/pr121531.c new file mode 100644 index 0000000..32c6957 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr121531.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-mcpu=sifive-p670" } */ + +__attribute__((__vector_size__(sizeof(int)))) int v; +void foo() { v &= 1; } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c index fab8e79..ca0ea0b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c @@ -5,7 +5,7 @@ /* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */ /* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */ -/* { dg-final { scan-assembler-times {\tvfadd\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfadd\.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvfadd\.vv} 9 } } */ +/* { dg-final { scan-assembler-not {\tvfadd\.vf} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 9 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c index 80bdb68..c839ac7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c @@ -5,7 +5,7 @@ /* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */ /* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */ -/* { dg-final { scan-assembler-times {\tvfadd\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfadd\.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvfadd\.vv} 9 } } */ +/* { dg-final { scan-assembler-not {\tvfadd\.vf} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 9 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c index 7197bf2..70f2651 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c @@ -4,6 +4,6 @@ #include "vmul-template.h" /* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */ -/* { dg-final { scan-assembler-times {\tvfmul\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfmul\.vf} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfmul\.vv} 6 } } */ +/* { dg-final { scan-assembler-not {\tvfmul\.vf} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 6 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c index a9c7f9b..01eb7e7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c @@ -4,6 +4,6 @@ #include "vmul-template.h" /* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */ -/* { dg-final { scan-assembler-times {\tvfmul\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfmul\.vf} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfmul\.vv} 6 } } */ +/* { dg-final { scan-assembler-not {\tvfmul\.vf} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 6 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c index 28b9235..c57ac80 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c @@ -6,9 +6,9 @@ /* { dg-final { scan-assembler-times {\tvsub\.vv} 16 } } */ /* { dg-final { scan-assembler-times {\tvrsub\.vi} 16 } } */ -/* { dg-final { scan-assembler-times {\tvfsub\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfsub\.vf} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfrsub\.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvfsub\.vv} 12 } } */ +/* { dg-final { scan-assembler-not {\tvfsub\.vf} } } */ +/* { dg-final { scan-assembler-not {\tvfrsub\.vf} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 12 "optimized" } } */ /* Do not expect vfrsub for now, because we do not properly diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c index b048949..a79d727 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c @@ -6,9 +6,9 @@ /* { dg-final { scan-assembler-times {\tvsub\.vv} 16 } } */ /* { dg-final { scan-assembler-times {\tvrsub\.vi} 16 } } */ -/* { dg-final { scan-assembler-times {\tvfsub\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfsub\.vf} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfrsub\.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvfsub\.vv} 12 } } */ +/* { dg-final { scan-assembler-not {\tvfsub\.vf} } } */ +/* { dg-final { scan-assembler-not {\tvfrsub\.vf} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 12 "optimized" } } */ /* Do not expect vfrsub for now, because we do not properly diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c index b9cfc23..850679e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c @@ -3,13 +3,13 @@ #include "cond_copysign-template.h" -/* { dg-final { scan-assembler-times {\tvfsgnj\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfsgnj\.vf} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfsgnj\.vv} 6 } } */ +/* { dg-final { scan-assembler-not {\tvfsgnj\.vf} } } */ /* 1. The vectorizer wraps scalar variants of copysign into vector constants which expand cannot handle currently. 2. match.pd convert .COPYSIGN (1, b) + COND_MUL to AND + XOR currently. */ /* { dg-final { scan-assembler-times {\tvfsgnjx\.vv} 6 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfsgnjn\.vf} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 6 } } */ +/* { dg-final { scan-assembler-not {\tvfsgnjn\.vf} } } */ /* { dg-final { scan-assembler-not {\tvmerge\.vvm} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c index f9f63eb..84c6c45 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c @@ -3,13 +3,13 @@ #include "cond_copysign-template.h" -/* { dg-final { scan-assembler-times {\tvfsgnj\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfsgnj\.vf} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfsgnj\.vv} 6 } } */ +/* { dg-final { scan-assembler-not {\tvfsgnj\.vf} } } */ /* 1. The vectorizer wraps scalar variants of copysign into vector constants which expand cannot handle currently. 2. match.pd convert .COPYSIGN (1, b) + COND_MUL to AND + XOR currently. */ /* { dg-final { scan-assembler-times {\tvfsgnjx\.vv} 6 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfsgnjn\.vf} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 6 } } */ +/* { dg-final { scan-assembler-not {\tvfsgnjn\.vf} } } */ /* { dg-final { scan-assembler-not {\tvmerge\.vvm} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c index 1aac306..02dc6b8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 18 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */ +/* { dg-final { scan-assembler-not {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c index 947e43c..7adedf9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c @@ -28,6 +28,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 12 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 12 } } */ +/* { dg-final { scan-assembler-not {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c index 8a8d7d0..d414f21 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 18 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */ +/* { dg-final { scan-assembler-not {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c index e282d2c..97d7415 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 18 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */ +/* { dg-final { scan-assembler-not {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c index ef8631d..faee13b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c @@ -29,11 +29,11 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vmadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vmadd\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vnmsub\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmadd\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vmadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vmadd\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vnmsub\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vfmadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmadd\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* { dg-final { scan-assembler-times {vfnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c index e3aaba2..1ea22fa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c @@ -29,11 +29,11 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* { dg-final { scan-assembler-times {vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c index f91bec1..a487023 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c @@ -29,11 +29,11 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* { dg-final { scan-assembler-times {vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c index 381d405..3f2689f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c @@ -28,12 +28,12 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* { dg-final { scan-assembler-times {vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ /* NOTE: 14 vmerge is need for other purpose. */ /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c index cb878167..da20ad8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c @@ -29,12 +29,12 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* { dg-final { scan-assembler-times {vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ /* NOTE: 14 vmerge is need for other purpose. */ /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c index 95368ad..d34c190 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c index c07b331..b9db723 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c index a01ba8d..473689c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c index 9aabfb5..e41af42 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c index a050d04..720eb16 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c @@ -28,6 +28,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c index d251430..684d3aa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c @@ -28,6 +28,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c index 790ba2d..727b3e3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c @@ -28,6 +28,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c index 684ae87..e62d9c5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c @@ -28,6 +28,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c index 116131b..b693f0c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax-1.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c index 6ac47cb..f504fb1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax-2.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c index 2d445a9..d20c833 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax-3.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c index ae64206..be4dc33 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax-4.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c index ad4dd9d..530fe00 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh-1.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c index f7fbf22..4ee5c65 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh-2.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c index 7af181f..c44a462 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh-3.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c index 22ff91b..693d63d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh-4.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c index 1e367b3..82a9ea2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c @@ -26,6 +26,6 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {vfmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmsub\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmsub\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c index 3af559d..eadeeb8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c @@ -26,6 +26,6 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c index e777c8c..f00d5f6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c @@ -26,7 +26,7 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* NOTE: 3 vmerge is need for other purpose. */ /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c index e777c8c..f00d5f6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c @@ -26,7 +26,7 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* NOTE: 3 vmerge is need for other purpose. */ /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c index 46f2b5f..6303f41 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c @@ -26,7 +26,7 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* NOTE: 3 vmerge is need for other purpose. */ /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c index 0f85dfc..1447f40 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c @@ -26,6 +26,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 9 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ +/* { dg-final { scan-assembler-not {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c index 6cdb2c4..6bc03a0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c @@ -25,6 +25,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 6 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-not {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c index 5a921cb..c1c2d4e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c @@ -26,6 +26,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 9 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ +/* { dg-final { scan-assembler-not {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c index 939e6bd..e9edd23 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c @@ -26,6 +26,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 9 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ +/* { dg-final { scan-assembler-not {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c index 608fbef..ccfb651 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c @@ -25,6 +25,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 9 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ +/* { dg-final { scan-assembler-not {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121334.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121334.c new file mode 100644 index 0000000..a2ded48 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121334.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 -fno-vect-cost-model" } */ + +char arr[64]; + +void init () +{ + for (int i = 8; i >= 0; i--) + arr[i] = i; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121742.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121742.c new file mode 100644 index 0000000..08491f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121742.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ + +typedef unsigned long uint64_t; +typedef unsigned int uint32_t; +typedef unsigned char uint8_t; +typedef uint8_t a __attribute__((vector_size(4))); +int b, c; + +uint64_t d() { + a e = {5, 9, 1, 5}; + a bla = {0, 0, 0, 0}; + int *f = &b; + uint32_t g = 0; + int i = 0; + for (; i < 2; i++) + for (c = 0; c <= 2; c++) { + *f ^= e[3] + 9; + e = __builtin_shufflevector( + ~__builtin_shufflevector(bla, e, 1, 4, 3, 4), e, 0, 1, 1, 7); + } + return g; +} + +int main() { + int j = d (); + if (b != 0) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c index 101ad57..2953d18 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c @@ -39,5 +39,5 @@ DEF_MINMAX_VX (min, 128, double, <) DEF_MINMAX_VX (min, 256, double, <) DEF_MINMAX_VX (min, 512, double, <) -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c index 004a95c..db156ac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c @@ -39,5 +39,5 @@ DEF_MINMAX_VX (min, 128, double, <=) DEF_MINMAX_VX (min, 256, double, <=) DEF_MINMAX_VX (min, 512, double, <=) -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c index 297f049..3af7e64 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c @@ -39,5 +39,5 @@ DEF_OP_VX (mul, 128, double, *) DEF_OP_VX (mul, 256, double, *) DEF_OP_VX (mul, 512, double, *) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c index f49bf28..f1d5944 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c @@ -39,5 +39,5 @@ DEF_OP_VI_15 (mul, 128, double, *) DEF_OP_VI_15 (mul, 256, double, *) DEF_OP_VI_15 (mul, 512, double, *) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c index bb62ce2..89af160 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c @@ -54,5 +54,5 @@ DEF_OP_V (nearbyint, 512, double, __builtin_nearbyint) /* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ /* { dg-final { scan-assembler-times {vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ /* { dg-final { scan-assembler-times {vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ -/* { dg-final { scan-assembler-times {frflags\s+[atx][0-9]+} 30 } } */ -/* { dg-final { scan-assembler-times {fsflags\s+[atx][0-9]+} 30 } } */ +/* { dg-final { scan-assembler-times {frflags\s+[atx][0-9]+} 32 } } */ +/* { dg-final { scan-assembler-times {fsflags\s+[atx][0-9]+} 32 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c index 811f26c..7e56330 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c @@ -2,6 +2,7 @@ /* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=0" } */ #include "vf_mulop.h" +#include "vf_binop.h" DEF_VF_MULOP_CASE_0 (_Float16, +, +, add) DEF_VF_MULOP_CASE_0 (_Float16, -, +, sub) @@ -15,6 +16,10 @@ DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, +, acc) DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, +, sac) DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, -, nacc) DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, -, nsac) +DEF_VF_BINOP_CASE_0 (_Float16, *, mul) +DEF_VF_BINOP_REVERSE_CASE_0 (_Float16, /, rdiv) +DEF_VF_BINOP_CASE_2_WRAP (_Float16, MIN_FUNC_0_WRAP (_Float16), min) +DEF_VF_BINOP_CASE_2_WRAP (_Float16, MIN_FUNC_1_WRAP (_Float16), min) /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ @@ -28,3 +33,5 @@ DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, -, nsac) /* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c index ca82ead..e674cf7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c @@ -2,6 +2,7 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ #include "vf_mulop.h" +#include "vf_binop.h" DEF_VF_MULOP_CASE_0 (float, +, +, add) DEF_VF_MULOP_CASE_0 (float, -, +, sub) @@ -15,6 +16,10 @@ DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, +, acc) DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, +, sac) DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, -, nacc) DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, -, nsac) +DEF_VF_BINOP_CASE_0 (float, *, mul) +DEF_VF_BINOP_REVERSE_CASE_0 (float, /, rdiv) +DEF_VF_BINOP_CASE_2_WRAP (float, MIN_FUNC_0_WRAP (float), min) +DEF_VF_BINOP_CASE_2_WRAP (float, MIN_FUNC_1_WRAP (float), min) /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ @@ -28,3 +33,6 @@ DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, -, nsac) /* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c index 4de038c..b36e966 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c @@ -2,6 +2,7 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ #include "vf_mulop.h" +#include "vf_binop.h" DEF_VF_MULOP_CASE_0 (double, +, +, add) DEF_VF_MULOP_CASE_0 (double, -, +, sub) @@ -11,6 +12,10 @@ DEF_VF_MULOP_ACC_CASE_0 (double, +, +, acc) DEF_VF_MULOP_ACC_CASE_0 (double, -, +, sac) DEF_VF_MULOP_ACC_CASE_0 (double, +, -, nacc) DEF_VF_MULOP_ACC_CASE_0 (double, -, -, nsac) +DEF_VF_BINOP_CASE_0 (double, *, mul) +DEF_VF_BINOP_REVERSE_CASE_0 (double, /, rdiv) +DEF_VF_BINOP_CASE_2_WRAP (double, MIN_FUNC_0_WRAP (double), min) +DEF_VF_BINOP_CASE_2_WRAP (double, MIN_FUNC_1_WRAP (double), min) /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ @@ -20,3 +25,6 @@ DEF_VF_MULOP_ACC_CASE_0 (double, -, -, nsac) /* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfnmacc.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c index 3a39303..1914b18 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c @@ -15,5 +15,7 @@ /* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfmul.vf} } } */ +/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */ +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ /* { dg-final { scan-assembler-times {fcvt.s.h} 4 } } */ -/* { dg-final { scan-assembler-times {vfmv.v.f} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c index b4618ba..f8dab37 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c @@ -15,5 +15,7 @@ /* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfmul.vf} } } */ +/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */ +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ /* { dg-final { scan-assembler-times {fcvt.d.s} 4 } } */ -/* { dg-final { scan-assembler-times {vfmv.v.f} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c index a2ac67e..909770f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c @@ -11,3 +11,6 @@ /* { dg-final { scan-assembler-not {vfmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfmul.vf} } } */ +/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */ +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c index 58afaa4..c703ed6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c @@ -2,11 +2,12 @@ /* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=0" } */ #include "vf_mulop.h" +#include "vf_binop.h" -DEF_VF_MULOP_CASE_1 (_Float16, +, +, add, VF_MULOP_BODY_X16) -DEF_VF_MULOP_CASE_1 (_Float16, -, +, sub, VF_MULOP_BODY_X16) -DEF_VF_MULOP_CASE_1 (_Float16, +, -, nadd, VF_MULOP_BODY_X16) -DEF_VF_MULOP_CASE_1 (_Float16, -, -, nsub, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (_Float16, +, +, add, VF_MULOP_BODY_X128) +DEF_VF_MULOP_CASE_1 (_Float16, -, +, sub, VF_MULOP_BODY_X128) +DEF_VF_MULOP_CASE_1 (_Float16, +, -, nadd, VF_MULOP_BODY_X128) +DEF_VF_MULOP_CASE_1 (_Float16, -, -, nsub, VF_MULOP_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, +, acc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, +, sac, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, -, nacc, VF_MULOP_ACC_BODY_X128) @@ -15,6 +16,12 @@ DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, +, acc) DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, +, sac) DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, -, nacc) DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, -, nsac) +DEF_VF_BINOP_CASE_1 (_Float16, *, mul, VF_BINOP_BODY_X128) +DEF_VF_BINOP_REVERSE_CASE_1 (_Float16, /, rdiv, VF_BINOP_REVERSE_BODY_X128) +DEF_VF_BINOP_CASE_3_WRAP (_Float16, MIN_FUNC_0_WRAP (_Float16), min, + VF_BINOP_FUNC_BODY_X128) +DEF_VF_BINOP_CASE_3_WRAP (_Float16, MIN_FUNC_1_WRAP (_Float16), min, + VF_BINOP_FUNC_BODY_X128) /* { dg-final { scan-assembler {vfmadd.vf} } } */ /* { dg-final { scan-assembler {vfmsub.vf} } } */ @@ -28,3 +35,6 @@ DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, -, nsac) /* { dg-final { scan-assembler {vfwmsac.vf} } } */ /* { dg-final { scan-assembler {vfwnmacc.vf} } } */ /* { dg-final { scan-assembler {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler {vfmul.vf} } } */ +/* { dg-final { scan-assembler {vfrdiv.vf} } } */ +/* { dg-final { scan-assembler {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c index 0e95774..99b84dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c @@ -2,11 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ #include "vf_mulop.h" +#include "vf_binop.h" -DEF_VF_MULOP_CASE_1 (float, +, +, add, VF_MULOP_BODY_X16) -DEF_VF_MULOP_CASE_1 (float, -, +, sub, VF_MULOP_BODY_X16) -DEF_VF_MULOP_CASE_1 (float, +, -, nadd, VF_MULOP_BODY_X16) -DEF_VF_MULOP_CASE_1 (float, -, -, nsub, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (float, +, +, add, VF_MULOP_BODY_X128) +DEF_VF_MULOP_CASE_1 (float, -, +, sub, VF_MULOP_BODY_X128) +DEF_VF_MULOP_CASE_1 (float, +, -, nadd, VF_MULOP_BODY_X128) +DEF_VF_MULOP_CASE_1 (float, -, -, nsub, VF_MULOP_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (float, +, +, acc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (float, -, +, sac, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (float, +, -, nacc, VF_MULOP_ACC_BODY_X128) @@ -15,6 +16,12 @@ DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, +, acc) DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, +, sac) DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, -, nacc) DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, -, nsac) +DEF_VF_BINOP_CASE_1 (float, *, mul, VF_BINOP_BODY_X128) +DEF_VF_BINOP_REVERSE_CASE_1 (float, /, rdiv, VF_BINOP_REVERSE_BODY_X128) +DEF_VF_BINOP_CASE_3_WRAP (float, MIN_FUNC_0_WRAP (float), min, + VF_BINOP_FUNC_BODY_X128) +DEF_VF_BINOP_CASE_3_WRAP (float, MIN_FUNC_1_WRAP (float), min, + VF_BINOP_FUNC_BODY_X128) /* { dg-final { scan-assembler {vfmadd.vf} } } */ /* { dg-final { scan-assembler {vfmsub.vf} } } */ @@ -28,3 +35,6 @@ DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, -, nsac) /* { dg-final { scan-assembler {vfwmsac.vf} } } */ /* { dg-final { scan-assembler {vfwnmacc.vf} } } */ /* { dg-final { scan-assembler {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler {vfmul.vf} } } */ +/* { dg-final { scan-assembler {vfrdiv.vf} } } */ +/* { dg-final { scan-assembler {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c index 71bd7e1..889fed2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c @@ -2,15 +2,22 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ #include "vf_mulop.h" +#include "vf_binop.h" -DEF_VF_MULOP_CASE_1 (double, +, +, add, VF_MULOP_BODY_X16) -DEF_VF_MULOP_CASE_1 (double, -, +, sub, VF_MULOP_BODY_X16) -DEF_VF_MULOP_CASE_1 (double, +, -, nadd, VF_MULOP_BODY_X16) -DEF_VF_MULOP_CASE_1 (double, -, -, nsub, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (double, +, +, add, VF_MULOP_BODY_X128) +DEF_VF_MULOP_CASE_1 (double, -, +, sub, VF_MULOP_BODY_X128) +DEF_VF_MULOP_CASE_1 (double, +, -, nadd, VF_MULOP_BODY_X128) +DEF_VF_MULOP_CASE_1 (double, -, -, nsub, VF_MULOP_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (double, +, +, acc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (double, -, +, sac, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (double, +, -, nacc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (double, -, -, nsac, VF_MULOP_ACC_BODY_X128) +DEF_VF_BINOP_CASE_1 (double, *, mul, VF_BINOP_BODY_X128) +DEF_VF_BINOP_REVERSE_CASE_1 (double, /, rdiv, VF_BINOP_REVERSE_BODY_X128) +DEF_VF_BINOP_CASE_3_WRAP (double, MIN_FUNC_0_WRAP (double), min, + VF_BINOP_FUNC_BODY_X128) +DEF_VF_BINOP_CASE_3_WRAP (double, MIN_FUNC_1_WRAP (double), min, + VF_BINOP_FUNC_BODY_X128) /* { dg-final { scan-assembler {vfmadd.vf} } } */ /* { dg-final { scan-assembler {vfmsub.vf} } } */ @@ -20,3 +27,6 @@ DEF_VF_MULOP_ACC_CASE_1 (double, -, -, nsac, VF_MULOP_ACC_BODY_X128) /* { dg-final { scan-assembler {vfmsac.vf} } } */ /* { dg-final { scan-assembler {vfnmacc.vf} } } */ /* { dg-final { scan-assembler {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler {vfmul.vf} } } */ +/* { dg-final { scan-assembler {vfrdiv.vf} } } */ +/* { dg-final { scan-assembler {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c index 559df6c..9db8736 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c @@ -15,4 +15,7 @@ /* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfmul.vf} } } */ +/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */ +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ /* { dg-final { scan-assembler {fcvt.s.h} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c index 03f9c5a..577ad8d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c @@ -15,4 +15,7 @@ /* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfmul.vf} } } */ +/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */ +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ /* { dg-final { scan-assembler {fcvt.d.s} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c index d71bdde..30e5660 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c @@ -11,3 +11,6 @@ /* { dg-final { scan-assembler-not {vfmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfmul.vf} } } */ +/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */ +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c new file mode 100644 index 0000000..1a20ee7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" + +DEF_VF_BINOP_CASE_2_WRAP (_Float16, __builtin_fminf16, min) + +/* { dg-final { scan-assembler-times {vfmin.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c new file mode 100644 index 0000000..1e0f7f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" + +DEF_VF_BINOP_CASE_2_WRAP (float, __builtin_fminf, min) + +/* { dg-final { scan-assembler-times {vfmin.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c new file mode 100644 index 0000000..61db2df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" + +DEF_VF_BINOP_CASE_2_WRAP (double, __builtin_fmin, min) + +/* { dg-final { scan-assembler-times {vfmin.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c new file mode 100644 index 0000000..392580a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=1" } */ + +#include "vf-5-f16.c" + +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c new file mode 100644 index 0000000..9dbd226 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=1" } */ + +#include "vf-5-f32.c" + +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c new file mode 100644 index 0000000..44a17cd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=1" } */ + +#include "vf-5-f64.c" + +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c new file mode 100644 index 0000000..0883c882 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" + +DEF_VF_BINOP_CASE_3_WRAP (_Float16, __builtin_fminf16, min, VF_BINOP_FUNC_BODY_X128) + +/* { dg-final { scan-assembler {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c new file mode 100644 index 0000000..8528240 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" + +DEF_VF_BINOP_CASE_3_WRAP (float, __builtin_fminf, min, VF_BINOP_FUNC_BODY_X128) + +/* { dg-final { scan-assembler {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c new file mode 100644 index 0000000..474b339 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" + +DEF_VF_BINOP_CASE_3_WRAP (double, __builtin_fmin, min, VF_BINOP_FUNC_BODY_X128) + +/* { dg-final { scan-assembler {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c new file mode 100644 index 0000000..bd68b3c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=4" } */ + +#include "vf-7-f16.c" + +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c new file mode 100644 index 0000000..000402c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=4" } */ + +#include "vf-7-f32.c" + +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c new file mode 100644 index 0000000..89dec81 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=4" } */ + +#include "vf-7-f64.c" + +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h new file mode 100644 index 0000000..90436a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h @@ -0,0 +1,206 @@ +#ifndef HAVE_DEFINED_VF_BINOP_H +#define HAVE_DEFINED_VF_BINOP_H + +#include <stdint.h> + +#define DEF_VF_BINOP_CASE_0(T, OP, NAME) \ + void test_vf_binop_##NAME##_##T##_case_0 (T *restrict out, T *restrict in, \ + T f, unsigned n) \ + { \ + for (unsigned i = 0; i < n; i++) \ + out[i] = in[i] OP f; \ + } +#define DEF_VF_BINOP_CASE_0_WRAP(T, OP, NAME) DEF_VF_BINOP_CASE_0 (T, OP, NAME) +#define RUN_VF_BINOP_CASE_0(T, NAME, out, in, f, n) \ + test_vf_binop_##NAME##_##T##_case_0 (out, in, f, n) +#define RUN_VF_BINOP_CASE_0_WRAP(T, NAME, out, in, f, n) \ + RUN_VF_BINOP_CASE_0 (T, NAME, out, in, f, n) + +#define DEF_VF_BINOP_REVERSE_CASE_0(T, OP, NAME) \ + void test_vf_binop_reverse_##NAME##_##T##_case_0 (T *restrict out, \ + T *restrict in, T f, \ + unsigned n) \ + { \ + for (unsigned i = 0; i < n; i++) \ + out[i] = f OP in[i]; \ + } +#define DEF_VF_BINOP_REVERSE_CASE_0_WRAP(T, OP, NAME) \ + DEF_VF_BINOP_REVERSE_CASE_0 (T, OP, NAME) +#define RUN_VF_BINOP_REVERSE_CASE_0(T, NAME, out, in, f, n) \ + test_vf_binop_reverse_##NAME##_##T##_case_0 (out, in, f, n) +#define RUN_VF_BINOP_REVERSE_CASE_0_WRAP(T, NAME, out, in, f, n) \ + RUN_VF_BINOP_REVERSE_CASE_0 (T, NAME, out, in, f, n) + +#define VF_BINOP_BODY(op) \ + out[k + 0] = in[k + 0] op tmp; \ + out[k + 1] = in[k + 1] op tmp; \ + k += 2; + +#define VF_BINOP_BODY_X4(op) \ + VF_BINOP_BODY (op) \ + VF_BINOP_BODY (op) + +#define VF_BINOP_BODY_X8(op) \ + VF_BINOP_BODY_X4 (op) \ + VF_BINOP_BODY_X4 (op) + +#define VF_BINOP_BODY_X16(op) \ + VF_BINOP_BODY_X8 (op) \ + VF_BINOP_BODY_X8 (op) + +#define VF_BINOP_BODY_X32(op) \ + VF_BINOP_BODY_X16 (op) \ + VF_BINOP_BODY_X16 (op) + +#define VF_BINOP_BODY_X64(op) \ + VF_BINOP_BODY_X32 (op) \ + VF_BINOP_BODY_X32 (op) + +#define VF_BINOP_BODY_X128(op) \ + VF_BINOP_BODY_X64 (op) \ + VF_BINOP_BODY_X64 (op) + +#define DEF_VF_BINOP_CASE_1(T, OP, NAME, BODY) \ + void test_vf_binop_##NAME##_##T##_case_1 (T *restrict out, T *restrict in, \ + T f, unsigned n) \ + { \ + unsigned k = 0; \ + T tmp = f + 3.45; \ + \ + while (k < n) \ + { \ + tmp = tmp * 0x3.fp2; \ + BODY (OP) \ + } \ + } +#define DEF_VF_BINOP_CASE_1_WRAP(T, OP, NAME, BODY) \ + DEF_VF_BINOP_CASE_1 (T, OP, NAME, BODY) + +#define VF_BINOP_REVERSE_BODY(op) \ + out[k + 0] = tmp op in[k + 0]; \ + out[k + 1] = tmp op in[k + 1]; \ + k += 2; + +#define VF_BINOP_REVERSE_BODY_X4(op) \ + VF_BINOP_REVERSE_BODY (op) \ + VF_BINOP_REVERSE_BODY (op) + +#define VF_BINOP_REVERSE_BODY_X8(op) \ + VF_BINOP_REVERSE_BODY_X4 (op) \ + VF_BINOP_REVERSE_BODY_X4 (op) + +#define VF_BINOP_REVERSE_BODY_X16(op) \ + VF_BINOP_REVERSE_BODY_X8 (op) \ + VF_BINOP_REVERSE_BODY_X8 (op) + +#define VF_BINOP_REVERSE_BODY_X32(op) \ + VF_BINOP_REVERSE_BODY_X16 (op) \ + VF_BINOP_REVERSE_BODY_X16 (op) + +#define VF_BINOP_REVERSE_BODY_X64(op) \ + VF_BINOP_REVERSE_BODY_X32 (op) \ + VF_BINOP_REVERSE_BODY_X32 (op) + +#define VF_BINOP_REVERSE_BODY_X128(op) \ + VF_BINOP_REVERSE_BODY_X64 (op) \ + VF_BINOP_REVERSE_BODY_X64 (op) + +#define DEF_VF_BINOP_REVERSE_CASE_1(T, OP, NAME, BODY) \ + void test_vf_binop_reverse_##NAME##_##T##_case_1 (T *restrict out, \ + T *restrict in, T f, \ + unsigned n) \ + { \ + unsigned k = 0; \ + T tmp = f + 3.45; \ + \ + while (k < n) \ + { \ + tmp = tmp * 0x3.fp2; \ + BODY (OP) \ + } \ + } +#define DEF_VF_BINOP_REVERSE_CASE_1_WRAP(T, OP, NAME, BODY) \ + DEF_VF_BINOP_REVERSE_CASE_1 (T, OP, NAME, BODY) + +#endif + +#define DEF_MIN_0(T) \ + static inline T test_##T##_min_0 (T a, T b) { return a > b ? b : a; } + +#define DEF_MIN_1(T) \ + static inline T test_##T##_min_1 (T a, T b) { return a >= b ? b : a; } + +DEF_MIN_0 (_Float16) +DEF_MIN_0 (float) +DEF_MIN_0 (double) + +DEF_MIN_1 (_Float16) +DEF_MIN_1 (float) +DEF_MIN_1 (double) + +#define MIN_FUNC_0(T) test_##T##_min_0 +#define MIN_FUNC_0_WRAP(T) MIN_FUNC_0 (T) + +#define MIN_FUNC_1(T) test_##T##_min_1 +#define MIN_FUNC_1_WRAP(T) MIN_FUNC_1 (T) + +#define DEF_VF_BINOP_CASE_2(T, FUNC, NAME) \ + void test_vf_binop_##NAME##_##FUNC##_##T##_case_2 (T *restrict out, \ + T *restrict in, T f, \ + unsigned n) \ + { \ + for (unsigned i = 0; i < n; i++) \ + out[i] = FUNC (in[i], f); \ + } +#define DEF_VF_BINOP_CASE_2_WRAP(T, FUNC, NAME) \ + DEF_VF_BINOP_CASE_2 (T, FUNC, NAME) +#define RUN_VF_BINOP_CASE_2(T, NAME, FUNC, out, in, f, n) \ + test_vf_binop_##NAME##_##FUNC##_##T##_case_2 (out, in, f, n) +#define RUN_VF_BINOP_CASE_2_WRAP(T, NAME, FUNC, out, in, f, n) \ + RUN_VF_BINOP_CASE_2 (T, NAME, FUNC, out, in, f, n) + +#define DEF_VF_BINOP_CASE_3(T, FUNC, NAME, BODY) \ + void test_vf_binop_##NAME##_##FUNC##_##T##_case_3 (T *restrict out, \ + T *restrict in, T f, \ + unsigned n) \ + { \ + unsigned k = 0; \ + T tmp = f + 3; \ + \ + while (k < n) \ + { \ + tmp = tmp * 0x7.ap3; \ + BODY (FUNC) \ + } \ + } +#define DEF_VF_BINOP_CASE_3_WRAP(T, FUNC, NAME, BODY) \ + DEF_VF_BINOP_CASE_3 (T, FUNC, NAME, BODY) + +#define VF_BINOP_FUNC_BODY(func) \ + out[k + 0] = func (in[k + 0], tmp); \ + out[k + 1] = func (in[k + 1], tmp); \ + k += 2; + +#define VF_BINOP_FUNC_BODY_X4(op) \ + VF_BINOP_FUNC_BODY (op) \ + VF_BINOP_FUNC_BODY (op) + +#define VF_BINOP_FUNC_BODY_X8(op) \ + VF_BINOP_FUNC_BODY_X4 (op) \ + VF_BINOP_FUNC_BODY_X4 (op) + +#define VF_BINOP_FUNC_BODY_X16(op) \ + VF_BINOP_FUNC_BODY_X8 (op) \ + VF_BINOP_FUNC_BODY_X8 (op) + +#define VF_BINOP_FUNC_BODY_X32(op) \ + VF_BINOP_FUNC_BODY_X16 (op) \ + VF_BINOP_FUNC_BODY_X16 (op) + +#define VF_BINOP_FUNC_BODY_X64(op) \ + VF_BINOP_FUNC_BODY_X32 (op) \ + VF_BINOP_FUNC_BODY_X32 (op) + +#define VF_BINOP_FUNC_BODY_X128(op) \ + VF_BINOP_FUNC_BODY_X64 (op) \ + VF_BINOP_FUNC_BODY_X64 (op) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h new file mode 100644 index 0000000..e6ddd1e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h @@ -0,0 +1,451 @@ +#ifndef HAVE_DEFINED_VF_BINOP_DATA_H +#define HAVE_DEFINED_VF_BINOP_DATA_H + +#define N 16 + +#define TEST_BINOP_DATA(T, NAME) test_##T##_##NAME##_data +#define TEST_BINOP_DATA_WRAP(T, NAME) TEST_BINOP_DATA(T, NAME) + + +_Float16 TEST_BINOP_DATA(_Float16, mul)[][4][N] = +{ + { + { 0x1.0000000000000p+0f16 }, + { + 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, + 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, + 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, + 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, + }, + { + 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, + 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, + 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, + 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, + }, + }, + { + { 0x1.0000000000000p+7f16 }, + { + -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, + 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, + -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, + -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, + }, + { + -0x1.53c0000000000p+12f16, -0x1.53c0000000000p+12f16, -0x1.53c0000000000p+12f16, -0x1.53c0000000000p+12f16, + 0x1.c300000000000p+13f16, 0x1.c300000000000p+13f16, 0x1.c300000000000p+13f16, 0x1.c300000000000p+13f16, + -0x1.ffc0000000000p+14f16, -0x1.ffc0000000000p+14f16, -0x1.ffc0000000000p+14f16, -0x1.ffc0000000000p+14f16, + -0x1.94c0000000000p+13f16, -0x1.94c0000000000p+13f16, -0x1.94c0000000000p+13f16, -0x1.94c0000000000p+13f16, + }, + }, + { + { -0x1.fc00000000000p+6f16 }, + { + -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, + -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, + 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, + -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, + }, + { + 0x1.0400000000000p+12f16, 0x1.0400000000000p+12f16, 0x1.0400000000000p+12f16, 0x1.0400000000000p+12f16, + 0x1.e180000000000p+14f16, 0x1.e180000000000p+14f16, 0x1.e180000000000p+14f16, 0x1.e180000000000p+14f16, + -0x1.9380000000000p+11f16, -0x1.9380000000000p+11f16, -0x1.9380000000000p+11f16, -0x1.9380000000000p+11f16, + 0x1.06c0000000000p+12f16, 0x1.06c0000000000p+12f16, 0x1.06c0000000000p+12f16, 0x1.06c0000000000p+12f16, + }, + }, +}; + +float TEST_BINOP_DATA(float, mul)[][4][N] = +{ + { + { 0x1.4000000000000p+3f }, + { + 0x1.a022ea0000000p+60f, 0x1.a022ea0000000p+60f, 0x1.a022ea0000000p+60f, 0x1.a022ea0000000p+60f, + 0x1.aa49660000000p+62f, 0x1.aa49660000000p+62f, 0x1.aa49660000000p+62f, 0x1.aa49660000000p+62f, + -0x1.ac3a220000000p+62f, -0x1.ac3a220000000p+62f, -0x1.ac3a220000000p+62f, -0x1.ac3a220000000p+62f, + 0x1.62cc880000000p+58f, 0x1.62cc880000000p+58f, 0x1.62cc880000000p+58f, 0x1.62cc880000000p+58f, + }, + { + 0x1.0415d20000000p+64f, 0x1.0415d20000000p+64f, 0x1.0415d20000000p+64f, 0x1.0415d20000000p+64f, + 0x1.0a6de00000000p+66f, 0x1.0a6de00000000p+66f, 0x1.0a6de00000000p+66f, 0x1.0a6de00000000p+66f, + -0x1.0ba4540000000p+66f, -0x1.0ba4540000000p+66f, -0x1.0ba4540000000p+66f, -0x1.0ba4540000000p+66f, + 0x1.bb7faa0000000p+61f, 0x1.bb7faa0000000p+61f, 0x1.bb7faa0000000p+61f, 0x1.bb7faa0000000p+61f, + }, + }, + { + { 0x1.d1a94a0000000p+39f }, + { + 0x1.de3d100000000p+63f, 0x1.de3d100000000p+63f, 0x1.de3d100000000p+63f, 0x1.de3d100000000p+63f, + 0x1.82ed340000000p+60f, 0x1.82ed340000000p+60f, 0x1.82ed340000000p+60f, 0x1.82ed340000000p+60f, + 0x1.e4075c0000000p+63f, 0x1.e4075c0000000p+63f, 0x1.e4075c0000000p+63f, 0x1.e4075c0000000p+63f, + 0x1.b7f1700000000p+62f, 0x1.b7f1700000000p+62f, 0x1.b7f1700000000p+62f, 0x1.b7f1700000000p+62f, + }, + { + 0x1.b2f4960000000p+103f, 0x1.b2f4960000000p+103f, 0x1.b2f4960000000p+103f, 0x1.b2f4960000000p+103f, + 0x1.5fe85c0000000p+100f, 0x1.5fe85c0000000p+100f, 0x1.5fe85c0000000p+100f, 0x1.5fe85c0000000p+100f, + 0x1.b838ba0000000p+103f, 0x1.b838ba0000000p+103f, 0x1.b838ba0000000p+103f, 0x1.b838ba0000000p+103f, + 0x1.90203e0000000p+102f, 0x1.90203e0000000p+102f, 0x1.90203e0000000p+102f, 0x1.90203e0000000p+102f, + }, + }, + { + { 0x1.0c6f7a0000000p-20f }, + { + 0x1.de3d100000000p+63f, 0x1.de3d100000000p+63f, 0x1.de3d100000000p+63f, 0x1.de3d100000000p+63f, + 0x1.82ed340000000p+60f, 0x1.82ed340000000p+60f, 0x1.82ed340000000p+60f, 0x1.82ed340000000p+60f, + 0x1.e4075c0000000p+63f, 0x1.e4075c0000000p+63f, 0x1.e4075c0000000p+63f, 0x1.e4075c0000000p+63f, + 0x1.b7f1700000000p+62f, 0x1.b7f1700000000p+62f, 0x1.b7f1700000000p+62f, 0x1.b7f1700000000p+62f, + }, + { + 0x1.f5782e0000000p+43f, 0x1.f5782e0000000p+43f, 0x1.f5782e0000000p+43f, 0x1.f5782e0000000p+43f, + 0x1.95b8ce0000000p+40f, 0x1.95b8ce0000000p+40f, 0x1.95b8ce0000000p+40f, 0x1.95b8ce0000000p+40f, + 0x1.fb8a7a0000000p+43f, 0x1.fb8a7a0000000p+43f, 0x1.fb8a7a0000000p+43f, 0x1.fb8a7a0000000p+43f, + 0x1.cd50560000000p+42f, 0x1.cd50560000000p+42f, 0x1.cd50560000000p+42f, 0x1.cd50560000000p+42f, + }, + }, +}; + +double TEST_BINOP_DATA(double, mul)[][4][N] = +{ + { + { 0x1.0e15635000000p+40 }, + { + -0x1.1cadd278efdbap+511, -0x1.1cadd278efdbap+511, -0x1.1cadd278efdbap+511, -0x1.1cadd278efdbap+511, + 0x1.7ba13fea68f33p+511, 0x1.7ba13fea68f33p+511, 0x1.7ba13fea68f33p+511, 0x1.7ba13fea68f33p+511, + -0x1.2c51d0517111ep+511, -0x1.2c51d0517111ep+511, -0x1.2c51d0517111ep+511, -0x1.2c51d0517111ep+511, + 0x1.aca8567d5e741p+511, 0x1.aca8567d5e741p+511, 0x1.aca8567d5e741p+511, 0x1.aca8567d5e741p+511, + }, + { + -0x1.2c571cadff9bep+551, -0x1.2c571cadff9bep+551, -0x1.2c571cadff9bep+551, -0x1.2c571cadff9bep+551, + 0x1.9083c8e97706cp+551, 0x1.9083c8e97706cp+551, 0x1.9083c8e97706cp+551, 0x1.9083c8e97706cp+551, + -0x1.3cd760ed790fcp+551, -0x1.3cd760ed790fcp+551, -0x1.3cd760ed790fcp+551, -0x1.3cd760ed790fcp+551, + 0x1.c43d5b525ff4bp+551, 0x1.c43d5b525ff4bp+551, 0x1.c43d5b525ff4bp+551, 0x1.c43d5b525ff4bp+551, + }, + }, + { + { -0x1.34be569fb0edfp+79 }, + { + 0x1.9249ee7946e55p+511, 0x1.9249ee7946e55p+511, 0x1.9249ee7946e55p+511, 0x1.9249ee7946e55p+511, + -0x1.581af8ca64584p+510, -0x1.581af8ca64584p+510, -0x1.581af8ca64584p+510, -0x1.581af8ca64584p+510, + 0x1.48f04988397e9p+511, 0x1.48f04988397e9p+511, 0x1.48f04988397e9p+511, 0x1.48f04988397e9p+511, + -0x1.d54d7ad0a0415p+511, -0x1.d54d7ad0a0415p+511, -0x1.d54d7ad0a0415p+511, -0x1.d54d7ad0a0415p+511, + }, + { + -0x1.e52c0de8af5f2p+590, -0x1.e52c0de8af5f2p+590, -0x1.e52c0de8af5f2p+590, -0x1.e52c0de8af5f2p+590, + 0x1.9f004bc7dd179p+589, 0x1.9f004bc7dd179p+589, 0x1.9f004bc7dd179p+589, 0x1.9f004bc7dd179p+589, + -0x1.8cb5aa1c618f5p+590, -0x1.8cb5aa1c618f5p+590, -0x1.8cb5aa1c618f5p+590, -0x1.8cb5aa1c618f5p+590, + 0x1.1aff130877303p+591, 0x1.1aff130877303p+591, 0x1.1aff130877303p+591, 0x1.1aff130877303p+591, + }, + }, + { + { 0x1.5aac1aa995dfbp-511 }, + { + -0x1.b1dc3d62e68d9p+511, -0x1.b1dc3d62e68d9p+511, -0x1.b1dc3d62e68d9p+511, -0x1.b1dc3d62e68d9p+511, + 0x1.1ea30828d414dp+511, 0x1.1ea30828d414dp+511, 0x1.1ea30828d414dp+511, 0x1.1ea30828d414dp+511, + -0x1.f88d34164cbd0p+508, -0x1.f88d34164cbd0p+508, -0x1.f88d34164cbd0p+508, -0x1.f88d34164cbd0p+508, + 0x1.c9a81c74a1362p+510, 0x1.c9a81c74a1362p+510, 0x1.c9a81c74a1362p+510, 0x1.c9a81c74a1362p+510, + }, + { + -0x1.25c3ac1058579p+1, -0x1.25c3ac1058579p+1, -0x1.25c3ac1058579p+1, -0x1.25c3ac1058579p+1, + 0x1.84290c6b1a568p+0, 0x1.84290c6b1a568p+0, 0x1.84290c6b1a568p+0, 0x1.84290c6b1a568p+0, + -0x1.55a105e8db4bep-2, -0x1.55a105e8db4bep-2, -0x1.55a105e8db4bep-2, -0x1.55a105e8db4bep-2, + 0x1.35e071897f867p+0, 0x1.35e071897f867p+0, 0x1.35e071897f867p+0, 0x1.35e071897f867p+0, + }, + }, +}; + +_Float16 TEST_BINOP_DATA(_Float16, rdiv)[][4][N] = +{ + { + { 0x1.0000000000000p+0f16 }, + { + 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, + 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, + 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, + 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, + }, + { + 0x1.4800000000000p-5f16, 0x1.4800000000000p-5f16, 0x1.4800000000000p-5f16, 0x1.4800000000000p-5f16, + 0x1.2980000000000p-7f16, 0x1.2980000000000p-7f16, 0x1.2980000000000p-7f16, 0x1.2980000000000p-7f16, + 0x1.3780000000000p-6f16, 0x1.3780000000000p-6f16, 0x1.3780000000000p-6f16, 0x1.3780000000000p-6f16, + 0x1.64c0000000000p-5f16, 0x1.64c0000000000p-5f16, 0x1.64c0000000000p-5f16, 0x1.64c0000000000p-5f16, + }, + }, + { + { 0x1.0000000000000p+0f16 }, + { + -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, + 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, + -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, + -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, + }, + { + -0x1.81c0000000000p-6f16, -0x1.81c0000000000p-6f16, -0x1.81c0000000000p-6f16, -0x1.81c0000000000p-6f16, + 0x1.2280000000000p-7f16, 0x1.2280000000000p-7f16, 0x1.2280000000000p-7f16, 0x1.2280000000000p-7f16, + -0x1.0040000000000p-8f16, -0x1.0040000000000p-8f16, -0x1.0040000000000p-8f16, -0x1.0040000000000p-8f16, + -0x1.4400000000000p-7f16, -0x1.4400000000000p-7f16, -0x1.4400000000000p-7f16, -0x1.4400000000000p-7f16, + }, + }, + { + { 0x1.9000000000000p+6f16 }, + { + -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, + -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, + 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, + -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, + }, + { + -0x1.86c0000000000p+1f16, -0x1.86c0000000000p+1f16, -0x1.86c0000000000p+1f16, -0x1.86c0000000000p+1f16, + -0x1.a600000000000p-2f16, -0x1.a600000000000p-2f16, -0x1.a600000000000p-2f16, -0x1.a600000000000p-2f16, + 0x1.f7c0000000000p+1f16, 0x1.f7c0000000000p+1f16, 0x1.f7c0000000000p+1f16, 0x1.f7c0000000000p+1f16, + -0x1.82c0000000000p+1f16, -0x1.82c0000000000p+1f16, -0x1.82c0000000000p+1f16, -0x1.82c0000000000p+1f16, + }, + }, +}; + +float TEST_BINOP_DATA(float, rdiv)[][4][N] = +{ + { + { 0x1.0000000000000p+0f }, + { + 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, + 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, + 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, + 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, + }, + { + 0x1.47c7360000000p-61f, 0x1.47c7360000000p-61f, 0x1.47c7360000000p-61f, 0x1.47c7360000000p-61f, + 0x1.2969980000000p-63f, 0x1.2969980000000p-63f, 0x1.2969980000000p-63f, 0x1.2969980000000p-63f, + 0x1.37651e0000000p-62f, 0x1.37651e0000000p-62f, 0x1.37651e0000000p-62f, 0x1.37651e0000000p-62f, + 0x1.647b220000000p-61f, 0x1.647b220000000p-61f, 0x1.647b220000000p-61f, 0x1.647b220000000p-61f, + }, + }, + { + { 0x1.fffffe0000000p+63f }, + { + -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, + 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, + -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, + -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, + }, + { + -0x1.81a4f80000000p+2f, -0x1.81a4f80000000p+2f, -0x1.81a4f80000000p+2f, -0x1.81a4f80000000p+2f, + 0x1.227b0a0000000p+1f, 0x1.227b0a0000000p+1f, 0x1.227b0a0000000p+1f, 0x1.227b0a0000000p+1f, + -0x1.000efe0000000p+0f, -0x1.000efe0000000p+0f, -0x1.000efe0000000p+0f, -0x1.000efe0000000p+0f, + -0x1.43c6b20000000p+1f, -0x1.43c6b20000000p+1f, -0x1.43c6b20000000p+1f, -0x1.43c6b20000000p+1f, + }, + }, + { + { -0x1.d301720000000p+104f }, + { + -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, + -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, + 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, + -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, + }, + { + 0x1.c806200000000p+43f, 0x1.c806200000000p+43f, 0x1.c806200000000p+43f, 0x1.c806200000000p+43f, + 0x1.ec8b9e0000000p+40f, 0x1.ec8b9e0000000p+40f, 0x1.ec8b9e0000000p+40f, 0x1.ec8b9e0000000p+40f, + -0x1.25dcbc0000000p+44f, -0x1.25dcbc0000000p+44f, -0x1.25dcbc0000000p+44f, -0x1.25dcbc0000000p+44f, + 0x1.c348400000000p+43f, 0x1.c348400000000p+43f, 0x1.c348400000000p+43f, 0x1.c348400000000p+43f, + }, + }, +}; + +double TEST_BINOP_DATA(double, rdiv)[][4][N] = +{ + { + { 0x1.0000000000000p+0 }, + { + 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, + 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, + 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, + 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, + }, + { + 0x1.47c734d265b62p-509, 0x1.47c734d265b62p-509, 0x1.47c734d265b62p-509, 0x1.47c734d265b62p-509, + 0x1.296997569d3cdp-511, 0x1.296997569d3cdp-511, 0x1.296997569d3cdp-511, 0x1.296997569d3cdp-511, + 0x1.37651dc4c34fcp-510, 0x1.37651dc4c34fcp-510, 0x1.37651dc4c34fcp-510, 0x1.37651dc4c34fcp-510, + 0x1.647b1ff508275p-509, 0x1.647b1ff508275p-509, 0x1.647b1ff508275p-509, 0x1.647b1ff508275p-509, + }, + }, + { + { 0x1.afcef51f0fb5fp+265 }, + { + -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, + 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, + -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, + -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, + }, + { + -0x1.453e40c97ee2ap-244, -0x1.453e40c97ee2ap-244, -0x1.453e40c97ee2ap-244, -0x1.453e40c97ee2ap-244, + 0x1.e9f7fd1cca941p-246, 0x1.e9f7fd1cca941p-246, 0x1.e9f7fd1cca941p-246, 0x1.e9f7fd1cca941p-246, + -0x1.afe83ffcda969p-247, -0x1.afe83ffcda969p-247, -0x1.afe83ffcda969p-247, -0x1.afe83ffcda969p-247, + -0x1.1110a2fba3e0dp-245, -0x1.1110a2fba3e0dp-245, -0x1.1110a2fba3e0dp-245, -0x1.1110a2fba3e0dp-245, + }, + }, + { + { -0x1.ed8d34e547314p+597 }, + { + -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, + -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, + 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, + -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, + }, + { + 0x1.e1f211cce49a8p+88, 0x1.e1f211cce49a8p+88, 0x1.e1f211cce49a8p+88, 0x1.e1f211cce49a8p+88, + 0x1.044581e6878d3p+86, 0x1.044581e6878d3p+86, 0x1.044581e6878d3p+86, 0x1.044581e6878d3p+86, + -0x1.3690f29d3d5d0p+89, -0x1.3690f29d3d5d0p+89, -0x1.3690f29d3d5d0p+89, -0x1.3690f29d3d5d0p+89, + 0x1.dcef333871e2dp+88, 0x1.dcef333871e2dp+88, 0x1.dcef333871e2dp+88, 0x1.dcef333871e2dp+88, + }, + }, +}; + +_Float16 TEST_BINOP_DATA(_Float16, min)[][4][N] = +{ + { + { 0x1.0000000000000p+0f16 }, + { + 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, + 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, + 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, + 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, + }, + { + 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, + 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, + 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, + 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, + }, + }, + { + { 0x1.0000000000000p+0f16 }, + { + -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, + 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, + -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, + -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, + }, + { + -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, + 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, + -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, + -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, + }, + }, + { + { -0x1.0000000000000p+0f16 }, + { + -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, + -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, + 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, + -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, + }, + { + -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, + -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, + -0x1.0000000000000p+0f16, -0x1.0000000000000p+0f16, -0x1.0000000000000p+0f16, -0x1.0000000000000p+0f16, + -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, + }, + }, +}; + +float TEST_BINOP_DATA(float, min)[][4][N] = +{ + { + { 0x1.0000000000000p+0f }, + { + 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, + 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, + 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, + 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, + }, + { + 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, + 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, + 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, + 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, + }, + }, + { + { 0x1.0000000000000p+0f }, + { + -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, + 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, + -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, + -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, + }, + { + -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, + 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, + -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, + -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, + }, + }, + { + { -0x1.bc16d60000000p+59f }, + { + -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, + -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, + 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, + -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, + }, + { + -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, + -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, + -0x1.bc16d60000000p+59f, -0x1.bc16d60000000p+59f, -0x1.bc16d60000000p+59f, -0x1.bc16d60000000p+59f, + -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, + }, + }, +}; + +double TEST_BINOP_DATA(double, min)[][4][N] = +{ + { + { 0x1.0000000000000p+0 }, + { + 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, + 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, + 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, + 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, + }, + { + 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, + 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, + 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, + 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, + }, + }, + { + { 0x1.0000000000000p+0 }, + { + -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, + 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, + -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, + -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, + }, + { + -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, + 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, + -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, + -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, + }, + }, + { + { -0x1.317e5ef3ab327p+508 }, + { + -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, + -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, + 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, + -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, + }, + { + -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, + -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, + -0x1.317e5ef3ab327p+508, -0x1.317e5ef3ab327p+508, -0x1.317e5ef3ab327p+508, -0x1.317e5ef3ab327p+508, + -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, + }, + }, +}; + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_run.h new file mode 100644 index 0000000..aa70e7c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_run.h @@ -0,0 +1,42 @@ +#ifndef HAVE_DEFINED_VF_BINOP_RUN_H +#define HAVE_DEFINED_VF_BINOP_RUN_H + +#include <math.h> +#include <stdio.h> + +#define TYPE_FABS(x, T) \ + (__builtin_types_compatible_p (T, double) ? fabs (x) : fabsf (x)) + +#define MAX_RELATIVE_DIFF(T) \ + (__builtin_types_compatible_p (T, _Float16) ? 0.1f : \ + (__builtin_types_compatible_p (T, float) ? 0.01f : 0.01)) + +int +main () +{ + unsigned i, k; + T out[N]; + + for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++) + { + T f = TEST_DATA[i][0][0]; + T *in = TEST_DATA[i][1]; + T *expect = TEST_DATA[i][2]; + + TEST_RUN (T, NAME, out, in, f, N); + + for (k = 0; k < N; k++) + { + T diff = expect[k] - out[k]; + if (TYPE_FABS (diff, T) + > MAX_RELATIVE_DIFF (T) * TYPE_FABS (expect[k], T)) { + printf("Mismatch at i=%u, k=%u: expect=%f, out=%f, diff=%f\n", i, k, (double)expect[k], (double)out[k], (double)diff); + __builtin_abort (); + } + } + } + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c index fd8aa30..a54d9a1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c index 8fd8552..2289d04 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f16.c new file mode 100644 index 0000000..c84c773 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f16.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" +#include "vf_binop_data.h" + +#define T _Float16 +#define FUNC MIN_FUNC_0_WRAP(T) +#define NAME min + +DEF_VF_BINOP_CASE_2_WRAP (T, FUNC, NAME) + +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_2_WRAP(T, NAME, FUNC, out, in, f, n) + +#include "vf_binop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f32.c new file mode 100644 index 0000000..a2d024e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" +#include "vf_binop_data.h" + +#define T float +#define FUNC MIN_FUNC_0_WRAP(T) +#define NAME min + +DEF_VF_BINOP_CASE_2_WRAP (T, FUNC, NAME) + +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_2_WRAP(T, NAME, FUNC, out, in, f, n) + +#include "vf_binop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f64.c new file mode 100644 index 0000000..9a66f18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" +#include "vf_binop_data.h" + +#define T double +#define FUNC MIN_FUNC_0_WRAP(T) +#define NAME min + +DEF_VF_BINOP_CASE_2_WRAP (T, FUNC, NAME) + +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_2_WRAP(T, NAME, FUNC, out, in, f, n) + +#include "vf_binop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c index e91fd15..b6d944c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c index ca7e0db..e9253fe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f16.c new file mode 100644 index 0000000..5d57ec8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f16.c @@ -0,0 +1,19 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" +#include "vf_binop_data.h" + +#define T _Float16 +#define NAME mul + +DEF_VF_BINOP_CASE_0_WRAP (T, *, NAME) + +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_0_WRAP(T, NAME, out, in, f, n) + +#include "vf_binop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f32.c new file mode 100644 index 0000000..337380a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" +#include "vf_binop_data.h" + +#define T float +#define NAME mul + +DEF_VF_BINOP_CASE_0_WRAP (T, *, NAME) + +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_0_WRAP(T, NAME, out, in, f, n) + +#include "vf_binop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f64.c new file mode 100644 index 0000000..ec3d562 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" +#include "vf_binop_data.h" + +#define T double +#define NAME mul + +DEF_VF_BINOP_CASE_0_WRAP (T, *, NAME) + +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_0_WRAP(T, NAME, out, in, f, n) + +#include "vf_binop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c index b38e800..397e283 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c index fef5d77..6d846a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c index 7951d40..0b4f6e1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c index d0def86..acc7aa3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f16.c new file mode 100644 index 0000000..07fb540 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f16.c @@ -0,0 +1,19 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" +#include "vf_binop_data.h" + +#define T _Float16 +#define NAME rdiv + +DEF_VF_BINOP_REVERSE_CASE_0_WRAP (T, /, NAME) + +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_REVERSE_CASE_0_WRAP(T, NAME, out, in, f, n) + +#include "vf_binop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f32.c new file mode 100644 index 0000000..2fda776 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" +#include "vf_binop_data.h" + +#define T float +#define NAME rdiv + +DEF_VF_BINOP_REVERSE_CASE_0_WRAP (T, /, NAME) + +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_REVERSE_CASE_0_WRAP(T, NAME, out, in, f, n) + +#include "vf_binop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f64.c new file mode 100644 index 0000000..8f2958f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" +#include "vf_binop_data.h" + +#define T double +#define NAME rdiv + +DEF_VF_BINOP_REVERSE_CASE_0_WRAP (T, /, NAME) + +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_REVERSE_CASE_0_WRAP(T, NAME, out, in, f, n) + +#include "vf_binop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c index d4c527a..a858d27 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c index abce2f2..a04bd91 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c index ddf49d5..a00d620 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c index a874991..eeae215 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c index f84d7f5..ad2dacd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int16_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -20,4 +22,6 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmin.vx} 2 } } */ /* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssub.vx} 1 } } */ -/* { dg-final { scan-assembler-times {vaadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c index 70b6743..ebcdb0a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int32_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -20,4 +22,6 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmin.vx} 2 } } */ /* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssub.vx} 1 } } */ -/* { dg-final { scan-assembler-times {vaadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c index 986fa4c..f15d7b5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int64_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -20,4 +22,9 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmin.vx} 2 } } */ /* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssub.vx} 1 } } */ -/* { dg-final { scan-assembler-times {vaadd.vx} 1 { target { no-opts "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" } } } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 2 { target { no-opts + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } */ +/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c index c479295..c997348 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int8_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -20,4 +22,6 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmin.vx} 2 } } */ /* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssub.vx} 1 } } */ -/* { dg-final { scan-assembler-times {vaadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c index cb62e0f..27204de 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint16_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c index e2a5dbb..4c655c5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint32_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c index e7b1ef0..27f5253 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint64_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -19,4 +21,9 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vminu.vx} 2 } } */ /* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ -/* { dg-final { scan-assembler-times {vaaddu.vx} 1 { target { no-opts "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" } } } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 2 { target { no-opts { + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ +/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c index 559887e..8622b30 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint8_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -19,4 +21,6 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vminu.vx} 2 } } */ /* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ -/* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c index 05801a9..db272ef 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int16_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -21,3 +23,5 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler-not {vaadd.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c index f05f091..b3f99ba 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int32_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -21,3 +23,5 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler-not {vaadd.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c index adf9ccb..4fdf8f9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int64_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -21,3 +23,5 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler-not {vaadd.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c index 8b3f5bc..02cf934 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int8_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -21,3 +23,5 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler-not {vaadd.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c index 365e650..330d541 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint16_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c index c8fd42a..7095cc7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint32_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c index bdb76b4..29824ed 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint64_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c index fc9c101..525dd38 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint8_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c index 741f431..94f83ff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int16_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -21,3 +23,5 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler-not {vaadd.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c index 1741c22..7746809 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int32_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -21,3 +23,5 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler-not {vaadd.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c index d326357..ed31e79 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int64_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -21,3 +23,5 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler-not {vaadd.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c index 3137dc0..b9d1ddc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int8_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -21,3 +23,5 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler-not {vaadd.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c index 121daeb..7c98625 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint16_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c index 9616e7f..9de7c9f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint32_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c index cf985f0..b35a9b7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint64_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c index 3bb382d..9eeb272 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint8_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c index 86c8040..2ae4804 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c index e2d1613..88cfc72 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c index 06ffa15..6b29a72 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -35,4 +36,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_B /* { dg-final { scan-assembler {vmin.vx} } } */ /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ -/* { dg-final { scan-assembler {vaadd.vx} { target { no-opts "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" } } } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { no-opts { + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c index cb086aa..f862eb7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c index c851f23..3ecfce6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c index b7805c1..7ce1fe8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -31,5 +32,6 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_B /* { dg-final { scan-assembler {vremu.vx} } } */ /* { dg-final { scan-assembler {vmaxu.vx} } } */ /* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler {vsaddu.vx} } } */ /* { dg-final { scan-assembler {vssubu.vx} } } */ /* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c index 8295dc2..c84a30c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -33,4 +34,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_B /* { dg-final { scan-assembler {vminu.vx} } } */ /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ -/* { dg-final { scan-assembler {vaaddu.vx} { target { no-opts "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" } } } } */ +/* { dg-final { scan-assembler {vaaddu.vx} { target { no-opts { + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c index d214da9..9f3d7df 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c index 7c7bf09..df6872c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c index 6d161bd..05ed639 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c index 0409012..6776b1f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c index ed437319..d3e2785 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c index b7c7ad4..5497b5a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c index dd9c845..3a8e85f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c index 1fda062..060d591 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c index 725a55b..86a6c45 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c index 1e18342..9a1ff3a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c @@ -12,8 +12,8 @@ DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X8) DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X8) DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X8) DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X8) -DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) -DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c index fd6e47c..3e3acfc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c index 399d0f5..531c119 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c index 98567a3..990f3e4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c @@ -13,7 +13,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) -DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c index 3a215ea..f51e7a1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c index ac4d100..79b7477 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c index 5eb0ed6..ac5fd69 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c index 8b404b6..84aa06b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i16.c new file mode 100644 index 0000000..3770c96 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int16_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-times {vmerge.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i32.c new file mode 100644 index 0000000..1016100 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i32.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int32_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-times {vmerge.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i64.c new file mode 100644 index 0000000..6df25b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i64.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int64_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-times {vmerge.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i8.c new file mode 100644 index 0000000..738adb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i8.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int8_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-times {vmerge.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i16.c new file mode 100644 index 0000000..340a4aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int16_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-not {vmerge.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i32.c new file mode 100644 index 0000000..cba6822 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i32.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int32_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-not {vmerge.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i64.c new file mode 100644 index 0000000..45efd3a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i64.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int64_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-not {vmerge.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i8.c new file mode 100644 index 0000000..b6f0000 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i8.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int8_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-not {vmerge.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i16.c new file mode 100644 index 0000000..c1e1b30 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T int16_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-not {vmerge.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i32.c new file mode 100644 index 0000000..a626720 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i32.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T int32_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-not {vmerge.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i64.c new file mode 100644 index 0000000..17dc5bf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i64.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T int64_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-not {vmerge.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i8.c new file mode 100644 index 0000000..2aee2cf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i8.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T int8_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-not {vmerge.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h index b7c0f79..353ee16 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h @@ -363,14 +363,35 @@ DEF_AVG_FLOOR(int8_t, int16_t) DEF_AVG_FLOOR(int16_t, int32_t) DEF_AVG_FLOOR(int32_t, int64_t) +#define DEF_AVG_CEIL(NT, WT) \ +NT \ +test_##NT##_avg_ceil(NT x, NT y) \ +{ \ + return (NT)(((WT)x + (WT)y + 1) >> 1); \ +} + +DEF_AVG_CEIL(uint8_t, uint16_t) +DEF_AVG_CEIL(uint16_t, uint32_t) +DEF_AVG_CEIL(uint32_t, uint64_t) + +DEF_AVG_CEIL(int8_t, int16_t) +DEF_AVG_CEIL(int16_t, int32_t) +DEF_AVG_CEIL(int32_t, int64_t) + #ifdef HAS_INT128 DEF_AVG_FLOOR(uint64_t, uint128_t) DEF_AVG_FLOOR(int64_t, int128_t) + + DEF_AVG_CEIL(uint64_t, uint128_t) + DEF_AVG_CEIL(int64_t, int128_t) #endif #define AVG_FLOOR_FUNC(T) test_##T##_avg_floor #define AVG_FLOOR_FUNC_WRAP(T) AVG_FLOOR_FUNC(T) +#define AVG_CEIL_FUNC(T) test_##T##_avg_ceil +#define AVG_CEIL_FUNC_WRAP(T) AVG_CEIL_FUNC(T) + #define TEST_BINARY_VX_SIGNED_0(T) \ DEF_VX_BINARY_CASE_0_WRAP(T, +, add) \ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub) \ @@ -388,6 +409,7 @@ DEF_AVG_FLOOR(int32_t, int64_t) DEF_VX_BINARY_CASE_2_WRAP(T, SAT_S_ADD_FUNC(T), sat_add) \ DEF_VX_BINARY_CASE_2_WRAP(T, SAT_S_SUB_FUNC(T), sat_sub) \ DEF_VX_BINARY_CASE_2_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor) \ + DEF_VX_BINARY_CASE_2_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil) \ #define TEST_BINARY_VX_UNSIGNED_0(T) \ DEF_VX_BINARY_CASE_0_WRAP(T, +, add) \ @@ -405,5 +427,28 @@ DEF_AVG_FLOOR(int32_t, int64_t) DEF_VX_BINARY_CASE_2_WRAP(T, SAT_U_ADD_FUNC(T), sat_add) \ DEF_VX_BINARY_CASE_2_WRAP(T, SAT_U_SUB_FUNC(T), sat_sub) \ DEF_VX_BINARY_CASE_2_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor) \ + DEF_VX_BINARY_CASE_2_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil) \ + +/* For some special cases cannot be normalized as above */ + +#define DEF_VX_MERGE_0(T) \ +void \ +test_vx_merge_##T##_case_0 (T * restrict out, T * restrict in, \ + T x, unsigned n) \ +{ \ + for (unsigned i = 0; i < n; i++) \ + { \ + if (i % 2 == 0) \ + out[i] = x; \ + else \ + out[i] = in[i]; \ + } \ +} + +#define DEF_VX_MERGE_0_WRAP(T) DEF_VX_MERGE_0(T) + +#define RUN_VX_MERGE_0(T, out, in, x, n) \ + test_vx_merge_##T##_case_0(out, in, x, n) +#define RUN_VX_MERGE_0_WRAP(T, out, in, x, n) RUN_VX_MERGE_0(T, out, in, x, n) #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h index 6847309..e385bf2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h @@ -5298,4 +5298,592 @@ int64_t TEST_BINARY_DATA(int64_t, avg_floor)[][3][N] = }, }; +uint8_t TEST_BINARY_DATA(uint8_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 255, 255, 255, 255, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 191, 191, 191, 191, + 64, 64, 64, 64, + }, + }, + { + { 255 }, + { + 0, 0, 0, 0, + 255, 255, 255, 255, + 254, 254, 254, 254, + 1, 1, 1, 1, + }, + { + 128, 128, 128, 128, + 255, 255, 255, 255, + 255, 255, 255, 255, + 128, 128, 128, 128, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 49151, 49151, 49151, 49151, + 16384, 16384, 16384, 16384, + }, + }, + { + { 65535 }, + { + 0, 0, 0, 0, + 65535, 65535, 65535, 65535, + 65534, 65534, 65534, 65534, + 1, 1, 1, 1, + }, + { + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 32768, 32768, 32768, 32768, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 3221225471, 3221225471, 3221225471, 3221225471, + 1073741824, 1073741824, 1073741824, 1073741824, + }, + }, + { + { 4294967295 }, + { + 0, 0, 0, 0, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967294, 4294967294, 4294967294, 4294967294, + 1, 1, 1, 1, + }, + { + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 13835058055282163711ull, 13835058055282163711ull, 13835058055282163711ull, 13835058055282163711ull, + 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, + }, + }, + { + { 18446744073709551615ull }, + { + 0, 0, 0, 0, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 1, 1, 1, 1, + }, + { + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -128, -128, -128, -128, + -127, -127, -127, -127, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 0, 0, 0, 0, + 0, 0, 0, 0, + 64, 64, 64, 64, + }, + }, + { + {-128 }, + { + 0, 0, 0, 0, + -128, -128, -128, -128, + 126, 126, 126, 126, + 127, 127, 127, 127, + }, + { + -64, -64, -64, -64, + -128, -128, -128, -128, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 0, 0, 0, 0, + 0, 0, 0, 0, + 16384, 16384, 16384, 16384, + }, + }, + { + {-32768 }, + { + 0, 0, 0, 0, + -32768, -32768, -32768, -32768, + 32766, 32766, 32766, 32766, + 32767, 32767, 32767, 32767, + }, + { + -16384, -16384, -16384, -16384, + -32768, -32768, -32768, -32768, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 0, 0, 0, 0, + 0, 0, 0, 0, + 1073741824, 1073741824, 1073741824, 1073741824, + }, + }, + { + {-2147483648 }, + { + 0, 0, 0, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + 2147483646, 2147483646, 2147483646, 2147483646, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + { + -1073741824, -1073741824, -1073741824, -1073741824, + -2147483648, -2147483648, -2147483648, -2147483648, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 0, 0, 0, 0, + 0, 0, 0, 0, + 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, + }, + }, + { + {-9223372036854775808ull }, + { + 0, 0, 0, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + }, + { + -4611686018427387904ull, -4611686018427387904ull, -4611686018427387904ull, -4611686018427387904ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, merge)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 0, 2, 0, 2, + 0, 1, 0, 1, + 0, 0, 0, 0, + 0, 4, 0, 4, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -128, -128, -128, -128, + -127, -127, -127, -127, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 127, -128, 127, -128, + 127, -127, 127, -127, + 127, 1, 127, 1, + }, + }, + { + {-128 }, + { + 0, 0, 0, 0, + -128, -128, -128, -128, + 126, 126, 126, 126, + 127, 127, 127, 127, + }, + { + -128, 0, -128, 0, + -128, -128, -128, -128, + -128, 126, -128, 126, + -128, 127, -128, 127, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, merge)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 0, 2, 0, 2, + 0, 1, 0, 1, + 0, 0, 0, 0, + 0, 4, 0, 4, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 32767, -32768, 32767, -32768, + 32767, -32767, 32767, -32767, + 32767, 1, 32767, 1, + }, + }, + { + {-32768 }, + { + 0, 0, 0, 0, + -32768, -32768, -32768, -32768, + 32766, 32766, 32766, 32766, + 32767, 32767, 32767, 32767, + }, + { + -32768, 0, -32768, 0, + -32768, -32768, -32768, -32768, + -32768, 32766, -32768, 32766, + -32768, 32767, -32768, 32767, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, merge)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 0, 2, 0, 2, + 0, 1, 0, 1, + 0, 0, 0, 0, + 0, 4, 0, 4, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, -2147483648, 2147483647, -2147483648, + 2147483647, -2147483647, 2147483647, -2147483647, + 2147483647, 1, 2147483647, 1, + }, + }, + { + {-2147483648 }, + { + 0, 0, 0, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + 2147483646, 2147483646, 2147483646, 2147483646, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + { + -2147483648, 0, -2147483648, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, 2147483646, -2147483648, 2147483646, + -2147483648, 2147483647, -2147483648, 2147483647, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, merge)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 0, 2, 0, 2, + 0, 1, 0, 1, + 0, 0, 0, 0, + 0, 4, 0, 4, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, -9223372036854775808ull, 9223372036854775807ull, -9223372036854775808ull, + 9223372036854775807ull, -9223372036854775807ull, 9223372036854775807ull, -9223372036854775807ull, + 9223372036854775807ull, 1, 9223372036854775807ull, 1, + }, + }, + { + {-9223372036854775808ull }, + { + 0, 0, 0, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + }, + { + -9223372036854775808ull, 0, -9223372036854775808ull, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775808ull, 9223372036854775806ull, -9223372036854775808ull, 9223372036854775806ull, + -9223372036854775808ull, 9223372036854775807ull, -9223372036854775808ull, 9223372036854775807ull, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h new file mode 100644 index 0000000..2325c7b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h @@ -0,0 +1,37 @@ +#ifndef HAVE_DEFINED_VX_VF_TERNARY_H +#define HAVE_DEFINED_VX_VF_TERNARY_H + +#include <stdint.h> + +#undef HAS_INT128 + +#if __riscv_xlen == 64 +#define HAS_INT128 +typedef unsigned __int128 uint128_t; +typedef signed __int128 int128_t; +#endif + +#define DEF_VX_TERNARY_CASE_0(T, OP_1, OP_2, NAME) \ +void \ +test_vx_ternary_##NAME##_##T##_case_0 (T * restrict vd, T * restrict vs2, \ + T rs1, unsigned n) \ +{ \ + for (unsigned i = 0; i < n; i++) \ + vd[i] = vd[i] OP_2 vs2[i] OP_1 rs1; \ +} +#define DEF_VX_TERNARY_CASE_0_WRAP(T, OP_1, OP_2, NAME) \ + DEF_VX_TERNARY_CASE_0(T, OP_1, OP_2, NAME) +#define RUN_VX_TERNARY_CASE_0(T, NAME, vd, vs2, rs1, n) \ + test_vx_ternary_##NAME##_##T##_case_0 (vd, vs2, rs1, n) +#define RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0(T, NAME, vd, vs2, rs1, n) + +#define TEST_TERNARY_VX_SIGNED_0(T) \ + DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, macc) \ + DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, nmsac) \ + +#define TEST_TERNARY_VX_UNSIGNED_0(T) \ + DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, macc) \ + DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, nmsac) \ + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h new file mode 100644 index 0000000..9ac1a7d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h @@ -0,0 +1,745 @@ +#ifndef HAVE_DEFINED_VX_TERNARY_DATA_H +#define HAVE_DEFINED_VX_TERNARY_DATA_H + +#define N 16 + +#define TEST_TERNARY_DATA(T, NAME) test_##T##_##NAME##_data +#define TEST_TERNARY_DATA_WRAP(T, NAME) TEST_TERNARY_DATA(T, NAME) + +int8_t TEST_TERNARY_DATA(int8_t, macc)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + -1, -1, -1, -1, + -3, -3, -3, -3, + }, + }, + { + { 127 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 9, 9, 9, 9, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { /* vd */ + 127, 127, 127, 127, + 2, 2, 2, 2, + 0, 0, 0, 0, + -128, -128, -128, -128, + }, + { + 127, 127, 127, 127, + 121, 121, 121, 121, + 8, 8, 8, 8, + -126, -126, -126, -126, + }, + }, +}; + +int16_t TEST_TERNARY_DATA(int16_t, macc)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + -1, -1, -1, -1, + -3, -3, -3, -3, + }, + }, + { + { 32767 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 9, 9, 9, 9, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { /* vd */ + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + 0, 0, 0, 0, + -32768, -32768, -32768, -32768, + }, + { + 32767, 32767, 32767, 32767, + 32761, 32761, 32761, 32761, + 8, 8, 8, 8, + -32766, -32766, -32766, -32766, + }, + }, +}; + +int32_t TEST_TERNARY_DATA(int32_t, macc)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + -1, -1, -1, -1, + -3, -3, -3, -3, + }, + }, + { + { 2147483647 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 9, 9, 9, 9, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { /* vd */ + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + 0, 0, 0, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483641, 2147483641, 2147483641, 2147483641, + 8, 8, 8, 8, + -2147483646, -2147483646, -2147483646, -2147483646, + }, + }, +}; + +int64_t TEST_TERNARY_DATA(int64_t, macc)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + -1, -1, -1, -1, + -3, -3, -3, -3, + }, + }, + { + { 9223372036854775807ull }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 9, 9, 9, 9, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { /* vd */ + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + 0, 0, 0, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775801ull, 9223372036854775801ull, 9223372036854775801ull, 9223372036854775801ull, + 8, 8, 8, 8, + -9223372036854775806ull, -9223372036854775806ull, -9223372036854775806ull, -9223372036854775806ull, + }, + }, +}; + +uint8_t TEST_TERNARY_DATA(uint8_t, macc)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 6, 6, 6, 6, + 3, 3, 3, 3, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + 6, 6, 6, 6, + 7, 7, 7, 7, + }, + }, + { + { 255 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 5, 5, 5, 5, + 3, 3, 3, 3, + 1, 1, 1, 1, + }, + { /* vd */ + 127, 127, 127, 127, + 255, 255, 255, 255, + 0, 0, 0, 0, + 128, 128, 128, 128, + }, + { + 127, 127, 127, 127, + 250, 250, 250, 250, + 253, 253, 253, 253, + 127, 127, 127, 127, + }, + }, +}; + +uint16_t TEST_TERNARY_DATA(uint16_t, macc)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 6, 6, 6, 6, + 3, 3, 3, 3, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + 6, 6, 6, 6, + 7, 7, 7, 7, + }, + }, + { + { 65535 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 5, 5, 5, 5, + 3, 3, 3, 3, + 1, 1, 1, 1, + }, + { /* vd */ + 32767, 32767, 32767, 32767, + 65535, 65535, 65535, 65535, + 0, 0, 0, 0, + 32768, 32768, 32768, 32768, + }, + { + 32767, 32767, 32767, 32767, + 65530, 65530, 65530, 65530, + 65533, 65533, 65533, 65533, + 32767, 32767, 32767, 32767, + }, + }, +}; + +uint32_t TEST_TERNARY_DATA(uint32_t, macc)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 6, 6, 6, 6, + 3, 3, 3, 3, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + 6, 6, 6, 6, + 7, 7, 7, 7, + }, + }, + { + { 4294967295 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 5, 5, 5, 5, + 3, 3, 3, 3, + 1, 1, 1, 1, + }, + { /* vd */ + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967295, 4294967295, 4294967295, 4294967295, + 0, 0, 0, 0, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967290, 4294967290, 4294967290, 4294967290, + 4294967293, 4294967293, 4294967293, 4294967293, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + }, +}; + +uint64_t TEST_TERNARY_DATA(uint64_t, macc)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 6, 6, 6, 6, + 3, 3, 3, 3, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + 6, 6, 6, 6, + 7, 7, 7, 7, + }, + }, + { + { 18446744073709551615ull }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 5, 5, 5, 5, + 3, 3, 3, 3, + 1, 1, 1, 1, + }, + { /* vd */ + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 0, 0, 0, 0, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 18446744073709551610ull, 18446744073709551610ull, 18446744073709551610ull, 18446744073709551610ull, + 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + }, + }, +}; + +int8_t TEST_TERNARY_DATA(int8_t, nmsac)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { 127 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { /* vd */ + 127, 127, 127, 127, + 2, 2, 2, 2, + 0, 0, 0, 0, + -128, -128, -128, -128, + }, + { + 127, 127, 127, 127, + -125, -125, -125, -125, + -8, -8, -8, -8, + 126, 126, 126, 126, + }, + }, +}; + +int16_t TEST_TERNARY_DATA(int16_t, nmsac)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { 32767 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { /* vd */ + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + 0, 0, 0, 0, + -32768, -32768, -32768, -32768, + }, + { + 32767, 32767, 32767, 32767, + -32765, -32765, -32765, -32765, + -8, -8, -8, -8, + 32766, 32766, 32766, 32766, + }, + }, +}; + +int32_t TEST_TERNARY_DATA(int32_t, nmsac)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { 2147483647 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { /* vd */ + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + 0, 0, 0, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483645, -2147483645, -2147483645, -2147483645, + -8, -8, -8, -8, + 2147483646, 2147483646, 2147483646, 2147483646, + }, + }, +}; + +int64_t TEST_TERNARY_DATA(int64_t, nmsac)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { 9223372036854775807ull }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { /* vd */ + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + 0, 0, 0, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775805ull, -9223372036854775805ull, -9223372036854775805ull, -9223372036854775805ull, + -8, -8, -8, -8, + 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, + }, + }, +}; + +uint8_t TEST_TERNARY_DATA(uint8_t, nmsac)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 7, 7, 7, 7, + 5, 5, 5, 5, + }, + }, + { + { 128 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 8, 8, 8, 8, + 2, 2, 2, 2, + }, + { /* vd */ + 127, 127, 127, 127, + 255, 255, 255, 255, + 254, 254, 254, 254, + 252, 252, 252, 252, + }, + { + 127, 127, 127, 127, + 127, 127, 127, 127, + 254, 254, 254, 254, + 252, 252, 252, 252, + }, + }, +}; + +uint16_t TEST_TERNARY_DATA(uint16_t, nmsac)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 7, 7, 7, 7, + 5, 5, 5, 5, + }, + }, + { + { 32768 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 8, 8, 8, 8, + 2, 2, 2, 2, + }, + { /* vd */ + 32767, 32767, 32767, 32767, + 65535, 65535, 65535, 65535, + 65534, 65534, 65534, 65534, + 65532, 65532, 65532, 65532, + }, + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + 65534, 65534, 65534, 65534, + 65532, 65532, 65532, 65532, + }, + }, +}; + +uint32_t TEST_TERNARY_DATA(uint32_t, nmsac)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 7, 7, 7, 7, + 5, 5, 5, 5, + }, + }, + { + { 2147483648 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 8, 8, 8, 8, + 2, 2, 2, 2, + }, + { /* vd */ + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967292, 4294967292, 4294967292, 4294967292, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967292, 4294967292, 4294967292, 4294967292, + }, + }, +}; + +uint64_t TEST_TERNARY_DATA(uint64_t, nmsac)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 7, 7, 7, 7, + 5, 5, 5, 5, + }, + }, + { + { 9223372036854775808ull }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 8, 8, 8, 8, + 2, 2, 2, 2, + }, + { /* vd */ + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, + }, + }, +}; + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_run.h new file mode 100644 index 0000000..cf1926f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_run.h @@ -0,0 +1,26 @@ +#ifndef HAVE_DEFINED_VX_TERNARY_RUN_H +#define HAVE_DEFINED_VX_TERNARY_RUN_H + +int +main () +{ + unsigned i, k; + + for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++) + { + T rs1 = TEST_DATA[i][0][0]; + T *vs2 = TEST_DATA[i][1]; + T *vd = TEST_DATA[i][2]; + T *expect = TEST_DATA[i][3]; + + TEST_RUN (T, NAME, vd, vs2, rs1, N); + + for (k = 0; k < N; k++) + if (vd[k] != expect[k]) + __builtin_abort (); + } + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i16.c new file mode 100644 index 0000000..8def643 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i32.c new file mode 100644 index 0000000..d9ca67d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i64.c new file mode 100644 index 0000000..313109a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i8.c new file mode 100644 index 0000000..47e4a5d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u16.c new file mode 100644 index 0000000..6297672 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u32.c new file mode 100644 index 0000000..30db24b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u64.c new file mode 100644 index 0000000..db3c911 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u8.c new file mode 100644 index 0000000..a7755f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i16.c new file mode 100644 index 0000000..1310727 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int16_t +#define NAME macc +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i32.c new file mode 100644 index 0000000..10174cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int32_t +#define NAME macc +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i64.c new file mode 100644 index 0000000..a33f714 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int64_t +#define NAME macc +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i8.c new file mode 100644 index 0000000..dbb1c67 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int8_t +#define NAME macc +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u16.c new file mode 100644 index 0000000..8ec9d05 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint16_t +#define NAME macc +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u32.c new file mode 100644 index 0000000..46d5c4d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint32_t +#define NAME macc +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u64.c new file mode 100644 index 0000000..cd857b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint64_t +#define NAME macc +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u8.c new file mode 100644 index 0000000..05fa397 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint8_t +#define NAME macc +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i16.c new file mode 100644 index 0000000..2845874 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME merge + +DEF_VX_MERGE_0_WRAP(T) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_MERGE_0_WRAP(T, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i32.c new file mode 100644 index 0000000..57545fb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME merge + +DEF_VX_MERGE_0_WRAP(T) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_MERGE_0_WRAP(T, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i64.c new file mode 100644 index 0000000..fbcb086 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME merge + +DEF_VX_MERGE_0_WRAP(T) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_MERGE_0_WRAP(T, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i8.c new file mode 100644 index 0000000..0c5500a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME merge + +DEF_VX_MERGE_0_WRAP(T) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_MERGE_0_WRAP(T, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i16.c new file mode 100644 index 0000000..6deee02 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int16_t +#define NAME nmsac +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i32.c new file mode 100644 index 0000000..65d376b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int32_t +#define NAME nmsac +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i64.c new file mode 100644 index 0000000..832023a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int64_t +#define NAME nmsac +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i8.c new file mode 100644 index 0000000..ae48e2e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int8_t +#define NAME nmsac +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u16.c new file mode 100644 index 0000000..9427fdd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint16_t +#define NAME nmsac +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u32.c new file mode 100644 index 0000000..da9fc9c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint32_t +#define NAME nmsac +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u64.c new file mode 100644 index 0000000..5e4cde4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint64_t +#define NAME nmsac +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u8.c new file mode 100644 index 0000000..ab52580 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint8_t +#define NAME nmsac +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h index e40902a..035545c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h @@ -693,4 +693,52 @@ sat_u_mul_##NT##_from_##WT##_fmt_1 (NT a, NT b) \ sat_u_mul_##NT##_from_##WT##_fmt_1 (a, b) #define RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, a, b) RUN_SAT_U_MUL_FMT_1(NT, WT, a, b) +#define DEF_SAT_U_MUL_FMT_2(T) \ +T __attribute__((noinline)) \ +sat_u_mul_##T##_fmt_2 (T a, T b) \ +{ \ + T result; \ + if (__builtin_mul_overflow(a, b, &result)) \ + return -1; \ + else \ + return result; \ +} + +#define DEF_SAT_U_MUL_FMT_2_WRAP(T) DEF_SAT_U_MUL_FMT_2(T) +#define RUN_SAT_U_MUL_FMT_2(T, a, b) sat_u_mul_##T##_fmt_2 (a, b) +#define RUN_SAT_U_MUL_FMT_2_WRAP(T, a, b) RUN_SAT_U_MUL_FMT_2(T, a, b) + +#define DEF_SAT_U_MUL_FMT_3(NT, WT) \ +NT __attribute__((noinline)) \ +sat_u_mul_##NT##_from_##WT##_fmt_3 (NT a, NT b) \ +{ \ + WT x = (WT)a * (WT)b; \ + if ((x >> sizeof(a) * 8) == 0) \ + return (NT)x; \ + else \ + return (NT)-1; \ +} + +#define DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) DEF_SAT_U_MUL_FMT_3(NT, WT) +#define RUN_SAT_U_MUL_FMT_3(NT, WT, a, b) \ + sat_u_mul_##NT##_from_##WT##_fmt_3 (a, b) +#define RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, a, b) RUN_SAT_U_MUL_FMT_3(NT, WT, a, b) + +#define DEF_SAT_U_MUL_FMT_4(NT, WT) \ +NT __attribute__((noinline)) \ +sat_u_mul_##NT##_from_##WT##_fmt_4 (NT a, NT b) \ +{ \ + WT x = (WT)a * (WT)b; \ + NT max = -1; \ + if (x >= (WT)(max)) \ + return max; \ + else \ + return (NT)x; \ +} + +#define DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) DEF_SAT_U_MUL_FMT_4(NT, WT) +#define RUN_SAT_U_MUL_FMT_4(NT, WT, a, b) \ + sat_u_mul_##NT##_from_##WT##_fmt_4 (a, b) +#define RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, a, b) RUN_SAT_U_MUL_FMT_4(NT, WT, a, b) + #endif diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u32.c new file mode 100644 index 0000000..7409232 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint32_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c index 8d5449b..fa3758a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c @@ -9,3 +9,5 @@ DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) /* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ +/* { dg-final { scan-assembler-times "mulhu" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c index d8a01d1..b1bf4fa 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c @@ -10,3 +10,4 @@ DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) /* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ /* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ +/* { dg-final { scan-assembler-times "mulhu" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u16.c new file mode 100644 index 0000000..ec79e5d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u16.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint16_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u32.c new file mode 100644 index 0000000..eb95184 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint32_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u16-from-u64.c new file mode 100644 index 0000000..b1d33a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u16-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u32-from-u64.c new file mode 100644 index 0000000..af5ffecf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u32-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u8-from-u64.c new file mode 100644 index 0000000..d65cab0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u8-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u16.c new file mode 100644 index 0000000..714a7f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u16.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define T uint16_t + +DEF_SAT_U_MUL_FMT_2_WRAP(T) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u32.c new file mode 100644 index 0000000..bd6eafc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define T uint32_t + +DEF_SAT_U_MUL_FMT_2_WRAP(T) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u64.c new file mode 100644 index 0000000..c96687f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define T uint64_t + +DEF_SAT_U_MUL_FMT_2_WRAP(T) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u8.c new file mode 100644 index 0000000..a92447f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u8.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define T uint8_t + +DEF_SAT_U_MUL_FMT_2_WRAP(T) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u128.c new file mode 100644 index 0000000..1093701 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u128.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u32.c new file mode 100644 index 0000000..c7bff58 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint32_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u64.c new file mode 100644 index 0000000..13b13ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u64.rv32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u64.rv32.c new file mode 100644 index 0000000..b1f7d7a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u64.rv32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u128.c new file mode 100644 index 0000000..0775bb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u128.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u64.c new file mode 100644 index 0000000..0cbd4e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u64.rv32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u64.rv32.c new file mode 100644 index 0000000..99d15b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u64.rv32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ +/* { dg-final { scan-assembler-times "mulhu" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u64-from-u128.c new file mode 100644 index 0000000..70b1389 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u64-from-u128.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint64_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ +/* { dg-final { scan-assembler-times "mulhu" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u128.c new file mode 100644 index 0000000..4474eb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u128.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u16.c new file mode 100644 index 0000000..eef6490 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u16.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint16_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u32.c new file mode 100644 index 0000000..8e839c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint32_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u64.c new file mode 100644 index 0000000..81a3a24 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u64.rv32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u64.rv32.c new file mode 100644 index 0000000..40bfcef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u64.rv32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u128.c new file mode 100644 index 0000000..d3cef16 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u128.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u32.c new file mode 100644 index 0000000..d7e7356 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint32_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv32.c new file mode 100644 index 0000000..7533823 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32 -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv64.c new file mode 100644 index 0000000..ae4f8c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u128.c new file mode 100644 index 0000000..037497c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u128.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv32.c new file mode 100644 index 0000000..f10cd40 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32 -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv64.c new file mode 100644 index 0000000..6229f51 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u64-from-u128.c new file mode 100644 index 0000000..e852851 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u64-from-u128.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint64_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u128.c new file mode 100644 index 0000000..4ae5c8c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u128.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u16.c new file mode 100644 index 0000000..2580c23 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u16.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint16_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u32.c new file mode 100644 index 0000000..43ca2c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint32_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv32.c new file mode 100644 index 0000000..c5b84cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32 -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv64.c new file mode 100644 index 0000000..51a27a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u32.c new file mode 100644 index 0000000..e212391 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint32_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c index 065afb8..79d3fb3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { rv32 } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c index 062bbc9..ad63db3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { rv32 } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u16.c new file mode 100644 index 0000000..f5a0ab5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint16_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u32.c new file mode 100644 index 0000000..32074a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint32_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c index e6f632b..16ca905 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { rv32 } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u16.c new file mode 100644 index 0000000..73f619b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_2_WRAP(NT, x, y) + +DEF_SAT_U_MUL_FMT_2_WRAP(NT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u32.c new file mode 100644 index 0000000..4965ef3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint32_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_2_WRAP(NT, x, y) + +DEF_SAT_U_MUL_FMT_2_WRAP(NT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u64.c new file mode 100644 index 0000000..1868e81 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_2_WRAP(NT, x, y) + +DEF_SAT_U_MUL_FMT_2_WRAP(NT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u8.c new file mode 100644 index 0000000..2b2551c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_2_WRAP(NT, x, y) + +DEF_SAT_U_MUL_FMT_2_WRAP(NT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u128.c new file mode 100644 index 0000000..561ee21 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u32.c new file mode 100644 index 0000000..e491989 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint32_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u64.c new file mode 100644 index 0000000..14c6ae5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u64.rv32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u64.rv32.c new file mode 100644 index 0000000..35eabc8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u64.rv32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u128.c new file mode 100644 index 0000000..d2bf073 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint32_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u64.c new file mode 100644 index 0000000..74c63fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u64.rv32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u64.rv32.c new file mode 100644 index 0000000..015f038 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u64.rv32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u64-from-u128.c new file mode 100644 index 0000000..77bfce8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u64-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint64_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u128.c new file mode 100644 index 0000000..3c84067 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u16.c new file mode 100644 index 0000000..7b2bd71 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint16_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u32.c new file mode 100644 index 0000000..abfa965 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint32_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u64.c new file mode 100644 index 0000000..74c63fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u64.rv32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u64.rv32.c new file mode 100644 index 0000000..015f038 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u64.rv32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u128.c new file mode 100644 index 0000000..ec23d81 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u32.c new file mode 100644 index 0000000..e175988 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint32_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u64.c new file mode 100644 index 0000000..5d4e28b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u128.c new file mode 100644 index 0000000..d8beb8f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint32_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u64.c new file mode 100644 index 0000000..afc9c9a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint32_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u64-from-u128.c new file mode 100644 index 0000000..d5f20f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u64-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint64_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u128.c new file mode 100644 index 0000000..9d44541 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u16.c new file mode 100644 index 0000000..cd52087 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint16_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u32.c new file mode 100644 index 0000000..f6ae187 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint32_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u64.c new file mode 100644 index 0000000..f94cc9d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c index 883cce2..f3a9ba9 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { rv64 } } } */ +/* { dg-do run { target { rv64 && riscv_b_ok } } } */ /* { dg-options "-march=rv64gc_zba -mabi=lp64d -O2" } */ struct { diff --git a/gcc/testsuite/gcc.target/riscv/zba-shadd.c b/gcc/testsuite/gcc.target/riscv/zba-shadd.c index 61305d3..445ffb2 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-shadd.c +++ b/gcc/testsuite/gcc.target/riscv/zba-shadd.c @@ -1,7 +1,15 @@ /* { dg-do compile } */ /* { dg-options "-O2 -march=rv64gc_zba -mabi=lp64" } */ -unsigned long foo(unsigned int a, unsigned long b) +unsigned long foo1(unsigned int a, unsigned long b) +{ + a = a << 1; + unsigned long c = (unsigned long) a; + unsigned long d = b + (c<<1); + return d; +} + +unsigned long foo2(unsigned int a, unsigned long b) { a = a << 1; unsigned long c = (unsigned long) a; @@ -9,5 +17,15 @@ unsigned long foo(unsigned int a, unsigned long b) return d; } +unsigned long foo3(unsigned int a, unsigned long b) +{ + a = a << 1; + unsigned long c = (unsigned long) a; + unsigned long d = b + (c<<3); + return d; +} + +/* { dg-final { scan-assembler "sh1add.uw" } } */ /* { dg-final { scan-assembler "sh2add.uw" } } */ +/* { dg-final { scan-assembler "sh3add.uw" } } */ /* { dg-final { scan-assembler-not {\mzext} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-sext.c b/gcc/testsuite/gcc.target/riscv/zbb-sext.c new file mode 100644 index 0000000..1ad3e71 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbb-sext.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zbb -mabi=lp64" } */ + +#include<stdint.h> + +int8_t foo1(uint8_t a) { + return a; +} + +int16_t foo2(uint16_t a) { + return a; +} + +/* { dg-final { scan-assembler "sext.b" } } */ +/* { dg-final { scan-assembler "sext.h" } } */ diff --git a/gcc/testsuite/gcc.target/s390/bitint-1.c b/gcc/testsuite/gcc.target/s390/bitint-1.c new file mode 100644 index 0000000..8bdf2ae --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/bitint-1.c @@ -0,0 +1,83 @@ +/* { dg-do compile { target bitint } } */ +/* { dg-options "-O2 -march=z9-109" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +/* Verify calling convention. */ + +static_assert (sizeof (_BitInt(5)) == 1); +static_assert (sizeof (_BitInt(9)) == 2); +static_assert (sizeof (_BitInt(17)) == 4); +static_assert (sizeof (_BitInt(33)) == 8); + +/* +** bitint5_zero_extend_call: +** lghi %r2,22 +** jg bitint5_zero_extend@PLT +*/ + +void bitint5_zero_extend (unsigned _BitInt(5) x); +void bitint5_zero_extend_call (void) { bitint5_zero_extend (22wbu); } + +/* +** bitint5_sign_extend_call: +** lghi %r2,-10 +** jg bitint5_sign_extend@PLT +*/ + +void bitint5_sign_extend (_BitInt(5) x); +void bitint5_sign_extend_call (void) { bitint5_sign_extend (-10wb); } + +/* +** bitint9_zero_extend_call: +** lghi %r2,422 +** jg bitint9_zero_extend@PLT +*/ + +void bitint9_zero_extend (unsigned _BitInt(9) x); +void bitint9_zero_extend_call (void) { bitint9_zero_extend (422wbu); } + +/* +** bitint9_sign_extend_call: +** lghi %r2,-90 +** jg bitint9_sign_extend@PLT +*/ + +void bitint9_sign_extend (_BitInt(9) x); +void bitint9_sign_extend_call (void) { bitint9_sign_extend (-90wb); } + +/* +** bitint17_zero_extend_call: +** lgfi %r2,108198 +** jg bitint17_zero_extend@PLT +*/ + +void bitint17_zero_extend (unsigned _BitInt(17) x); +void bitint17_zero_extend_call (void) { bitint17_zero_extend (108198wbu); } + +/* +** bitint17_sign_extend_call: +** lghi %r2,-22874 +** jg bitint17_sign_extend@PLT +*/ + +void bitint17_sign_extend (_BitInt(17) x); +void bitint17_sign_extend_call (void) { bitint17_sign_extend (-22874wb); } + +/* +** bitint33_zero_extend_call: +** llihl %r2,1 +** oilf %r2,2795939494 +** jg bitint33_zero_extend@PLT +*/ + +void bitint33_zero_extend (unsigned _BitInt(33) x); +void bitint33_zero_extend_call (void) { bitint33_zero_extend (7090906790wbu); } + +/* +** bitint33_sign_extend_call: +** lgfi %r2,-1499027802 +** jg bitint33_sign_extend@PLT +*/ + +void bitint33_sign_extend (_BitInt(33) x); +void bitint33_sign_extend_call (void) { bitint33_sign_extend (-1499027802wb); } diff --git a/gcc/testsuite/gcc.target/s390/bitint-2.c b/gcc/testsuite/gcc.target/s390/bitint-2.c new file mode 100644 index 0000000..9b0e6b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/bitint-2.c @@ -0,0 +1,32 @@ +/* { dg-do run { target bitint } } */ +/* { dg-options "-std=c23" } */ + +/* Verify calling convention. */ + +static_assert (sizeof (_BitInt(65)) == 16); + +[[gnu::noipa]] void +bitint65_zero_extend (unsigned _BitInt(65) x) +{ + static const char y[16] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0xBA, 0xDC, 0x0F, 0xFE, 0xE0, 0xDD, 0xF0, 0x0D}; + if (__builtin_memcmp (&x, y, 16) != 0) + __builtin_abort (); +} + +[[gnu::noipa]] void +bitint65_sign_extend (signed _BitInt(65) x) +{ + static const char y[16] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xBA, 0xDC, 0x0F, 0xFE, 0xE0, 0xDD, 0xF0, 0x0D}; + if (__builtin_memcmp (&x, y, 16) != 0) + __builtin_abort (); +} + +int +main (void) +{ + bitint65_zero_extend (0x1BADC0FFEE0DDF00Dwbu); + bitint65_sign_extend (0x1BADC0FFEE0DDF00Dwb); + return 0; +} diff --git a/gcc/testsuite/gcc.target/s390/bitint-3.c b/gcc/testsuite/gcc.target/s390/bitint-3.c new file mode 100644 index 0000000..9132028 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/bitint-3.c @@ -0,0 +1,28 @@ +/* { dg-do compile { target bitint } } */ +/* { dg-options "-march=z9-109 -fdump-rtl-expand" } */ + +/* Verify calling convention. */ + +/* { dg-final { scan-rtl-dump-times "zero_extend:DI.*reg:QI" 1 "expand" } } */ +void bitint5_zero_extend (unsigned _BitInt(5) x); +void bitint5_zero_extend_call (unsigned _BitInt(5) x) { bitint5_zero_extend (x + 1); } + +/* { dg-final { scan-rtl-dump-times "sign_extend:DI.*reg:QI" 1 "expand" } } */ +void bitint5_sign_extend (_BitInt(5) x); +void bitint5_sign_extend_call (_BitInt(5) x) { bitint5_sign_extend (x + 1); } + +/* { dg-final { scan-rtl-dump-times "zero_extend:DI.*reg:HI" 1 "expand" } } */ +void bitint9_zero_extend (unsigned _BitInt(9) x); +void bitint9_zero_extend_call (unsigned _BitInt(9) x) { bitint9_zero_extend (x + 1); } + +/* { dg-final { scan-rtl-dump-times "sign_extend:DI.*reg:HI" 1 "expand" } } */ +void bitint9_sign_extend (_BitInt(9) x); +void bitint9_sign_extend_call (_BitInt(9) x) { bitint9_sign_extend (x + 1); } + +/* { dg-final { scan-rtl-dump-times "zero_extend:DI.*reg:SI" 1 "expand" } } */ +void bitint17_zero_extend (unsigned _BitInt(17) x); +void bitint17_zero_extend_call (unsigned _BitInt(17) x) { bitint17_zero_extend (x + 1); } + +/* { dg-final { scan-rtl-dump-times "sign_extend:DI.*reg:SI" 1 "expand" } } */ +void bitint17_sign_extend (_BitInt(17) x); +void bitint17_sign_extend_call (_BitInt(17) x) { bitint17_sign_extend (x + 1); } diff --git a/gcc/testsuite/gcc.target/s390/bitint-4.c b/gcc/testsuite/gcc.target/s390/bitint-4.c new file mode 100644 index 0000000..dce72d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/bitint-4.c @@ -0,0 +1,71 @@ +/* { dg-do compile { target bitint } } */ +/* { dg-options "-march=z9-109 -O2" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +/* Verify calling convention. */ + +struct s_bitint5 { + short a; + unsigned _BitInt(5) b; + char c; +}; + +static_assert (sizeof (struct s_bitint5) == 4); + +/* +** s_bitint5_call: +** iilf %r2,2758168 +** jg s_bitint5@PLT +*/ + +void s_bitint5 (struct s_bitint5 x); +void s_bitint5_call (void) { s_bitint5 ((struct s_bitint5){42, 22wbu, 24}); } + +struct s_bitint9 { + short a; + unsigned _BitInt(9) b; +}; + +static_assert (sizeof (struct s_bitint9) == 4); + +/* +** s_bitint9_call: +** iilf %r2,2752934 +** jg s_bitint9@PLT +*/ + +void s_bitint9 (struct s_bitint9 x); +void s_bitint9_call (void) { s_bitint9 ((struct s_bitint9){42, 422wbu}); } + +struct s_bitint17 { + int a; + unsigned _BitInt(17) b; +}; + +static_assert (sizeof (struct s_bitint17) == 8); + +/* +** s_bitint17_call: +** llihl %r2,42 +** oilf %r2,108198 +** jg s_bitint17@PLT +*/ + +void s_bitint17 (struct s_bitint17 x); +void s_bitint17_call (void) { s_bitint17 ((struct s_bitint17){42, 108198wbu}); } + +struct s_bitint33 { + unsigned _BitInt(33) b; +}; + +static_assert (sizeof (struct s_bitint33) == 8); + +/* +** s_bitint33_call: +** llihl %r2,1 +** oilf %r2,2795939494 +** jg s_bitint33@PLT +*/ + +void s_bitint33 (struct s_bitint33 x); +void s_bitint33_call (void) { s_bitint33 ((struct s_bitint33){7090906790wbu}); } diff --git a/gcc/testsuite/gcc.target/s390/spaceship-fp-1.c b/gcc/testsuite/gcc.target/s390/spaceship-fp-1.c new file mode 100644 index 0000000..34b9ba6 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-fp-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mzarch -march=z13 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, -128\)} 3 optimized } } */ +/* { dg-final { scan-assembler-times {\tk[edx]br\t} 3 } } */ +/* { dg-final { scan-assembler-not {\tbrc} } } */ +/* { dg-final { scan-assembler-not {\tc[edx]br\t} } } */ + +#define TEST(T, U) \ + int test_##U (T x, T y) \ + { \ + if (x == y) \ + return 0; \ + else if (x < y) \ + return -1; \ + else if (x > y) \ + return 1; \ + else \ + return -128; \ + } + +TEST (float, float) +TEST (double, double) +TEST (long double, longdouble) diff --git a/gcc/testsuite/gcc.target/s390/spaceship-fp-2.c b/gcc/testsuite/gcc.target/s390/spaceship-fp-2.c new file mode 100644 index 0000000..6fe4d22 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-fp-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mzarch -march=z13 -ffinite-math-only -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, -128\)} 3 optimized } } */ +/* { dg-final { scan-assembler-times {\tc[edx]br\t} 3 } } */ +/* { dg-final { scan-assembler-not {\tbrc} } } */ +/* { dg-final { scan-assembler-not {\tk[edx]br\t} } } */ + +#define TEST(T, U) \ + int test_##U (T x, T y) \ + { \ + if (x == y) \ + return 0; \ + else if (x < y) \ + return -1; \ + else if (x > y) \ + return 1; \ + else \ + return -128; \ + } + +TEST (float, float) +TEST (double, double) +TEST (long double, longdouble) diff --git a/gcc/testsuite/gcc.target/s390/spaceship-fp-3.c b/gcc/testsuite/gcc.target/s390/spaceship-fp-3.c new file mode 100644 index 0000000..2f567d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-fp-3.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mzarch -march=z13 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 42\)} 3 optimized } } */ +/* { dg-final { scan-assembler-times {\tk[edx]br\t} 3 } } */ +/* { dg-final { scan-assembler-not {\tbrc} } } */ +/* { dg-final { scan-assembler-not {\tc[edx]br\t} } } */ + +#define TEST(T, U) \ + int test_##U (T x, T y) \ + { \ + if (x == y) \ + return 0; \ + else if (x < y) \ + return -1; \ + else if (x > y) \ + return 1; \ + else \ + return 42; \ + } + +TEST (float, float) +TEST (double, double) +TEST (long double, longdouble) diff --git a/gcc/testsuite/gcc.target/s390/spaceship-fp-4.c b/gcc/testsuite/gcc.target/s390/spaceship-fp-4.c new file mode 100644 index 0000000..4531ecb --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-fp-4.c @@ -0,0 +1,53 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mzarch -march=z13 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 0\)} 3 optimized } } */ +/* { dg-final { scan-assembler-times {\tk[edx]br\t} 3 } } */ +/* { dg-final { scan-assembler-not {\tloc} } } */ +/* { dg-final { scan-assembler-not {\tbrc} } } */ +/* { dg-final { scan-assembler-not {\tc[edx]br\t} } } */ + +/* By time of writing this we emit + + kebr %f0,%f2 + jo .L2 + je .L3 + jnh .L10 + jg f3@PLT +.L10: + jg f2@PLT +.L3: + jg f1@PLT +.L2: + jg f4@PLT + + which is not optimal. Instead we could fold the conditional branch with the + unconditional into something along the lines + + kebr %f0,%f2 + jo f4@PLT + je f1@PLT + jnh f2@PLT + jg f3@PLT +*/ + +void f1 (void); +void f2 (void); +void f3 (void); +void f4 (void); + +#define TEST(T, U) \ + void test_##U (T x, T y) \ + { \ + if (x == y) \ + f1 (); \ + else if (x < y) \ + f2 (); \ + else if (x > y) \ + f3 (); \ + else \ + f4 (); \ + } + +TEST (float, float) +TEST (double, double) +TEST (long double, longdouble) diff --git a/gcc/testsuite/gcc.target/s390/spaceship-int-1.c b/gcc/testsuite/gcc.target/s390/spaceship-int-1.c new file mode 100644 index 0000000..8ca2677 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-int-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mzarch -march=z13 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, -1\)} 4 optimized } } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 1\)} 5 optimized } } */ +/* { dg-final { scan-assembler-times {\tlhi} 9 } } */ +/* { dg-final { scan-assembler-times {\tloc} 18 } } */ + +#define TEST(T, U) \ + int test_##U (T x, T y) \ + { \ + if (x == y) \ + return 0; \ + else if (x < y) \ + return -1; \ + else \ + return 1; \ + } + +TEST(signed char, schar) +TEST(unsigned char, uchar) +TEST(char, char) + +TEST(short, sshort) +TEST(unsigned short, ushort) + +TEST(int, sint) +TEST(unsigned int, uint) + +TEST(long, slong) +TEST(unsigned long, ulong) diff --git a/gcc/testsuite/gcc.target/s390/spaceship-int-2.c b/gcc/testsuite/gcc.target/s390/spaceship-int-2.c new file mode 100644 index 0000000..5f7975c --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-int-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -mzarch -march=z13 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, -1\)} 1 optimized } } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 1\)} 1 optimized } } */ +/* { dg-final { scan-assembler-times {\tvecg} 1 } } */ +/* { dg-final { scan-assembler-times {\tveclg} 1 } } */ +/* { dg-final { scan-assembler-times {\tvchlgs} 2 } } */ +/* { dg-final { scan-assembler-times {\tvceqgs} 2 } } */ +/* { dg-final { scan-assembler-times {\tlhi} 2 } } */ +/* { dg-final { scan-assembler-times {\tloc} 4 } } */ + +#define TEST(T, U) \ + int test_##U (T x, T y) \ + { \ + if (x == y) \ + return 0; \ + else if (x < y) \ + return -1; \ + else \ + return 1; \ + } + +TEST(__int128, sint128) +TEST(unsigned __int128, uint128) diff --git a/gcc/testsuite/gcc.target/s390/spaceship-int-3.c b/gcc/testsuite/gcc.target/s390/spaceship-int-3.c new file mode 100644 index 0000000..46b0e4a --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-int-3.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -march=z17 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, -1\)} 1 optimized } } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 1\)} 1 optimized } } */ +/* { dg-final { scan-assembler-times {\tvecq\t} 1 } } */ +/* { dg-final { scan-assembler-times {\tveclq\t} 1 } } */ +/* { dg-final { scan-assembler-times {\tloc} 4 } } */ + +#define TEST(T, U) \ + int test_##U (T x, T y) \ + { \ + if (x == y) \ + return 0; \ + else if (x < y) \ + return -1; \ + else \ + return 1; \ + } + +TEST(__int128, sint128) +TEST(unsigned __int128, uint128) diff --git a/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-1.c b/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-1.c index 11df6c1..b2cb35f 100644 --- a/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-1.c +++ b/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target s390_vx } */ +/* { dg-require-effective-target s390_mvx } */ /* { dg-additional-options "-O2" } */ /* { dg-final { scan-assembler-not {\tllg?[fhc]r\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-2.c b/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-2.c new file mode 100644 index 0000000..9bace28 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-2.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target s390_mvx } */ +/* { dg-additional-options "-O2" } */ +/* { dg-final { scan-assembler-not {\tllg?[fhc]r\t} } } */ + +typedef unsigned char __attribute__ ((vector_size (1))) V1QI; +typedef unsigned char __attribute__ ((vector_size (2))) V2QI; +typedef unsigned char __attribute__ ((vector_size (4))) V4QI; +typedef unsigned char __attribute__ ((vector_size (8))) V8QI; +typedef unsigned char __attribute__ ((vector_size (16))) V16QI; + +typedef unsigned short __attribute__ ((vector_size (2))) V1HI; +typedef unsigned short __attribute__ ((vector_size (4))) V2HI; +typedef unsigned short __attribute__ ((vector_size (8))) V4HI; +typedef unsigned short __attribute__ ((vector_size (16))) V8HI; + +typedef unsigned int __attribute__ ((vector_size (4))) V1SI; +typedef unsigned int __attribute__ ((vector_size (8))) V2SI; +typedef unsigned int __attribute__ ((vector_size (16))) V4SI; + +#define TEST(T, U) unsigned T test_ ## _ ## U (U x, int i) { return x[i]; } + +TEST (char, V1QI) +TEST (char, V2QI) +TEST (char, V4QI) +TEST (char, V8QI) +TEST (char, V16QI) + +TEST (short, V1HI) +TEST (short, V2HI) +TEST (short, V4HI) +TEST (short, V8HI) + +TEST (int, V1SI) +TEST (int, V2SI) +TEST (int, V4SI) diff --git a/gcc/testsuite/gcc.target/xtensa/bswap-SSAI8.c b/gcc/testsuite/gcc.target/xtensa/bswap-SSAI8.c new file mode 100644 index 0000000..010554b --- /dev/null +++ b/gcc/testsuite/gcc.target/xtensa/bswap-SSAI8.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +extern void foo(void); + +void test_0(volatile unsigned int a[], unsigned int b) +{ + a[0] = __builtin_bswap32(a[0]); + a[1] = a[1] >> 9; + a[2] = __builtin_bswap32(a[2]); + a[3] = a[3] << b; + a[4] = __builtin_bswap32(a[4]); + foo(); + a[5] = __builtin_bswap32(a[5]); + a[6] = __builtin_stdc_rotate_left (a[6], 13); + a[7] = __builtin_bswap32(a[7]); + asm volatile ("# asm volatile"); + a[8] = __builtin_bswap32(a[8]); + a[9] = (a[9] << 9) | (b >> 23); + a[10] = __builtin_bswap32(a[10]); +} + +void test_1(volatile unsigned long long a[]) +{ + a[0] = __builtin_bswap64(a[0]); + a[1] = __builtin_bswap64(a[1]); +} + +/* { dg-final { scan-assembler-times "ssai\t8" 7 } } */ |