diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/riscv')
297 files changed, 5161 insertions, 191 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/add-synthesis-1.c b/gcc/testsuite/gcc.target/riscv/add-synthesis-1.c new file mode 100644 index 0000000..247096c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/add-synthesis-1.c @@ -0,0 +1,40 @@ +/* { dg-options "-march=rv32gcb -mabi=ilp32d" { target { rv32 } } } */ +/* { dg-options "-march=rv64gcb -mabi=lp64d" { target { rv64 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + + + +#if __riscv_xlen == 64 +#define TYPE long +#else +#define TYPE int +#endif + +#define T(C) TYPE foo_##C (TYPE x) { return x + C; } +#define TM(C) TYPE foo_M##C (TYPE x) { return x + -C; } + +/* These cases were selected because they all can be synthesized + at expansion time without synthesizing the constant directly. + + That makes the assembler scan testing simpler. I've verified + by hand that cases that should synthesize the constant do in + fact still generate code that way. */ +T (2050) +T (4094) +T (4100) +T (8200) + +TM (2049) +TM (4096) +TM (4100) +TM (8200) + +#if __riscv_xlen == 64 +TM (0x200000000) +#endif + +/* We have 4/5 tests which should use shNadd insns and 4 + which used paired addi insns. */ +/* { dg-final { scan-assembler-times "sh.add\t" 4 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "sh.add\t" 5 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "addi\t" 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/add-synthesis-2.c b/gcc/testsuite/gcc.target/riscv/add-synthesis-2.c new file mode 100644 index 0000000..a047615 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/add-synthesis-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target rv64 } } */ +/* { dg-options "-march=rv64gcb -mabi=lp64d" { target { rv64 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + + + +#define T(C) int foo_##C (int x) { return x + C; } +#define TM(C) int foo_M##C (int x) { return x + -C; } + +/* These cases were selected because they all can be synthesized + at expansion time without synthesizing the constant directly. + + That makes the assembler scan testing simpler. I've verified + by hand that cases that should synthesize the constant do in + fact still generate code that way. */ +T (2050) +T (4094) + +TM (2049) +TM (4096) + +/* We have 4/5 tests which should use shNadd insns and 4 + which used paired addi insns. */ +/* { dg-final { scan-assembler-times "addiw\t" 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/amo/pr121213.c b/gcc/testsuite/gcc.target/riscv/amo/pr121213.c new file mode 100644 index 0000000..3b2d694 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo/pr121213.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc -mabi=lp64" { target { rv64 } } } */ +/* { dg-options "-O2 -march=rv32gc -mabi=ilp32" { target { rv32 } } } */ + +void test0(unsigned long* lock) { + while (!__atomic_exchange_n(lock, 0, __ATOMIC_ACQUIRE)); +} + + +void test1(unsigned* lock) { + while (!__atomic_exchange_n(lock, 0, __ATOMIC_ACQUIRE)); +} + +/* { dg-final { scan-assembler-not "\tli" } } */ +/* { dg-final { scan-assembler-times "\tamoswap...aq\t\[axt\]\[0-9\],zero," 2 } } */ +/* { dg-final { scan-assembler-not "\tsext" { xfail *-*-* } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/arch-25.c b/gcc/testsuite/gcc.target/riscv/arch-25.c index 9201883..ca4d0ee 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-25.c +++ b/gcc/testsuite/gcc.target/riscv/arch-25.c @@ -1,5 +1,4 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64i_zcf -mabi=lp64" } */ int foo() {} -/* { dg-error "'-march=rv64i_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv64ic_zca_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64.*zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-ss-2.c b/gcc/testsuite/gcc.target/riscv/arch-ss-2.c index f1d7724..457063b 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-ss-2.c +++ b/gcc/testsuite/gcc.target/riscv/arch-ss-2.c @@ -3,13 +3,8 @@ int foo() { } -/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': ssnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': smnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': smmpm extension supports in rv64 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': sspm extension supports in rv64 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': supm extension supports in rv64 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': ssnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': smnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': smmpm extension supports in rv64 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': sspm extension supports in rv64 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': supm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32.\*ssnpm.*': ssnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32.\*smnpm.*': smnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32.\*smmpm.*': smmpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32.\*sspm.*': sspm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32.\*supm.*': supm extension supports in rv64 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-1.c b/gcc/testsuite/gcc.target/riscv/arch-unset-1.c new file mode 100644 index 0000000..971b936 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-unset-1.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i -march=unset -mcpu=sifive-x280 -mabi=lp64 -misa-spec=20191213" } */ +int foo() +{ +} + +/* { dg-final { scan-assembler "\.attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-2.c b/gcc/testsuite/gcc.target/riscv/arch-unset-2.c new file mode 100644 index 0000000..9840658 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-unset-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i -march=unset -mcpu=sifive-x280 -march=rv64i -mabi=lp64 -misa-spec=20191213" } */ +int foo() +{ +} + +/* { dg-final { scan-assembler "\.attribute arch, \"rv64i2p1\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-3.c b/gcc/testsuite/gcc.target/riscv/arch-unset-3.c new file mode 100644 index 0000000..5ddc224 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-unset-3.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i -march=unset -mcpu=sifive-x280 -march=rv64i -march=unset -mabi=lp64 -misa-spec=20191213" } */ +int foo() +{ +} + +/* { dg-final { scan-assembler "\.attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-4.c b/gcc/testsuite/gcc.target/riscv/arch-unset-4.c new file mode 100644 index 0000000..c16821d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-unset-4.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i -march=unset -mcpu=sifive-x280 -march=unset -march=rv64i -march=unset -march=rv64i -mabi=lp64 -misa-spec=20191213" } */ +int foo() +{ +} + +/* { dg-final { scan-assembler "\.attribute arch, \"rv64i2p1\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-5.c b/gcc/testsuite/gcc.target/riscv/arch-unset-5.c new file mode 100644 index 0000000..368c129 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-unset-5.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i -march=unset -mabi=lp64 -misa-spec=20191213" } */ +int foo() +{ +} + +/* { dg-error "At least one valid -mcpu option must be given after -march=unset" "" { target { "riscv*-*-*" } } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c b/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c index 5d6185d..585395e 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c +++ b/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c @@ -3,5 +3,4 @@ int foo() { } -/* { dg-error "'-march=rv64gc_zilsd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv64imafdc_zicsr_zifencei_zilsd_zmmul_zaamo_zalrsc_zca_zcd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64g.*zilsd.*': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-zilsd-3.c b/gcc/testsuite/gcc.target/riscv/arch-zilsd-3.c index 3cda120..3328599 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-zilsd-3.c +++ b/gcc/testsuite/gcc.target/riscv/arch-zilsd-3.c @@ -3,7 +3,5 @@ int foo() { } -/* { dg-error "'-march=rv64gc_zclsd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv64gc_zclsd': zclsd extension supports in rv32 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv64imafdc_zicsr_zifencei_zilsd_zmmul_zaamo_zalrsc_zca_zcd_zclsd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv64imafdc_zicsr_zifencei_zilsd_zmmul_zaamo_zalrsc_zca_zcd_zclsd': zclsd extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64.*zclsd.*': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64.*zclsd.*': zclsd extension supports in rv32 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c index bb9e310..c96d0b5 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c @@ -4,7 +4,7 @@ /* XuanTie C908v => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_ zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_sstc_svinval_svnapot_svpbmt_xtheadba_ xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_ -xtheadmemidx_xtheadmempair_xtheadsync_xtheadvdot */ +xtheadmemidx_xtheadmempair_xtheadsync */ #if !((__riscv_xlen == 64) \ && !defined(__riscv_32e) \ @@ -39,8 +39,7 @@ xtheadmemidx_xtheadmempair_xtheadsync_xtheadvdot */ && defined(__riscv_xtheadmac) \ && defined(__riscv_xtheadmemidx) \ && defined(__riscv_xtheadmempair) \ - && defined(__riscv_xtheadsync) \ - && defined (__riscv__xtheadvdot)) + && defined(__riscv_xtheadsync)) #error "unexpected arch" #endif diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c index 1f21d07..806949e 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ /* { dg-options "-mcpu=xt-c920v2" { target { rv64 } } } */ -/* XuanTie C920v2 => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_zbs_zvfbfmin_zvfbfwma_zvfh_sscofpmf_sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadsync_xtheadvdot */ +/* XuanTie C920v2 => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_zbs_zvfbfmin_zvfbfwma_zvfh_sscofpmf_sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadsync */ #if !((__riscv_xlen == 64) \ && !defined(__riscv_32e) \ @@ -45,8 +45,7 @@ && defined(__riscv_xtheadcmo) \ && defined(__riscv_xtheadcondmov) \ && defined(__riscv_xtheadfmemidx) \ - && defined(__riscv_xtheadsync) \ - && defined(__riscv_xtheadvdot)) + && defined(__riscv_xtheadsync)) #error "unexpected arch" #endif diff --git a/gcc/testsuite/gcc.target/riscv/mipsprefetch.c b/gcc/testsuite/gcc.target/riscv/mipsprefetch.c new file mode 100644 index 0000000..b58aa0f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mipsprefetch.c @@ -0,0 +1,31 @@ +/* pic used here to prevent the assembler to emit .nopic directive. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv32imafd_xmipscbop -fpic" { target { rv32 } } } */ +/* { dg-options "-march=rv64imafd_xmipscbop -fpic -mabi=lp64d" { target { rv64 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + + +void prefetch_read(char *a) +{ + __builtin_prefetch (&a[3], 0, 0); +} + +void prefetch_write(char *a) +{ + __builtin_prefetch (&a[1], 1, 0); +} + +void prefetch_read_out_range_offset(char *a) +{ + __builtin_prefetch (&a[512], 0, 1); +} + +void prefetch_write_out_range_offset(char *a) +{ + __builtin_prefetch (&a[1024], 1, 1); +} + +/* { dg-final { scan-assembler-times "mips.pref\t8,0\\(\[a-x0-9\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "mips.pref\t8,3\\(\[a-x0-9\]+\\)" 1 } } */ +/* { dg-final { scan-assembler-times "nop" 2 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/nozicond-2.c b/gcc/testsuite/gcc.target/riscv/nozicond-2.c index f705253..588d41a 100644 --- a/gcc/testsuite/gcc.target/riscv/nozicond-2.c +++ b/gcc/testsuite/gcc.target/riscv/nozicond-2.c @@ -9,7 +9,7 @@ long foo2 (long c) { return c >= 0 ? -1 : 1; } /* We don't support 4->3 splitters, so this fails. We could perhaps try to catch it in the expander as a special case rather than waiting for combine. */ -/* { dg-final { scan-assembler-times {srai\t} 2 { xfail *-*-* } } } */ -/* { dg-final { scan-assembler-times {ori\t} 2 { xfail *-*-* } } } */ -/* { dg-final { scan-assembler-times {not\t} 2 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {srai\t} 2 } } */ +/* { dg-final { scan-assembler-times {ori\t} 2 } } */ +/* { dg-final { scan-assembler-times {not\t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr116085.c b/gcc/testsuite/gcc.target/riscv/pr116085.c index 998d82bd..880f835 100644 --- a/gcc/testsuite/gcc.target/riscv/pr116085.c +++ b/gcc/testsuite/gcc.target/riscv/pr116085.c @@ -1,5 +1,4 @@ -/* { dg-do run } */ -/* { dg-require-effective-target rv64 } */ +/* { dg-do run { target { rv64 && riscv_b_ok } } } */ /* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-ext-dce" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/riscv/pr117690.c b/gcc/testsuite/gcc.target/riscv/pr117690.c index 9c06ab4..d0784a1 100644 --- a/gcc/testsuite/gcc.target/riscv/pr117690.c +++ b/gcc/testsuite/gcc.target/riscv/pr117690.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv64*-*-* } } } */ +/* { dg-do run { target { rv64 && riscv_b_ok } } } */ /* { dg-options "-march=rv64gc_zba_zbb -mabi=lp64d" } */ #define myconst 0x4fffaffb0fffefffUL; diff --git a/gcc/testsuite/gcc.target/riscv/pr119275.c b/gcc/testsuite/gcc.target/riscv/pr119275.c new file mode 100644 index 0000000..02a1a7b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr119275.c @@ -0,0 +1,26 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-march=rv64gv -mabi=lp64d -mrvv-vector-bits=zvl" { target { rv64 } } } */ + +__int128 h, j; +int y; +double d; +void *p; +char *q; +char x; +long u; + +char *bar(int, int); + +typedef __attribute__((__vector_size__ (2))) char V; + +void +foo(V v) +{ + x += *bar (0, 0); + for(;;) { + __builtin_strcat (p, 7 + q); + d += __builtin_stdc_rotate_left ( + (unsigned __int128) u | h << *__builtin_strcat (p, 7 + q), j); + u += (long) __builtin_memmove (&y, &v, 2); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/pr120333.c b/gcc/testsuite/gcc.target/riscv/pr120333.c index 17b376f..3417d22 100644 --- a/gcc/testsuite/gcc.target/riscv/pr120333.c +++ b/gcc/testsuite/gcc.target/riscv/pr120333.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { rv64 } } } */ +/* { dg-do run { target { rv64 && riscv_b_ok } } } */ /* { dg-additional-options "-march=rv64gcb -std=gnu23" } */ __attribute__ ((noipa)) _Bool diff --git a/gcc/testsuite/gcc.target/riscv/pr120553-1.c b/gcc/testsuite/gcc.target/riscv/pr120553-1.c new file mode 100644 index 0000000..95ff1d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120553-1.c @@ -0,0 +1,90 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb_zicond -mbranch-cost=3 -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb_zicond -mbranch-cost=3 -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define ONE 1U +#define TYPE int +#else +#define ONE 1ULL +#define TYPE long +#endif + +#define T1(N) TYPE test1_##N (TYPE c) { return c < 0 ? -ONE : (ONE << N); } \ + TYPE test2_##N (TYPE c) { return c >= 0 ? (ONE << N) : -ONE; } \ + +T1(0) +T1(1) +T1(2) +T1(3) +T1(4) +T1(5) +T1(6) +T1(7) +T1(8) +T1(9) +T1(10) +T1(11) +T1(12) +T1(13) +T1(14) +T1(15) +T1(16) +T1(17) +T1(18) +T1(19) +T1(20) +T1(21) +T1(22) +T1(23) +T1(24) +T1(25) +T1(26) +T1(27) +T1(28) +T1(29) +T1(30) +T1(31) +#if __riscv_xlen == 64 +T1(32) +T1(33) +T1(34) +T1(35) +T1(36) +T1(37) +T1(38) +T1(39) +T1(40) +T1(41) +T1(42) +T1(43) +T1(44) +T1(45) +T1(46) +T1(47) +T1(48) +T1(49) +T1(50) +T1(51) +T1(52) +T1(53) +T1(54) +T1(55) +T1(56) +T1(57) +T1(58) +T1(59) +T1(60) +T1(61) +T1(62) +T1(63) +#endif + +/* { dg-final { scan-assembler-times "\\t(srai)" 128 { target rv64 } } } */ +/* { dg-final { scan-assembler-times "\\t(ori|bset)" 128 { target rv64 } } } */ + +/* { dg-final { scan-assembler-times "\\t(srai)" 64 { target rv32 } } } */ +/* { dg-final { scan-assembler-times "\\t(ori|bset)" 64 { target rv32 } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/pr120553-2.c b/gcc/testsuite/gcc.target/riscv/pr120553-2.c new file mode 100644 index 0000000..1501f86 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120553-2.c @@ -0,0 +1,90 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb_zicond -mbranch-cost=3 -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb_zicond -mbranch-cost=3 -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define ONE 1U +#define TYPE int +#else +#define ONE 1ULL +#define TYPE long +#endif + +#define T1(N) TYPE test1_##N (TYPE c) { return c >= 0 ? -ONE : (ONE << N); } \ + TYPE test2_##N (TYPE c) { return c < 0 ? (ONE << N) : -ONE; } \ + +T1(0) +T1(1) +T1(2) +T1(3) +T1(4) +T1(5) +T1(6) +T1(7) +T1(8) +T1(9) +T1(10) +T1(11) +T1(12) +T1(13) +T1(14) +T1(15) +T1(16) +T1(17) +T1(18) +T1(19) +T1(20) +T1(21) +T1(22) +T1(23) +T1(24) +T1(25) +T1(26) +T1(27) +T1(28) +T1(29) +T1(30) +T1(31) +#if __riscv_xlen == 64 +T1(32) +T1(33) +T1(34) +T1(35) +T1(36) +T1(37) +T1(38) +T1(39) +T1(40) +T1(41) +T1(42) +T1(43) +T1(44) +T1(45) +T1(46) +T1(47) +T1(48) +T1(49) +T1(50) +T1(51) +T1(52) +T1(53) +T1(54) +T1(55) +T1(56) +T1(57) +T1(58) +T1(59) +T1(60) +T1(61) +T1(62) +T1(63) +#endif + +/* { dg-final { scan-assembler-times "\\t(srai)" 128 { target rv64 } } } */ +/* { dg-final { scan-assembler-times "\\t(orn|ori|bset)" 128 { target rv64 } } } */ + +/* { dg-final { scan-assembler-times "\\t(srai)" 64 { target rv32 } } } */ +/* { dg-final { scan-assembler-times "\\t(orn|ori|bset)" 64 { target rv32 } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/pr120553-3.c b/gcc/testsuite/gcc.target/riscv/pr120553-3.c new file mode 100644 index 0000000..09ec714 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120553-3.c @@ -0,0 +1,90 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb_zicond -mbranch-cost=3 -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb_zicond -mbranch-cost=3 -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define ONE 1U +#define TYPE int +#else +#define ONE 1ULL +#define TYPE long +#endif + +#define T1(N) TYPE test1_##N (TYPE c) { return c < 0 ? -ONE : 0xff; } \ + TYPE test2_##N (TYPE c) { return c >= 0 ? 0xff : -ONE; } \ + +T1(0) +T1(1) +T1(2) +T1(3) +T1(4) +T1(5) +T1(6) +T1(7) +T1(8) +T1(9) +T1(10) +T1(11) +T1(12) +T1(13) +T1(14) +T1(15) +T1(16) +T1(17) +T1(18) +T1(19) +T1(20) +T1(21) +T1(22) +T1(23) +T1(24) +T1(25) +T1(26) +T1(27) +T1(28) +T1(29) +T1(30) +T1(31) +#if __riscv_xlen == 64 +T1(32) +T1(33) +T1(34) +T1(35) +T1(36) +T1(37) +T1(38) +T1(39) +T1(40) +T1(41) +T1(42) +T1(43) +T1(44) +T1(45) +T1(46) +T1(47) +T1(48) +T1(49) +T1(50) +T1(51) +T1(52) +T1(53) +T1(54) +T1(55) +T1(56) +T1(57) +T1(58) +T1(59) +T1(60) +T1(61) +T1(62) +T1(63) +#endif + +/* { dg-final { scan-assembler-times "\\t(srai)" 128 { target rv64 } } } */ +/* { dg-final { scan-assembler-times "\\t(ori|bset)" 128 { target rv64 } } } */ + +/* { dg-final { scan-assembler-times "\\t(srai)" 64 { target rv32 } } } */ +/* { dg-final { scan-assembler-times "\\t(ori|bset)" 64 { target rv32 } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/pr120553-4.c b/gcc/testsuite/gcc.target/riscv/pr120553-4.c new file mode 100644 index 0000000..bc8c1b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120553-4.c @@ -0,0 +1,90 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb_zicond -mbranch-cost=3 -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb_zicond -mbranch-cost=3 -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define ONE 1U +#define TYPE int +#else +#define ONE 1ULL +#define TYPE long +#endif + +#define T1(N) TYPE test1_##N (TYPE c) { return c < 0 ? -ONE : 0x7ff; } \ + TYPE test2_##N (TYPE c) { return c >= 0 ? 0x7ff : -ONE; } \ + +T1(0) +T1(1) +T1(2) +T1(3) +T1(4) +T1(5) +T1(6) +T1(7) +T1(8) +T1(9) +T1(10) +T1(11) +T1(12) +T1(13) +T1(14) +T1(15) +T1(16) +T1(17) +T1(18) +T1(19) +T1(20) +T1(21) +T1(22) +T1(23) +T1(24) +T1(25) +T1(26) +T1(27) +T1(28) +T1(29) +T1(30) +T1(31) +#if __riscv_xlen == 64 +T1(32) +T1(33) +T1(34) +T1(35) +T1(36) +T1(37) +T1(38) +T1(39) +T1(40) +T1(41) +T1(42) +T1(43) +T1(44) +T1(45) +T1(46) +T1(47) +T1(48) +T1(49) +T1(50) +T1(51) +T1(52) +T1(53) +T1(54) +T1(55) +T1(56) +T1(57) +T1(58) +T1(59) +T1(60) +T1(61) +T1(62) +T1(63) +#endif + +/* { dg-final { scan-assembler-times "\\t(srai)" 128 { target rv64 } } } */ +/* { dg-final { scan-assembler-times "\\t(ori|bset)" 128 { target rv64 } } } */ + +/* { dg-final { scan-assembler-times "\\t(srai)" 64 { target rv32 } } } */ +/* { dg-final { scan-assembler-times "\\t(ori|bset)" 64 { target rv32 } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/pr120553-5.c b/gcc/testsuite/gcc.target/riscv/pr120553-5.c new file mode 100644 index 0000000..1e48330 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120553-5.c @@ -0,0 +1,91 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb_zicond -mbranch-cost=3 -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb_zicond -mbranch-cost=3 -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define ONE 1U +#define TYPE int +#else +#define ONE 1ULL +#define TYPE long +#endif + +#define T1(N) TYPE test1_##N (TYPE c) { return c < 0 ? ~(ONE << N) : 0; } \ + TYPE test2_##N (TYPE c) { return c >= 0 ? 0 : ~(ONE << N); } \ + +T1(0) +T1(1) +T1(2) +T1(3) +T1(4) +T1(5) +T1(6) +T1(7) +T1(8) +T1(9) +T1(10) +T1(11) +T1(12) +T1(13) +T1(14) +T1(15) +T1(16) +T1(17) +T1(18) +T1(19) +T1(20) +T1(21) +T1(22) +T1(23) +T1(24) +T1(25) +T1(26) +T1(27) +T1(28) +T1(29) +T1(30) +T1(31) +#if __riscv_xlen == 64 +T1(32) +T1(33) +T1(34) +T1(35) +T1(36) +T1(37) +T1(38) +T1(39) +T1(40) +T1(41) +T1(42) +T1(43) +T1(44) +T1(45) +T1(46) +T1(47) +T1(48) +T1(49) +T1(50) +T1(51) +T1(52) +T1(53) +T1(54) +T1(55) +T1(56) +T1(57) +T1(58) +T1(59) +T1(60) +T1(61) +T1(62) +T1(63) +#endif + +/* The MSB case isn't handled the way we want. */ +/* { dg-final { scan-assembler-times "\\t(srai)" 126 { target rv64 } } } */ +/* { dg-final { scan-assembler-times "\\t(slli|andi|bclr)" 126 { target rv64 } } } */ + +/* { dg-final { scan-assembler-times "\\t(srai)" 62 { target rv32 } } } */ +/* { dg-final { scan-assembler-times "\\t(slli|andi|bclr)" 62 { target rv32 } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/pr120553-6.c b/gcc/testsuite/gcc.target/riscv/pr120553-6.c new file mode 100644 index 0000000..6c409af --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120553-6.c @@ -0,0 +1,91 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb_zicond -mbranch-cost=3 -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb_zicond -mbranch-cost=3 -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define ONE 1U +#define TYPE int +#else +#define ONE 1ULL +#define TYPE long +#endif + +#define T1(N) TYPE test1_##N (TYPE c) { return c >= 0 ? ~(ONE << N) : 0; } \ + TYPE test2_##N (TYPE c) { return c < 0 ? 0 : ~(ONE << N); } \ + +T1(0) +T1(1) +T1(2) +T1(3) +T1(4) +T1(5) +T1(6) +T1(7) +T1(8) +T1(9) +T1(10) +T1(11) +T1(12) +T1(13) +T1(14) +T1(15) +T1(16) +T1(17) +T1(18) +T1(19) +T1(20) +T1(21) +T1(22) +T1(23) +T1(24) +T1(25) +T1(26) +T1(27) +T1(28) +T1(29) +T1(30) +T1(31) +#if __riscv_xlen == 64 +T1(32) +T1(33) +T1(34) +T1(35) +T1(36) +T1(37) +T1(38) +T1(39) +T1(40) +T1(41) +T1(42) +T1(43) +T1(44) +T1(45) +T1(46) +T1(47) +T1(48) +T1(49) +T1(50) +T1(51) +T1(52) +T1(53) +T1(54) +T1(55) +T1(56) +T1(57) +T1(58) +T1(59) +T1(60) +T1(61) +T1(62) +T1(63) +#endif + +/* Not working for the high bit case yet. */ +/* { dg-final { scan-assembler-times "\\t(srai)" 126 { target rv64 } } } */ +/* { dg-final { scan-assembler-times "\\t(andn|andi|bclr)" 126 { target rv64 } } } */ + +/* { dg-final { scan-assembler-times "\\t(srai)" 62 { target rv32 } } } */ +/* { dg-final { scan-assembler-times "\\t(andn|andi|bclr)" 62 { target rv32 } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/pr120553-7.c b/gcc/testsuite/gcc.target/riscv/pr120553-7.c new file mode 100644 index 0000000..27953f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120553-7.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb_zicond -mbranch-cost=3 -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb_zicond -mbranch-cost=3 -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define TYPE int +#else +#define TYPE long +#endif + +#define T1(N) TYPE test1_##N (TYPE c) { return c < 0 ? ~0xff : 0; } \ + TYPE test2_##N (TYPE c) { return c >= 0 ? 0 : ~0xff; } \ + +T1(0) + +/* { dg-final { scan-assembler-times "\\t(srai)" 2 } } */ +/* { dg-final { scan-assembler-times "\\t(slli|andi|bclr)" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr120553-8.c b/gcc/testsuite/gcc.target/riscv/pr120553-8.c new file mode 100644 index 0000000..90bec45 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120553-8.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb_zicond -mbranch-cost=3 -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb_zicond -mbranch-cost=3 -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define TYPE int +#else +#define TYPE long +#endif + +#define T1(N) TYPE test1_##N (TYPE c) { return c < 0 ? ~0x7ff : 0; } \ + TYPE test2_##N (TYPE c) { return c >= 0 ? 0 : ~0x7ff; } \ + +T1(0) + +/* { dg-final { scan-assembler-times "\\t(srai)" 2 } } */ +/* { dg-final { scan-assembler-times "\\t(slli|andi|bclr)" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr121113.c b/gcc/testsuite/gcc.target/riscv/pr121113.c new file mode 100644 index 0000000..091fa82 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr121113.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c23 -mcpu=xiangshan-kunminghu" } */ + +_Float16 f, g; +void foo() { f /= g; } diff --git a/gcc/testsuite/gcc.target/riscv/pr121160.c b/gcc/testsuite/gcc.target/riscv/pr121160.c new file mode 100644 index 0000000..93cca8a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr121160.c @@ -0,0 +1,60 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -ffast-math -O2" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32d -ffast-math -O2" { target { rv32 } } } */ + + +typedef long int ssize_t; +typedef float MagickRealType; +typedef unsigned short Quantum; +typedef unsigned long long MagickSizeType; +typedef struct _PixelPacket +{ + Quantum blue, green, red, opacity; +} PixelPacket; +static inline Quantum +ClampToQuantum (const MagickRealType value) +{ + if (value <= 0.0f) + return ((Quantum) 0); + if (value >= (MagickRealType) ((Quantum) 65535)) + return (((Quantum) 65535)); + return ((Quantum) (value + 0.5f)); +} + +static inline float +HalfToSinglePrecision (const unsigned short half) +{ + typedef union _SinglePrecision + { + unsigned int fixed_point; + float single_precision; + } SinglePrecision; + register unsigned int exponent, significand, sign_bit; + SinglePrecision map; + unsigned int value; + if (significand == 0) + value = sign_bit << 31; + else + { + while ((significand & 0x00000400) == 0) + { + significand <<= 1; + } + value = (sign_bit << 31) | (exponent << 23) | (significand << 13); + } + map.fixed_point = value; + return (map.single_precision); +} + +void +ImportBlueQuantum (const MagickSizeType number_pixels, + PixelPacket *restrict q) +{ + register ssize_t x; + unsigned short pixel; + { + for (x = 0; x < (ssize_t) number_pixels; x++) + q->blue = ClampToQuantum (HalfToSinglePrecision (pixel)); + } +} + diff --git a/gcc/testsuite/gcc.target/riscv/pr121531.c b/gcc/testsuite/gcc.target/riscv/pr121531.c new file mode 100644 index 0000000..32c6957 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr121531.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-mcpu=sifive-p670" } */ + +__attribute__((__vector_size__(sizeof(int)))) int v; +void foo() { v &= 1; } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c index fab8e79..ca0ea0b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c @@ -5,7 +5,7 @@ /* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */ /* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */ -/* { dg-final { scan-assembler-times {\tvfadd\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfadd\.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvfadd\.vv} 9 } } */ +/* { dg-final { scan-assembler-not {\tvfadd\.vf} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 9 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c index 80bdb68..c839ac7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c @@ -5,7 +5,7 @@ /* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */ /* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */ -/* { dg-final { scan-assembler-times {\tvfadd\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfadd\.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvfadd\.vv} 9 } } */ +/* { dg-final { scan-assembler-not {\tvfadd\.vf} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 9 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c index 7197bf2..70f2651 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c @@ -4,6 +4,6 @@ #include "vmul-template.h" /* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */ -/* { dg-final { scan-assembler-times {\tvfmul\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfmul\.vf} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfmul\.vv} 6 } } */ +/* { dg-final { scan-assembler-not {\tvfmul\.vf} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 6 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c index a9c7f9b..01eb7e7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c @@ -4,6 +4,6 @@ #include "vmul-template.h" /* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */ -/* { dg-final { scan-assembler-times {\tvfmul\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfmul\.vf} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfmul\.vv} 6 } } */ +/* { dg-final { scan-assembler-not {\tvfmul\.vf} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 6 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c index 28b9235..c57ac80 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c @@ -6,9 +6,9 @@ /* { dg-final { scan-assembler-times {\tvsub\.vv} 16 } } */ /* { dg-final { scan-assembler-times {\tvrsub\.vi} 16 } } */ -/* { dg-final { scan-assembler-times {\tvfsub\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfsub\.vf} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfrsub\.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvfsub\.vv} 12 } } */ +/* { dg-final { scan-assembler-not {\tvfsub\.vf} } } */ +/* { dg-final { scan-assembler-not {\tvfrsub\.vf} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 12 "optimized" } } */ /* Do not expect vfrsub for now, because we do not properly diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c index b048949..a79d727 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c @@ -6,9 +6,9 @@ /* { dg-final { scan-assembler-times {\tvsub\.vv} 16 } } */ /* { dg-final { scan-assembler-times {\tvrsub\.vi} 16 } } */ -/* { dg-final { scan-assembler-times {\tvfsub\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfsub\.vf} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfrsub\.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvfsub\.vv} 12 } } */ +/* { dg-final { scan-assembler-not {\tvfsub\.vf} } } */ +/* { dg-final { scan-assembler-not {\tvfrsub\.vf} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 12 "optimized" } } */ /* Do not expect vfrsub for now, because we do not properly diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c index b9cfc23..850679e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c @@ -3,13 +3,13 @@ #include "cond_copysign-template.h" -/* { dg-final { scan-assembler-times {\tvfsgnj\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfsgnj\.vf} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfsgnj\.vv} 6 } } */ +/* { dg-final { scan-assembler-not {\tvfsgnj\.vf} } } */ /* 1. The vectorizer wraps scalar variants of copysign into vector constants which expand cannot handle currently. 2. match.pd convert .COPYSIGN (1, b) + COND_MUL to AND + XOR currently. */ /* { dg-final { scan-assembler-times {\tvfsgnjx\.vv} 6 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfsgnjn\.vf} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 6 } } */ +/* { dg-final { scan-assembler-not {\tvfsgnjn\.vf} } } */ /* { dg-final { scan-assembler-not {\tvmerge\.vvm} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c index f9f63eb..84c6c45 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c @@ -3,13 +3,13 @@ #include "cond_copysign-template.h" -/* { dg-final { scan-assembler-times {\tvfsgnj\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfsgnj\.vf} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfsgnj\.vv} 6 } } */ +/* { dg-final { scan-assembler-not {\tvfsgnj\.vf} } } */ /* 1. The vectorizer wraps scalar variants of copysign into vector constants which expand cannot handle currently. 2. match.pd convert .COPYSIGN (1, b) + COND_MUL to AND + XOR currently. */ /* { dg-final { scan-assembler-times {\tvfsgnjx\.vv} 6 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfsgnjn\.vf} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 6 } } */ +/* { dg-final { scan-assembler-not {\tvfsgnjn\.vf} } } */ /* { dg-final { scan-assembler-not {\tvmerge\.vvm} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c index 1aac306..02dc6b8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 18 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */ +/* { dg-final { scan-assembler-not {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c index 947e43c..7adedf9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c @@ -28,6 +28,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 12 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 12 } } */ +/* { dg-final { scan-assembler-not {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c index 8a8d7d0..d414f21 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 18 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */ +/* { dg-final { scan-assembler-not {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c index e282d2c..97d7415 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 18 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */ +/* { dg-final { scan-assembler-not {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c index ef8631d..faee13b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c @@ -29,11 +29,11 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vmadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vmadd\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vnmsub\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmadd\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vmadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vmadd\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vnmsub\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vfmadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmadd\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* { dg-final { scan-assembler-times {vfnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c index e3aaba2..1ea22fa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c @@ -29,11 +29,11 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* { dg-final { scan-assembler-times {vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c index f91bec1..a487023 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c @@ -29,11 +29,11 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* { dg-final { scan-assembler-times {vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c index 381d405..3f2689f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c @@ -28,12 +28,12 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* { dg-final { scan-assembler-times {vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ /* NOTE: 14 vmerge is need for other purpose. */ /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c index cb878167..da20ad8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c @@ -29,12 +29,12 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ +/* { dg-final { scan-assembler-not {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */ +/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* { dg-final { scan-assembler-times {vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ /* NOTE: 14 vmerge is need for other purpose. */ /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c index 95368ad..d34c190 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c index c07b331..b9db723 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c index a01ba8d..473689c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c index 9aabfb5..e41af42 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c index a050d04..720eb16 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c @@ -28,6 +28,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c index d251430..684d3aa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c @@ -28,6 +28,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c index 790ba2d..727b3e3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c @@ -28,6 +28,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c index 684ae87..e62d9c5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c @@ -28,6 +28,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c index 116131b..b693f0c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax-1.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c index 6ac47cb..f504fb1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax-2.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c index 2d445a9..d20c833 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax-3.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c index ae64206..be4dc33 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax-4.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c index ad4dd9d..530fe00 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh-1.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c index f7fbf22..4ee5c65 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh-2.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c index 7af181f..c44a462 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh-3.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c index 22ff91b..693d63d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh-4.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c index 1e367b3..82a9ea2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c @@ -26,6 +26,6 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {vfmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmsub\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmsub\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c index 3af559d..eadeeb8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c @@ -26,6 +26,6 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c index e777c8c..f00d5f6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c @@ -26,7 +26,7 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* NOTE: 3 vmerge is need for other purpose. */ /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c index e777c8c..f00d5f6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c @@ -26,7 +26,7 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* NOTE: 3 vmerge is need for other purpose. */ /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c index 46f2b5f..6303f41 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c @@ -26,7 +26,7 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ +/* { dg-final { scan-assembler-not {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} } } */ /* NOTE: 3 vmerge is need for other purpose. */ /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c index 0f85dfc..1447f40 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c @@ -26,6 +26,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 9 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ +/* { dg-final { scan-assembler-not {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c index 6cdb2c4..6bc03a0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c @@ -25,6 +25,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 6 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ +/* { dg-final { scan-assembler-not {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c index 5a921cb..c1c2d4e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c @@ -26,6 +26,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 9 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ +/* { dg-final { scan-assembler-not {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c index 939e6bd..e9edd23 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c @@ -26,6 +26,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 9 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ +/* { dg-final { scan-assembler-not {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c index 608fbef..ccfb651 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c @@ -25,6 +25,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ -/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 9 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */ +/* { dg-final { scan-assembler-not {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121334.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121334.c new file mode 100644 index 0000000..a2ded48 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121334.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 -fno-vect-cost-model" } */ + +char arr[64]; + +void init () +{ + for (int i = 8; i >= 0; i--) + arr[i] = i; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121742.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121742.c new file mode 100644 index 0000000..08491f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121742.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ + +typedef unsigned long uint64_t; +typedef unsigned int uint32_t; +typedef unsigned char uint8_t; +typedef uint8_t a __attribute__((vector_size(4))); +int b, c; + +uint64_t d() { + a e = {5, 9, 1, 5}; + a bla = {0, 0, 0, 0}; + int *f = &b; + uint32_t g = 0; + int i = 0; + for (; i < 2; i++) + for (c = 0; c <= 2; c++) { + *f ^= e[3] + 9; + e = __builtin_shufflevector( + ~__builtin_shufflevector(bla, e, 1, 4, 3, 4), e, 0, 1, 1, 7); + } + return g; +} + +int main() { + int j = d (); + if (b != 0) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c index 101ad57..2953d18 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c @@ -39,5 +39,5 @@ DEF_MINMAX_VX (min, 128, double, <) DEF_MINMAX_VX (min, 256, double, <) DEF_MINMAX_VX (min, 512, double, <) -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c index 004a95c..db156ac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c @@ -39,5 +39,5 @@ DEF_MINMAX_VX (min, 128, double, <=) DEF_MINMAX_VX (min, 256, double, <=) DEF_MINMAX_VX (min, 512, double, <=) -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c index 297f049..3af7e64 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c @@ -39,5 +39,5 @@ DEF_OP_VX (mul, 128, double, *) DEF_OP_VX (mul, 256, double, *) DEF_OP_VX (mul, 512, double, *) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c index f49bf28..f1d5944 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c @@ -39,5 +39,5 @@ DEF_OP_VI_15 (mul, 128, double, *) DEF_OP_VI_15 (mul, 256, double, *) DEF_OP_VI_15 (mul, 512, double, *) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c index bb62ce2..89af160 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c @@ -54,5 +54,5 @@ DEF_OP_V (nearbyint, 512, double, __builtin_nearbyint) /* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ /* { dg-final { scan-assembler-times {vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ /* { dg-final { scan-assembler-times {vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ -/* { dg-final { scan-assembler-times {frflags\s+[atx][0-9]+} 30 } } */ -/* { dg-final { scan-assembler-times {fsflags\s+[atx][0-9]+} 30 } } */ +/* { dg-final { scan-assembler-times {frflags\s+[atx][0-9]+} 32 } } */ +/* { dg-final { scan-assembler-times {fsflags\s+[atx][0-9]+} 32 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c index 811f26c..7e56330 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c @@ -2,6 +2,7 @@ /* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=0" } */ #include "vf_mulop.h" +#include "vf_binop.h" DEF_VF_MULOP_CASE_0 (_Float16, +, +, add) DEF_VF_MULOP_CASE_0 (_Float16, -, +, sub) @@ -15,6 +16,10 @@ DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, +, acc) DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, +, sac) DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, -, nacc) DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, -, nsac) +DEF_VF_BINOP_CASE_0 (_Float16, *, mul) +DEF_VF_BINOP_REVERSE_CASE_0 (_Float16, /, rdiv) +DEF_VF_BINOP_CASE_2_WRAP (_Float16, MIN_FUNC_0_WRAP (_Float16), min) +DEF_VF_BINOP_CASE_2_WRAP (_Float16, MIN_FUNC_1_WRAP (_Float16), min) /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ @@ -28,3 +33,5 @@ DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, -, nsac) /* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c index ca82ead..e674cf7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c @@ -2,6 +2,7 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ #include "vf_mulop.h" +#include "vf_binop.h" DEF_VF_MULOP_CASE_0 (float, +, +, add) DEF_VF_MULOP_CASE_0 (float, -, +, sub) @@ -15,6 +16,10 @@ DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, +, acc) DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, +, sac) DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, -, nacc) DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, -, nsac) +DEF_VF_BINOP_CASE_0 (float, *, mul) +DEF_VF_BINOP_REVERSE_CASE_0 (float, /, rdiv) +DEF_VF_BINOP_CASE_2_WRAP (float, MIN_FUNC_0_WRAP (float), min) +DEF_VF_BINOP_CASE_2_WRAP (float, MIN_FUNC_1_WRAP (float), min) /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ @@ -28,3 +33,6 @@ DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, -, nsac) /* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c index 4de038c..b36e966 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c @@ -2,6 +2,7 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ #include "vf_mulop.h" +#include "vf_binop.h" DEF_VF_MULOP_CASE_0 (double, +, +, add) DEF_VF_MULOP_CASE_0 (double, -, +, sub) @@ -11,6 +12,10 @@ DEF_VF_MULOP_ACC_CASE_0 (double, +, +, acc) DEF_VF_MULOP_ACC_CASE_0 (double, -, +, sac) DEF_VF_MULOP_ACC_CASE_0 (double, +, -, nacc) DEF_VF_MULOP_ACC_CASE_0 (double, -, -, nsac) +DEF_VF_BINOP_CASE_0 (double, *, mul) +DEF_VF_BINOP_REVERSE_CASE_0 (double, /, rdiv) +DEF_VF_BINOP_CASE_2_WRAP (double, MIN_FUNC_0_WRAP (double), min) +DEF_VF_BINOP_CASE_2_WRAP (double, MIN_FUNC_1_WRAP (double), min) /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ @@ -20,3 +25,6 @@ DEF_VF_MULOP_ACC_CASE_0 (double, -, -, nsac) /* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfnmacc.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c index 3a39303..1914b18 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c @@ -15,5 +15,7 @@ /* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfmul.vf} } } */ +/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */ +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ /* { dg-final { scan-assembler-times {fcvt.s.h} 4 } } */ -/* { dg-final { scan-assembler-times {vfmv.v.f} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c index b4618ba..f8dab37 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c @@ -15,5 +15,7 @@ /* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfmul.vf} } } */ +/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */ +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ /* { dg-final { scan-assembler-times {fcvt.d.s} 4 } } */ -/* { dg-final { scan-assembler-times {vfmv.v.f} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c index a2ac67e..909770f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c @@ -11,3 +11,6 @@ /* { dg-final { scan-assembler-not {vfmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfmul.vf} } } */ +/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */ +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c index 58afaa4..c703ed6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c @@ -2,11 +2,12 @@ /* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=0" } */ #include "vf_mulop.h" +#include "vf_binop.h" -DEF_VF_MULOP_CASE_1 (_Float16, +, +, add, VF_MULOP_BODY_X16) -DEF_VF_MULOP_CASE_1 (_Float16, -, +, sub, VF_MULOP_BODY_X16) -DEF_VF_MULOP_CASE_1 (_Float16, +, -, nadd, VF_MULOP_BODY_X16) -DEF_VF_MULOP_CASE_1 (_Float16, -, -, nsub, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (_Float16, +, +, add, VF_MULOP_BODY_X128) +DEF_VF_MULOP_CASE_1 (_Float16, -, +, sub, VF_MULOP_BODY_X128) +DEF_VF_MULOP_CASE_1 (_Float16, +, -, nadd, VF_MULOP_BODY_X128) +DEF_VF_MULOP_CASE_1 (_Float16, -, -, nsub, VF_MULOP_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, +, acc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, +, sac, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, -, nacc, VF_MULOP_ACC_BODY_X128) @@ -15,6 +16,12 @@ DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, +, acc) DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, +, sac) DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, -, nacc) DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, -, nsac) +DEF_VF_BINOP_CASE_1 (_Float16, *, mul, VF_BINOP_BODY_X128) +DEF_VF_BINOP_REVERSE_CASE_1 (_Float16, /, rdiv, VF_BINOP_REVERSE_BODY_X128) +DEF_VF_BINOP_CASE_3_WRAP (_Float16, MIN_FUNC_0_WRAP (_Float16), min, + VF_BINOP_FUNC_BODY_X128) +DEF_VF_BINOP_CASE_3_WRAP (_Float16, MIN_FUNC_1_WRAP (_Float16), min, + VF_BINOP_FUNC_BODY_X128) /* { dg-final { scan-assembler {vfmadd.vf} } } */ /* { dg-final { scan-assembler {vfmsub.vf} } } */ @@ -28,3 +35,6 @@ DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, -, nsac) /* { dg-final { scan-assembler {vfwmsac.vf} } } */ /* { dg-final { scan-assembler {vfwnmacc.vf} } } */ /* { dg-final { scan-assembler {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler {vfmul.vf} } } */ +/* { dg-final { scan-assembler {vfrdiv.vf} } } */ +/* { dg-final { scan-assembler {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c index 0e95774..99b84dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c @@ -2,11 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ #include "vf_mulop.h" +#include "vf_binop.h" -DEF_VF_MULOP_CASE_1 (float, +, +, add, VF_MULOP_BODY_X16) -DEF_VF_MULOP_CASE_1 (float, -, +, sub, VF_MULOP_BODY_X16) -DEF_VF_MULOP_CASE_1 (float, +, -, nadd, VF_MULOP_BODY_X16) -DEF_VF_MULOP_CASE_1 (float, -, -, nsub, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (float, +, +, add, VF_MULOP_BODY_X128) +DEF_VF_MULOP_CASE_1 (float, -, +, sub, VF_MULOP_BODY_X128) +DEF_VF_MULOP_CASE_1 (float, +, -, nadd, VF_MULOP_BODY_X128) +DEF_VF_MULOP_CASE_1 (float, -, -, nsub, VF_MULOP_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (float, +, +, acc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (float, -, +, sac, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (float, +, -, nacc, VF_MULOP_ACC_BODY_X128) @@ -15,6 +16,12 @@ DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, +, acc) DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, +, sac) DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, -, nacc) DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, -, nsac) +DEF_VF_BINOP_CASE_1 (float, *, mul, VF_BINOP_BODY_X128) +DEF_VF_BINOP_REVERSE_CASE_1 (float, /, rdiv, VF_BINOP_REVERSE_BODY_X128) +DEF_VF_BINOP_CASE_3_WRAP (float, MIN_FUNC_0_WRAP (float), min, + VF_BINOP_FUNC_BODY_X128) +DEF_VF_BINOP_CASE_3_WRAP (float, MIN_FUNC_1_WRAP (float), min, + VF_BINOP_FUNC_BODY_X128) /* { dg-final { scan-assembler {vfmadd.vf} } } */ /* { dg-final { scan-assembler {vfmsub.vf} } } */ @@ -28,3 +35,6 @@ DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, -, nsac) /* { dg-final { scan-assembler {vfwmsac.vf} } } */ /* { dg-final { scan-assembler {vfwnmacc.vf} } } */ /* { dg-final { scan-assembler {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler {vfmul.vf} } } */ +/* { dg-final { scan-assembler {vfrdiv.vf} } } */ +/* { dg-final { scan-assembler {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c index 71bd7e1..889fed2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c @@ -2,15 +2,22 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ #include "vf_mulop.h" +#include "vf_binop.h" -DEF_VF_MULOP_CASE_1 (double, +, +, add, VF_MULOP_BODY_X16) -DEF_VF_MULOP_CASE_1 (double, -, +, sub, VF_MULOP_BODY_X16) -DEF_VF_MULOP_CASE_1 (double, +, -, nadd, VF_MULOP_BODY_X16) -DEF_VF_MULOP_CASE_1 (double, -, -, nsub, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (double, +, +, add, VF_MULOP_BODY_X128) +DEF_VF_MULOP_CASE_1 (double, -, +, sub, VF_MULOP_BODY_X128) +DEF_VF_MULOP_CASE_1 (double, +, -, nadd, VF_MULOP_BODY_X128) +DEF_VF_MULOP_CASE_1 (double, -, -, nsub, VF_MULOP_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (double, +, +, acc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (double, -, +, sac, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (double, +, -, nacc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (double, -, -, nsac, VF_MULOP_ACC_BODY_X128) +DEF_VF_BINOP_CASE_1 (double, *, mul, VF_BINOP_BODY_X128) +DEF_VF_BINOP_REVERSE_CASE_1 (double, /, rdiv, VF_BINOP_REVERSE_BODY_X128) +DEF_VF_BINOP_CASE_3_WRAP (double, MIN_FUNC_0_WRAP (double), min, + VF_BINOP_FUNC_BODY_X128) +DEF_VF_BINOP_CASE_3_WRAP (double, MIN_FUNC_1_WRAP (double), min, + VF_BINOP_FUNC_BODY_X128) /* { dg-final { scan-assembler {vfmadd.vf} } } */ /* { dg-final { scan-assembler {vfmsub.vf} } } */ @@ -20,3 +27,6 @@ DEF_VF_MULOP_ACC_CASE_1 (double, -, -, nsac, VF_MULOP_ACC_BODY_X128) /* { dg-final { scan-assembler {vfmsac.vf} } } */ /* { dg-final { scan-assembler {vfnmacc.vf} } } */ /* { dg-final { scan-assembler {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler {vfmul.vf} } } */ +/* { dg-final { scan-assembler {vfrdiv.vf} } } */ +/* { dg-final { scan-assembler {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c index 559df6c..9db8736 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c @@ -15,4 +15,7 @@ /* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfmul.vf} } } */ +/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */ +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ /* { dg-final { scan-assembler {fcvt.s.h} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c index 03f9c5a..577ad8d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c @@ -15,4 +15,7 @@ /* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfmul.vf} } } */ +/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */ +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ /* { dg-final { scan-assembler {fcvt.d.s} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c index d71bdde..30e5660 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c @@ -11,3 +11,6 @@ /* { dg-final { scan-assembler-not {vfmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfmul.vf} } } */ +/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */ +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c new file mode 100644 index 0000000..1a20ee7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" + +DEF_VF_BINOP_CASE_2_WRAP (_Float16, __builtin_fminf16, min) + +/* { dg-final { scan-assembler-times {vfmin.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c new file mode 100644 index 0000000..1e0f7f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" + +DEF_VF_BINOP_CASE_2_WRAP (float, __builtin_fminf, min) + +/* { dg-final { scan-assembler-times {vfmin.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c new file mode 100644 index 0000000..61db2df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" + +DEF_VF_BINOP_CASE_2_WRAP (double, __builtin_fmin, min) + +/* { dg-final { scan-assembler-times {vfmin.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c new file mode 100644 index 0000000..392580a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=1" } */ + +#include "vf-5-f16.c" + +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c new file mode 100644 index 0000000..9dbd226 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=1" } */ + +#include "vf-5-f32.c" + +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c new file mode 100644 index 0000000..44a17cd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=1" } */ + +#include "vf-5-f64.c" + +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c new file mode 100644 index 0000000..0883c882 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" + +DEF_VF_BINOP_CASE_3_WRAP (_Float16, __builtin_fminf16, min, VF_BINOP_FUNC_BODY_X128) + +/* { dg-final { scan-assembler {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c new file mode 100644 index 0000000..8528240 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" + +DEF_VF_BINOP_CASE_3_WRAP (float, __builtin_fminf, min, VF_BINOP_FUNC_BODY_X128) + +/* { dg-final { scan-assembler {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c new file mode 100644 index 0000000..474b339 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" + +DEF_VF_BINOP_CASE_3_WRAP (double, __builtin_fmin, min, VF_BINOP_FUNC_BODY_X128) + +/* { dg-final { scan-assembler {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c new file mode 100644 index 0000000..bd68b3c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=4" } */ + +#include "vf-7-f16.c" + +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c new file mode 100644 index 0000000..000402c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=4" } */ + +#include "vf-7-f32.c" + +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c new file mode 100644 index 0000000..89dec81 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=4" } */ + +#include "vf-7-f64.c" + +/* { dg-final { scan-assembler-not {vfmin.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h new file mode 100644 index 0000000..90436a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h @@ -0,0 +1,206 @@ +#ifndef HAVE_DEFINED_VF_BINOP_H +#define HAVE_DEFINED_VF_BINOP_H + +#include <stdint.h> + +#define DEF_VF_BINOP_CASE_0(T, OP, NAME) \ + void test_vf_binop_##NAME##_##T##_case_0 (T *restrict out, T *restrict in, \ + T f, unsigned n) \ + { \ + for (unsigned i = 0; i < n; i++) \ + out[i] = in[i] OP f; \ + } +#define DEF_VF_BINOP_CASE_0_WRAP(T, OP, NAME) DEF_VF_BINOP_CASE_0 (T, OP, NAME) +#define RUN_VF_BINOP_CASE_0(T, NAME, out, in, f, n) \ + test_vf_binop_##NAME##_##T##_case_0 (out, in, f, n) +#define RUN_VF_BINOP_CASE_0_WRAP(T, NAME, out, in, f, n) \ + RUN_VF_BINOP_CASE_0 (T, NAME, out, in, f, n) + +#define DEF_VF_BINOP_REVERSE_CASE_0(T, OP, NAME) \ + void test_vf_binop_reverse_##NAME##_##T##_case_0 (T *restrict out, \ + T *restrict in, T f, \ + unsigned n) \ + { \ + for (unsigned i = 0; i < n; i++) \ + out[i] = f OP in[i]; \ + } +#define DEF_VF_BINOP_REVERSE_CASE_0_WRAP(T, OP, NAME) \ + DEF_VF_BINOP_REVERSE_CASE_0 (T, OP, NAME) +#define RUN_VF_BINOP_REVERSE_CASE_0(T, NAME, out, in, f, n) \ + test_vf_binop_reverse_##NAME##_##T##_case_0 (out, in, f, n) +#define RUN_VF_BINOP_REVERSE_CASE_0_WRAP(T, NAME, out, in, f, n) \ + RUN_VF_BINOP_REVERSE_CASE_0 (T, NAME, out, in, f, n) + +#define VF_BINOP_BODY(op) \ + out[k + 0] = in[k + 0] op tmp; \ + out[k + 1] = in[k + 1] op tmp; \ + k += 2; + +#define VF_BINOP_BODY_X4(op) \ + VF_BINOP_BODY (op) \ + VF_BINOP_BODY (op) + +#define VF_BINOP_BODY_X8(op) \ + VF_BINOP_BODY_X4 (op) \ + VF_BINOP_BODY_X4 (op) + +#define VF_BINOP_BODY_X16(op) \ + VF_BINOP_BODY_X8 (op) \ + VF_BINOP_BODY_X8 (op) + +#define VF_BINOP_BODY_X32(op) \ + VF_BINOP_BODY_X16 (op) \ + VF_BINOP_BODY_X16 (op) + +#define VF_BINOP_BODY_X64(op) \ + VF_BINOP_BODY_X32 (op) \ + VF_BINOP_BODY_X32 (op) + +#define VF_BINOP_BODY_X128(op) \ + VF_BINOP_BODY_X64 (op) \ + VF_BINOP_BODY_X64 (op) + +#define DEF_VF_BINOP_CASE_1(T, OP, NAME, BODY) \ + void test_vf_binop_##NAME##_##T##_case_1 (T *restrict out, T *restrict in, \ + T f, unsigned n) \ + { \ + unsigned k = 0; \ + T tmp = f + 3.45; \ + \ + while (k < n) \ + { \ + tmp = tmp * 0x3.fp2; \ + BODY (OP) \ + } \ + } +#define DEF_VF_BINOP_CASE_1_WRAP(T, OP, NAME, BODY) \ + DEF_VF_BINOP_CASE_1 (T, OP, NAME, BODY) + +#define VF_BINOP_REVERSE_BODY(op) \ + out[k + 0] = tmp op in[k + 0]; \ + out[k + 1] = tmp op in[k + 1]; \ + k += 2; + +#define VF_BINOP_REVERSE_BODY_X4(op) \ + VF_BINOP_REVERSE_BODY (op) \ + VF_BINOP_REVERSE_BODY (op) + +#define VF_BINOP_REVERSE_BODY_X8(op) \ + VF_BINOP_REVERSE_BODY_X4 (op) \ + VF_BINOP_REVERSE_BODY_X4 (op) + +#define VF_BINOP_REVERSE_BODY_X16(op) \ + VF_BINOP_REVERSE_BODY_X8 (op) \ + VF_BINOP_REVERSE_BODY_X8 (op) + +#define VF_BINOP_REVERSE_BODY_X32(op) \ + VF_BINOP_REVERSE_BODY_X16 (op) \ + VF_BINOP_REVERSE_BODY_X16 (op) + +#define VF_BINOP_REVERSE_BODY_X64(op) \ + VF_BINOP_REVERSE_BODY_X32 (op) \ + VF_BINOP_REVERSE_BODY_X32 (op) + +#define VF_BINOP_REVERSE_BODY_X128(op) \ + VF_BINOP_REVERSE_BODY_X64 (op) \ + VF_BINOP_REVERSE_BODY_X64 (op) + +#define DEF_VF_BINOP_REVERSE_CASE_1(T, OP, NAME, BODY) \ + void test_vf_binop_reverse_##NAME##_##T##_case_1 (T *restrict out, \ + T *restrict in, T f, \ + unsigned n) \ + { \ + unsigned k = 0; \ + T tmp = f + 3.45; \ + \ + while (k < n) \ + { \ + tmp = tmp * 0x3.fp2; \ + BODY (OP) \ + } \ + } +#define DEF_VF_BINOP_REVERSE_CASE_1_WRAP(T, OP, NAME, BODY) \ + DEF_VF_BINOP_REVERSE_CASE_1 (T, OP, NAME, BODY) + +#endif + +#define DEF_MIN_0(T) \ + static inline T test_##T##_min_0 (T a, T b) { return a > b ? b : a; } + +#define DEF_MIN_1(T) \ + static inline T test_##T##_min_1 (T a, T b) { return a >= b ? b : a; } + +DEF_MIN_0 (_Float16) +DEF_MIN_0 (float) +DEF_MIN_0 (double) + +DEF_MIN_1 (_Float16) +DEF_MIN_1 (float) +DEF_MIN_1 (double) + +#define MIN_FUNC_0(T) test_##T##_min_0 +#define MIN_FUNC_0_WRAP(T) MIN_FUNC_0 (T) + +#define MIN_FUNC_1(T) test_##T##_min_1 +#define MIN_FUNC_1_WRAP(T) MIN_FUNC_1 (T) + +#define DEF_VF_BINOP_CASE_2(T, FUNC, NAME) \ + void test_vf_binop_##NAME##_##FUNC##_##T##_case_2 (T *restrict out, \ + T *restrict in, T f, \ + unsigned n) \ + { \ + for (unsigned i = 0; i < n; i++) \ + out[i] = FUNC (in[i], f); \ + } +#define DEF_VF_BINOP_CASE_2_WRAP(T, FUNC, NAME) \ + DEF_VF_BINOP_CASE_2 (T, FUNC, NAME) +#define RUN_VF_BINOP_CASE_2(T, NAME, FUNC, out, in, f, n) \ + test_vf_binop_##NAME##_##FUNC##_##T##_case_2 (out, in, f, n) +#define RUN_VF_BINOP_CASE_2_WRAP(T, NAME, FUNC, out, in, f, n) \ + RUN_VF_BINOP_CASE_2 (T, NAME, FUNC, out, in, f, n) + +#define DEF_VF_BINOP_CASE_3(T, FUNC, NAME, BODY) \ + void test_vf_binop_##NAME##_##FUNC##_##T##_case_3 (T *restrict out, \ + T *restrict in, T f, \ + unsigned n) \ + { \ + unsigned k = 0; \ + T tmp = f + 3; \ + \ + while (k < n) \ + { \ + tmp = tmp * 0x7.ap3; \ + BODY (FUNC) \ + } \ + } +#define DEF_VF_BINOP_CASE_3_WRAP(T, FUNC, NAME, BODY) \ + DEF_VF_BINOP_CASE_3 (T, FUNC, NAME, BODY) + +#define VF_BINOP_FUNC_BODY(func) \ + out[k + 0] = func (in[k + 0], tmp); \ + out[k + 1] = func (in[k + 1], tmp); \ + k += 2; + +#define VF_BINOP_FUNC_BODY_X4(op) \ + VF_BINOP_FUNC_BODY (op) \ + VF_BINOP_FUNC_BODY (op) + +#define VF_BINOP_FUNC_BODY_X8(op) \ + VF_BINOP_FUNC_BODY_X4 (op) \ + VF_BINOP_FUNC_BODY_X4 (op) + +#define VF_BINOP_FUNC_BODY_X16(op) \ + VF_BINOP_FUNC_BODY_X8 (op) \ + VF_BINOP_FUNC_BODY_X8 (op) + +#define VF_BINOP_FUNC_BODY_X32(op) \ + VF_BINOP_FUNC_BODY_X16 (op) \ + VF_BINOP_FUNC_BODY_X16 (op) + +#define VF_BINOP_FUNC_BODY_X64(op) \ + VF_BINOP_FUNC_BODY_X32 (op) \ + VF_BINOP_FUNC_BODY_X32 (op) + +#define VF_BINOP_FUNC_BODY_X128(op) \ + VF_BINOP_FUNC_BODY_X64 (op) \ + VF_BINOP_FUNC_BODY_X64 (op) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h new file mode 100644 index 0000000..e6ddd1e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h @@ -0,0 +1,451 @@ +#ifndef HAVE_DEFINED_VF_BINOP_DATA_H +#define HAVE_DEFINED_VF_BINOP_DATA_H + +#define N 16 + +#define TEST_BINOP_DATA(T, NAME) test_##T##_##NAME##_data +#define TEST_BINOP_DATA_WRAP(T, NAME) TEST_BINOP_DATA(T, NAME) + + +_Float16 TEST_BINOP_DATA(_Float16, mul)[][4][N] = +{ + { + { 0x1.0000000000000p+0f16 }, + { + 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, + 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, + 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, + 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, + }, + { + 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, + 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, + 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, + 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, + }, + }, + { + { 0x1.0000000000000p+7f16 }, + { + -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, + 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, + -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, + -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, + }, + { + -0x1.53c0000000000p+12f16, -0x1.53c0000000000p+12f16, -0x1.53c0000000000p+12f16, -0x1.53c0000000000p+12f16, + 0x1.c300000000000p+13f16, 0x1.c300000000000p+13f16, 0x1.c300000000000p+13f16, 0x1.c300000000000p+13f16, + -0x1.ffc0000000000p+14f16, -0x1.ffc0000000000p+14f16, -0x1.ffc0000000000p+14f16, -0x1.ffc0000000000p+14f16, + -0x1.94c0000000000p+13f16, -0x1.94c0000000000p+13f16, -0x1.94c0000000000p+13f16, -0x1.94c0000000000p+13f16, + }, + }, + { + { -0x1.fc00000000000p+6f16 }, + { + -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, + -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, + 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, + -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, + }, + { + 0x1.0400000000000p+12f16, 0x1.0400000000000p+12f16, 0x1.0400000000000p+12f16, 0x1.0400000000000p+12f16, + 0x1.e180000000000p+14f16, 0x1.e180000000000p+14f16, 0x1.e180000000000p+14f16, 0x1.e180000000000p+14f16, + -0x1.9380000000000p+11f16, -0x1.9380000000000p+11f16, -0x1.9380000000000p+11f16, -0x1.9380000000000p+11f16, + 0x1.06c0000000000p+12f16, 0x1.06c0000000000p+12f16, 0x1.06c0000000000p+12f16, 0x1.06c0000000000p+12f16, + }, + }, +}; + +float TEST_BINOP_DATA(float, mul)[][4][N] = +{ + { + { 0x1.4000000000000p+3f }, + { + 0x1.a022ea0000000p+60f, 0x1.a022ea0000000p+60f, 0x1.a022ea0000000p+60f, 0x1.a022ea0000000p+60f, + 0x1.aa49660000000p+62f, 0x1.aa49660000000p+62f, 0x1.aa49660000000p+62f, 0x1.aa49660000000p+62f, + -0x1.ac3a220000000p+62f, -0x1.ac3a220000000p+62f, -0x1.ac3a220000000p+62f, -0x1.ac3a220000000p+62f, + 0x1.62cc880000000p+58f, 0x1.62cc880000000p+58f, 0x1.62cc880000000p+58f, 0x1.62cc880000000p+58f, + }, + { + 0x1.0415d20000000p+64f, 0x1.0415d20000000p+64f, 0x1.0415d20000000p+64f, 0x1.0415d20000000p+64f, + 0x1.0a6de00000000p+66f, 0x1.0a6de00000000p+66f, 0x1.0a6de00000000p+66f, 0x1.0a6de00000000p+66f, + -0x1.0ba4540000000p+66f, -0x1.0ba4540000000p+66f, -0x1.0ba4540000000p+66f, -0x1.0ba4540000000p+66f, + 0x1.bb7faa0000000p+61f, 0x1.bb7faa0000000p+61f, 0x1.bb7faa0000000p+61f, 0x1.bb7faa0000000p+61f, + }, + }, + { + { 0x1.d1a94a0000000p+39f }, + { + 0x1.de3d100000000p+63f, 0x1.de3d100000000p+63f, 0x1.de3d100000000p+63f, 0x1.de3d100000000p+63f, + 0x1.82ed340000000p+60f, 0x1.82ed340000000p+60f, 0x1.82ed340000000p+60f, 0x1.82ed340000000p+60f, + 0x1.e4075c0000000p+63f, 0x1.e4075c0000000p+63f, 0x1.e4075c0000000p+63f, 0x1.e4075c0000000p+63f, + 0x1.b7f1700000000p+62f, 0x1.b7f1700000000p+62f, 0x1.b7f1700000000p+62f, 0x1.b7f1700000000p+62f, + }, + { + 0x1.b2f4960000000p+103f, 0x1.b2f4960000000p+103f, 0x1.b2f4960000000p+103f, 0x1.b2f4960000000p+103f, + 0x1.5fe85c0000000p+100f, 0x1.5fe85c0000000p+100f, 0x1.5fe85c0000000p+100f, 0x1.5fe85c0000000p+100f, + 0x1.b838ba0000000p+103f, 0x1.b838ba0000000p+103f, 0x1.b838ba0000000p+103f, 0x1.b838ba0000000p+103f, + 0x1.90203e0000000p+102f, 0x1.90203e0000000p+102f, 0x1.90203e0000000p+102f, 0x1.90203e0000000p+102f, + }, + }, + { + { 0x1.0c6f7a0000000p-20f }, + { + 0x1.de3d100000000p+63f, 0x1.de3d100000000p+63f, 0x1.de3d100000000p+63f, 0x1.de3d100000000p+63f, + 0x1.82ed340000000p+60f, 0x1.82ed340000000p+60f, 0x1.82ed340000000p+60f, 0x1.82ed340000000p+60f, + 0x1.e4075c0000000p+63f, 0x1.e4075c0000000p+63f, 0x1.e4075c0000000p+63f, 0x1.e4075c0000000p+63f, + 0x1.b7f1700000000p+62f, 0x1.b7f1700000000p+62f, 0x1.b7f1700000000p+62f, 0x1.b7f1700000000p+62f, + }, + { + 0x1.f5782e0000000p+43f, 0x1.f5782e0000000p+43f, 0x1.f5782e0000000p+43f, 0x1.f5782e0000000p+43f, + 0x1.95b8ce0000000p+40f, 0x1.95b8ce0000000p+40f, 0x1.95b8ce0000000p+40f, 0x1.95b8ce0000000p+40f, + 0x1.fb8a7a0000000p+43f, 0x1.fb8a7a0000000p+43f, 0x1.fb8a7a0000000p+43f, 0x1.fb8a7a0000000p+43f, + 0x1.cd50560000000p+42f, 0x1.cd50560000000p+42f, 0x1.cd50560000000p+42f, 0x1.cd50560000000p+42f, + }, + }, +}; + +double TEST_BINOP_DATA(double, mul)[][4][N] = +{ + { + { 0x1.0e15635000000p+40 }, + { + -0x1.1cadd278efdbap+511, -0x1.1cadd278efdbap+511, -0x1.1cadd278efdbap+511, -0x1.1cadd278efdbap+511, + 0x1.7ba13fea68f33p+511, 0x1.7ba13fea68f33p+511, 0x1.7ba13fea68f33p+511, 0x1.7ba13fea68f33p+511, + -0x1.2c51d0517111ep+511, -0x1.2c51d0517111ep+511, -0x1.2c51d0517111ep+511, -0x1.2c51d0517111ep+511, + 0x1.aca8567d5e741p+511, 0x1.aca8567d5e741p+511, 0x1.aca8567d5e741p+511, 0x1.aca8567d5e741p+511, + }, + { + -0x1.2c571cadff9bep+551, -0x1.2c571cadff9bep+551, -0x1.2c571cadff9bep+551, -0x1.2c571cadff9bep+551, + 0x1.9083c8e97706cp+551, 0x1.9083c8e97706cp+551, 0x1.9083c8e97706cp+551, 0x1.9083c8e97706cp+551, + -0x1.3cd760ed790fcp+551, -0x1.3cd760ed790fcp+551, -0x1.3cd760ed790fcp+551, -0x1.3cd760ed790fcp+551, + 0x1.c43d5b525ff4bp+551, 0x1.c43d5b525ff4bp+551, 0x1.c43d5b525ff4bp+551, 0x1.c43d5b525ff4bp+551, + }, + }, + { + { -0x1.34be569fb0edfp+79 }, + { + 0x1.9249ee7946e55p+511, 0x1.9249ee7946e55p+511, 0x1.9249ee7946e55p+511, 0x1.9249ee7946e55p+511, + -0x1.581af8ca64584p+510, -0x1.581af8ca64584p+510, -0x1.581af8ca64584p+510, -0x1.581af8ca64584p+510, + 0x1.48f04988397e9p+511, 0x1.48f04988397e9p+511, 0x1.48f04988397e9p+511, 0x1.48f04988397e9p+511, + -0x1.d54d7ad0a0415p+511, -0x1.d54d7ad0a0415p+511, -0x1.d54d7ad0a0415p+511, -0x1.d54d7ad0a0415p+511, + }, + { + -0x1.e52c0de8af5f2p+590, -0x1.e52c0de8af5f2p+590, -0x1.e52c0de8af5f2p+590, -0x1.e52c0de8af5f2p+590, + 0x1.9f004bc7dd179p+589, 0x1.9f004bc7dd179p+589, 0x1.9f004bc7dd179p+589, 0x1.9f004bc7dd179p+589, + -0x1.8cb5aa1c618f5p+590, -0x1.8cb5aa1c618f5p+590, -0x1.8cb5aa1c618f5p+590, -0x1.8cb5aa1c618f5p+590, + 0x1.1aff130877303p+591, 0x1.1aff130877303p+591, 0x1.1aff130877303p+591, 0x1.1aff130877303p+591, + }, + }, + { + { 0x1.5aac1aa995dfbp-511 }, + { + -0x1.b1dc3d62e68d9p+511, -0x1.b1dc3d62e68d9p+511, -0x1.b1dc3d62e68d9p+511, -0x1.b1dc3d62e68d9p+511, + 0x1.1ea30828d414dp+511, 0x1.1ea30828d414dp+511, 0x1.1ea30828d414dp+511, 0x1.1ea30828d414dp+511, + -0x1.f88d34164cbd0p+508, -0x1.f88d34164cbd0p+508, -0x1.f88d34164cbd0p+508, -0x1.f88d34164cbd0p+508, + 0x1.c9a81c74a1362p+510, 0x1.c9a81c74a1362p+510, 0x1.c9a81c74a1362p+510, 0x1.c9a81c74a1362p+510, + }, + { + -0x1.25c3ac1058579p+1, -0x1.25c3ac1058579p+1, -0x1.25c3ac1058579p+1, -0x1.25c3ac1058579p+1, + 0x1.84290c6b1a568p+0, 0x1.84290c6b1a568p+0, 0x1.84290c6b1a568p+0, 0x1.84290c6b1a568p+0, + -0x1.55a105e8db4bep-2, -0x1.55a105e8db4bep-2, -0x1.55a105e8db4bep-2, -0x1.55a105e8db4bep-2, + 0x1.35e071897f867p+0, 0x1.35e071897f867p+0, 0x1.35e071897f867p+0, 0x1.35e071897f867p+0, + }, + }, +}; + +_Float16 TEST_BINOP_DATA(_Float16, rdiv)[][4][N] = +{ + { + { 0x1.0000000000000p+0f16 }, + { + 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, + 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, + 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, + 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, + }, + { + 0x1.4800000000000p-5f16, 0x1.4800000000000p-5f16, 0x1.4800000000000p-5f16, 0x1.4800000000000p-5f16, + 0x1.2980000000000p-7f16, 0x1.2980000000000p-7f16, 0x1.2980000000000p-7f16, 0x1.2980000000000p-7f16, + 0x1.3780000000000p-6f16, 0x1.3780000000000p-6f16, 0x1.3780000000000p-6f16, 0x1.3780000000000p-6f16, + 0x1.64c0000000000p-5f16, 0x1.64c0000000000p-5f16, 0x1.64c0000000000p-5f16, 0x1.64c0000000000p-5f16, + }, + }, + { + { 0x1.0000000000000p+0f16 }, + { + -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, + 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, + -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, + -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, + }, + { + -0x1.81c0000000000p-6f16, -0x1.81c0000000000p-6f16, -0x1.81c0000000000p-6f16, -0x1.81c0000000000p-6f16, + 0x1.2280000000000p-7f16, 0x1.2280000000000p-7f16, 0x1.2280000000000p-7f16, 0x1.2280000000000p-7f16, + -0x1.0040000000000p-8f16, -0x1.0040000000000p-8f16, -0x1.0040000000000p-8f16, -0x1.0040000000000p-8f16, + -0x1.4400000000000p-7f16, -0x1.4400000000000p-7f16, -0x1.4400000000000p-7f16, -0x1.4400000000000p-7f16, + }, + }, + { + { 0x1.9000000000000p+6f16 }, + { + -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, + -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, + 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, + -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, + }, + { + -0x1.86c0000000000p+1f16, -0x1.86c0000000000p+1f16, -0x1.86c0000000000p+1f16, -0x1.86c0000000000p+1f16, + -0x1.a600000000000p-2f16, -0x1.a600000000000p-2f16, -0x1.a600000000000p-2f16, -0x1.a600000000000p-2f16, + 0x1.f7c0000000000p+1f16, 0x1.f7c0000000000p+1f16, 0x1.f7c0000000000p+1f16, 0x1.f7c0000000000p+1f16, + -0x1.82c0000000000p+1f16, -0x1.82c0000000000p+1f16, -0x1.82c0000000000p+1f16, -0x1.82c0000000000p+1f16, + }, + }, +}; + +float TEST_BINOP_DATA(float, rdiv)[][4][N] = +{ + { + { 0x1.0000000000000p+0f }, + { + 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, + 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, + 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, + 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, + }, + { + 0x1.47c7360000000p-61f, 0x1.47c7360000000p-61f, 0x1.47c7360000000p-61f, 0x1.47c7360000000p-61f, + 0x1.2969980000000p-63f, 0x1.2969980000000p-63f, 0x1.2969980000000p-63f, 0x1.2969980000000p-63f, + 0x1.37651e0000000p-62f, 0x1.37651e0000000p-62f, 0x1.37651e0000000p-62f, 0x1.37651e0000000p-62f, + 0x1.647b220000000p-61f, 0x1.647b220000000p-61f, 0x1.647b220000000p-61f, 0x1.647b220000000p-61f, + }, + }, + { + { 0x1.fffffe0000000p+63f }, + { + -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, + 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, + -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, + -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, + }, + { + -0x1.81a4f80000000p+2f, -0x1.81a4f80000000p+2f, -0x1.81a4f80000000p+2f, -0x1.81a4f80000000p+2f, + 0x1.227b0a0000000p+1f, 0x1.227b0a0000000p+1f, 0x1.227b0a0000000p+1f, 0x1.227b0a0000000p+1f, + -0x1.000efe0000000p+0f, -0x1.000efe0000000p+0f, -0x1.000efe0000000p+0f, -0x1.000efe0000000p+0f, + -0x1.43c6b20000000p+1f, -0x1.43c6b20000000p+1f, -0x1.43c6b20000000p+1f, -0x1.43c6b20000000p+1f, + }, + }, + { + { -0x1.d301720000000p+104f }, + { + -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, + -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, + 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, + -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, + }, + { + 0x1.c806200000000p+43f, 0x1.c806200000000p+43f, 0x1.c806200000000p+43f, 0x1.c806200000000p+43f, + 0x1.ec8b9e0000000p+40f, 0x1.ec8b9e0000000p+40f, 0x1.ec8b9e0000000p+40f, 0x1.ec8b9e0000000p+40f, + -0x1.25dcbc0000000p+44f, -0x1.25dcbc0000000p+44f, -0x1.25dcbc0000000p+44f, -0x1.25dcbc0000000p+44f, + 0x1.c348400000000p+43f, 0x1.c348400000000p+43f, 0x1.c348400000000p+43f, 0x1.c348400000000p+43f, + }, + }, +}; + +double TEST_BINOP_DATA(double, rdiv)[][4][N] = +{ + { + { 0x1.0000000000000p+0 }, + { + 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, + 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, + 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, + 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, + }, + { + 0x1.47c734d265b62p-509, 0x1.47c734d265b62p-509, 0x1.47c734d265b62p-509, 0x1.47c734d265b62p-509, + 0x1.296997569d3cdp-511, 0x1.296997569d3cdp-511, 0x1.296997569d3cdp-511, 0x1.296997569d3cdp-511, + 0x1.37651dc4c34fcp-510, 0x1.37651dc4c34fcp-510, 0x1.37651dc4c34fcp-510, 0x1.37651dc4c34fcp-510, + 0x1.647b1ff508275p-509, 0x1.647b1ff508275p-509, 0x1.647b1ff508275p-509, 0x1.647b1ff508275p-509, + }, + }, + { + { 0x1.afcef51f0fb5fp+265 }, + { + -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, + 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, + -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, + -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, + }, + { + -0x1.453e40c97ee2ap-244, -0x1.453e40c97ee2ap-244, -0x1.453e40c97ee2ap-244, -0x1.453e40c97ee2ap-244, + 0x1.e9f7fd1cca941p-246, 0x1.e9f7fd1cca941p-246, 0x1.e9f7fd1cca941p-246, 0x1.e9f7fd1cca941p-246, + -0x1.afe83ffcda969p-247, -0x1.afe83ffcda969p-247, -0x1.afe83ffcda969p-247, -0x1.afe83ffcda969p-247, + -0x1.1110a2fba3e0dp-245, -0x1.1110a2fba3e0dp-245, -0x1.1110a2fba3e0dp-245, -0x1.1110a2fba3e0dp-245, + }, + }, + { + { -0x1.ed8d34e547314p+597 }, + { + -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, + -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, + 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, + -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, + }, + { + 0x1.e1f211cce49a8p+88, 0x1.e1f211cce49a8p+88, 0x1.e1f211cce49a8p+88, 0x1.e1f211cce49a8p+88, + 0x1.044581e6878d3p+86, 0x1.044581e6878d3p+86, 0x1.044581e6878d3p+86, 0x1.044581e6878d3p+86, + -0x1.3690f29d3d5d0p+89, -0x1.3690f29d3d5d0p+89, -0x1.3690f29d3d5d0p+89, -0x1.3690f29d3d5d0p+89, + 0x1.dcef333871e2dp+88, 0x1.dcef333871e2dp+88, 0x1.dcef333871e2dp+88, 0x1.dcef333871e2dp+88, + }, + }, +}; + +_Float16 TEST_BINOP_DATA(_Float16, min)[][4][N] = +{ + { + { 0x1.0000000000000p+0f16 }, + { + 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, + 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, + 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, + 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, + }, + { + 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, + 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, + 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, + 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, + }, + }, + { + { 0x1.0000000000000p+0f16 }, + { + -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, + 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, + -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, + -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, + }, + { + -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, + 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, + -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, + -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, + }, + }, + { + { -0x1.0000000000000p+0f16 }, + { + -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, + -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, + 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, + -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, + }, + { + -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, + -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, + -0x1.0000000000000p+0f16, -0x1.0000000000000p+0f16, -0x1.0000000000000p+0f16, -0x1.0000000000000p+0f16, + -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, + }, + }, +}; + +float TEST_BINOP_DATA(float, min)[][4][N] = +{ + { + { 0x1.0000000000000p+0f }, + { + 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, + 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, + 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, + 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, + }, + { + 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, + 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, + 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, + 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, + }, + }, + { + { 0x1.0000000000000p+0f }, + { + -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, + 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, + -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, + -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, + }, + { + -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, + 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, + -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, + -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, + }, + }, + { + { -0x1.bc16d60000000p+59f }, + { + -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, + -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, + 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, + -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, + }, + { + -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, + -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, + -0x1.bc16d60000000p+59f, -0x1.bc16d60000000p+59f, -0x1.bc16d60000000p+59f, -0x1.bc16d60000000p+59f, + -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, + }, + }, +}; + +double TEST_BINOP_DATA(double, min)[][4][N] = +{ + { + { 0x1.0000000000000p+0 }, + { + 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, + 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, + 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, + 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, + }, + { + 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, + 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, + 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, + 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, + }, + }, + { + { 0x1.0000000000000p+0 }, + { + -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, + 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, + -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, + -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, + }, + { + -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, + 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, + -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, + -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, + }, + }, + { + { -0x1.317e5ef3ab327p+508 }, + { + -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, + -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, + 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, + -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, + }, + { + -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, + -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, + -0x1.317e5ef3ab327p+508, -0x1.317e5ef3ab327p+508, -0x1.317e5ef3ab327p+508, -0x1.317e5ef3ab327p+508, + -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, + }, + }, +}; + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_run.h new file mode 100644 index 0000000..aa70e7c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_run.h @@ -0,0 +1,42 @@ +#ifndef HAVE_DEFINED_VF_BINOP_RUN_H +#define HAVE_DEFINED_VF_BINOP_RUN_H + +#include <math.h> +#include <stdio.h> + +#define TYPE_FABS(x, T) \ + (__builtin_types_compatible_p (T, double) ? fabs (x) : fabsf (x)) + +#define MAX_RELATIVE_DIFF(T) \ + (__builtin_types_compatible_p (T, _Float16) ? 0.1f : \ + (__builtin_types_compatible_p (T, float) ? 0.01f : 0.01)) + +int +main () +{ + unsigned i, k; + T out[N]; + + for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++) + { + T f = TEST_DATA[i][0][0]; + T *in = TEST_DATA[i][1]; + T *expect = TEST_DATA[i][2]; + + TEST_RUN (T, NAME, out, in, f, N); + + for (k = 0; k < N; k++) + { + T diff = expect[k] - out[k]; + if (TYPE_FABS (diff, T) + > MAX_RELATIVE_DIFF (T) * TYPE_FABS (expect[k], T)) { + printf("Mismatch at i=%u, k=%u: expect=%f, out=%f, diff=%f\n", i, k, (double)expect[k], (double)out[k], (double)diff); + __builtin_abort (); + } + } + } + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c index fd8aa30..a54d9a1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c index 8fd8552..2289d04 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f16.c new file mode 100644 index 0000000..c84c773 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f16.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" +#include "vf_binop_data.h" + +#define T _Float16 +#define FUNC MIN_FUNC_0_WRAP(T) +#define NAME min + +DEF_VF_BINOP_CASE_2_WRAP (T, FUNC, NAME) + +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_2_WRAP(T, NAME, FUNC, out, in, f, n) + +#include "vf_binop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f32.c new file mode 100644 index 0000000..a2d024e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" +#include "vf_binop_data.h" + +#define T float +#define FUNC MIN_FUNC_0_WRAP(T) +#define NAME min + +DEF_VF_BINOP_CASE_2_WRAP (T, FUNC, NAME) + +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_2_WRAP(T, NAME, FUNC, out, in, f, n) + +#include "vf_binop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f64.c new file mode 100644 index 0000000..9a66f18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" +#include "vf_binop_data.h" + +#define T double +#define FUNC MIN_FUNC_0_WRAP(T) +#define NAME min + +DEF_VF_BINOP_CASE_2_WRAP (T, FUNC, NAME) + +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_2_WRAP(T, NAME, FUNC, out, in, f, n) + +#include "vf_binop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c index e91fd15..b6d944c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c index ca7e0db..e9253fe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f16.c new file mode 100644 index 0000000..5d57ec8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f16.c @@ -0,0 +1,19 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" +#include "vf_binop_data.h" + +#define T _Float16 +#define NAME mul + +DEF_VF_BINOP_CASE_0_WRAP (T, *, NAME) + +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_0_WRAP(T, NAME, out, in, f, n) + +#include "vf_binop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f32.c new file mode 100644 index 0000000..337380a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" +#include "vf_binop_data.h" + +#define T float +#define NAME mul + +DEF_VF_BINOP_CASE_0_WRAP (T, *, NAME) + +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_0_WRAP(T, NAME, out, in, f, n) + +#include "vf_binop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f64.c new file mode 100644 index 0000000..ec3d562 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" +#include "vf_binop_data.h" + +#define T double +#define NAME mul + +DEF_VF_BINOP_CASE_0_WRAP (T, *, NAME) + +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_0_WRAP(T, NAME, out, in, f, n) + +#include "vf_binop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c index b38e800..397e283 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c index fef5d77..6d846a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c index 7951d40..0b4f6e1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c index d0def86..acc7aa3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f16.c new file mode 100644 index 0000000..07fb540 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f16.c @@ -0,0 +1,19 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" +#include "vf_binop_data.h" + +#define T _Float16 +#define NAME rdiv + +DEF_VF_BINOP_REVERSE_CASE_0_WRAP (T, /, NAME) + +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_REVERSE_CASE_0_WRAP(T, NAME, out, in, f, n) + +#include "vf_binop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f32.c new file mode 100644 index 0000000..2fda776 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" +#include "vf_binop_data.h" + +#define T float +#define NAME rdiv + +DEF_VF_BINOP_REVERSE_CASE_0_WRAP (T, /, NAME) + +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_REVERSE_CASE_0_WRAP(T, NAME, out, in, f, n) + +#include "vf_binop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f64.c new file mode 100644 index 0000000..8f2958f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_binop.h" +#include "vf_binop_data.h" + +#define T double +#define NAME rdiv + +DEF_VF_BINOP_REVERSE_CASE_0_WRAP (T, /, NAME) + +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_REVERSE_CASE_0_WRAP(T, NAME, out, in, f, n) + +#include "vf_binop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c index d4c527a..a858d27 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c index abce2f2..a04bd91 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c index ddf49d5..a00d620 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c index a874991..eeae215 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c @@ -1,6 +1,6 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-require-effective-target riscv_v_ok } */ -/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-require-effective-target riscv_zvfh_ok } */ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvfh" } */ /* { dg-additional-options "--param=fpr2vr-cost=0" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c index f84d7f5..ad2dacd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int16_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -20,4 +22,6 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmin.vx} 2 } } */ /* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssub.vx} 1 } } */ -/* { dg-final { scan-assembler-times {vaadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c index 70b6743..ebcdb0a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int32_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -20,4 +22,6 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmin.vx} 2 } } */ /* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssub.vx} 1 } } */ -/* { dg-final { scan-assembler-times {vaadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c index 986fa4c..f15d7b5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int64_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -20,4 +22,9 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmin.vx} 2 } } */ /* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssub.vx} 1 } } */ -/* { dg-final { scan-assembler-times {vaadd.vx} 1 { target { no-opts "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" } } } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 2 { target { no-opts + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } */ +/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c index c479295..c997348 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int8_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -20,4 +22,6 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmin.vx} 2 } } */ /* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssub.vx} 1 } } */ -/* { dg-final { scan-assembler-times {vaadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c index cb62e0f..27204de 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint16_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c index e2a5dbb..4c655c5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint32_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c index e7b1ef0..27f5253 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint64_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -19,4 +21,9 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vminu.vx} 2 } } */ /* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ -/* { dg-final { scan-assembler-times {vaaddu.vx} 1 { target { no-opts "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" } } } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 2 { target { no-opts { + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ +/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c index 559887e..8622b30 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint8_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -19,4 +21,6 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vminu.vx} 2 } } */ /* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ -/* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c index 05801a9..db272ef 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int16_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -21,3 +23,5 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler-not {vaadd.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c index f05f091..b3f99ba 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int32_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -21,3 +23,5 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler-not {vaadd.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c index adf9ccb..4fdf8f9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int64_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -21,3 +23,5 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler-not {vaadd.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c index 8b3f5bc..02cf934 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int8_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -21,3 +23,5 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler-not {vaadd.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c index 365e650..330d541 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint16_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c index c8fd42a..7095cc7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint32_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c index bdb76b4..29824ed 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint64_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c index fc9c101..525dd38 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint8_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c index 741f431..94f83ff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int16_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -21,3 +23,5 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler-not {vaadd.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c index 1741c22..7746809 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int32_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -21,3 +23,5 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler-not {vaadd.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c index d326357..ed31e79 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int64_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -21,3 +23,5 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler-not {vaadd.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c index 3137dc0..b9d1ddc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T int8_t TEST_BINARY_VX_SIGNED_0(T) +TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -21,3 +23,5 @@ TEST_BINARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler-not {vaadd.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c index 121daeb..7c98625 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint16_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c index 9616e7f..9de7c9f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint32_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c index cf985f0..b35a9b7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint64_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c index 3bb382d..9eeb272 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c @@ -2,10 +2,12 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ #include "vx_binary.h" +#include "vx_ternary.h" #define T uint8_t TEST_BINARY_VX_UNSIGNED_0(T) +TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -20,3 +22,5 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vmacc.vx} } } */ +/* { dg-final { scan-assembler-not {vnmsac.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c index 86c8040..2ae4804 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c index e2d1613..88cfc72 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c index 06ffa15..6b29a72 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -35,4 +36,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_B /* { dg-final { scan-assembler {vmin.vx} } } */ /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ -/* { dg-final { scan-assembler {vaadd.vx} { target { no-opts "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" } } } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { no-opts { + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c index cb086aa..f862eb7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c index c851f23..3ecfce6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c index b7805c1..7ce1fe8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -31,5 +32,6 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_B /* { dg-final { scan-assembler {vremu.vx} } } */ /* { dg-final { scan-assembler {vmaxu.vx} } } */ /* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler {vsaddu.vx} } } */ /* { dg-final { scan-assembler {vssubu.vx} } } */ /* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c index 8295dc2..c84a30c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -33,4 +34,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_B /* { dg-final { scan-assembler {vminu.vx} } } */ /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ -/* { dg-final { scan-assembler {vaaddu.vx} { target { no-opts "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" } } } } */ +/* { dg-final { scan-assembler {vaaddu.vx} { target { no-opts { + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c index d214da9..9f3d7df 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c index 7c7bf09..df6872c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c index 6d161bd..05ed639 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c index 0409012..6776b1f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c index ed437319..d3e2785 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c index b7c7ad4..5497b5a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c index dd9c845..3a8e85f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c index 1fda062..060d591 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c index 725a55b..86a6c45 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c index 1e18342..9a1ff3a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c @@ -12,8 +12,8 @@ DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X8) DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X8) DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X8) DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X8) -DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) -DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c index fd6e47c..3e3acfc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c index 399d0f5..531c119 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c index 98567a3..990f3e4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c @@ -13,7 +13,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) -DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) @@ -21,6 +21,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c index 3a215ea..f51e7a1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c index ac4d100..79b7477 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c index 5eb0ed6..ac5fd69 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c index 8b404b6..84aa06b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c @@ -20,6 +20,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i16.c new file mode 100644 index 0000000..3770c96 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int16_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-times {vmerge.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i32.c new file mode 100644 index 0000000..1016100 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i32.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int32_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-times {vmerge.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i64.c new file mode 100644 index 0000000..6df25b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i64.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int64_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-times {vmerge.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i8.c new file mode 100644 index 0000000..738adb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-1-i8.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int8_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-times {vmerge.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i16.c new file mode 100644 index 0000000..340a4aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int16_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-not {vmerge.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i32.c new file mode 100644 index 0000000..cba6822 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i32.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int32_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-not {vmerge.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i64.c new file mode 100644 index 0000000..45efd3a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i64.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int64_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-not {vmerge.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i8.c new file mode 100644 index 0000000..b6f0000 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-2-i8.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int8_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-not {vmerge.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i16.c new file mode 100644 index 0000000..c1e1b30 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T int16_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-not {vmerge.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i32.c new file mode 100644 index 0000000..a626720 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i32.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T int32_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-not {vmerge.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i64.c new file mode 100644 index 0000000..17dc5bf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i64.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T int64_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-not {vmerge.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i8.c new file mode 100644 index 0000000..2aee2cf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-merge-3-i8.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T int8_t + +DEF_VX_MERGE_0_WRAP(T) + +/* { dg-final { scan-assembler-not {vmerge.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h index b7c0f79..353ee16 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h @@ -363,14 +363,35 @@ DEF_AVG_FLOOR(int8_t, int16_t) DEF_AVG_FLOOR(int16_t, int32_t) DEF_AVG_FLOOR(int32_t, int64_t) +#define DEF_AVG_CEIL(NT, WT) \ +NT \ +test_##NT##_avg_ceil(NT x, NT y) \ +{ \ + return (NT)(((WT)x + (WT)y + 1) >> 1); \ +} + +DEF_AVG_CEIL(uint8_t, uint16_t) +DEF_AVG_CEIL(uint16_t, uint32_t) +DEF_AVG_CEIL(uint32_t, uint64_t) + +DEF_AVG_CEIL(int8_t, int16_t) +DEF_AVG_CEIL(int16_t, int32_t) +DEF_AVG_CEIL(int32_t, int64_t) + #ifdef HAS_INT128 DEF_AVG_FLOOR(uint64_t, uint128_t) DEF_AVG_FLOOR(int64_t, int128_t) + + DEF_AVG_CEIL(uint64_t, uint128_t) + DEF_AVG_CEIL(int64_t, int128_t) #endif #define AVG_FLOOR_FUNC(T) test_##T##_avg_floor #define AVG_FLOOR_FUNC_WRAP(T) AVG_FLOOR_FUNC(T) +#define AVG_CEIL_FUNC(T) test_##T##_avg_ceil +#define AVG_CEIL_FUNC_WRAP(T) AVG_CEIL_FUNC(T) + #define TEST_BINARY_VX_SIGNED_0(T) \ DEF_VX_BINARY_CASE_0_WRAP(T, +, add) \ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub) \ @@ -388,6 +409,7 @@ DEF_AVG_FLOOR(int32_t, int64_t) DEF_VX_BINARY_CASE_2_WRAP(T, SAT_S_ADD_FUNC(T), sat_add) \ DEF_VX_BINARY_CASE_2_WRAP(T, SAT_S_SUB_FUNC(T), sat_sub) \ DEF_VX_BINARY_CASE_2_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor) \ + DEF_VX_BINARY_CASE_2_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil) \ #define TEST_BINARY_VX_UNSIGNED_0(T) \ DEF_VX_BINARY_CASE_0_WRAP(T, +, add) \ @@ -405,5 +427,28 @@ DEF_AVG_FLOOR(int32_t, int64_t) DEF_VX_BINARY_CASE_2_WRAP(T, SAT_U_ADD_FUNC(T), sat_add) \ DEF_VX_BINARY_CASE_2_WRAP(T, SAT_U_SUB_FUNC(T), sat_sub) \ DEF_VX_BINARY_CASE_2_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor) \ + DEF_VX_BINARY_CASE_2_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil) \ + +/* For some special cases cannot be normalized as above */ + +#define DEF_VX_MERGE_0(T) \ +void \ +test_vx_merge_##T##_case_0 (T * restrict out, T * restrict in, \ + T x, unsigned n) \ +{ \ + for (unsigned i = 0; i < n; i++) \ + { \ + if (i % 2 == 0) \ + out[i] = x; \ + else \ + out[i] = in[i]; \ + } \ +} + +#define DEF_VX_MERGE_0_WRAP(T) DEF_VX_MERGE_0(T) + +#define RUN_VX_MERGE_0(T, out, in, x, n) \ + test_vx_merge_##T##_case_0(out, in, x, n) +#define RUN_VX_MERGE_0_WRAP(T, out, in, x, n) RUN_VX_MERGE_0(T, out, in, x, n) #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h index 6847309..e385bf2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h @@ -5298,4 +5298,592 @@ int64_t TEST_BINARY_DATA(int64_t, avg_floor)[][3][N] = }, }; +uint8_t TEST_BINARY_DATA(uint8_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 255, 255, 255, 255, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 191, 191, 191, 191, + 64, 64, 64, 64, + }, + }, + { + { 255 }, + { + 0, 0, 0, 0, + 255, 255, 255, 255, + 254, 254, 254, 254, + 1, 1, 1, 1, + }, + { + 128, 128, 128, 128, + 255, 255, 255, 255, + 255, 255, 255, 255, + 128, 128, 128, 128, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 49151, 49151, 49151, 49151, + 16384, 16384, 16384, 16384, + }, + }, + { + { 65535 }, + { + 0, 0, 0, 0, + 65535, 65535, 65535, 65535, + 65534, 65534, 65534, 65534, + 1, 1, 1, 1, + }, + { + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 32768, 32768, 32768, 32768, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 3221225471, 3221225471, 3221225471, 3221225471, + 1073741824, 1073741824, 1073741824, 1073741824, + }, + }, + { + { 4294967295 }, + { + 0, 0, 0, 0, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967294, 4294967294, 4294967294, 4294967294, + 1, 1, 1, 1, + }, + { + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 13835058055282163711ull, 13835058055282163711ull, 13835058055282163711ull, 13835058055282163711ull, + 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, + }, + }, + { + { 18446744073709551615ull }, + { + 0, 0, 0, 0, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 1, 1, 1, 1, + }, + { + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -128, -128, -128, -128, + -127, -127, -127, -127, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 0, 0, 0, 0, + 0, 0, 0, 0, + 64, 64, 64, 64, + }, + }, + { + {-128 }, + { + 0, 0, 0, 0, + -128, -128, -128, -128, + 126, 126, 126, 126, + 127, 127, 127, 127, + }, + { + -64, -64, -64, -64, + -128, -128, -128, -128, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 0, 0, 0, 0, + 0, 0, 0, 0, + 16384, 16384, 16384, 16384, + }, + }, + { + {-32768 }, + { + 0, 0, 0, 0, + -32768, -32768, -32768, -32768, + 32766, 32766, 32766, 32766, + 32767, 32767, 32767, 32767, + }, + { + -16384, -16384, -16384, -16384, + -32768, -32768, -32768, -32768, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 0, 0, 0, 0, + 0, 0, 0, 0, + 1073741824, 1073741824, 1073741824, 1073741824, + }, + }, + { + {-2147483648 }, + { + 0, 0, 0, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + 2147483646, 2147483646, 2147483646, 2147483646, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + { + -1073741824, -1073741824, -1073741824, -1073741824, + -2147483648, -2147483648, -2147483648, -2147483648, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 0, 0, 0, 0, + 0, 0, 0, 0, + 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, + }, + }, + { + {-9223372036854775808ull }, + { + 0, 0, 0, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + }, + { + -4611686018427387904ull, -4611686018427387904ull, -4611686018427387904ull, -4611686018427387904ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, merge)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 0, 2, 0, 2, + 0, 1, 0, 1, + 0, 0, 0, 0, + 0, 4, 0, 4, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -128, -128, -128, -128, + -127, -127, -127, -127, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 127, -128, 127, -128, + 127, -127, 127, -127, + 127, 1, 127, 1, + }, + }, + { + {-128 }, + { + 0, 0, 0, 0, + -128, -128, -128, -128, + 126, 126, 126, 126, + 127, 127, 127, 127, + }, + { + -128, 0, -128, 0, + -128, -128, -128, -128, + -128, 126, -128, 126, + -128, 127, -128, 127, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, merge)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 0, 2, 0, 2, + 0, 1, 0, 1, + 0, 0, 0, 0, + 0, 4, 0, 4, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 32767, -32768, 32767, -32768, + 32767, -32767, 32767, -32767, + 32767, 1, 32767, 1, + }, + }, + { + {-32768 }, + { + 0, 0, 0, 0, + -32768, -32768, -32768, -32768, + 32766, 32766, 32766, 32766, + 32767, 32767, 32767, 32767, + }, + { + -32768, 0, -32768, 0, + -32768, -32768, -32768, -32768, + -32768, 32766, -32768, 32766, + -32768, 32767, -32768, 32767, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, merge)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 0, 2, 0, 2, + 0, 1, 0, 1, + 0, 0, 0, 0, + 0, 4, 0, 4, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, -2147483648, 2147483647, -2147483648, + 2147483647, -2147483647, 2147483647, -2147483647, + 2147483647, 1, 2147483647, 1, + }, + }, + { + {-2147483648 }, + { + 0, 0, 0, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + 2147483646, 2147483646, 2147483646, 2147483646, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + { + -2147483648, 0, -2147483648, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, 2147483646, -2147483648, 2147483646, + -2147483648, 2147483647, -2147483648, 2147483647, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, merge)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 0, 2, 0, 2, + 0, 1, 0, 1, + 0, 0, 0, 0, + 0, 4, 0, 4, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, -9223372036854775808ull, 9223372036854775807ull, -9223372036854775808ull, + 9223372036854775807ull, -9223372036854775807ull, 9223372036854775807ull, -9223372036854775807ull, + 9223372036854775807ull, 1, 9223372036854775807ull, 1, + }, + }, + { + {-9223372036854775808ull }, + { + 0, 0, 0, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + }, + { + -9223372036854775808ull, 0, -9223372036854775808ull, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775808ull, 9223372036854775806ull, -9223372036854775808ull, 9223372036854775806ull, + -9223372036854775808ull, 9223372036854775807ull, -9223372036854775808ull, 9223372036854775807ull, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h new file mode 100644 index 0000000..2325c7b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h @@ -0,0 +1,37 @@ +#ifndef HAVE_DEFINED_VX_VF_TERNARY_H +#define HAVE_DEFINED_VX_VF_TERNARY_H + +#include <stdint.h> + +#undef HAS_INT128 + +#if __riscv_xlen == 64 +#define HAS_INT128 +typedef unsigned __int128 uint128_t; +typedef signed __int128 int128_t; +#endif + +#define DEF_VX_TERNARY_CASE_0(T, OP_1, OP_2, NAME) \ +void \ +test_vx_ternary_##NAME##_##T##_case_0 (T * restrict vd, T * restrict vs2, \ + T rs1, unsigned n) \ +{ \ + for (unsigned i = 0; i < n; i++) \ + vd[i] = vd[i] OP_2 vs2[i] OP_1 rs1; \ +} +#define DEF_VX_TERNARY_CASE_0_WRAP(T, OP_1, OP_2, NAME) \ + DEF_VX_TERNARY_CASE_0(T, OP_1, OP_2, NAME) +#define RUN_VX_TERNARY_CASE_0(T, NAME, vd, vs2, rs1, n) \ + test_vx_ternary_##NAME##_##T##_case_0 (vd, vs2, rs1, n) +#define RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0(T, NAME, vd, vs2, rs1, n) + +#define TEST_TERNARY_VX_SIGNED_0(T) \ + DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, macc) \ + DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, nmsac) \ + +#define TEST_TERNARY_VX_UNSIGNED_0(T) \ + DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, macc) \ + DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, nmsac) \ + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h new file mode 100644 index 0000000..9ac1a7d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h @@ -0,0 +1,745 @@ +#ifndef HAVE_DEFINED_VX_TERNARY_DATA_H +#define HAVE_DEFINED_VX_TERNARY_DATA_H + +#define N 16 + +#define TEST_TERNARY_DATA(T, NAME) test_##T##_##NAME##_data +#define TEST_TERNARY_DATA_WRAP(T, NAME) TEST_TERNARY_DATA(T, NAME) + +int8_t TEST_TERNARY_DATA(int8_t, macc)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + -1, -1, -1, -1, + -3, -3, -3, -3, + }, + }, + { + { 127 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 9, 9, 9, 9, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { /* vd */ + 127, 127, 127, 127, + 2, 2, 2, 2, + 0, 0, 0, 0, + -128, -128, -128, -128, + }, + { + 127, 127, 127, 127, + 121, 121, 121, 121, + 8, 8, 8, 8, + -126, -126, -126, -126, + }, + }, +}; + +int16_t TEST_TERNARY_DATA(int16_t, macc)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + -1, -1, -1, -1, + -3, -3, -3, -3, + }, + }, + { + { 32767 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 9, 9, 9, 9, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { /* vd */ + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + 0, 0, 0, 0, + -32768, -32768, -32768, -32768, + }, + { + 32767, 32767, 32767, 32767, + 32761, 32761, 32761, 32761, + 8, 8, 8, 8, + -32766, -32766, -32766, -32766, + }, + }, +}; + +int32_t TEST_TERNARY_DATA(int32_t, macc)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + -1, -1, -1, -1, + -3, -3, -3, -3, + }, + }, + { + { 2147483647 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 9, 9, 9, 9, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { /* vd */ + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + 0, 0, 0, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483641, 2147483641, 2147483641, 2147483641, + 8, 8, 8, 8, + -2147483646, -2147483646, -2147483646, -2147483646, + }, + }, +}; + +int64_t TEST_TERNARY_DATA(int64_t, macc)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + -1, -1, -1, -1, + -3, -3, -3, -3, + }, + }, + { + { 9223372036854775807ull }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 9, 9, 9, 9, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { /* vd */ + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + 0, 0, 0, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775801ull, 9223372036854775801ull, 9223372036854775801ull, 9223372036854775801ull, + 8, 8, 8, 8, + -9223372036854775806ull, -9223372036854775806ull, -9223372036854775806ull, -9223372036854775806ull, + }, + }, +}; + +uint8_t TEST_TERNARY_DATA(uint8_t, macc)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 6, 6, 6, 6, + 3, 3, 3, 3, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + 6, 6, 6, 6, + 7, 7, 7, 7, + }, + }, + { + { 255 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 5, 5, 5, 5, + 3, 3, 3, 3, + 1, 1, 1, 1, + }, + { /* vd */ + 127, 127, 127, 127, + 255, 255, 255, 255, + 0, 0, 0, 0, + 128, 128, 128, 128, + }, + { + 127, 127, 127, 127, + 250, 250, 250, 250, + 253, 253, 253, 253, + 127, 127, 127, 127, + }, + }, +}; + +uint16_t TEST_TERNARY_DATA(uint16_t, macc)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 6, 6, 6, 6, + 3, 3, 3, 3, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + 6, 6, 6, 6, + 7, 7, 7, 7, + }, + }, + { + { 65535 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 5, 5, 5, 5, + 3, 3, 3, 3, + 1, 1, 1, 1, + }, + { /* vd */ + 32767, 32767, 32767, 32767, + 65535, 65535, 65535, 65535, + 0, 0, 0, 0, + 32768, 32768, 32768, 32768, + }, + { + 32767, 32767, 32767, 32767, + 65530, 65530, 65530, 65530, + 65533, 65533, 65533, 65533, + 32767, 32767, 32767, 32767, + }, + }, +}; + +uint32_t TEST_TERNARY_DATA(uint32_t, macc)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 6, 6, 6, 6, + 3, 3, 3, 3, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + 6, 6, 6, 6, + 7, 7, 7, 7, + }, + }, + { + { 4294967295 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 5, 5, 5, 5, + 3, 3, 3, 3, + 1, 1, 1, 1, + }, + { /* vd */ + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967295, 4294967295, 4294967295, 4294967295, + 0, 0, 0, 0, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967290, 4294967290, 4294967290, 4294967290, + 4294967293, 4294967293, 4294967293, 4294967293, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + }, +}; + +uint64_t TEST_TERNARY_DATA(uint64_t, macc)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 6, 6, 6, 6, + 3, 3, 3, 3, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + 6, 6, 6, 6, + 7, 7, 7, 7, + }, + }, + { + { 18446744073709551615ull }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 5, 5, 5, 5, + 3, 3, 3, 3, + 1, 1, 1, 1, + }, + { /* vd */ + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 0, 0, 0, 0, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 18446744073709551610ull, 18446744073709551610ull, 18446744073709551610ull, 18446744073709551610ull, + 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + }, + }, +}; + +int8_t TEST_TERNARY_DATA(int8_t, nmsac)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { 127 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { /* vd */ + 127, 127, 127, 127, + 2, 2, 2, 2, + 0, 0, 0, 0, + -128, -128, -128, -128, + }, + { + 127, 127, 127, 127, + -125, -125, -125, -125, + -8, -8, -8, -8, + 126, 126, 126, 126, + }, + }, +}; + +int16_t TEST_TERNARY_DATA(int16_t, nmsac)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { 32767 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { /* vd */ + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + 0, 0, 0, 0, + -32768, -32768, -32768, -32768, + }, + { + 32767, 32767, 32767, 32767, + -32765, -32765, -32765, -32765, + -8, -8, -8, -8, + 32766, 32766, 32766, 32766, + }, + }, +}; + +int32_t TEST_TERNARY_DATA(int32_t, nmsac)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { 2147483647 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { /* vd */ + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + 0, 0, 0, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483645, -2147483645, -2147483645, -2147483645, + -8, -8, -8, -8, + 2147483646, 2147483646, 2147483646, 2147483646, + }, + }, +}; + +int64_t TEST_TERNARY_DATA(int64_t, nmsac)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { 9223372036854775807ull }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + -8, -8, -8, -8, + -2, -2, -2, -2, + }, + { /* vd */ + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + 0, 0, 0, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775805ull, -9223372036854775805ull, -9223372036854775805ull, -9223372036854775805ull, + -8, -8, -8, -8, + 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, + }, + }, +}; + +uint8_t TEST_TERNARY_DATA(uint8_t, nmsac)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 7, 7, 7, 7, + 5, 5, 5, 5, + }, + }, + { + { 128 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 8, 8, 8, 8, + 2, 2, 2, 2, + }, + { /* vd */ + 127, 127, 127, 127, + 255, 255, 255, 255, + 254, 254, 254, 254, + 252, 252, 252, 252, + }, + { + 127, 127, 127, 127, + 127, 127, 127, 127, + 254, 254, 254, 254, + 252, 252, 252, 252, + }, + }, +}; + +uint16_t TEST_TERNARY_DATA(uint16_t, nmsac)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 7, 7, 7, 7, + 5, 5, 5, 5, + }, + }, + { + { 32768 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 8, 8, 8, 8, + 2, 2, 2, 2, + }, + { /* vd */ + 32767, 32767, 32767, 32767, + 65535, 65535, 65535, 65535, + 65534, 65534, 65534, 65534, + 65532, 65532, 65532, 65532, + }, + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + 65534, 65534, 65534, 65534, + 65532, 65532, 65532, 65532, + }, + }, +}; + +uint32_t TEST_TERNARY_DATA(uint32_t, nmsac)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 7, 7, 7, 7, + 5, 5, 5, 5, + }, + }, + { + { 2147483648 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 8, 8, 8, 8, + 2, 2, 2, 2, + }, + { /* vd */ + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967292, 4294967292, 4294967292, 4294967292, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967292, 4294967292, 4294967292, 4294967292, + }, + }, +}; + +uint64_t TEST_TERNARY_DATA(uint64_t, nmsac)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + { /* vd */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 7, 7, 7, 7, + 5, 5, 5, 5, + }, + }, + { + { 9223372036854775808ull }, /* rs1 */ + { /* vs2 */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 8, 8, 8, 8, + 2, 2, 2, 2, + }, + { /* vd */ + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, + }, + }, +}; + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_run.h new file mode 100644 index 0000000..cf1926f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_run.h @@ -0,0 +1,26 @@ +#ifndef HAVE_DEFINED_VX_TERNARY_RUN_H +#define HAVE_DEFINED_VX_TERNARY_RUN_H + +int +main () +{ + unsigned i, k; + + for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++) + { + T rs1 = TEST_DATA[i][0][0]; + T *vs2 = TEST_DATA[i][1]; + T *vd = TEST_DATA[i][2]; + T *expect = TEST_DATA[i][3]; + + TEST_RUN (T, NAME, vd, vs2, rs1, N); + + for (k = 0; k < N; k++) + if (vd[k] != expect[k]) + __builtin_abort (); + } + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i16.c new file mode 100644 index 0000000..8def643 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i32.c new file mode 100644 index 0000000..d9ca67d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i64.c new file mode 100644 index 0000000..313109a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i8.c new file mode 100644 index 0000000..47e4a5d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u16.c new file mode 100644 index 0000000..6297672 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u32.c new file mode 100644 index 0000000..30db24b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u64.c new file mode 100644 index 0000000..db3c911 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u8.c new file mode 100644 index 0000000..a7755f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i16.c new file mode 100644 index 0000000..1310727 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int16_t +#define NAME macc +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i32.c new file mode 100644 index 0000000..10174cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int32_t +#define NAME macc +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i64.c new file mode 100644 index 0000000..a33f714 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int64_t +#define NAME macc +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i8.c new file mode 100644 index 0000000..dbb1c67 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int8_t +#define NAME macc +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u16.c new file mode 100644 index 0000000..8ec9d05 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint16_t +#define NAME macc +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u32.c new file mode 100644 index 0000000..46d5c4d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint32_t +#define NAME macc +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u64.c new file mode 100644 index 0000000..cd857b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint64_t +#define NAME macc +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u8.c new file mode 100644 index 0000000..05fa397 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint8_t +#define NAME macc +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i16.c new file mode 100644 index 0000000..2845874 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME merge + +DEF_VX_MERGE_0_WRAP(T) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_MERGE_0_WRAP(T, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i32.c new file mode 100644 index 0000000..57545fb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME merge + +DEF_VX_MERGE_0_WRAP(T) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_MERGE_0_WRAP(T, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i64.c new file mode 100644 index 0000000..fbcb086 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME merge + +DEF_VX_MERGE_0_WRAP(T) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_MERGE_0_WRAP(T, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i8.c new file mode 100644 index 0000000..0c5500a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmerge-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME merge + +DEF_VX_MERGE_0_WRAP(T) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_MERGE_0_WRAP(T, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i16.c new file mode 100644 index 0000000..6deee02 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int16_t +#define NAME nmsac +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i32.c new file mode 100644 index 0000000..65d376b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int32_t +#define NAME nmsac +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i64.c new file mode 100644 index 0000000..832023a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int64_t +#define NAME nmsac +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i8.c new file mode 100644 index 0000000..ae48e2e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T int8_t +#define NAME nmsac +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u16.c new file mode 100644 index 0000000..9427fdd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint16_t +#define NAME nmsac +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u32.c new file mode 100644 index 0000000..da9fc9c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint32_t +#define NAME nmsac +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u64.c new file mode 100644 index 0000000..5e4cde4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint64_t +#define NAME nmsac +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u8.c new file mode 100644 index 0000000..ab52580 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint8_t +#define NAME nmsac +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h index e40902a..035545c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h @@ -693,4 +693,52 @@ sat_u_mul_##NT##_from_##WT##_fmt_1 (NT a, NT b) \ sat_u_mul_##NT##_from_##WT##_fmt_1 (a, b) #define RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, a, b) RUN_SAT_U_MUL_FMT_1(NT, WT, a, b) +#define DEF_SAT_U_MUL_FMT_2(T) \ +T __attribute__((noinline)) \ +sat_u_mul_##T##_fmt_2 (T a, T b) \ +{ \ + T result; \ + if (__builtin_mul_overflow(a, b, &result)) \ + return -1; \ + else \ + return result; \ +} + +#define DEF_SAT_U_MUL_FMT_2_WRAP(T) DEF_SAT_U_MUL_FMT_2(T) +#define RUN_SAT_U_MUL_FMT_2(T, a, b) sat_u_mul_##T##_fmt_2 (a, b) +#define RUN_SAT_U_MUL_FMT_2_WRAP(T, a, b) RUN_SAT_U_MUL_FMT_2(T, a, b) + +#define DEF_SAT_U_MUL_FMT_3(NT, WT) \ +NT __attribute__((noinline)) \ +sat_u_mul_##NT##_from_##WT##_fmt_3 (NT a, NT b) \ +{ \ + WT x = (WT)a * (WT)b; \ + if ((x >> sizeof(a) * 8) == 0) \ + return (NT)x; \ + else \ + return (NT)-1; \ +} + +#define DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) DEF_SAT_U_MUL_FMT_3(NT, WT) +#define RUN_SAT_U_MUL_FMT_3(NT, WT, a, b) \ + sat_u_mul_##NT##_from_##WT##_fmt_3 (a, b) +#define RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, a, b) RUN_SAT_U_MUL_FMT_3(NT, WT, a, b) + +#define DEF_SAT_U_MUL_FMT_4(NT, WT) \ +NT __attribute__((noinline)) \ +sat_u_mul_##NT##_from_##WT##_fmt_4 (NT a, NT b) \ +{ \ + WT x = (WT)a * (WT)b; \ + NT max = -1; \ + if (x >= (WT)(max)) \ + return max; \ + else \ + return (NT)x; \ +} + +#define DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) DEF_SAT_U_MUL_FMT_4(NT, WT) +#define RUN_SAT_U_MUL_FMT_4(NT, WT, a, b) \ + sat_u_mul_##NT##_from_##WT##_fmt_4 (a, b) +#define RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, a, b) RUN_SAT_U_MUL_FMT_4(NT, WT, a, b) + #endif diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u32.c new file mode 100644 index 0000000..7409232 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint32_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c index 8d5449b..fa3758a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c @@ -9,3 +9,5 @@ DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) /* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ +/* { dg-final { scan-assembler-times "mulhu" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c index d8a01d1..b1bf4fa 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c @@ -10,3 +10,4 @@ DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) /* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ /* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ +/* { dg-final { scan-assembler-times "mulhu" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u16.c new file mode 100644 index 0000000..ec79e5d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u16.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint16_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u32.c new file mode 100644 index 0000000..eb95184 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint32_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u16-from-u64.c new file mode 100644 index 0000000..b1d33a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u16-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u32-from-u64.c new file mode 100644 index 0000000..af5ffecf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u32-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u8-from-u64.c new file mode 100644 index 0000000..d65cab0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u8-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u16.c new file mode 100644 index 0000000..714a7f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u16.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define T uint16_t + +DEF_SAT_U_MUL_FMT_2_WRAP(T) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u32.c new file mode 100644 index 0000000..bd6eafc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define T uint32_t + +DEF_SAT_U_MUL_FMT_2_WRAP(T) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u64.c new file mode 100644 index 0000000..c96687f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define T uint64_t + +DEF_SAT_U_MUL_FMT_2_WRAP(T) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u8.c new file mode 100644 index 0000000..a92447f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u8.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define T uint8_t + +DEF_SAT_U_MUL_FMT_2_WRAP(T) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u128.c new file mode 100644 index 0000000..1093701 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u128.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u32.c new file mode 100644 index 0000000..c7bff58 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint32_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u64.c new file mode 100644 index 0000000..13b13ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u64.rv32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u64.rv32.c new file mode 100644 index 0000000..b1f7d7a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u64.rv32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u128.c new file mode 100644 index 0000000..0775bb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u128.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u64.c new file mode 100644 index 0000000..0cbd4e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u64.rv32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u64.rv32.c new file mode 100644 index 0000000..99d15b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u64.rv32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ +/* { dg-final { scan-assembler-times "mulhu" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u64-from-u128.c new file mode 100644 index 0000000..70b1389 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u64-from-u128.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint64_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ +/* { dg-final { scan-assembler-times "mulhu" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u128.c new file mode 100644 index 0000000..4474eb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u128.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u16.c new file mode 100644 index 0000000..eef6490 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u16.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint16_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u32.c new file mode 100644 index 0000000..8e839c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint32_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u64.c new file mode 100644 index 0000000..81a3a24 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u64.rv32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u64.rv32.c new file mode 100644 index 0000000..40bfcef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u64.rv32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u128.c new file mode 100644 index 0000000..d3cef16 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u128.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u32.c new file mode 100644 index 0000000..d7e7356 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint32_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv32.c new file mode 100644 index 0000000..7533823 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32 -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv64.c new file mode 100644 index 0000000..ae4f8c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u128.c new file mode 100644 index 0000000..037497c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u128.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv32.c new file mode 100644 index 0000000..f10cd40 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32 -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv64.c new file mode 100644 index 0000000..6229f51 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u64-from-u128.c new file mode 100644 index 0000000..e852851 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u64-from-u128.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint64_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u128.c new file mode 100644 index 0000000..4ae5c8c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u128.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u16.c new file mode 100644 index 0000000..2580c23 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u16.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint16_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u32.c new file mode 100644 index 0000000..43ca2c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint32_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv32.c new file mode 100644 index 0000000..c5b84cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32 -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv64.c new file mode 100644 index 0000000..51a27a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u32.c new file mode 100644 index 0000000..e212391 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint32_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c index 065afb8..79d3fb3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { rv32 } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c index 062bbc9..ad63db3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { rv32 } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u16.c new file mode 100644 index 0000000..f5a0ab5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint16_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u32.c new file mode 100644 index 0000000..32074a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint32_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c index e6f632b..16ca905 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { rv32 } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u16.c new file mode 100644 index 0000000..73f619b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_2_WRAP(NT, x, y) + +DEF_SAT_U_MUL_FMT_2_WRAP(NT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u32.c new file mode 100644 index 0000000..4965ef3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint32_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_2_WRAP(NT, x, y) + +DEF_SAT_U_MUL_FMT_2_WRAP(NT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u64.c new file mode 100644 index 0000000..1868e81 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_2_WRAP(NT, x, y) + +DEF_SAT_U_MUL_FMT_2_WRAP(NT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u8.c new file mode 100644 index 0000000..2b2551c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_2_WRAP(NT, x, y) + +DEF_SAT_U_MUL_FMT_2_WRAP(NT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u128.c new file mode 100644 index 0000000..561ee21 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u32.c new file mode 100644 index 0000000..e491989 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint32_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u64.c new file mode 100644 index 0000000..14c6ae5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u64.rv32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u64.rv32.c new file mode 100644 index 0000000..35eabc8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u64.rv32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u128.c new file mode 100644 index 0000000..d2bf073 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint32_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u64.c new file mode 100644 index 0000000..74c63fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u64.rv32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u64.rv32.c new file mode 100644 index 0000000..015f038 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u64.rv32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u64-from-u128.c new file mode 100644 index 0000000..77bfce8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u64-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint64_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u128.c new file mode 100644 index 0000000..3c84067 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u16.c new file mode 100644 index 0000000..7b2bd71 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint16_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u32.c new file mode 100644 index 0000000..abfa965 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint32_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u64.c new file mode 100644 index 0000000..74c63fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u64.rv32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u64.rv32.c new file mode 100644 index 0000000..015f038 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u64.rv32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_3_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u128.c new file mode 100644 index 0000000..ec23d81 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u32.c new file mode 100644 index 0000000..e175988 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint32_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u64.c new file mode 100644 index 0000000..5d4e28b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u128.c new file mode 100644 index 0000000..d8beb8f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint32_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u64.c new file mode 100644 index 0000000..afc9c9a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint32_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u64-from-u128.c new file mode 100644 index 0000000..d5f20f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u64-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint64_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u128.c new file mode 100644 index 0000000..9d44541 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u16.c new file mode 100644 index 0000000..cd52087 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint16_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u32.c new file mode 100644 index 0000000..f6ae187 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint32_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u64.c new file mode 100644 index 0000000..f94cc9d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c index 883cce2..f3a9ba9 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { rv64 } } } */ +/* { dg-do run { target { rv64 && riscv_b_ok } } } */ /* { dg-options "-march=rv64gc_zba -mabi=lp64d -O2" } */ struct { diff --git a/gcc/testsuite/gcc.target/riscv/zba-shadd.c b/gcc/testsuite/gcc.target/riscv/zba-shadd.c index 61305d3..445ffb2 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-shadd.c +++ b/gcc/testsuite/gcc.target/riscv/zba-shadd.c @@ -1,7 +1,15 @@ /* { dg-do compile } */ /* { dg-options "-O2 -march=rv64gc_zba -mabi=lp64" } */ -unsigned long foo(unsigned int a, unsigned long b) +unsigned long foo1(unsigned int a, unsigned long b) +{ + a = a << 1; + unsigned long c = (unsigned long) a; + unsigned long d = b + (c<<1); + return d; +} + +unsigned long foo2(unsigned int a, unsigned long b) { a = a << 1; unsigned long c = (unsigned long) a; @@ -9,5 +17,15 @@ unsigned long foo(unsigned int a, unsigned long b) return d; } +unsigned long foo3(unsigned int a, unsigned long b) +{ + a = a << 1; + unsigned long c = (unsigned long) a; + unsigned long d = b + (c<<3); + return d; +} + +/* { dg-final { scan-assembler "sh1add.uw" } } */ /* { dg-final { scan-assembler "sh2add.uw" } } */ +/* { dg-final { scan-assembler "sh3add.uw" } } */ /* { dg-final { scan-assembler-not {\mzext} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-sext.c b/gcc/testsuite/gcc.target/riscv/zbb-sext.c new file mode 100644 index 0000000..1ad3e71 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbb-sext.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zbb -mabi=lp64" } */ + +#include<stdint.h> + +int8_t foo1(uint8_t a) { + return a; +} + +int16_t foo2(uint16_t a) { + return a; +} + +/* { dg-final { scan-assembler "sext.b" } } */ +/* { dg-final { scan-assembler "sext.h" } } */ |