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Diffstat (limited to 'gcc/doc/invoke.texi')
| -rw-r--r-- | gcc/doc/invoke.texi | 170 |
1 files changed, 145 insertions, 25 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ef06b0b..e9fe4ef 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -956,11 +956,16 @@ See RS/6000 and PowerPC Options. -mtda=@var{n} -msda=@var{n} -mzda=@var{n} @gol -mapp-regs -mno-app-regs @gol -mdisable-callt -mno-disable-callt @gol --mv850e2v3 @gol --mv850e2 @gol --mv850e1 -mv850es @gol --mv850e @gol --mv850 -mbig-switch} +-mv850e2v3 -mv850e2 -mv850e1 -mv850es @gol +-mv850e -mv850 -mv850e3v5 @gol +-mloop @gol +-mrelax @gol +-mlong-jumps @gol +-msoft-float @gol +-mhard-float @gol +-mgcc-abi @gol +-mrh850-abi @gol +-mbig-switch} @emph{VAX Options} @gccoptlist{-mg -mgnu -munix} @@ -6083,7 +6088,7 @@ vectorizer passes print the source location of loops which got successfully vectorized. @item missed Print information about missed optimizations. Individual passes -control which informations to include in the output. For example, +control which information to include in the output. For example, @smallexample gcc -O2 -ftree-vectorize -fopt-info-vec-missed @@ -8401,7 +8406,7 @@ requires the complete toolchain to be aware of LTO. It requires a linker with linker plugin support for basic functionality. Additionally, @command{nm}, @command{ar} and @command{ranlib} need to support linker plugins to allow a full-featured build environment -(capable of building static libraries etc). gcc provides the @command{gcc-ar}, +(capable of building static libraries etc). GCC provides the @command{gcc-ar}, @command{gcc-nm}, @command{gcc-ranlib} wrappers to pass the right options to these tools. With non fat LTO makefiles need to be modified to use them. @@ -19591,26 +19596,20 @@ the first 32 kilobytes of memory. @opindex mv850 Specify that the target processor is the V850. -@item -mbig-switch -@opindex mbig-switch -Generate code suitable for big switch tables. Use this option only if -the assembler/linker complain about out of range branches within a switch -table. - -@item -mapp-regs -@opindex mapp-regs -This option causes r2 and r5 to be used in the code generated by -the compiler. This setting is the default. +@item -mv850e3v5 +@opindex mv850e3v5 +Specify that the target processor is the V850E3V5. The preprocessor +constant @samp{__v850e3v5__} is defined if this option is used. -@item -mno-app-regs -@opindex mno-app-regs -This option causes r2 and r5 to be treated as fixed registers. +@item -mv850e2v4 +@opindex mv850e2v4 +Specify that the target processor is the V850E3V5. This is an alias for +the @option{-mv850e3v5} option. @item -mv850e2v3 @opindex mv850e2v3 Specify that the target processor is the V850E2V3. The preprocessor -constant @samp{__v850e2v3__} is defined if -this option is used. +constant @samp{__v850e2v3__} is defined if this option is used. @item -mv850e2 @opindex mv850e2 @@ -19634,7 +19633,7 @@ Specify that the target processor is the V850E@. The preprocessor constant @samp{__v850e__} is defined if this option is used. If neither @option{-mv850} nor @option{-mv850e} nor @option{-mv850e1} -nor @option{-mv850e2} nor @option{-mv850e2v3} +nor @option{-mv850e2} nor @option{-mv850e2v3} nor @option{-mv850e3v5} are defined then a default target processor is chosen and the relevant @samp{__v850*__} preprocessor constant is defined. @@ -19642,10 +19641,131 @@ The preprocessor constants @samp{__v850} and @samp{__v851__} are always defined, regardless of which processor variant is the target. @item -mdisable-callt +@itemx -mno-disable-callt @opindex mdisable-callt +@opindex mno-disable-callt This option suppresses generation of the @code{CALLT} instruction for the -v850e, v850e1, v850e2 and v850e2v3 flavors of the v850 architecture. The default is -@option{-mno-disable-callt} which allows the @code{CALLT} instruction to be used. +v850e, v850e1, v850e2, v850e2v3 and v850e3v5 flavors of the v850 +architecture. + +This option is enabled by default when the RH850 ABI is +in use (see @option{-mrh850-abi}), and disabled by default when the +GCC ABI is in use. If @code{CALLT} instructions are being generated +then the C preprocessor symbol @code{__V850_CALLT__} will be defined. + +@item -mrelax +@itemx -mno-relax +@opindex mrelax +@opindex mno-relax +Pass on (or do not pass on) the @option{-mrelax} command line option +to the assembler. + +@item -mlong-jumps +@itemx -mno-long-jumps +@opindex mlong-jumps +@opindex mno-long-jumps +Disable (or re-enable) the generation of PC-relative jump instructions. + +@item -msoft-float +@itemx -mhard-float +@opindex msoft-float +@opindex mhard-float +Disable (or re-enable) the generation of hardware floating point +instructions. This option is only significant when the target +architecture is @samp{V850E2V3} or higher. If hardware floating point +instructions are being generated then the C preprocessor symbol +@code{__FPU_OK__} will be defined, otherwise the symbol +@code{__NO_FPU__} will be defined. + +@item -mloop +@opindex mloop +Enables the use of the e3v5 LOOP instruction. The use of this +instruction is not enabled by default when the e3v5 architecture is +selected because its use is still experimental. + +@item -mrh850-abi +@itemx -mghs +@opindex mrh850-abi +@opindex mghs +Enables support for the RH850 version of the V850 ABI. This is the +default. With this version of the ABI the following rules apply: + +@itemize +@item +Integer sized structures and unions are returned via a memory pointer +rather than a register. + +@item +Large structures and unions (more than 8 bytes in size) are passed by +value. + +@item +Functions are aligned to 16-bit boundaries. + +@item +The @option{-m8byte-align} command line option is supported. + +@item +The @option{-mdisable-callt} command line option is enabled by +default. The @option{-mno-disable-callt} command line option is not +supported. +@end itemize + +When this version of the ABI is enabled the C preprocessor symbol +@code{__V850_RH850_ABI__} is defined. + +@item -mgcc-abi +@opindex mgcc-abi +Enables support for the old GCC version of the V850 ABI. With this +version of the ABI the following rules apply: + +@itemize +@item +Integer sized structures and unions are returned in register @code{r10}. + +@item +Large structures and unions (more than 8 bytes in size) are passed by +reference. + +@item +Functions are aligned to 32-bit boundaries, unless optimizing for +size. + +@item +The @option{-m8byte-align} command line option is not supported. + +@item +The @option{-mdisable-callt} command line option is supported but not +enabled by default. +@end itemize + +When this version of the ABI is enabled the C preprocessor symbol +@code{__V850_GCC_ABI__} is defined. + +@item -m8byte-align +@itemx -mno-8byte-align +@opindex m8byte-align +@opindex mno-8byte-align +Enables support for @code{doubles} and @code{long long} types to be +aligned on 8-byte boundaries. The default is to restrict the +alignment of all objects to at most 4-bytes. When +@option{-m8byte-align} is in effect the C preprocessor symbol +@code{__V850_8BYTE_ALIGN__} will be defined. + +@item -mbig-switch +@opindex mbig-switch +Generate code suitable for big switch tables. Use this option only if +the assembler/linker complain about out of range branches within a switch +table. + +@item -mapp-regs +@opindex mapp-regs +This option causes r2 and r5 to be used in the code generated by +the compiler. This setting is the default. + +@item -mno-app-regs +@opindex mno-app-regs +This option causes r2 and r5 to be treated as fixed registers. @end table |