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-rw-r--r--gcc/doc/invoke.texi9
1 files changed, 7 insertions, 2 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 3d83bf5..284594d 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -651,7 +651,7 @@ Objective-C and Objective-C++ Dialects}.
-mmixed-code -mq-class -mRcq -mRcw -msize-level=@var{level} @gol
-mtune=@var{cpu} -mmultcost=@var{num} @gol
-munalign-prob-threshold=@var{probability} -mmpy-option=@var{multo} @gol
--mdiv-rem -mcode-density -mll64 -mfpu=@var{fpu} -mrf16}
+-mdiv-rem -mcode-density -mll64 -mfpu=@var{fpu} -mrf16 -mbranch-index}
@emph{ARM Options}
@gccoptlist{-mapcs-frame -mno-apcs-frame @gol
@@ -15839,6 +15839,11 @@ This option instructs the compiler to generate code for a 16-entry
register file. This option defines the @code{__ARC_RF16__}
preprocessor macro.
+@item -mbranch-index
+@opindex mbranch-index
+Enable use of @code{bi} or @code{bih} instructions to implement jump
+tables.
+
@end table
The following options are passed through to the assembler, and also
@@ -16010,7 +16015,7 @@ This is the default for @option{-Os}.
@item -mcompact-casesi
@opindex mcompact-casesi
Enable compact @code{casesi} pattern. This is the default for @option{-Os},
-and only available for ARCv1 cores.
+and only available for ARCv1 cores. This option is deprecated.
@item -mno-cond-exec
@opindex mno-cond-exec