diff options
Diffstat (limited to 'gcc/config')
-rw-r--r-- | gcc/config/alpha/alpha.c | 12 | ||||
-rw-r--r-- | gcc/config/arc/arc.c | 2 | ||||
-rw-r--r-- | gcc/config/arm/arm.c | 28 | ||||
-rw-r--r-- | gcc/config/avr/avr.c | 18 | ||||
-rw-r--r-- | gcc/config/c4x/c4x.c | 2 | ||||
-rw-r--r-- | gcc/config/d30v/d30v.c | 2 | ||||
-rw-r--r-- | gcc/config/h8300/h8300.c | 4 | ||||
-rw-r--r-- | gcc/config/i386/i386.c | 62 | ||||
-rw-r--r-- | gcc/config/i386/i386.h | 46 | ||||
-rw-r--r-- | gcc/config/m68hc11/m68hc11.c | 6 | ||||
-rw-r--r-- | gcc/config/m68hc11/m68hc11.h | 24 | ||||
-rw-r--r-- | gcc/config/m68k/m68k.c | 4 | ||||
-rw-r--r-- | gcc/config/m88k/m88k.c | 15 | ||||
-rw-r--r-- | gcc/config/m88k/m88k.h | 4 | ||||
-rw-r--r-- | gcc/config/mcore/mcore.c | 2 | ||||
-rw-r--r-- | gcc/config/mips/elf64.h | 5 | ||||
-rw-r--r-- | gcc/config/mips/iris6gld.h | 6 | ||||
-rw-r--r-- | gcc/config/mips/mips.c | 4 | ||||
-rw-r--r-- | gcc/config/mips/mips.h | 2 | ||||
-rw-r--r-- | gcc/config/ns32k/ns32k.c | 2 | ||||
-rw-r--r-- | gcc/config/pa/pa.c | 6 | ||||
-rw-r--r-- | gcc/config/rs6000/rs6000.c | 12 | ||||
-rw-r--r-- | gcc/config/sparc/sparc.c | 40 | ||||
-rw-r--r-- | gcc/config/sparc/sparc.h | 8 |
24 files changed, 163 insertions, 153 deletions
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index 4439368..1b59954 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -221,10 +221,10 @@ void override_options () { int i; - static struct cpu_table { - const char *name; - enum processor_type processor; - int flags; + static const struct cpu_table { + const char *const name; + const enum processor_type processor; + const int flags; } cpu_table[] = { #define EV5_MASK (MASK_CPU_EV5) #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX) @@ -2985,8 +2985,8 @@ alpha_lookup_xfloating_lib_func (code) { struct xfloating_op { - enum rtx_code code; - const char *func; + const enum rtx_code code; + const char *const func; }; static const struct xfloating_op vms_xfloating_ops[] = diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 6875a6f..49b0f16 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -1299,7 +1299,7 @@ arc_output_function_epilogue (file, size) /* Emit the return instruction. */ { - static int regs[4] = { + static const int regs[4] = { 0, RETURN_ADDR_REGNUM, ILINK1_REGNUM, ILINK2_REGNUM }; fprintf (file, "\tj.d %s\n", reg_names[regs[fn_type]]); diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index fcd90dd..3e2192b 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -286,13 +286,13 @@ static const char *const arm_condition_codes[] = struct processors { - const char * name; - unsigned int flags; + const char *const name; + const unsigned int flags; }; /* Not all of these give usefully different compilation alternatives, but there is no simple way of generalizing them. */ -static struct processors all_cores[] = +static const struct processors all_cores[] = { /* ARM Cores */ @@ -345,7 +345,7 @@ static struct processors all_cores[] = {NULL, 0} }; -static struct processors all_architectures[] = +static const struct processors all_architectures[] = { /* ARM Architectures */ @@ -436,12 +436,12 @@ arm_override_options () /* If the user did not specify a processor, choose one for them. */ if (insn_flags == 0) { - struct processors * sel; + const struct processors * sel; unsigned int sought; - static struct cpu_default + static const struct cpu_default { - int cpu; - const char * name; + const int cpu; + const char *const name; } cpu_defaults[] = { @@ -460,7 +460,7 @@ arm_override_options () { TARGET_CPU_generic, "arm" }, { 0, 0 } }; - struct cpu_default * def; + const struct cpu_default * def; /* Find the default. */ for (def = cpu_defaults; def->name; def++) @@ -513,7 +513,7 @@ arm_override_options () if (sel->name == NULL) { unsigned int current_bit_count = 0; - struct processors * best_fit = NULL; + const struct processors * best_fit = NULL; /* Ideally we would like to issue an error message here saying that it was not possible to find a CPU compatible @@ -760,12 +760,12 @@ arm_add_gc_roots () typedef struct { - const char * arg; - unsigned long return_value; + const char *const arg; + const unsigned long return_value; } isr_attribute_arg; -static isr_attribute_arg isr_attribute_args [] = +static const isr_attribute_arg isr_attribute_args [] = { { "IRQ", ARM_FT_ISR }, { "irq", ARM_FT_ISR }, @@ -789,7 +789,7 @@ static unsigned long arm_isr_value (argument) tree argument; { - isr_attribute_arg * ptr; + const isr_attribute_arg * ptr; const char * arg; /* No argument - default to IRQ. */ diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c index ed54cbb..b576773 100644 --- a/gcc/config/avr/avr.c +++ b/gcc/config/avr/avr.c @@ -120,8 +120,8 @@ enum avr_arch { }; struct mcu_type_s { - const char *name; - enum avr_arch arch; + const char *const name; + const enum avr_arch arch; }; /* List of all known AVR MCU types - if updated, it has to be kept @@ -242,7 +242,7 @@ avr_init_once () /* return register class from register number */ -static int reg_class_tab[]={ +static const int reg_class_tab[]={ GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,GENERAL_REGS, GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,GENERAL_REGS, GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,GENERAL_REGS, @@ -4831,7 +4831,7 @@ void order_regs_for_local_alloc () { unsigned int i; - int order_0[] = { + static const int order_0[] = { 24,25, 18,19, 20,21, @@ -4843,7 +4843,7 @@ order_regs_for_local_alloc () 0,1, 32,33,34,35 }; - int order_1[] = { + static const int order_1[] = { 18,19, 20,21, 22,23, @@ -4855,7 +4855,7 @@ order_regs_for_local_alloc () 0,1, 32,33,34,35 }; - int order_2[] = { + static const int order_2[] = { 25,24, 23,22, 21,20, @@ -4869,9 +4869,9 @@ order_regs_for_local_alloc () 32,33,34,35 }; - int *order = (TARGET_ORDER_1 ? order_1 : - TARGET_ORDER_2 ? order_2 : - order_0); + const int *order = (TARGET_ORDER_1 ? order_1 : + TARGET_ORDER_2 ? order_2 : + order_0); for (i=0; i < ARRAY_SIZE (order_0); ++i) reg_alloc_order[i] = order[i]; } diff --git a/gcc/config/c4x/c4x.c b/gcc/config/c4x/c4x.c index 7ed86b2..b59d344 100644 --- a/gcc/config/c4x/c4x.c +++ b/gcc/config/c4x/c4x.c @@ -503,7 +503,7 @@ c4x_hard_regno_rename_ok (regno1, regno2) Don't use R0 to pass arguments in, we use 0 to indicate a stack argument. */ -static int c4x_int_reglist[3][6] = +static const int c4x_int_reglist[3][6] = { {AR2_REGNO, R2_REGNO, R3_REGNO, RC_REGNO, RS_REGNO, RE_REGNO}, {AR2_REGNO, R3_REGNO, RC_REGNO, RS_REGNO, RE_REGNO, 0}, diff --git a/gcc/config/d30v/d30v.c b/gcc/config/d30v/d30v.c index 2af7b26..a5d8745 100644 --- a/gcc/config/d30v/d30v.c +++ b/gcc/config/d30v/d30v.c @@ -247,7 +247,7 @@ override_options () #if 0 { - static char *names[] = REG_CLASS_NAMES; + static const char *const names[] = REG_CLASS_NAMES; fprintf (stderr, "Register %s class is %s, can hold modes", reg_names[regno], names[class]); for (mode1 = VOIDmode; (int)mode1 < NUM_MACHINE_MODES; diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c index 34686a6..a0ed2b2 100644 --- a/gcc/config/h8300/h8300.c +++ b/gcc/config/h8300/h8300.c @@ -2006,8 +2006,8 @@ enum shift_mode struct shift_insn { - const char *assembler; - int cc_valid; + const char *const assembler; + const int cc_valid; }; /* Assembler instruction shift table. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index d88c853..933459a 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -48,6 +48,7 @@ Boston, MA 02111-1307, USA. */ #endif /* Processor costs (relative to an add) */ +static const struct processor_costs size_cost = { /* costs for tunning for size */ 2, /* cost of an add instruction */ 3, /* cost of a lea instruction */ @@ -80,6 +81,7 @@ struct processor_costs size_cost = { /* costs for tunning for size */ 3, /* MMX or SSE register to integer */ }; /* Processor costs (relative to an add) */ +static const struct processor_costs i386_cost = { /* 386 specific costs */ 1, /* cost of an add instruction */ 1, /* cost of a lea instruction */ @@ -112,6 +114,7 @@ struct processor_costs i386_cost = { /* 386 specific costs */ 3, /* MMX or SSE register to integer */ }; +static const struct processor_costs i486_cost = { /* 486 specific costs */ 1, /* cost of an add instruction */ 1, /* cost of a lea instruction */ @@ -144,6 +147,7 @@ struct processor_costs i486_cost = { /* 486 specific costs */ 3 /* MMX or SSE register to integer */ }; +static const struct processor_costs pentium_cost = { 1, /* cost of an add instruction */ 1, /* cost of a lea instruction */ @@ -176,6 +180,7 @@ struct processor_costs pentium_cost = { 3 /* MMX or SSE register to integer */ }; +static const struct processor_costs pentiumpro_cost = { 1, /* cost of an add instruction */ 1, /* cost of a lea instruction */ @@ -208,6 +213,7 @@ struct processor_costs pentiumpro_cost = { 3 /* MMX or SSE register to integer */ }; +static const struct processor_costs k6_cost = { 1, /* cost of an add instruction */ 2, /* cost of a lea instruction */ @@ -240,6 +246,7 @@ struct processor_costs k6_cost = { 6 /* MMX or SSE register to integer */ }; +static const struct processor_costs athlon_cost = { 1, /* cost of an add instruction */ 2, /* cost of a lea instruction */ @@ -272,6 +279,7 @@ struct processor_costs athlon_cost = { 6 /* MMX or SSE register to integer */ }; +static const struct processor_costs pentium4_cost = { 1, /* cost of an add instruction */ 1, /* cost of a lea instruction */ @@ -304,7 +312,7 @@ struct processor_costs pentium4_cost = { 10, /* MMX or SSE register to integer */ }; -struct processor_costs *ix86_cost = &pentium_cost; +const struct processor_costs *ix86_cost = &pentium_cost; /* Processor feature/optimization bitmasks. */ #define m_386 (1<<PROCESSOR_I386) @@ -641,10 +649,10 @@ struct ix86_address static int ix86_decompose_address PARAMS ((rtx, struct ix86_address *)); struct builtin_description; -static rtx ix86_expand_sse_comi PARAMS ((struct builtin_description *, tree, - rtx)); -static rtx ix86_expand_sse_compare PARAMS ((struct builtin_description *, tree, - rtx)); +static rtx ix86_expand_sse_comi PARAMS ((const struct builtin_description *, + tree, rtx)); +static rtx ix86_expand_sse_compare PARAMS ((const struct builtin_description *, + tree, rtx)); static rtx ix86_expand_unop1_builtin PARAMS ((enum insn_code, tree, rtx)); static rtx ix86_expand_unop_builtin PARAMS ((enum insn_code, tree, rtx, int)); static rtx ix86_expand_binop_builtin PARAMS ((enum insn_code, tree, rtx)); @@ -770,13 +778,13 @@ override_options () static struct ptt { - struct processor_costs *cost; /* Processor costs */ - int target_enable; /* Target flags to enable. */ - int target_disable; /* Target flags to disable. */ - int align_loop; /* Default alignments. */ - int align_jump; - int align_func; - int branch_cost; + const struct processor_costs *cost; /* Processor costs */ + const int target_enable; /* Target flags to enable. */ + const int target_disable; /* Target flags to disable. */ + const int align_loop; /* Default alignments. */ + const int align_jump; + const int align_func; + const int branch_cost; } const processor_target_table[PROCESSOR_max] = { @@ -791,8 +799,8 @@ override_options () static struct pta { - const char *name; /* processor name or nickname. */ - enum processor_type processor; + const char *const name; /* processor name or nickname. */ + const enum processor_type processor; } const processor_alias_table[] = { @@ -10708,15 +10716,15 @@ do { \ struct builtin_description { - unsigned int mask; - enum insn_code icode; - const char * name; - enum ix86_builtins code; - enum rtx_code comparison; - unsigned int flag; + const unsigned int mask; + const enum insn_code icode; + const char *const name; + const enum ix86_builtins code; + const enum rtx_code comparison; + const unsigned int flag; }; -static struct builtin_description bdesc_comi[] = +static const struct builtin_description bdesc_comi[] = { { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, EQ, 0 }, { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, LT, 0 }, @@ -10732,7 +10740,7 @@ static struct builtin_description bdesc_comi[] = { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, NE, 0 } }; -static struct builtin_description bdesc_2arg[] = +static const struct builtin_description bdesc_2arg[] = { /* SSE */ { MASK_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, 0, 0 }, @@ -10865,7 +10873,7 @@ static struct builtin_description bdesc_2arg[] = }; -static struct builtin_description bdesc_1arg[] = +static const struct builtin_description bdesc_1arg[] = { { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB, 0, 0 }, { MASK_SSE, CODE_FOR_sse_movmskps, 0, IX86_BUILTIN_MOVMSKPS, 0, 0 }, @@ -10894,7 +10902,7 @@ ix86_init_builtins () void ix86_init_mmx_sse_builtins () { - struct builtin_description * d; + const struct builtin_description * d; size_t i; tree endlink = void_list_node; @@ -11472,7 +11480,7 @@ ix86_expand_unop1_builtin (icode, arglist, target) static rtx ix86_expand_sse_compare (d, arglist, target) - struct builtin_description *d; + const struct builtin_description *d; tree arglist; rtx target; { @@ -11524,7 +11532,7 @@ ix86_expand_sse_compare (d, arglist, target) static rtx ix86_expand_sse_comi (d, arglist, target) - struct builtin_description *d; + const struct builtin_description *d; tree arglist; rtx target; { @@ -11585,7 +11593,7 @@ ix86_expand_builtin (exp, target, subtarget, mode, ignore) enum machine_mode mode ATTRIBUTE_UNUSED; int ignore ATTRIBUTE_UNUSED; { - struct builtin_description *d; + const struct builtin_description *d; size_t i; enum insn_code icode; tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 174c594..0bf603a 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -51,42 +51,42 @@ Boston, MA 02111-1307, USA. */ /* Define the specific costs for a given cpu */ struct processor_costs { - int add; /* cost of an add instruction */ - int lea; /* cost of a lea instruction */ - int shift_var; /* variable shift costs */ - int shift_const; /* constant shift costs */ - int mult_init; /* cost of starting a multiply */ - int mult_bit; /* cost of multiply per each bit set */ - int divide; /* cost of a divide/mod */ - int large_insn; /* insns larger than this cost more */ - int move_ratio; /* The threshold of number of scalar + const int add; /* cost of an add instruction */ + const int lea; /* cost of a lea instruction */ + const int shift_var; /* variable shift costs */ + const int shift_const; /* constant shift costs */ + const int mult_init; /* cost of starting a multiply */ + const int mult_bit; /* cost of multiply per each bit set */ + const int divide; /* cost of a divide/mod */ + const int large_insn; /* insns larger than this cost more */ + const int move_ratio; /* The threshold of number of scalar memory-to-memory move insns. */ - int movzbl_load; /* cost of loading using movzbl */ - int int_load[3]; /* cost of loading integer registers + const int movzbl_load; /* cost of loading using movzbl */ + const int int_load[3]; /* cost of loading integer registers in QImode, HImode and SImode relative to reg-reg move (2). */ - int int_store[3]; /* cost of storing integer register + const int int_store[3]; /* cost of storing integer register in QImode, HImode and SImode */ - int fp_move; /* cost of reg,reg fld/fst */ - int fp_load[3]; /* cost of loading FP register + const int fp_move; /* cost of reg,reg fld/fst */ + const int fp_load[3]; /* cost of loading FP register in SFmode, DFmode and XFmode */ - int fp_store[3]; /* cost of storing FP register + const int fp_store[3]; /* cost of storing FP register in SFmode, DFmode and XFmode */ - int mmx_move; /* cost of moving MMX register. */ - int mmx_load[2]; /* cost of loading MMX register + const int mmx_move; /* cost of moving MMX register. */ + const int mmx_load[2]; /* cost of loading MMX register in SImode and DImode */ - int mmx_store[2]; /* cost of storing MMX register + const int mmx_store[2]; /* cost of storing MMX register in SImode and DImode */ - int sse_move; /* cost of moving SSE register. */ - int sse_load[3]; /* cost of loading SSE register + const int sse_move; /* cost of moving SSE register. */ + const int sse_load[3]; /* cost of loading SSE register in SImode, DImode and TImode*/ - int sse_store[3]; /* cost of storing SSE register + const int sse_store[3]; /* cost of storing SSE register in SImode, DImode and TImode*/ - int mmxsse_to_integer; /* cost of moving mmxsse register to + const int mmxsse_to_integer; /* cost of moving mmxsse register to integer and vice versa. */ }; -extern struct processor_costs *ix86_cost; +extern const struct processor_costs *ix86_cost; /* Run-time compilation parameters selecting different hardware subsets. */ diff --git a/gcc/config/m68hc11/m68hc11.c b/gcc/config/m68hc11/m68hc11.c index 494de47..fa0179a 100644 --- a/gcc/config/m68hc11/m68hc11.c +++ b/gcc/config/m68hc11/m68hc11.c @@ -128,10 +128,10 @@ rtx m68hc11_compare_op0; rtx m68hc11_compare_op1; -struct processor_costs *m68hc11_cost; +const struct processor_costs *m68hc11_cost; /* Costs for a 68HC11. */ -struct processor_costs m6811_cost = { +static const struct processor_costs m6811_cost = { /* add */ COSTS_N_INSNS (2), /* logical */ @@ -166,7 +166,7 @@ struct processor_costs m6811_cost = { }; /* Costs for a 68HC12. */ -struct processor_costs m6812_cost = { +static const struct processor_costs m6812_cost = { /* add */ COSTS_N_INSNS (1), /* logical */ diff --git a/gcc/config/m68hc11/m68hc11.h b/gcc/config/m68hc11/m68hc11.h index 3ec7159..07e640b 100644 --- a/gcc/config/m68hc11/m68hc11.h +++ b/gcc/config/m68hc11/m68hc11.h @@ -212,21 +212,21 @@ extern const char *m68hc11_soft_reg_count; /* Define cost parameters for a given processor variant. */ struct processor_costs { - int add; /* cost of an add instruction */ - int logical; /* cost of a logical instruction */ - int shift_var; - int shiftQI_const[8]; - int shiftHI_const[16]; - int multQI; - int multHI; - int multSI; - int divQI; - int divHI; - int divSI; + const int add; /* cost of an add instruction */ + const int logical; /* cost of a logical instruction */ + const int shift_var; + const int shiftQI_const[8]; + const int shiftHI_const[16]; + const int multQI; + const int multHI; + const int multSI; + const int divQI; + const int divHI; + const int divSI; }; /* Costs for the current processor. */ -extern struct processor_costs *m68hc11_cost; +extern const struct processor_costs *m68hc11_cost; /* target machine storage layout */ diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c index 3a832ff..a83168a 100644 --- a/gcc/config/m68k/m68k.c +++ b/gcc/config/m68k/m68k.c @@ -3049,7 +3049,7 @@ static const char *const strings_68881[7] = { "1e16" }; -int codes_68881[7] = { +static const int codes_68881[7] = { 0x0f, 0x32, 0x33, @@ -3216,7 +3216,7 @@ static const char *const strings_FPA[38] = { }; -int codes_FPA[38] = { +static const int codes_FPA[38] = { /* small rationals */ 0x200, 0xe, diff --git a/gcc/config/m88k/m88k.c b/gcc/config/m88k/m88k.c index 1de96f2..db5e069 100644 --- a/gcc/config/m88k/m88k.c +++ b/gcc/config/m88k/m88k.c @@ -485,15 +485,15 @@ legitimize_address (pic, orig, reg, scratch) #define MOVSTR_SI_LIMIT_88110 72 #define MOVSTR_DI_LIMIT_88110 72 -static enum machine_mode mode_from_align[] = +static const enum machine_mode mode_from_align[] = {VOIDmode, QImode, HImode, VOIDmode, SImode, VOIDmode, VOIDmode, VOIDmode, DImode}; -static int max_from_align[] = {0, MOVSTR_QI, MOVSTR_HI, 0, MOVSTR_SI, - 0, 0, 0, MOVSTR_DI}; -static int all_from_align[] = {0, MOVSTR_QI, MOVSTR_ODD_HI, 0, MOVSTR_ODD_SI, - 0, 0, 0, MOVSTR_ODD_DI}; +static const int max_from_align[] = {0, MOVSTR_QI, MOVSTR_HI, 0, MOVSTR_SI, + 0, 0, 0, MOVSTR_DI}; +static const int all_from_align[] = {0, MOVSTR_QI, MOVSTR_ODD_HI, 0, + MOVSTR_ODD_SI, 0, 0, 0, MOVSTR_ODD_DI}; -static int best_from_align[3][9] = { +static const int best_from_align[3][9] = { {0, MOVSTR_QI_LIMIT_88100, MOVSTR_HI_LIMIT_88100, 0, MOVSTR_SI_LIMIT_88100, 0, 0, 0, MOVSTR_DI_LIMIT_88100}, {0, MOVSTR_QI_LIMIT_88110, MOVSTR_HI_LIMIT_88110, 0, MOVSTR_SI_LIMIT_88110, @@ -1534,7 +1534,8 @@ output_option (file, sep, type, name, indent, pos, max) return pos + fprintf (file, "%s%s%s", sep, type, name); } -static struct { const char *const name; int value; } m_options[] = TARGET_SWITCHES; +static const struct { const char *const name; const int value; } m_options[] = +TARGET_SWITCHES; static void output_options (file, f_options, f_len, W_options, W_len, diff --git a/gcc/config/m88k/m88k.h b/gcc/config/m88k/m88k.h index 881acd8..abcc050 100644 --- a/gcc/config/m88k/m88k.h +++ b/gcc/config/m88k/m88k.h @@ -690,8 +690,8 @@ extern int flag_pic; /* -fpic */ write-over scoreboard delays between caller and callee. */ #define ORDER_REGS_FOR_LOCAL_ALLOC \ { \ - static int leaf[] = REG_LEAF_ALLOC_ORDER; \ - static int nonleaf[] = REG_ALLOC_ORDER; \ + static const int leaf[] = REG_LEAF_ALLOC_ORDER; \ + static const int nonleaf[] = REG_ALLOC_ORDER; \ \ memcpy (reg_alloc_order, regs_ever_live[1] ? nonleaf : leaf, \ FIRST_PSEUDO_REGISTER * sizeof (int)); \ diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c index 0a4a2b5..7b83cd9 100644 --- a/gcc/config/mcore/mcore.c +++ b/gcc/config/mcore/mcore.c @@ -1877,7 +1877,7 @@ mcore_store_multiple_operation (op, mode) known constants. DEST and SRC are registers. OFFSET is the known starting point for the output pattern. */ -static enum machine_mode mode_from_align[] = +static const enum machine_mode mode_from_align[] = { VOIDmode, QImode, HImode, VOIDmode, SImode, VOIDmode, VOIDmode, VOIDmode, DImode diff --git a/gcc/config/mips/elf64.h b/gcc/config/mips/elf64.h index e07ce46..cc94020 100644 --- a/gcc/config/mips/elf64.h +++ b/gcc/config/mips/elf64.h @@ -197,8 +197,9 @@ do { \ #define UNIQUE_SECTION(DECL,RELOC) \ do { \ int len, size, sec; \ - char *name, *string, *prefix; \ - static char *prefixes[4][2] = { \ + const char *name, *prefix; \ + char *string; \ + static const char *const prefixes[4][2] = { \ { ".text.", ".gnu.linkonce.t." }, \ { ".rodata.", ".gnu.linkonce.r." }, \ { ".data.", ".gnu.linkonce.d." }, \ diff --git a/gcc/config/mips/iris6gld.h b/gcc/config/mips/iris6gld.h index 409af7d..addc0f7 100644 --- a/gcc/config/mips/iris6gld.h +++ b/gcc/config/mips/iris6gld.h @@ -54,10 +54,10 @@ Boston, MA 02111-1307, USA. */ { \ int len; \ int sec; \ - char *name; \ + const char *name; \ char *string; \ - char *prefix; \ - static char *prefixes[/*4*/3][2] = \ + const char *prefix; \ + static const char *const prefixes[/*4*/3][2] = \ { \ { ".text.", ".gnu.linkonce.t." }, \ { ".rodata.", ".gnu.linkonce.r." }, \ diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index d88b61d..9ff5be6 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -345,7 +345,7 @@ char mips_reg_names[][8] = /* Mips software names for the registers, used to overwrite the mips_reg_names array. */ -char mips_sw_reg_names[][8] = +static const char mips_sw_reg_names[][8] = { "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3", "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", @@ -360,7 +360,7 @@ char mips_sw_reg_names[][8] = }; /* Map hard register number to register class */ -enum reg_class mips_regno_to_class[] = +const enum reg_class mips_regno_to_class[] = { GR_REGS, GR_REGS, M16_NA_REGS, M16_NA_REGS, M16_REGS, M16_REGS, M16_REGS, M16_REGS, diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index dfb8aff..121628a 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1982,7 +1982,7 @@ enum reg_class choose a class which is "minimal", meaning that no smaller class also contains the register. */ -extern enum reg_class mips_regno_to_class[]; +extern const enum reg_class mips_regno_to_class[]; #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ] diff --git a/gcc/config/ns32k/ns32k.c b/gcc/config/ns32k/ns32k.c index a7e89c2..7d923c8 100644 --- a/gcc/config/ns32k/ns32k.c +++ b/gcc/config/ns32k/ns32k.c @@ -1195,7 +1195,7 @@ print_operand_address (file, addr) register FILE *file; register rtx addr; { - static char scales[] = { 'b', 'w', 'd', 0, 'q', }; + static const char scales[] = { 'b', 'w', 'd', 0, 'q', }; rtx offset, base, indexexp, tmp; int scale; extern int flag_pic; diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index dda9d97..fa23eaa 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -4457,7 +4457,7 @@ enum millicodes { remI, remU, divI, divU, mulI, mulU, end1000 }; static void import_milli PARAMS ((enum millicodes)); static char imported[(int) end1000]; static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"}; -static char import_string[] = ".IMPORT $$....,MILLICODE"; +static const char import_string[] = ".IMPORT $$....,MILLICODE"; #define MILLI_START 10 static void @@ -4490,8 +4490,8 @@ output_mul_insn (unsignedp, insn) /* Emit the rtl for doing a division by a constant. */ /* Do magic division millicodes exist for this value? */ -static int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, - 1, 1}; +static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, + 1, 1}; /* We'll use an array to keep track of the magic millicodes and whether or not we've used them already. [n][0] is signed, [n][1] is diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 88420ba..9025619 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -164,7 +164,7 @@ char rs6000_reg_names[][8] = }; #ifdef TARGET_REGNAMES -static char alt_reg_names[][8] = +static const char alt_reg_names[][8] = { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", @@ -227,11 +227,11 @@ rs6000_override_options (default_cpu) static struct ptt { - const char *name; /* Canonical processor name. */ - enum processor_type processor; /* Processor type enum value. */ - int target_enable; /* Target flags to enable. */ - int target_disable; /* Target flags to disable. */ - } processor_target_table[] + const char *const name; /* Canonical processor name. */ + const enum processor_type processor; /* Processor type enum value. */ + const int target_enable; /* Target flags to enable. */ + const int target_disable; /* Target flags to disable. */ + } const processor_target_table[] = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS, POWER_MASKS | POWERPC_MASKS}, {"power", PROCESSOR_POWER, diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 27cd5b3..1af8c5f 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -87,7 +87,7 @@ static rtx leaf_label; registers. FRAME_POINTER_REGNUM cannot be remapped by this function to eliminate it. You must use -fomit-frame-pointer to get that. */ -char leaf_reg_remap[] = +const char leaf_reg_remap[] = { 0, 1, 2, 3, 4, 5, 6, 7, -1, -1, -1, -1, -1, -1, 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, @@ -226,9 +226,9 @@ void sparc_override_options () { static struct code_model { - const char *name; - int value; - } cmodels[] = { + const char *const name; + const int value; + } const cmodels[] = { { "32", CM_32 }, { "medlow", CM_MEDLOW }, { "medmid", CM_MEDMID }, @@ -236,12 +236,12 @@ sparc_override_options () { "embmedany", CM_EMBMEDANY }, { 0, 0 } }; - struct code_model *cmodel; + const struct code_model *cmodel; /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ static struct cpu_default { - int cpu; - const char *name; - } cpu_default[] = { + const int cpu; + const char *const name; + } const cpu_default[] = { /* There must be one entry here for each TARGET_CPU value. */ { TARGET_CPU_sparc, "cypress" }, { TARGET_CPU_sparclet, "tsc701" }, @@ -254,14 +254,14 @@ sparc_override_options () { TARGET_CPU_ultrasparc, "ultrasparc" }, { 0, 0 } }; - struct cpu_default *def; + const struct cpu_default *def; /* Table of values for -m{cpu,tune}=. */ static struct cpu_table { - const char *name; - enum processor_type processor; - int disable; - int enable; - } cpu_table[] = { + const char *const name; + const enum processor_type processor; + const int disable; + const int enable; + } const cpu_table[] = { { "v7", PROCESSOR_V7, MASK_ISA, 0 }, { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 }, { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 }, @@ -286,8 +286,8 @@ sparc_override_options () |MASK_DEPRECATED_V8_INSNS}, { 0, 0, 0, 0 } }; - struct cpu_table *cpu; - struct sparc_cpu_select *sel; + const struct cpu_table *cpu; + const struct sparc_cpu_select *sel; int fpu; #ifndef SPARC_BI_ARCH @@ -5564,13 +5564,13 @@ output_return (operands) /* Leaf functions and non-leaf functions have different needs. */ -static int +static const int reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; -static int +static const int reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; -static int *reg_alloc_orders[] = { +static const int *const reg_alloc_orders[] = { reg_leaf_alloc_order, reg_nonleaf_alloc_order}; @@ -5583,7 +5583,7 @@ order_regs_for_local_alloc () { last_order_nonleaf = !last_order_nonleaf; memcpy ((char *) reg_alloc_order, - (char *) reg_alloc_orders[last_order_nonleaf], + (const char *) reg_alloc_orders[last_order_nonleaf], FIRST_PSEUDO_REGISTER * sizeof (int)); } } diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 9835881..bf43ba9 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -721,9 +721,9 @@ extern enum processor_type sparc_cpu; struct sparc_cpu_select { const char *string; - const char *name; - int set_tune_p; - int set_arch_p; + const char *const name; + const int set_tune_p; + const int set_arch_p; }; extern struct sparc_cpu_select sparc_select[]; @@ -1433,7 +1433,7 @@ extern enum reg_class sparc_regno_reg_class[]; extern char sparc_leaf_regs[]; #define LEAF_REGISTERS sparc_leaf_regs -extern char leaf_reg_remap[]; +extern const char leaf_reg_remap[]; #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) /* The class value for index registers, and the one for base regs. */ |