diff options
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/arm/arm-fpus.def | 44 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 4 | ||||
| -rw-r--r-- | gcc/config/arm/arm.h | 34 |
3 files changed, 24 insertions, 58 deletions
diff --git a/gcc/config/arm/arm-fpus.def b/gcc/config/arm/arm-fpus.def index 1be718f..ae8197d 100644 --- a/gcc/config/arm/arm-fpus.def +++ b/gcc/config/arm/arm-fpus.def @@ -19,31 +19,31 @@ /* Before using #include to read this file, define a macro: - ARM_FPU(NAME, ISA, FEATURES) + ARM_FPU(NAME, ISA) The arguments are the fields of struct arm_fpu_desc. genopt.sh assumes no whitespace up to the first "," in each entry. */ -ARM_FPU("vfp", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), FPU_VFPv2 | FPU_DBL) -ARM_FPU("vfpv2", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), FPU_VFPv2 | FPU_DBL) -ARM_FPU("vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32), FPU_VFPv3 | FPU_D32) -ARM_FPU("vfpv3-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_D32 | FPU_FP16) -ARM_FPU("vfpv3-d16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL), FPU_VFPv3 | FPU_DBL) -ARM_FPU("vfpv3-d16-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_DBL | FPU_FP16) -ARM_FPU("vfpv3xd", ISA_FEAT(ISA_VFPv3), FPU_VFPv3) -ARM_FPU("vfpv3xd-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_FP16) -ARM_FPU("neon", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON), FPU_VFPv3 | FPU_NEON) -ARM_FPU("neon-vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON), FPU_VFPv3 | FPU_NEON) -ARM_FPU("neon-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_NEON | FPU_FP16) -ARM_FPU("vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_D32), FPU_VFPv4 | FPU_D32 | FPU_FP16) -ARM_FPU("neon-vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_NEON), FPU_VFPv4 | FPU_NEON | FPU_FP16) -ARM_FPU("vfpv4-d16", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_DBL), FPU_VFPv4 | FPU_DBL | FPU_FP16) -ARM_FPU("fpv4-sp-d16", ISA_FEAT(ISA_VFPv4), FPU_VFPv4 | FPU_FP16) -ARM_FPU("fpv5-sp-d16", ISA_FEAT(ISA_FPv5), FPU_VFPv5 | FPU_FP16) -ARM_FPU("fpv5-d16", ISA_FEAT(ISA_FPv5) ISA_FEAT(ISA_FP_DBL), FPU_VFPv5 | FPU_DBL | FPU_FP16) -ARM_FPU("fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_FP_D32), FPU_ARMv8 | FPU_D32 | FPU_FP16) -ARM_FPU("neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_NEON), FPU_ARMv8 | FPU_NEON | FPU_FP16) -ARM_FPU("crypto-neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_CRYPTO), FPU_ARMv8 | FPU_CRYPTO | FPU_FP16) +ARM_FPU("vfp", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL)) +ARM_FPU("vfpv2", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL)) +ARM_FPU("vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32)) +ARM_FPU("vfpv3-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32) ISA_FEAT(isa_bit_fp16conv)) +ARM_FPU("vfpv3-d16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL)) +ARM_FPU("vfpv3-d16-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL) ISA_FEAT(isa_bit_fp16conv)) +ARM_FPU("vfpv3xd", ISA_FEAT(ISA_VFPv3)) +ARM_FPU("vfpv3xd-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(isa_bit_fp16conv)) +ARM_FPU("neon", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON)) +ARM_FPU("neon-vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON)) +ARM_FPU("neon-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON) ISA_FEAT(isa_bit_fp16conv)) +ARM_FPU("vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_D32)) +ARM_FPU("neon-vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_NEON)) +ARM_FPU("vfpv4-d16", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_DBL)) +ARM_FPU("fpv4-sp-d16", ISA_FEAT(ISA_VFPv4)) +ARM_FPU("fpv5-sp-d16", ISA_FEAT(ISA_FPv5)) +ARM_FPU("fpv5-d16", ISA_FEAT(ISA_FPv5) ISA_FEAT(ISA_FP_DBL)) +ARM_FPU("fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_FP_D32)) +ARM_FPU("neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_NEON)) +ARM_FPU("crypto-neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_CRYPTO)) /* Compatibility aliases. */ -ARM_FPU("vfp3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32), FPU_VFPv3 | FPU_D32) +ARM_FPU("vfp3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32)) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 1d3bb89..522989d 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2328,8 +2328,8 @@ char arm_arch_name[] = "__ARM_ARCH_PROFILE__"; const struct arm_fpu_desc all_fpus[] = { -#define ARM_FPU(NAME, ISA, FEATURES) \ - { NAME, {ISA isa_nobit}, FEATURES }, +#define ARM_FPU(NAME, ISA) \ + { NAME, {ISA isa_nobit} }, #include "arm-fpus.def" #undef ARM_FPU }; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 17f030b..4582d2e 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -326,44 +326,10 @@ extern tree arm_fp16_type_node; {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, -/* FPU feature sets. */ - -typedef unsigned long arm_fpu_feature_set; - -/* Test for an FPU feature. */ -#define ARM_FPU_FSET_HAS(S,F) (((S) & (F)) == (F)) - -/* FPU Features. */ -#define FPU_FL_NONE (0u) -#define FPU_FL_NEON (1u << 0) /* NEON instructions. */ -#define FPU_FL_FP16 (1u << 1) /* Half-precision. */ -#define FPU_FL_CRYPTO (1u << 2) /* Crypto extensions. */ -#define FPU_FL_DBL (1u << 3) /* Has double precision. */ -#define FPU_FL_D32 (1u << 4) /* Has 32 double precision regs. */ -#define FPU_FL_VFPv2 (1u << 5) /* Has VFPv2 features. */ -#define FPU_FL_VFPv3 (1u << 6) /* Has VFPv3 extensions. */ -#define FPU_FL_VFPv4 (1u << 7) /* Has VFPv4 extensions. */ -#define FPU_FL_VFPv5 (1u << 8) /* Has VFPv5 extensions. */ -#define FPU_FL_ARMv8 (1u << 9) /* Has ARMv8 extensions to VFP. */ - -/* Some useful combinations. */ -#define FPU_VFPv2 (FPU_FL_VFPv2) -#define FPU_VFPv3 (FPU_VFPv2 | FPU_FL_VFPv3) -#define FPU_VFPv4 (FPU_VFPv3 | FPU_FL_VFPv4) -#define FPU_VFPv5 (FPU_VFPv4 | FPU_FL_VFPv5) -#define FPU_ARMv8 (FPU_VFPv5 | FPU_FL_ARMv8) - -#define FPU_DBL (FPU_FL_DBL) -#define FPU_D32 (FPU_DBL | FPU_FL_D32) -#define FPU_NEON (FPU_D32 | FPU_FL_NEON) -#define FPU_CRYPTO (FPU_NEON | FPU_FL_CRYPTO) -#define FPU_FP16 (FPU_FL_FP16) - extern const struct arm_fpu_desc { const char *name; enum isa_feature isa_bits[isa_num_bits]; - arm_fpu_feature_set features; } all_fpus[]; /* Which floating point hardware to schedule for. */ |