diff options
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/aarch64/aarch64-sve2.md | 60 | ||||
| -rw-r--r-- | gcc/config/aarch64/iterators.md | 35 |
2 files changed, 94 insertions, 1 deletions
diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index 2334e5a..ee9acdc 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -63,3 +63,63 @@ movprfx\t%0, %2\;<sur>h<addsub>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>" [(set_attr "movprfx" "*,yes")] ) + +;; Multiply long top / bottom. +(define_insn "<su>mull<bt><Vwide>" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (unspec:<VWIDE> [(match_operand:SVE_BHSI 1 "register_operand" "w") + (match_operand:SVE_BHSI 2 "register_operand" "w")] + MULLBT))] + "TARGET_SVE2" + "<su>mull<bt>\t%0.<Vewtype>, %1.<Vetype>, %2.<Vetype>" +) + +;; (Rounding) Right shift narrow bottom. +(define_insn "<r>shrnb<mode>" + [(set (match_operand:SVE_BHSI 0 "register_operand" "=w") + (unspec:SVE_BHSI + [(match_operand:<VWIDE> 1 "register_operand" "w") + (match_operand 2 "aarch64_simd_shift_imm_offset_<Vel>" "")] + SHRNB))] + "TARGET_SVE2" + "<r>shrnb\t%0.<Vetype>, %1.<Vewtype>, #%2" +) + +;; (Rounding) Right shift narrow top. +(define_insn "<r>shrnt<mode>" + [(set (match_operand:SVE_BHSI 0 "register_operand" "=w") + (unspec:SVE_BHSI + [(match_operand:SVE_BHSI 1 "register_operand" "0") + (match_operand:<VWIDE> 2 "register_operand" "w") + (match_operand 3 "aarch64_simd_shift_imm_offset_<Vel>" "i")] + SHRNT))] + "TARGET_SVE2" + "<r>shrnt\t%0.<Vetype>, %2.<Vewtype>, #%3" +) + +;; Unpredicated integer multiply-high-with-(round-and-)scale. +(define_expand "<su>mulh<r>s<mode>3" + [(set (match_operand:SVE_BHSI 0 "register_operand") + (unspec:SVE_BHSI + [(match_dup 3) + (unspec:SVE_BHSI [(match_operand:SVE_BHSI 1 "register_operand") + (match_operand:SVE_BHSI 2 "register_operand")] + MULHRS)] + UNSPEC_PRED_X))] + "TARGET_SVE2" + { + operands[3] = aarch64_ptrue_reg (<VPRED>mode); + + rtx prod_b = gen_reg_rtx (<VWIDE>mode); + rtx prod_t = gen_reg_rtx (<VWIDE>mode); + emit_insn (gen_<su>mullb<Vwide> (prod_b, operands[1], operands[2])); + emit_insn (gen_<su>mullt<Vwide> (prod_t, operands[1], operands[2])); + + rtx shift = GEN_INT (GET_MODE_UNIT_BITSIZE (<MODE>mode) - 1); + emit_insn (gen_<r>shrnb<mode> (operands[0], prod_b, shift)); + emit_insn (gen_<r>shrnt<mode> (operands[0], operands[0], prod_t, shift)); + + DONE; + } +) + diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 49d227f..d23f0fc 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -378,6 +378,10 @@ UNSPEC_RSUBHN2 ; Used in aarch64-simd.md. UNSPEC_SQDMULH ; Used in aarch64-simd.md. UNSPEC_SQRDMULH ; Used in aarch64-simd.md. + UNSPEC_SMULLB ; Used in aarch64-sve2.md. + UNSPEC_SMULLT ; Used in aarch64-sve2.md. + UNSPEC_UMULLB ; Used in aarch64-sve2.md. + UNSPEC_UMULLT ; Used in aarch64-sve2.md. UNSPEC_PMUL ; Used in aarch64-simd.md. UNSPEC_FMULX ; Used in aarch64-simd.md. UNSPEC_USQADD ; Used in aarch64-simd.md. @@ -400,6 +404,10 @@ UNSPEC_UQSHRN ; Used in aarch64-simd.md. UNSPEC_SQRSHRN ; Used in aarch64-simd.md. UNSPEC_UQRSHRN ; Used in aarch64-simd.md. + UNSPEC_SHRNB ; Used in aarch64-sve2.md. + UNSPEC_SHRNT ; Used in aarch64-sve2.md. + UNSPEC_RSHRNB ; Used in aarch64-sve2.md. + UNSPEC_RSHRNT ; Used in aarch64-sve2.md. UNSPEC_SSHL ; Used in aarch64-simd.md. UNSPEC_USHL ; Used in aarch64-simd.md. UNSPEC_SRSHL ; Used in aarch64-simd.md. @@ -523,6 +531,10 @@ UNSPEC_FCMLA90 ; Used in aarch64-simd.md. UNSPEC_FCMLA180 ; Used in aarch64-simd.md. UNSPEC_FCMLA270 ; Used in aarch64-simd.md. + UNSPEC_SMULHS ; Used in aarch64-sve2.md. + UNSPEC_SMULHRS ; Used in aarch64-sve2.md. + UNSPEC_UMULHS ; Used in aarch64-sve2.md. + UNSPEC_UMULHRS ; Used in aarch64-sve2.md. ]) ;; ------------------------------------------------------------------ @@ -1588,6 +1600,13 @@ (define_int_iterator RHADD [UNSPEC_SRHADD UNSPEC_URHADD]) +(define_int_iterator MULLBT [UNSPEC_SMULLB UNSPEC_UMULLB + UNSPEC_SMULLT UNSPEC_UMULLT]) + +(define_int_iterator SHRNB [UNSPEC_SHRNB UNSPEC_RSHRNB]) + +(define_int_iterator SHRNT [UNSPEC_SHRNT UNSPEC_RSHRNT]) + (define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT]) (define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN @@ -1607,6 +1626,9 @@ (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH]) +(define_int_iterator MULHRS [UNSPEC_SMULHS UNSPEC_UMULHS + UNSPEC_SMULHRS UNSPEC_UMULHRS]) + (define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD]) (define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN]) @@ -1872,7 +1894,11 @@ (UNSPEC_COND_FCVTZS "s") (UNSPEC_COND_FCVTZU "u") (UNSPEC_COND_SCVTF "s") - (UNSPEC_COND_UCVTF "u")]) + (UNSPEC_COND_UCVTF "u") + (UNSPEC_SMULLB "s") (UNSPEC_UMULLB "u") + (UNSPEC_SMULLT "s") (UNSPEC_UMULLT "u") + (UNSPEC_SMULHS "s") (UNSPEC_UMULHS "u") + (UNSPEC_SMULHRS "s") (UNSPEC_UMULHRS "u")]) (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u") (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur") @@ -1910,6 +1936,10 @@ (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r") + (UNSPEC_SHRNB "") (UNSPEC_SHRNT "") + (UNSPEC_RSHRNB "r") (UNSPEC_RSHRNT "r") + (UNSPEC_SMULHS "") (UNSPEC_UMULHS "") + (UNSPEC_SMULHRS "r") (UNSPEC_UMULHRS "r") ]) (define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l") @@ -1922,6 +1952,9 @@ (UNSPEC_SHADD "") (UNSPEC_UHADD "u") (UNSPEC_SRHADD "") (UNSPEC_URHADD "u")]) +(define_int_attr bt [(UNSPEC_SMULLB "b") (UNSPEC_UMULLB "b") + (UNSPEC_SMULLT "t") (UNSPEC_UMULLT "t")]) + (define_int_attr addsub [(UNSPEC_SHADD "add") (UNSPEC_UHADD "add") (UNSPEC_SRHADD "add") |