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-rw-r--r--gcc/config/aarch64/aarch64.md27
1 files changed, 27 insertions, 0 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 88f6610..2c0dbab 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -5361,6 +5361,33 @@
[(set_attr "type" "bfm")]
)
+; Zero-extended version of above (aarch64_bfxil)
+(define_insn "*aarch64_bfxilsi_uxtw"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (zero_extend:DI (ior:SI (and:SI (match_operand:SI 1 "register_operand"
+ "r,0")
+ (match_operand:SI 3 "const_int_operand" "n, Ulc"))
+ (and:SI (match_operand:SI 2 "register_operand" "0,r")
+ (match_operand:SI 4 "const_int_operand" "Ulc, n")))))]
+ "(INTVAL (operands[3]) == ~INTVAL (operands[4]))
+ && (aarch64_high_bits_all_ones_p (INTVAL (operands[3]))
+ || aarch64_high_bits_all_ones_p (INTVAL (operands[4])))"
+ {
+ switch (which_alternative)
+ {
+ case 0:
+ operands[3] = GEN_INT (ctz_hwi (~INTVAL (operands[3])));
+ return "bfxil\\t%0, %1, 0, %3";
+ case 1:
+ operands[3] = GEN_INT (ctz_hwi (~INTVAL (operands[4])));
+ return "bfxil\\t%0, %2, 0, %3";
+ default:
+ gcc_unreachable ();
+ }
+ }
+ [(set_attr "type" "bfm")]
+)
+
;; There are no canonicalisation rules for the position of the lshiftrt, ashift
;; operations within an IOR/AND RTX, therefore we have two patterns matching
;; each valid permutation.