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-rw-r--r--gcc/config/alpha/alpha.c17
-rw-r--r--gcc/config/alpha/alpha.h10
-rw-r--r--gcc/config/i386/i386.c16
-rw-r--r--gcc/config/i386/i386.h8
-rw-r--r--gcc/config/powerpcspe/powerpcspe-protos.h1
-rw-r--r--gcc/config/powerpcspe/powerpcspe.c9
-rw-r--r--gcc/config/powerpcspe/powerpcspe.h7
-rw-r--r--gcc/config/rs6000/rs6000-protos.h1
-rw-r--r--gcc/config/rs6000/rs6000.c9
-rw-r--r--gcc/config/rs6000/rs6000.h7
-rw-r--r--gcc/config/s390/s390.c15
-rw-r--r--gcc/config/s390/s390.h7
-rw-r--r--gcc/config/sparc/sparc.c27
-rw-r--r--gcc/config/sparc/sparc.h12
14 files changed, 85 insertions, 61 deletions
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index ecc915d..28fe467 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -1688,6 +1688,21 @@ alpha_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
return NO_REGS;
}
+
+/* Implement TARGET_SECONDARY_MEMORY_NEEDED_MODE. If MODE is
+ floating-point, use it. Otherwise, widen to a word like the default.
+ This is needed because we always store integers in FP registers in
+ quadword format. This whole area is very tricky! */
+
+static machine_mode
+alpha_secondary_memory_needed_mode (machine_mode mode)
+{
+ if (GET_MODE_CLASS (mode) == MODE_FLOAT)
+ return mode;
+ if (GET_MODE_SIZE (mode) >= 4)
+ return mode;
+ return mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (mode), 0).require ();
+}
/* Given SEQ, which is an INSN list, look for any MEMs in either
a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
@@ -10062,6 +10077,8 @@ alpha_modes_tieable_p (machine_mode mode1, machine_mode mode2)
#undef TARGET_SECONDARY_RELOAD
#define TARGET_SECONDARY_RELOAD alpha_secondary_reload
+#undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
+#define TARGET_SECONDARY_MEMORY_NEEDED_MODE alpha_secondary_memory_needed_mode
#undef TARGET_SCALAR_MODE_SUPPORTED_P
#define TARGET_SCALAR_MODE_SUPPORTED_P alpha_scalar_mode_supported_p
diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h
index 56ba895..10f32b7 100644
--- a/gcc/config/alpha/alpha.h
+++ b/gcc/config/alpha/alpha.h
@@ -486,16 +486,6 @@ enum reg_class {
(! TARGET_FIX && (((CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS) \
|| ((CLASS2) == FLOAT_REGS && (CLASS1) != FLOAT_REGS)))
-/* Specify the mode to be used for memory when a secondary memory
- location is needed. If MODE is floating-point, use it. Otherwise,
- widen to a word like the default. This is needed because we always
- store integers in FP registers in quadword format. This whole
- area is very tricky! */
-#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
- (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \
- : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \
- : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0).require ())
-
/* Return the class of registers that cannot change mode from FROM to TO. */
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index edcc2d6..a508f56 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -41162,6 +41162,20 @@ ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
return inline_secondary_memory_needed (class1, class2, mode, strict);
}
+/* Implement TARGET_SECONDARY_MEMORY_NEEDED_MODE.
+
+ get_secondary_mem widens integral modes to BITS_PER_WORD.
+ There is no need to emit full 64 bit move on 64 bit targets
+ for integral modes that can be moved using 32 bit move. */
+
+static machine_mode
+ix86_secondary_memory_needed_mode (machine_mode mode)
+{
+ if (GET_MODE_BITSIZE (mode) < 32 && INTEGRAL_MODE_P (mode))
+ return mode_for_size (32, GET_MODE_CLASS (mode), 0).require ();
+ return mode;
+}
+
/* Implement the TARGET_CLASS_MAX_NREGS hook.
On the 80386, this is the size of MODE in words,
@@ -53206,6 +53220,8 @@ ix86_run_selftests (void)
#undef TARGET_SECONDARY_RELOAD
#define TARGET_SECONDARY_RELOAD ix86_secondary_reload
+#undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
+#define TARGET_SECONDARY_MEMORY_NEEDED_MODE ix86_secondary_memory_needed_mode
#undef TARGET_CLASS_MAX_NREGS
#define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index a89782a..09b8da5 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1524,14 +1524,6 @@ enum reg_class
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
-/* Get_secondary_mem widens integral modes to BITS_PER_WORD.
- There is no need to emit full 64 bit move on 64 bit targets
- for integral modes that can be moved using 32 bit move. */
-#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
- (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \
- ? mode_for_size (32, GET_MODE_CLASS (MODE), 0).require () \
- : MODE)
-
/* Return a class of registers that cannot change FROM mode to TO mode. */
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
diff --git a/gcc/config/powerpcspe/powerpcspe-protos.h b/gcc/config/powerpcspe/powerpcspe-protos.h
index 20587ba..f3aa41b 100644
--- a/gcc/config/powerpcspe/powerpcspe-protos.h
+++ b/gcc/config/powerpcspe/powerpcspe-protos.h
@@ -154,7 +154,6 @@ extern void rs6000_emit_le_vsx_move (rtx, rtx, machine_mode);
extern bool valid_sf_si_move (rtx, rtx, machine_mode);
extern void rs6000_emit_move (rtx, rtx, machine_mode);
extern rtx rs6000_secondary_memory_needed_rtx (machine_mode);
-extern machine_mode rs6000_secondary_memory_needed_mode (machine_mode);
extern rtx (*rs6000_legitimize_reload_address_ptr) (rtx, machine_mode,
int, int, int, int *);
extern bool rs6000_legitimate_offset_address_p (machine_mode, rtx,
diff --git a/gcc/config/powerpcspe/powerpcspe.c b/gcc/config/powerpcspe/powerpcspe.c
index 7784676..9b8d68b 100644
--- a/gcc/config/powerpcspe/powerpcspe.c
+++ b/gcc/config/powerpcspe/powerpcspe.c
@@ -1897,6 +1897,8 @@ static const struct attribute_spec rs6000_attribute_table[] =
#undef TARGET_SECONDARY_RELOAD
#define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
+#undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
+#define TARGET_SECONDARY_MEMORY_NEEDED_MODE rs6000_secondary_memory_needed_mode
#undef TARGET_LEGITIMATE_ADDRESS_P
#define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
@@ -21811,10 +21813,9 @@ rs6000_secondary_memory_needed_rtx (machine_mode mode)
return ret;
}
-/* Return the mode to be used for memory when a secondary memory
- location is needed. For SDmode values we need to use DDmode, in
- all other cases we can use the same mode. */
-machine_mode
+/* Implement TARGET_SECONDARY_MEMORY_NEEDED_MODE. For SDmode values we
+ need to use DDmode, in all other cases we can use the same mode. */
+static machine_mode
rs6000_secondary_memory_needed_mode (machine_mode mode)
{
if (lra_in_progress && mode == SDmode)
diff --git a/gcc/config/powerpcspe/powerpcspe.h b/gcc/config/powerpcspe/powerpcspe.h
index c4b6dc3..5d1a138 100644
--- a/gcc/config/powerpcspe/powerpcspe.h
+++ b/gcc/config/powerpcspe/powerpcspe.h
@@ -1611,13 +1611,6 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
#define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
rs6000_secondary_memory_needed_rtx (MODE)
-/* Specify the mode to be used for memory when a secondary memory
- location is needed. For cpus that cannot load/store SDmode values
- from the 64-bit FP registers without using a full 64-bit
- load/store, we need a wider mode. */
-#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
- rs6000_secondary_memory_needed_mode (MODE)
-
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS.
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index f9be5d3..b21652b 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -155,7 +155,6 @@ extern void rs6000_emit_le_vsx_permute (rtx, rtx, machine_mode);
extern void rs6000_emit_le_vsx_move (rtx, rtx, machine_mode);
extern bool valid_sf_si_move (rtx, rtx, machine_mode);
extern void rs6000_emit_move (rtx, rtx, machine_mode);
-extern machine_mode rs6000_secondary_memory_needed_mode (machine_mode);
extern rtx (*rs6000_legitimize_reload_address_ptr) (rtx, machine_mode,
int, int, int, int *);
extern bool rs6000_legitimate_offset_address_p (machine_mode, rtx,
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 1338371..a4a89d0 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1876,6 +1876,8 @@ static const struct attribute_spec rs6000_attribute_table[] =
#undef TARGET_SECONDARY_RELOAD
#define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
+#undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
+#define TARGET_SECONDARY_MEMORY_NEEDED_MODE rs6000_secondary_memory_needed_mode
#undef TARGET_LEGITIMATE_ADDRESS_P
#define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
@@ -19242,10 +19244,9 @@ mems_ok_for_quad_peep (rtx mem1, rtx mem2)
return 1;
}
-/* Return the mode to be used for memory when a secondary memory
- location is needed. For SDmode values we need to use DDmode, in
- all other cases we can use the same mode. */
-machine_mode
+/* Implement TARGET_SECONDARY_RELOAD_NEEDED_MODE. For SDmode values we
+ need to use DDmode, in all other cases we can use the same mode. */
+static machine_mode
rs6000_secondary_memory_needed_mode (machine_mode mode)
{
if (lra_in_progress && mode == SDmode)
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 7ac6e3b..1a7ce96 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1514,13 +1514,6 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE)
-/* Specify the mode to be used for memory when a secondary memory
- location is needed. For cpus that cannot load/store SDmode values
- from the 64-bit FP registers without using a full 64-bit
- load/store, we need a wider mode. */
-#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
- rs6000_secondary_memory_needed_mode (MODE)
-
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS.
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 46d6c32..1319f68 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -4409,6 +4409,19 @@ s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
return NO_REGS;
}
+/* Implement TARGET_SECONDARY_MEMORY_NEEDED_MODE.
+
+ get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit
+ because the movsi and movsf patterns don't handle r/f moves. */
+
+static machine_mode
+s390_secondary_memory_needed_mode (machine_mode mode)
+{
+ if (GET_MODE_BITSIZE (mode) < 32)
+ return mode_for_size (32, GET_MODE_CLASS (mode), 0).require ();
+ return mode;
+}
+
/* Generate code to load SRC, which is PLUS that is not a
legitimate operand for the LA instruction, into TARGET.
SCRATCH may be used as scratch register. */
@@ -15959,6 +15972,8 @@ s390_asan_shadow_offset (void)
#undef TARGET_SECONDARY_RELOAD
#define TARGET_SECONDARY_RELOAD s390_secondary_reload
+#undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
+#define TARGET_SECONDARY_MEMORY_NEEDED_MODE s390_secondary_memory_needed_mode
#undef TARGET_LIBGCC_CMP_RETURN_MODE
#define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h
index 0682fb6..b4a23c3 100644
--- a/gcc/config/s390/s390.h
+++ b/gcc/config/s390/s390.h
@@ -599,13 +599,6 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
&& (!TARGET_VX || (SCALAR_FLOAT_MODE_P (MODE) \
&& GET_MODE_SIZE (MODE) > 8)))
-/* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit
- because the movsi and movsf patterns don't handle r/f moves. */
-#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
- (GET_MODE_BITSIZE (MODE) < 32 \
- ? mode_for_size (32, GET_MODE_CLASS (MODE), 0).require () \
- : (MODE))
-
/* Stack layout and calling conventions. */
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 9a7e467..469b03d 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -672,6 +672,7 @@ static void sparc_print_operand_address (FILE *, machine_mode, rtx);
static reg_class_t sparc_secondary_reload (bool, rtx, reg_class_t,
machine_mode,
secondary_reload_info *);
+static machine_mode sparc_secondary_memory_needed_mode (machine_mode);
static scalar_int_mode sparc_cstore_mode (enum insn_code icode);
static void sparc_atomic_assign_expand_fenv (tree *, tree *, tree *);
static bool sparc_fixed_condition_code_regs (unsigned int *, unsigned int *);
@@ -859,6 +860,8 @@ char sparc_hard_reg_printed[8];
#undef TARGET_SECONDARY_RELOAD
#define TARGET_SECONDARY_RELOAD sparc_secondary_reload
+#undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
+#define TARGET_SECONDARY_MEMORY_NEEDED_MODE sparc_secondary_memory_needed_mode
#undef TARGET_CONDITIONAL_REGISTER_USAGE
#define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
@@ -13050,6 +13053,30 @@ sparc_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
return NO_REGS;
}
+/* Implement TARGET_SECONDARY_MEMORY_NEEDED_MODE.
+
+ get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
+ because the movsi and movsf patterns don't handle r/f moves.
+ For v8 we copy the default definition. */
+
+static machine_mode
+sparc_secondary_memory_needed_mode (machine_mode mode)
+{
+ if (TARGET_ARCH64)
+ {
+ if (GET_MODE_BITSIZE (mode) < 32)
+ return mode_for_size (32, GET_MODE_CLASS (mode), 0).require ();
+ return mode;
+ }
+ else
+ {
+ if (GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
+ return mode_for_size (BITS_PER_WORD,
+ GET_MODE_CLASS (mode), 0).require ();
+ return mode;
+ }
+}
+
/* Emit code to conditionally move either OPERANDS[2] or OPERANDS[3] into
OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index e037897..51bc318 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -1055,18 +1055,6 @@ extern char leaf_reg_remap[];
|| GET_MODE_SIZE (MODE) > 8 \
|| GET_MODE_SIZE (MODE) < 4))
-/* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
- because the movsi and movsf patterns don't handle r/f moves.
- For v8 we copy the default definition. */
-#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
- (TARGET_ARCH64 \
- ? (GET_MODE_BITSIZE (MODE) < 32 \
- ? mode_for_size (32, GET_MODE_CLASS (MODE), 0).require () \
- : MODE) \
- : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
- ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0).require () \
- : MODE))
-
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS. */
/* On SPARC, this is the size of MODE in words. */
generated by cgit v1.1 at 2025-09-04 10:52:31 +0000