diff options
Diffstat (limited to 'gcc/config/xtensa/xtensa.md')
| -rw-r--r-- | gcc/config/xtensa/xtensa.md | 35 |
1 files changed, 28 insertions, 7 deletions
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 0b557c1..2bb2672 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -52,20 +52,41 @@ [(set_attr "type" "multi")]) -;; Functional units. +;; Pipeline model. -(define_function_unit "memory" 1 0 (eq_attr "type" "load,fload") 2 0) +;; The Xtensa basically has simple 5-stage RISC pipeline. +;; Most instructions complete in 1 cycle, and it is OK to assume that +;; everything is fully pipelined. The exceptions have special insn +;; reservations in the pipeline description below. The Xtensa can +;; issue one instruction per cycle, so defining CPU units is unnecessary. -(define_function_unit "sreg" 1 1 (eq_attr "type" "rsr") 2 0) +(define_insn_reservation "xtensa_any_insn" 1 + (eq_attr "type" "!load,fload,rsr,mul16,mul32,fmadd,fconv") + "nothing") -(define_function_unit "mul16" 1 0 (eq_attr "type" "mul16") 2 0) +(define_insn_reservation "xtensa_memory" 2 + (eq_attr "type" "load,fload") + "nothing") -(define_function_unit "mul32" 1 0 (eq_attr "type" "mul32") 2 0) +(define_insn_reservation "xtensa_sreg" 2 + (eq_attr "type" "rsr") + "nothing") -(define_function_unit "fpmadd" 1 0 (eq_attr "type" "fmadd") 4 0) +(define_insn_reservation "xtensa_mul16" 2 + (eq_attr "type" "mul16") + "nothing") -(define_function_unit "fpconv" 1 0 (eq_attr "type" "fconv") 2 0) +(define_insn_reservation "xtensa_mul32" 2 + (eq_attr "type" "mul32") + "nothing") +(define_insn_reservation "xtensa_fmadd" 4 + (eq_attr "type" "fmadd") + "nothing") + +(define_insn_reservation "xtensa_fconv" 2 + (eq_attr "type" "fconv") + "nothing") ;; Addition. |