diff options
Diffstat (limited to 'gcc/config/sparc/sparc.h')
| -rw-r--r-- | gcc/config/sparc/sparc.h | 28 |
1 files changed, 22 insertions, 6 deletions
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 94b8773..0ff70f6 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -207,7 +207,8 @@ extern enum cmodel sparc_cmodel; which requires the following macro to be true if enabled. Prior to V9, there are no instructions to even talk about memory synchronization. Note that the UltraSPARC III processors don't implement RMO, unlike the - UltraSPARC II processors. Niagara does not implement RMO either. + UltraSPARC II processors. Niagara and Niagara-2 do not implement RMO + either. Default to false; for example, Solaris never enables RMO, only ever uses total memory ordering (TMO). */ @@ -240,11 +241,13 @@ extern enum cmodel sparc_cmodel; #define TARGET_CPU_ultrasparc 8 #define TARGET_CPU_ultrasparc3 9 #define TARGET_CPU_niagara 10 +#define TARGET_CPU_niagara2 11 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \ - || TARGET_CPU_DEFAULT == TARGET_CPU_niagara + || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \ + || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 #define CPP_CPU32_DEFAULT_SPEC "" #define ASM_CPU32_DEFAULT_SPEC "" @@ -269,6 +272,10 @@ extern enum cmodel sparc_cmodel; #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" #define ASM_CPU64_DEFAULT_SPEC "-Av9b" #endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 +#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" +#define ASM_CPU64_DEFAULT_SPEC "-Av9b" +#endif #else @@ -360,6 +367,7 @@ extern enum cmodel sparc_cmodel; %{mcpu=ultrasparc:-D__sparc_v9__} \ %{mcpu=ultrasparc3:-D__sparc_v9__} \ %{mcpu=niagara:-D__sparc_v9__} \ +%{mcpu=niagara2:-D__sparc_v9__} \ %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \ " #define CPP_ARCH32_SPEC "" @@ -410,6 +418,7 @@ extern enum cmodel sparc_cmodel; %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ %{mcpu=niagara:%{!mv8plus:-Av9b}} \ +%{mcpu=niagara2:%{!mv8plus:-Av9b}} \ %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \ " @@ -534,7 +543,8 @@ enum processor_type { PROCESSOR_V9, PROCESSOR_ULTRASPARC, PROCESSOR_ULTRASPARC3, - PROCESSOR_NIAGARA + PROCESSOR_NIAGARA, + PROCESSOR_NIAGARA2 }; /* This is set from -m{cpu,tune}=xxx. */ @@ -2155,7 +2165,8 @@ do { \ || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \ ? ((sparc_cpu == PROCESSOR_ULTRASPARC \ || sparc_cpu == PROCESSOR_ULTRASPARC3 \ - || sparc_cpu == PROCESSOR_NIAGARA) ? 12 : 6) : 2) + || sparc_cpu == PROCESSOR_NIAGARA \ + || sparc_cpu == PROCESSOR_NIAGARA2) ? 12 : 6) : 2) /* Provide the cost of a branch. For pre-v9 processors we use a value of 3 to take into account the potential annulling of @@ -2168,7 +2179,10 @@ do { \ mispredicted branch. On Niagara, normal branches insert 3 bubbles into the pipe - and annulled branches insert 4 bubbles. */ + and annulled branches insert 4 bubbles. + + On Niagara-2, a not-taken branch costs 1 cycle whereas a taken + branch costs 6 cycles. */ #define BRANCH_COST \ ((sparc_cpu == PROCESSOR_V9 \ @@ -2178,7 +2192,9 @@ do { \ ? 9 \ : (sparc_cpu == PROCESSOR_NIAGARA \ ? 4 \ - : 3))) + : (sparc_cpu == PROCESSOR_NIAGARA2 \ + ? 5 \ + : 3)))) /* Control the assembler format that we output. */ |