diff options
Diffstat (limited to 'gcc/config/sparc/sparc.c')
| -rw-r--r-- | gcc/config/sparc/sparc.c | 88 |
1 files changed, 44 insertions, 44 deletions
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 5885288..c6efe19 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -2068,21 +2068,21 @@ sparc_expand_move (machine_mode mode, rtx *operands) switch (mode) { - case QImode: + case E_QImode: /* All QImode constants require only one insn, so proceed. */ break; - case HImode: - case SImode: + case E_HImode: + case E_SImode: sparc_emit_set_const32 (operands[0], operands[1]); return true; - case DImode: + case E_DImode: /* input_operand should have filtered out 32-bit mode. */ sparc_emit_set_const64 (operands[0], operands[1]); return true; - case TImode: + case E_TImode: { rtx high, low; /* TImode isn't available in 32-bit mode. */ @@ -3475,10 +3475,10 @@ emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands) case FLOAT_EXTEND: switch (GET_MODE (operands[1])) { - case SFmode: + case E_SFmode: func = "_Qp_stoq"; break; - case DFmode: + case E_DFmode: func = "_Qp_dtoq"; break; default: @@ -3489,10 +3489,10 @@ emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands) case FLOAT_TRUNCATE: switch (GET_MODE (operands[0])) { - case SFmode: + case E_SFmode: func = "_Qp_qtos"; break; - case DFmode: + case E_DFmode: func = "_Qp_qtod"; break; default: @@ -3503,12 +3503,12 @@ emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands) case FLOAT: switch (GET_MODE (operands[1])) { - case SImode: + case E_SImode: func = "_Qp_itoq"; if (TARGET_ARCH64) operands[1] = gen_rtx_SIGN_EXTEND (DImode, operands[1]); break; - case DImode: + case E_DImode: func = "_Qp_xtoq"; break; default: @@ -3519,12 +3519,12 @@ emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands) case UNSIGNED_FLOAT: switch (GET_MODE (operands[1])) { - case SImode: + case E_SImode: func = "_Qp_uitoq"; if (TARGET_ARCH64) operands[1] = gen_rtx_ZERO_EXTEND (DImode, operands[1]); break; - case DImode: + case E_DImode: func = "_Qp_uxtoq"; break; default: @@ -3535,10 +3535,10 @@ emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands) case FIX: switch (GET_MODE (operands[0])) { - case SImode: + case E_SImode: func = "_Qp_qtoi"; break; - case DImode: + case E_DImode: func = "_Qp_qtox"; break; default: @@ -3549,10 +3549,10 @@ emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands) case UNSIGNED_FIX: switch (GET_MODE (operands[0])) { - case SImode: + case E_SImode: func = "_Qp_qtoui"; break; - case DImode: + case E_DImode: func = "_Qp_qtoux"; break; default: @@ -7699,11 +7699,11 @@ sparc_preferred_simd_mode (machine_mode mode) if (TARGET_VIS) switch (mode) { - case SImode: + case E_SImode: return V2SImode; - case HImode: + case E_HImode: return V4HImode; - case QImode: + case E_QImode: return V8QImode; default:; @@ -7973,23 +7973,23 @@ output_cbranch (rtx op, rtx dest, int label, int reversed, int annul, switch (mode) { - case CCmode: - case CCNZmode: - case CCCmode: - case CCVmode: + case E_CCmode: + case E_CCNZmode: + case E_CCCmode: + case E_CCVmode: labelno = "%%icc, "; if (v8) labelno = ""; break; - case CCXmode: - case CCXNZmode: - case CCXCmode: - case CCXVmode: + case E_CCXmode: + case E_CCXNZmode: + case E_CCXCmode: + case E_CCXVmode: labelno = "%%xcc, "; gcc_assert (!v8); break; - case CCFPmode: - case CCFPEmode: + case E_CCFPmode: + case E_CCFPEmode: { static char v9_fcc_labelno[] = "%%fccX, "; /* Set the char indicating the number of the fcc reg to use. */ @@ -9047,16 +9047,16 @@ sparc_print_operand (FILE *file, rtx x, int code) { switch (GET_MODE (x)) { - case CCmode: - case CCNZmode: - case CCCmode: - case CCVmode: + case E_CCmode: + case E_CCNZmode: + case E_CCCmode: + case E_CCVmode: s = "%icc"; break; - case CCXmode: - case CCXNZmode: - case CCXCmode: - case CCXVmode: + case E_CCXmode: + case E_CCXNZmode: + case E_CCXCmode: + case E_CCXVmode: s = "%xcc"; break; default: @@ -12439,7 +12439,7 @@ sparc_expand_vec_perm_bmask (machine_mode vmode, rtx sel) sel = gen_lowpart (DImode, sel); switch (vmode) { - case V2SImode: + case E_V2SImode: /* inp = xxxxxxxAxxxxxxxB */ t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16), NULL_RTX, 1, OPTAB_DIRECT); @@ -12458,7 +12458,7 @@ sparc_expand_vec_perm_bmask (machine_mode vmode, rtx sel) /* sel = { A*4, A*4+1, A*4+2, ... } */ break; - case V4HImode: + case E_V4HImode: /* inp = xxxAxxxBxxxCxxxD */ t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (8), NULL_RTX, 1, OPTAB_DIRECT); @@ -12495,7 +12495,7 @@ sparc_expand_vec_perm_bmask (machine_mode vmode, rtx sel) /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */ break; - case V8QImode: + case E_V8QImode: /* input = xAxBxCxDxExFxGxH */ sel = expand_simple_binop (DImode, AND, sel, GEN_INT ((HOST_WIDE_INT)0x0f0f0f0f << 32 @@ -12793,15 +12793,15 @@ vector_init_bshuffle (rtx target, rtx elt, machine_mode mode, switch (mode) { - case V2SImode: + case E_V2SImode: final_insn = gen_bshufflev2si_vis (target, t1, t1); bmask = 0x45674567; break; - case V4HImode: + case E_V4HImode: final_insn = gen_bshufflev4hi_vis (target, t1, t1); bmask = 0x67676767; break; - case V8QImode: + case E_V8QImode: final_insn = gen_bshufflev8qi_vis (target, t1, t1); bmask = 0x77777777; break; |