diff options
Diffstat (limited to 'gcc/config/sparc/sparc.c')
| -rw-r--r-- | gcc/config/sparc/sparc.c | 25 |
1 files changed, 21 insertions, 4 deletions
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 57b008e..159685d 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -675,6 +675,8 @@ static scalar_int_mode sparc_cstore_mode (enum insn_code icode); static void sparc_atomic_assign_expand_fenv (tree *, tree *, tree *); static bool sparc_fixed_condition_code_regs (unsigned int *, unsigned int *); static unsigned int sparc_min_arithmetic_precision (void); +static bool sparc_hard_regno_mode_ok (unsigned int, machine_mode); + #ifdef SUBTARGET_ATTRIBUTE_TABLE /* Table of valid machine attributes. */ @@ -899,6 +901,9 @@ char sparc_hard_reg_printed[8]; #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1 +#undef TARGET_HARD_REGNO_MODE_OK +#define TARGET_HARD_REGNO_MODE_OK sparc_hard_regno_mode_ok + struct gcc_target targetm = TARGET_INITIALIZER; /* Return the memory reference contained in X if any, zero otherwise. */ @@ -4974,7 +4979,7 @@ enum sparc_mode_class { registers can hold double-word quantities in 32-bit mode. */ /* This points to either the 32-bit or the 64-bit version. */ -const int *hard_regno_mode_classes; +static const int *hard_regno_mode_classes; static const int hard_32bit_mode_classes[] = { S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, @@ -5026,7 +5031,7 @@ static const int hard_64bit_mode_classes[] = { CC_MODES, 0, D_MODES }; -int sparc_mode_class [NUM_MACHINE_MODES]; +static int sparc_mode_class [NUM_MACHINE_MODES]; enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; @@ -13122,10 +13127,22 @@ sparc_regmode_natural_size (machine_mode mode) return size; } +/* Implement TARGET_HARD_REGNO_MODE_OK. + + ??? Because of the funny way we pass parameters we should allow certain + ??? types of float/complex values to be in integer registers during + ??? RTL generation. This only matters on arch32. */ + +static bool +sparc_hard_regno_mode_ok (unsigned int regno, machine_mode mode) +{ + return (hard_regno_mode_classes[regno] & sparc_mode_class[mode]) != 0; +} + /* Return TRUE if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. - If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, - for any hard reg, then this must be FALSE for correct output. + If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1 + and MODE2, for any hard reg, then this must be FALSE for correct output. For V9 we have to deal with the fact that only the lower 32 floating point registers are 32-bit addressable. */ |