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-rw-r--r--gcc/config/s390/s390.md154
1 files changed, 77 insertions, 77 deletions
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 39e9aba..ef73692 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -158,10 +158,10 @@
(define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
cs,vs,store,idiv,
imulhi,imulsi,imuldi,
- branch,jsr,fsimpd,fsimps,
- floadd,floads,fstored, fstores,
- fmuld,fmuls,fdivd,fdivs,
- ftoi,itof,fsqrtd,fsqrts,
+ branch,jsr,fsimpdf,fsimpsf,
+ floaddf,floadsf,fstoredf,fstoresf,
+ fmuldf,fmulsf,fdivdf,fdivsf,
+ ftoi,itof,fsqrtdf,fsqrtsf,
other"
(cond [(eq_attr "op_type" "NN") (const_string "other")
(eq_attr "op_type" "SS") (const_string "cs")]
@@ -701,7 +701,7 @@
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ltdbr\t%0,%0"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
+ (set_attr "type" "fsimpdf")])
(define_insn "*cmpdf_ccs_0_ibm"
[(set (reg 33)
@@ -710,7 +710,7 @@
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"ltdr\t%0,%0"
[(set_attr "op_type" "RR")
- (set_attr "type" "fsimpd")])
+ (set_attr "type" "fsimpdf")])
(define_insn "*cmpdf_ccs"
[(set (reg 33)
@@ -721,7 +721,7 @@
cdbr\t%0,%1
cdb\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd")])
+ (set_attr "type" "fsimpdf")])
(define_insn "*cmpdf_ccs_ibm"
[(set (reg 33)
@@ -732,7 +732,7 @@
cdr\t%0,%1
cd\t%0,%1"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimpd")])
+ (set_attr "type" "fsimpdf")])
; SF instructions
@@ -744,7 +744,7 @@
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ltebr\t%0,%0"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimpsf")])
(define_insn "*cmpsf_ccs_0_ibm"
[(set (reg 33)
@@ -753,7 +753,7 @@
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lter\t%0,%0"
[(set_attr "op_type" "RR")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimpsf")])
(define_insn "*cmpsf_ccs"
[(set (reg 33)
@@ -764,7 +764,7 @@
cebr\t%0,%1
ceb\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimpsf")])
(define_insn "*cmpsf_ccs"
[(set (reg 33)
@@ -775,7 +775,7 @@
cer\t%0,%1
ce\t%0,%1"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimpsf")])
;;
@@ -904,7 +904,7 @@
[(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
(set_attr "type" "*,*,*,*,*,la,lr,load,store,
- floadd,floadd,floadd,fstored,fstored,*,*,*,*,*")])
+ floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
@@ -955,7 +955,7 @@
stdy\t%1,%0
#"
[(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS")
- (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,*")])
+ (set_attr "type" "lm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
@@ -1119,7 +1119,7 @@
[(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,
RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
(set_attr "type" "*,*,*,la,lr,load,load,store,store,
- floads,floads,floads,fstores,fstores,*,*,*,*,*")])
+ floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
(define_insn "*movsi_esa"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
@@ -1139,7 +1139,7 @@
lam\t%0,%0,%S1
#"
[(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
- (set_attr "type" "*,lr,load,store,floads,floads,fstores,*,*,*,*,*")])
+ (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
@@ -1396,7 +1396,7 @@
stg\t%1,%0
#"
[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
- (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,*")])
+ (set_attr "type" "floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
(define_insn "*movdf_31"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
@@ -1414,7 +1414,7 @@
#
#"
[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
- (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,*")])
+ (set_attr "type" "floaddf,floaddf,floaddf,fstoredf,fstoredf,lm,stm,*,*,*")])
(define_split
[(set (match_operand:DF 0 "nonimmediate_operand" "")
@@ -1491,7 +1491,7 @@
sty\t%1,%0
#"
[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
- (set_attr "type" "floads,floads,floads,fstores,fstores,
+ (set_attr "type" "floadsf,floadsf,floadsf,fstoresf,fstoresf,
lr,load,load,store,store,*")])
;
@@ -3074,7 +3074,7 @@
ler\t%0,%1
le\t%0,%1"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "floads,floads")])
+ (set_attr "type" "floadsf")])
;
; extendsfdf2 instruction pattern(s).
@@ -3100,7 +3100,7 @@
ldebr\t%0,%1
ldeb\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "floads,floads")])
+ (set_attr "type" "floadsf")])
(define_insn "extendsfdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
@@ -3111,7 +3111,7 @@
sdr\t%0,%0\;ler\t%0,%1
sdr\t%0,%0\;le\t%0,%1"
[(set_attr "length" "4,6")
- (set_attr "type" "floads,floads")])
+ (set_attr "type" "floadsf")])
;;
@@ -3536,7 +3536,7 @@
adbr\t%0,%2
adb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd,fsimpd")])
+ (set_attr "type" "fsimpdf")])
(define_insn "*adddf3_cc"
[(set (reg 33)
@@ -3550,7 +3550,7 @@
adbr\t%0,%2
adb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd,fsimpd")])
+ (set_attr "type" "fsimpdf")])
(define_insn "*adddf3_cconly"
[(set (reg 33)
@@ -3563,7 +3563,7 @@
adbr\t%0,%2
adb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd,fsimpd")])
+ (set_attr "type" "fsimpdf")])
(define_insn "*adddf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
@@ -3575,7 +3575,7 @@
adr\t%0,%2
ad\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimpd,fsimpd")])
+ (set_attr "type" "fsimpdf")])
;
; addsf3 instruction pattern(s).
@@ -3600,7 +3600,7 @@
aebr\t%0,%2
aeb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps,fsimps")])
+ (set_attr "type" "fsimpsf")])
(define_insn "*addsf3_cc"
[(set (reg 33)
@@ -3614,7 +3614,7 @@
aebr\t%0,%2
aeb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps,fsimps")])
+ (set_attr "type" "fsimpsf")])
(define_insn "*addsf3_cconly"
[(set (reg 33)
@@ -3627,9 +3627,9 @@
aebr\t%0,%2
aeb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps,fsimps")])
+ (set_attr "type" "fsimpsf")])
-(define_insn "*addsf3"
+(define_insn "*addsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
(match_operand:SF 2 "general_operand" "f,R")))
@@ -3639,7 +3639,7 @@
aer\t%0,%2
ae\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimps,fsimps")])
+ (set_attr "type" "fsimpsf")])
;;
@@ -4004,7 +4004,7 @@
sdbr\t%0,%2
sdb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd,fsimpd")])
+ (set_attr "type" "fsimpdf")])
(define_insn "*subdf3_cc"
[(set (reg 33)
@@ -4018,7 +4018,7 @@
sdbr\t%0,%2
sdb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd,fsimpd")])
+ (set_attr "type" "fsimpdf")])
(define_insn "*subdf3_cconly"
[(set (reg 33)
@@ -4031,7 +4031,7 @@
sdbr\t%0,%2
sdb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd,fsimpd")])
+ (set_attr "type" "fsimpdf")])
(define_insn "*subdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
@@ -4043,7 +4043,7 @@
sdr\t%0,%2
sd\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimpd,fsimpd")])
+ (set_attr "type" "fsimpdf")])
;
; subsf3 instruction pattern(s).
@@ -4068,7 +4068,7 @@
sebr\t%0,%2
seb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps,fsimps")])
+ (set_attr "type" "fsimpsf")])
(define_insn "*subsf3_cc"
[(set (reg 33)
@@ -4082,7 +4082,7 @@
sebr\t%0,%2
seb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps,fsimps")])
+ (set_attr "type" "fsimpsf")])
(define_insn "*subsf3_cconly"
[(set (reg 33)
@@ -4095,7 +4095,7 @@
sebr\t%0,%2
seb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps,fsimps")])
+ (set_attr "type" "fsimpsf")])
(define_insn "*subsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
@@ -4107,7 +4107,7 @@
ser\t%0,%2
se\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimps,fsimps")])
+ (set_attr "type" "fsimpsf")])
;;
@@ -4339,7 +4339,7 @@
mdbr\t%0,%2
mdb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmuld")])
+ (set_attr "type" "fmuldf")])
(define_insn "*muldf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
@@ -4350,7 +4350,7 @@
mdr\t%0,%2
md\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fmuld")])
+ (set_attr "type" "fmuldf")])
(define_insn "*fmadddf"
[(set (match_operand:DF 0 "register_operand" "=f,f")
@@ -4362,7 +4362,7 @@
madbr\t%0,%1,%2
madb\t%0,%1,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmuld")])
+ (set_attr "type" "fmuldf")])
(define_insn "*fmsubdf"
[(set (match_operand:DF 0 "register_operand" "=f,f")
@@ -4374,7 +4374,7 @@
msdbr\t%0,%1,%2
msdb\t%0,%1,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmuld")])
+ (set_attr "type" "fmuldf")])
;
; mulsf3 instruction pattern(s).
@@ -4396,7 +4396,7 @@
meebr\t%0,%2
meeb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmuls")])
+ (set_attr "type" "fmulsf")])
(define_insn "*mulsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
@@ -4407,7 +4407,7 @@
mer\t%0,%2
me\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fmuls")])
+ (set_attr "type" "fmulsf")])
(define_insn "*fmaddsf"
[(set (match_operand:SF 0 "register_operand" "=f,f")
@@ -4419,7 +4419,7 @@
maebr\t%0,%1,%2
maeb\t%0,%1,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmuls")])
+ (set_attr "type" "fmulsf")])
(define_insn "*fmsubsf"
[(set (match_operand:SF 0 "register_operand" "=f,f")
@@ -4431,7 +4431,7 @@
msebr\t%0,%1,%2
mseb\t%0,%1,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmuls")])
+ (set_attr "type" "fmulsf")])
;;
;;- Divide and modulo instructions.
@@ -4889,7 +4889,7 @@
ddbr\t%0,%2
ddb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fdivd")])
+ (set_attr "type" "fdivdf")])
(define_insn "*divdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
@@ -4900,7 +4900,7 @@
ddr\t%0,%2
dd\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fdivd")])
+ (set_attr "type" "fdivdf")])
;
; divsf3 instruction pattern(s).
@@ -4922,9 +4922,9 @@
debr\t%0,%2
deb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fdivs")])
+ (set_attr "type" "fdivsf")])
-(define_insn "*divsf3"
+(define_insn "*divsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 1 "register_operand" "0,0")
(match_operand:SF 2 "general_operand" "f,R")))]
@@ -4933,7 +4933,7 @@
der\t%0,%2
de\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fdivs")])
+ (set_attr "type" "fdivsf")])
;;
@@ -5913,7 +5913,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcdbr\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
+ (set_attr "type" "fsimpdf")])
(define_insn "*negdf2_cconly"
[(set (reg 33)
@@ -5923,7 +5923,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcdbr\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
+ (set_attr "type" "fsimpdf")])
(define_insn "*negdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
@@ -5932,7 +5932,7 @@
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcdbr\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
+ (set_attr "type" "fsimpdf")])
(define_insn "*negdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f")
@@ -5941,7 +5941,7 @@
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lcdr\t%0,%1"
[(set_attr "op_type" "RR")
- (set_attr "type" "fsimpd")])
+ (set_attr "type" "fsimpdf")])
;
; negsf2 instruction pattern(s).
@@ -5964,7 +5964,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcebr\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimpsf")])
(define_insn "*negsf2_cconly"
[(set (reg 33)
@@ -5974,7 +5974,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcebr\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimpsf")])
(define_insn "*negsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
@@ -5983,16 +5983,16 @@
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcebr\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimpsf")])
-(define_insn "*negsf2"
+(define_insn "*negsf2_ibm"
[(set (match_operand:SF 0 "register_operand" "=f")
(neg:SF (match_operand:SF 1 "register_operand" "f")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lcer\t%0,%1"
[(set_attr "op_type" "RR")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimpsf")])
;;
@@ -6071,7 +6071,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpdbr\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
+ (set_attr "type" "fsimpdf")])
(define_insn "*absdf2_cconly"
[(set (reg 33)
@@ -6081,7 +6081,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpdbr\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
+ (set_attr "type" "fsimpdf")])
(define_insn "*absdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
@@ -6090,7 +6090,7 @@
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpdbr\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
+ (set_attr "type" "fsimpdf")])
(define_insn "*absdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f")
@@ -6099,7 +6099,7 @@
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lpdr\t%0,%1"
[(set_attr "op_type" "RR")
- (set_attr "type" "fsimpd")])
+ (set_attr "type" "fsimpdf")])
;
; abssf2 instruction pattern(s).
@@ -6122,7 +6122,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpebr\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimpsf")])
(define_insn "*abssf2_cconly"
[(set (reg 33)
@@ -6132,7 +6132,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpebr\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimpsf")])
(define_insn "*abssf2"
[(set (match_operand:SF 0 "register_operand" "=f")
@@ -6141,7 +6141,7 @@
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpebr\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimpsf")])
(define_insn "*abssf2_ibm"
[(set (match_operand:SF 0 "register_operand" "=f")
@@ -6150,7 +6150,7 @@
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lper\t%0,%1"
[(set_attr "op_type" "RR")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimpsf")])
;;
;;- Negated absolute value instructions
@@ -6221,7 +6221,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lndbr\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
+ (set_attr "type" "fsimpdf")])
(define_insn "*negabsdf2_cconly"
[(set (reg 33)
@@ -6231,7 +6231,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lndbr\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
+ (set_attr "type" "fsimpdf")])
(define_insn "*negabsdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
@@ -6240,7 +6240,7 @@
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lndbr\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
+ (set_attr "type" "fsimpdf")])
(define_insn "*negabssf2_cc"
[(set (reg 33)
@@ -6251,7 +6251,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lnebr\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimpsf")])
(define_insn "*negabssf2_cconly"
[(set (reg 33)
@@ -6261,7 +6261,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lnebr\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimpsf")])
(define_insn "*negabssf2"
[(set (match_operand:SF 0 "register_operand" "=f")
@@ -6270,7 +6270,7 @@
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lnebr\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimpsf")])
;;
;;- Square root instructions.
@@ -6288,7 +6288,7 @@
sqdbr\t%0,%1
sqdb\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsqrtd")])
+ (set_attr "type" "fsqrtdf")])
;
; sqrtsf2 instruction pattern(s).
@@ -6302,7 +6302,7 @@
sqebr\t%0,%1
sqeb\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsqrts")])
+ (set_attr "type" "fsqrtsf")])
;;
;;- One complement instructions.
generated by cgit v1.1 at 2026-01-01 11:44:11 +0000