diff options
Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 450 |
1 files changed, 256 insertions, 194 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index ef50cd1..a8a5a95 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -37,7 +37,7 @@ ;; Define an insn type attribute. This is used in function unit delay ;; computations. -(define_attr "type" "integer,load,store,fpload,fpstore,imul,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,altivec" +(define_attr "type" "integer,load,store,fpload,fpstore,vecload,vecstore,imul,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,vecsimple,veccomplex,veccmp,vecperm,vecfloat,altivec" (const_string "integer")) ;; Length (in bytes). @@ -70,7 +70,7 @@ 2 1) (define_function_unit "lsu" 1 0 - (and (eq_attr "type" "load") + (and (eq_attr "type" "load,vecload") (eq_attr "cpu" "ppc7450")) 3 1) @@ -85,7 +85,7 @@ 2 1) (define_function_unit "lsu" 1 0 - (and (eq_attr "type" "store") + (and (eq_attr "type" "store,vecstore") (eq_attr "cpu" "ppc7450")) 3 1) @@ -317,6 +317,26 @@ (and (eq_attr "type" "cr_logical") (eq_attr "cpu" "ppc7450")) 1 1) +(define_function_unit "viu1" 1 0 + (and (eq_attr "type" "vecsimple") + (eq_attr "cpu" "ppc7450")) + 1 1) +(define_function_unit "viu2" 1 0 + (and (eq_attr "type" "veccomplex") + (eq_attr "cpu" "ppc7450")) + 4 1) +(define_function_unit "vfpu" 1 0 + (and (eq_attr "type" "veccmp") + (eq_attr "cpu" "ppc7450")) + 2 1) +(define_function_unit "vfpu" 1 0 + (and (eq_attr "type" "vecfloat") + (eq_attr "cpu" "ppc7450")) + 4 1) +(define_function_unit "vpu" 1 0 + (and (eq_attr "type" "vecperm") + (eq_attr "cpu" "ppc7450")) + 2 1) ; PPC750 has two integer units: a primary one which can perform all ; operations and a secondary one which is fed in lock step with the first @@ -13559,20 +13579,62 @@ ;; AltiVec patterns ;; Generic LVX load instruction. -(define_insn "altivec_lvx" +(define_insn "altivec_lvx_4si" [(set (match_operand:V4SI 0 "register_operand" "=v") (match_operand:V4SI 1 "memory_operand" "m"))] "TARGET_ALTIVEC" "lvx %0,%y1" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecload")]) + +(define_insn "altivec_lvx_8hi" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (match_operand:V8HI 1 "memory_operand" "m"))] + "TARGET_ALTIVEC" + "lvx %0,%y1" + [(set_attr "type" "vecload")]) + +(define_insn "altivec_lvx_16qi" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (match_operand:V16QI 1 "memory_operand" "m"))] + "TARGET_ALTIVEC" + "lvx %0,%y1" + [(set_attr "type" "vecload")]) + +(define_insn "altivec_lvx_4sf" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (match_operand:V4SF 1 "memory_operand" "m"))] + "TARGET_ALTIVEC" + "lvx %0,%y1" + [(set_attr "type" "vecload")]) ;; Generic STVX store instruction. -(define_insn "altivec_stvx" +(define_insn "altivec_stvx_4si" [(set (match_operand:V4SI 0 "memory_operand" "=m") (match_operand:V4SI 1 "register_operand" "v"))] "TARGET_ALTIVEC" "stvx %1,%y0" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecstore")]) + +(define_insn "altivec_stvx_8hi" + [(set (match_operand:V8HI 0 "memory_operand" "=m") + (match_operand:V8HI 1 "register_operand" "v"))] + "TARGET_ALTIVEC" + "stvx %1,%y0" + [(set_attr "type" "vecstore")]) + +(define_insn "altivec_stvx_16qi" + [(set (match_operand:V16QI 0 "memory_operand" "=m") + (match_operand:V16QI 1 "register_operand" "v"))] + "TARGET_ALTIVEC" + "stvx %1,%y0" + [(set_attr "type" "vecstore")]) + +(define_insn "altivec_stvx_4sf" + [(set (match_operand:V4SF 0 "memory_operand" "=m") + (match_operand:V4SF 1 "register_operand" "v"))] + "TARGET_ALTIVEC" + "stvx %1,%y0" + [(set_attr "type" "vecstore")]) ;; Vector move instructions. (define_expand "movv4si" @@ -13666,37 +13728,37 @@ ;; Simple binary operations. -(define_insn "altivec_vaddubm" +(define_insn "addv16qi3" [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 31))] + (plus:V16QI (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vaddubm %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vadduhm" +(define_insn "addv8hi3" [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 32))] + (plus:V8HI (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vadduhm %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vadduwm" +(define_insn "addv4si3" [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 33))] + (plus:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vadduwm %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vaddfp" +(define_insn "addv4sf3" [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v")] 34))] + (plus:V4SF (match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vaddfp %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecfloat")]) (define_insn "altivec_vaddcuw" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -13704,7 +13766,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 35))] "TARGET_ALTIVEC" "vaddcuw %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vaddubs" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -13712,7 +13774,7 @@ (match_operand:V16QI 2 "register_operand" "v")] 36))] "TARGET_ALTIVEC" "vaddubs %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vaddsbs" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -13720,7 +13782,7 @@ (match_operand:V16QI 2 "register_operand" "v")] 37))] "TARGET_ALTIVEC" "vaddsbs %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vadduhs" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -13728,7 +13790,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 38))] "TARGET_ALTIVEC" "vadduhs %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vaddshs" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -13736,7 +13798,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 39))] "TARGET_ALTIVEC" "vaddshs %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vadduws" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -13744,7 +13806,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 40))] "TARGET_ALTIVEC" "vadduws %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vaddsws" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -13752,15 +13814,15 @@ (match_operand:V4SI 2 "register_operand" "v")] 41))] "TARGET_ALTIVEC" "vaddsws %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vand" +(define_insn "andv4si3" [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 42))] + (and:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vand %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vandc" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -13768,7 +13830,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 43))] "TARGET_ALTIVEC" "vandc %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vavgub" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -13776,7 +13838,7 @@ (match_operand:V16QI 2 "register_operand" "v")] 44))] "TARGET_ALTIVEC" "vavgub %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vavgsb" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -13784,7 +13846,7 @@ (match_operand:V16QI 2 "register_operand" "v")] 45))] "TARGET_ALTIVEC" "vavgsb %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vavguh" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -13792,7 +13854,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 46))] "TARGET_ALTIVEC" "vavguh %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vavgsh" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -13800,7 +13862,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 47))] "TARGET_ALTIVEC" "vavgsh %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vavguw" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -13808,7 +13870,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 48))] "TARGET_ALTIVEC" "vavguw %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vavgsw" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -13816,7 +13878,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 49))] "TARGET_ALTIVEC" "vavgsw %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vcmpbfp" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -13824,7 +13886,7 @@ (match_operand:V4SF 2 "register_operand" "v")] 50))] "TARGET_ALTIVEC" "vcmpbfp %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccmp")]) (define_insn "altivec_vcmpequb" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -13832,7 +13894,7 @@ (match_operand:V16QI 2 "register_operand" "v")] 51))] "TARGET_ALTIVEC" "vcmpequb %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vcmpequh" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -13840,7 +13902,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 52))] "TARGET_ALTIVEC" "vcmpequh %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vcmpequw" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -13848,7 +13910,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 53))] "TARGET_ALTIVEC" "vcmpequw %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vcmpeqfp" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -13856,7 +13918,7 @@ (match_operand:V4SF 2 "register_operand" "v")] 54))] "TARGET_ALTIVEC" "vcmpeqfp %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccmp")]) (define_insn "altivec_vcmpgefp" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -13864,7 +13926,7 @@ (match_operand:V4SF 2 "register_operand" "v")] 55))] "TARGET_ALTIVEC" "vcmpgefp %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccmp")]) (define_insn "altivec_vcmpgtub" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -13872,7 +13934,7 @@ (match_operand:V16QI 2 "register_operand" "v")] 56))] "TARGET_ALTIVEC" "vcmpgtub %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vcmpgtsb" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -13880,7 +13942,7 @@ (match_operand:V16QI 2 "register_operand" "v")] 57))] "TARGET_ALTIVEC" "vcmpgtsb %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vcmpgtuh" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -13888,7 +13950,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 58))] "TARGET_ALTIVEC" "vcmpgtuh %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vcmpgtsh" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -13896,7 +13958,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 59))] "TARGET_ALTIVEC" "vcmpgtsh %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vcmpgtuw" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -13904,7 +13966,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 60))] "TARGET_ALTIVEC" "vcmpgtuw %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vcmpgtsw" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -13912,7 +13974,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 61))] "TARGET_ALTIVEC" "vcmpgtsw %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vcmpgtfp" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -13920,63 +13982,63 @@ (match_operand:V4SF 2 "register_operand" "v")] 62))] "TARGET_ALTIVEC" "vcmpgtfp %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccmp")]) -(define_insn "altivec_vmaxub" +(define_insn "umaxv16qi3" [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 63))] + (umax:V16QI (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vmaxub %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vmaxsb" +(define_insn "smaxv16qi3" [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 64))] + (smax:V16QI (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vmaxsb %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vmaxuh" +(define_insn "umaxv8hi3" [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 65))] + (umax:V8HI (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vmaxuh %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vmaxsh" +(define_insn "smaxv8hi3" [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 66))] + (smax:V8HI (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vmaxsh %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vmaxuw" +(define_insn "umaxv4si3" [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 67))] + (umax:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vmaxuw %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vmaxsw" +(define_insn "smaxv4si3" [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 68))] + (smax:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vmaxsw %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vmaxfp" +(define_insn "smaxv4sf3" [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v")] 69))] + (smax:V4SF (match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vmaxfp %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccmp")]) (define_insn "altivec_vmrghb" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -13984,7 +14046,7 @@ (match_operand:V16QI 2 "register_operand" "v")] 70))] "TARGET_ALTIVEC" "vmrghb %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vmrghh" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -13992,7 +14054,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 71))] "TARGET_ALTIVEC" "vmrghh %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vmrghw" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14000,7 +14062,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 72))] "TARGET_ALTIVEC" "vmrghw %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vmrglb" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -14008,7 +14070,7 @@ (match_operand:V16QI 2 "register_operand" "v")] 73))] "TARGET_ALTIVEC" "vmrglb %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vmrglh" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -14016,7 +14078,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 74))] "TARGET_ALTIVEC" "vmrglh %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vmrglw" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14024,63 +14086,63 @@ (match_operand:V4SI 2 "register_operand" "v")] 75))] "TARGET_ALTIVEC" "vmrglw %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) -(define_insn "altivec_vminub" +(define_insn "uminv16qi3" [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 76))] + (umin:V16QI (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vminub %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vminsb" +(define_insn "sminv16qi3" [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 77))] + (smin:V16QI (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vminsb %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vminuh" +(define_insn "uminv8hi3" [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 78))] + (umin:V8HI (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vminuh %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vminsh" +(define_insn "sminv8hi3" [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 79))] + (smin:V8HI (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vminsh %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vminuw" +(define_insn "uminv4si3" [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 80))] + (umin:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vminuw %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vminsw" +(define_insn "sminv4si3" [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 81))] + (smin:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vminsw %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vminfp" +(define_insn "sminv4sf3" [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v")] 82))] + (smin:V4SF (match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vminfp %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccmp")]) (define_insn "altivec_vmuleub" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -14088,7 +14150,7 @@ (match_operand:V16QI 2 "register_operand" "v")] 83))] "TARGET_ALTIVEC" "vmuleub %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccomplex")]) (define_insn "altivec_vmulesb" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -14096,7 +14158,7 @@ (match_operand:V16QI 2 "register_operand" "v")] 84))] "TARGET_ALTIVEC" "vmulesb %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccomplex")]) (define_insn "altivec_vmuleuh" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14104,7 +14166,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 85))] "TARGET_ALTIVEC" "vmuleuh %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccomplex")]) (define_insn "altivec_vmulesh" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14112,7 +14174,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 86))] "TARGET_ALTIVEC" "vmulesh %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccomplex")]) (define_insn "altivec_vmuloub" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -14120,7 +14182,7 @@ (match_operand:V16QI 2 "register_operand" "v")] 87))] "TARGET_ALTIVEC" "vmuloub %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccomplex")]) (define_insn "altivec_vmulosb" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -14128,7 +14190,7 @@ (match_operand:V16QI 2 "register_operand" "v")] 88))] "TARGET_ALTIVEC" "vmulosb %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccomplex")]) (define_insn "altivec_vmulouh" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14136,7 +14198,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 89))] "TARGET_ALTIVEC" "vmulouh %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccomplex")]) (define_insn "altivec_vmulosh" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14144,23 +14206,23 @@ (match_operand:V8HI 2 "register_operand" "v")] 90))] "TARGET_ALTIVEC" "vmulosh %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccomplex")]) (define_insn "altivec_vnor" [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 91))] + (not:V4SI (ior:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v"))))] "TARGET_ALTIVEC" "vnor %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vor" +(define_insn "iorv4si3" [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 92))] + (ior:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vor %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vpkuhum" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -14168,7 +14230,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 93))] "TARGET_ALTIVEC" "vpkuhum %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vpkuwum" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -14176,7 +14238,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 94))] "TARGET_ALTIVEC" "vpkuwum %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vpkpx" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -14184,7 +14246,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 95))] "TARGET_ALTIVEC" "vpkpx %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vpkuhss" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -14192,7 +14254,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 96))] "TARGET_ALTIVEC" "vpkuhss %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vpkshss" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -14200,7 +14262,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 97))] "TARGET_ALTIVEC" "vpkshss %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vpkuwss" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -14208,7 +14270,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 98))] "TARGET_ALTIVEC" "vpkuwss %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vpkswss" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -14216,7 +14278,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 99))] "TARGET_ALTIVEC" "vpkswss %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vpkuhus" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -14224,7 +14286,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 100))] "TARGET_ALTIVEC" "vpkuhus %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vpkshus" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -14232,7 +14294,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 101))] "TARGET_ALTIVEC" "vpkshus %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vpkuwus" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -14240,7 +14302,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 102))] "TARGET_ALTIVEC" "vpkuwus %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vpkswus" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -14248,7 +14310,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 103))] "TARGET_ALTIVEC" "vpkswus %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vrlb" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -14256,7 +14318,7 @@ (match_operand:V16QI 2 "register_operand" "v")] 104))] "TARGET_ALTIVEC" "vrlb %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vrlh" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -14264,7 +14326,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 105))] "TARGET_ALTIVEC" "vrlh %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vrlw" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14272,7 +14334,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 106))] "TARGET_ALTIVEC" "vrlw %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vslb" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -14280,7 +14342,7 @@ (match_operand:V16QI 2 "register_operand" "v")] 107))] "TARGET_ALTIVEC" "vslb %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vslh" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -14288,7 +14350,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 108))] "TARGET_ALTIVEC" "vslh %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vslw" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14296,7 +14358,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 109))] "TARGET_ALTIVEC" "vslw %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vsl" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14304,7 +14366,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 110))] "TARGET_ALTIVEC" "vsl %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vslo" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14312,7 +14374,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 111))] "TARGET_ALTIVEC" "vslo %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vsrb" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -14320,23 +14382,23 @@ (match_operand:V16QI 2 "register_operand" "v")] 112))] "TARGET_ALTIVEC" "vsrb %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vrsh" +(define_insn "altivec_vsrh" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") (match_operand:V8HI 2 "register_operand" "v")] 113))] "TARGET_ALTIVEC" - "vrsh %0,%1,%2" - [(set_attr "type" "altivec")]) + "vsrh %0,%1,%2" + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vrsw" +(define_insn "altivec_vsrw" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] 114))] "TARGET_ALTIVEC" - "vrsw %0,%1,%2" - [(set_attr "type" "altivec")]) + "vsrw %0,%1,%2" + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vsrab" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -14344,7 +14406,7 @@ (match_operand:V16QI 2 "register_operand" "v")] 115))] "TARGET_ALTIVEC" "vsrab %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vsrah" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -14352,7 +14414,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 116))] "TARGET_ALTIVEC" "vsrah %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vsraw" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14360,7 +14422,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 117))] "TARGET_ALTIVEC" "vsraw %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vsr" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14368,7 +14430,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 118))] "TARGET_ALTIVEC" "vsr %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) (define_insn "altivec_vsro" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14376,39 +14438,39 @@ (match_operand:V4SI 2 "register_operand" "v")] 119))] "TARGET_ALTIVEC" "vsro %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecperm")]) -(define_insn "altivec_vsububm" +(define_insn "subv16qi3" [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 120))] + (minus:V16QI (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vsububm %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vsubuhm" +(define_insn "subv8hi3" [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 121))] + (minus:V8HI (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vsubuhm %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vsubuwm" +(define_insn "subv4si3" [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 122))] + (minus:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vsubuwm %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vsubfp" +(define_insn "subv4sf3" [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v")] 123))] + (minus:V4SF (match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vsubfp %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecfloat")]) (define_insn "altivec_vsubcuw" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14416,7 +14478,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 124))] "TARGET_ALTIVEC" "vsubcuw %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vsububs" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -14424,7 +14486,7 @@ (match_operand:V16QI 2 "register_operand" "v")] 125))] "TARGET_ALTIVEC" "vsububs %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vsubsbs" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -14432,7 +14494,7 @@ (match_operand:V16QI 2 "register_operand" "v")] 126))] "TARGET_ALTIVEC" "vsubsbs %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vsubuhs" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -14440,7 +14502,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 127))] "TARGET_ALTIVEC" "vsubuhs %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vsubshs" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -14448,7 +14510,7 @@ (match_operand:V8HI 2 "register_operand" "v")] 128))] "TARGET_ALTIVEC" "vsubshs %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vsubuws" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14456,7 +14518,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 129))] "TARGET_ALTIVEC" "vsubuws %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vsubsws" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14464,7 +14526,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 130))] "TARGET_ALTIVEC" "vsubsws %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) (define_insn "altivec_vsum4ubs" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14472,7 +14534,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 131))] "TARGET_ALTIVEC" "vsum4ubs %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccomplex")]) (define_insn "altivec_vsum4sbs" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14480,7 +14542,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 132))] "TARGET_ALTIVEC" "vsum4sbs %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccomplex")]) (define_insn "altivec_vsum4shs" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14488,7 +14550,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 133))] "TARGET_ALTIVEC" "vsum4shs %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccomplex")]) (define_insn "altivec_vsum2sws" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14496,7 +14558,7 @@ (match_operand:V4SI 2 "register_operand" "v")] 134))] "TARGET_ALTIVEC" "vsum2sws %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccomplex")]) (define_insn "altivec_vsumsws" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -14504,12 +14566,12 @@ (match_operand:V4SI 2 "register_operand" "v")] 135))] "TARGET_ALTIVEC" "vsumsws %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "veccomplex")]) -(define_insn "altivec_vxor" +(define_insn "xorv4si3" [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 136))] + (xor:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] "TARGET_ALTIVEC" "vxor %0,%1,%2" - [(set_attr "type" "altivec")]) + [(set_attr "type" "vecsimple")]) |