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Diffstat (limited to 'gcc/config/rs6000/constraints.md')
| -rw-r--r-- | gcc/config/rs6000/constraints.md | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index a3abe6a..ef8f617 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -140,6 +140,10 @@ (and (match_code "const_int") (match_test "TARGET_VSX && (ival == VECTOR_ELEMENT_SCALAR_64BIT)"))) +(define_constraint "wE" + "Vector constant that can be loaded with the XXSPLTIB instruction." + (match_test "xxspltib_constant_nosplit (op, mode)")) + ;; Extended fusion store (define_memory_constraint "wF" "Memory operand suitable for power9 fusion load/stores" @@ -156,6 +160,12 @@ (and (match_test "TARGET_DIRECT_MOVE_128") (match_test "(ival == VECTOR_ELEMENT_MFVSRLD_64BIT)")))) +;; Generate the XXORC instruction to set a register to all 1's +(define_constraint "wM" + "Match vector constant with all 1's if the XXLORC instruction is available" + (and (match_test "TARGET_P8_VECTOR") + (match_operand 0 "all_ones_constant"))) + ;; ISA 3.0 vector d-form addresses (define_memory_constraint "wO" "Memory operand suitable for the ISA 3.0 vector d-form instructions." @@ -166,6 +176,10 @@ "Memory operand suitable for the load/store quad instructions" (match_operand 0 "quad_memory_operand")) +(define_constraint "wS" + "Vector constant that can be loaded with XXSPLTIB & sign extension." + (match_test "xxspltib_constant_split (op, mode)")) + ;; Altivec style load/store that ignores the bottom bits of the address (define_memory_constraint "wZ" "Indexed or indirect memory operand, ignoring the bottom 4 bits" |