diff options
Diffstat (limited to 'gcc/config/ia64/itanium2.md')
| -rw-r--r-- | gcc/config/ia64/itanium2.md | 134 |
1 files changed, 111 insertions, 23 deletions
diff --git a/gcc/config/ia64/itanium2.md b/gcc/config/ia64/itanium2.md index f16d185..a10971d 100644 --- a/gcc/config/ia64/itanium2.md +++ b/gcc/config/ia64/itanium2.md @@ -731,14 +731,38 @@ (eq_attr "itanium_class" "fcvtfx")) (eq (symbol_ref "bundling_p") (const_int 0))) "2_F") (define_insn_reservation "2_fld" 6 - (and (and (eq_attr "cpu" "itanium2") - (eq_attr "itanium_class" "fld")) - (eq (symbol_ref "bundling_p") (const_int 0))) "2_M") + (and (and (and (and (eq_attr "cpu" "itanium2") + (eq_attr "itanium_class" "fld")) + (eq_attr "data_speculative" "no")) + (eq_attr "check_load" "no")) + (eq (symbol_ref "bundling_p") (const_int 0))) + "2_M") +(define_insn_reservation "2_flda" 6 + (and (and (and (eq_attr "cpu" "itanium2") + (eq_attr "itanium_class" "fld")) + (eq_attr "data_speculative" "yes")) + (eq (symbol_ref "bundling_p") (const_int 0))) + "2_M_only_um01") +(define_insn_reservation "2_fldc" 0 + (and (and (and (eq_attr "cpu" "itanium2") + (eq_attr "itanium_class" "fld")) + (eq_attr "check_load" "yes")) + (eq (symbol_ref "bundling_p") (const_int 0))) + "2_M_only_um01") + (define_insn_reservation "2_fldp" 6 - (and (and (eq_attr "cpu" "itanium2") - (eq_attr "itanium_class" "fldp")) + (and (and (and (eq_attr "cpu" "itanium2") + (eq_attr "itanium_class" "fldp")) + (eq_attr "check_load" "no")) + (eq (symbol_ref "bundling_p") (const_int 0))) + "2_M_only_um01") +(define_insn_reservation "2_fldpc" 0 + (and (and (and (eq_attr "cpu" "itanium2") + (eq_attr "itanium_class" "fldp")) + (eq_attr "check_load" "yes")) (eq (symbol_ref "bundling_p") (const_int 0))) "2_M_only_um01") + (define_insn_reservation "2_fmac" 4 (and (and (eq_attr "cpu" "itanium2") (eq_attr "itanium_class" "fmac")) @@ -801,11 +825,19 @@ (eq_attr "itanium_class" "ishf")) (eq (symbol_ref "bundling_p") (const_int 0))) "2_I+2_only_ui0") + (define_insn_reservation "2_ld" 1 + (and (and (and (eq_attr "cpu" "itanium2") + (eq_attr "itanium_class" "ld")) + (eq_attr "check_load" "no")) + (eq (symbol_ref "bundling_p") (const_int 0))) + "2_M_only_um01") +(define_insn_reservation "2_ldc" 0 (and (and (eq_attr "cpu" "itanium2") - (eq_attr "itanium_class" "ld")) + (eq_attr "check_load" "yes")) (eq (symbol_ref "bundling_p") (const_int 0))) "2_M_only_um01") + (define_insn_reservation "2_long_i" 1 (and (and (eq_attr "cpu" "itanium2") (eq_attr "itanium_class" "long_i")) @@ -909,11 +941,22 @@ (eq_attr "itanium_class" "xtd")) (eq (symbol_ref "bundling_p") (const_int 0))) "2_I") -(define_insn_reservation "2_chk_s" 0 +(define_insn_reservation "2_chk_s_i" 0 (and (and (eq_attr "cpu" "itanium2") - (eq_attr "itanium_class" "chk_s")) + (eq_attr "itanium_class" "chk_s_i")) (eq (symbol_ref "bundling_p") (const_int 0))) "2_I|2_M_only_um23") +(define_insn_reservation "2_chk_s_f" 0 + (and (and (eq_attr "cpu" "itanium2") + (eq_attr "itanium_class" "chk_s_f")) + (eq (symbol_ref "bundling_p") (const_int 0))) + "2_M_only_um23") +(define_insn_reservation "2_chk_a" 0 + (and (and (eq_attr "cpu" "itanium2") + (eq_attr "itanium_class" "chk_a")) + (eq (symbol_ref "bundling_p") (const_int 0))) + "2_M_only_um01") + (define_insn_reservation "2_lfetch" 0 (and (and (eq_attr "cpu" "itanium2") (eq_attr "itanium_class" "lfetch")) @@ -1025,23 +1068,23 @@ (define_bypass 0 "2_tbit" "2_br,2_scall") (define_bypass 2 "2_ld" "2_ld" "ia64_ld_address_bypass_p") (define_bypass 2 "2_ld" "2_st" "ia64_st_address_bypass_p") -(define_bypass 2 "2_ld" "2_mmalua,2_mmmul,2_mmshf") +(define_bypass 2 "2_ld,2_ldc" "2_mmalua,2_mmmul,2_mmshf") (define_bypass 3 "2_ilog" "2_mmalua,2_mmmul,2_mmshf") (define_bypass 3 "2_ialu" "2_mmalua,2_mmmul,2_mmshf") -(define_bypass 3 "2_mmalua,2_mmmul,2_mmshf" "2_ialu,2_ilog,2_ishf,2_st,2_ld") +(define_bypass 3 "2_mmalua,2_mmmul,2_mmshf" "2_ialu,2_ilog,2_ishf,2_st,2_ld,2_ldc") (define_bypass 6 "2_tofr" "2_frfr,2_stf") (define_bypass 7 "2_fmac" "2_frfr,2_stf") ;; We don't use here fcmp because scall may be predicated. -(define_bypass 0 "2_fcvtfx,2_fld,2_fmac,2_fmisc,2_frar_i,2_frar_m,\ - 2_frbr,2_frfr,2_frpr,2_ialu,2_ilog,2_ishf,2_ld,2_long_i,\ +(define_bypass 0 "2_fcvtfx,2_fld,2_flda,2_fldc,2_fmac,2_fmisc,2_frar_i,2_frar_m,\ + 2_frbr,2_frfr,2_frpr,2_ialu,2_ilog,2_ishf,2_ld,2_ldc,2_long_i,\ 2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_toar_m,2_tofr,\ 2_xmpy,2_xtd" "2_scall") -(define_bypass 0 "2_unknown,2_ignore,2_stop_bit,2_br,2_fcmp,2_fcvtfx,2_fld,\ +(define_bypass 0 "2_unknown,2_ignore,2_stop_bit,2_br,2_fcmp,2_fcvtfx,2_fld,2_flda,2_fldc,\ 2_fmac,2_fmisc,2_frar_i,2_frar_m,2_frbr,2_frfr,2_frpr,\ - 2_ialu,2_icmp,2_ilog,2_ishf,2_ld,2_chk_s,2_long_i,\ + 2_ialu,2_icmp,2_ilog,2_ishf,2_ld,2_ldc,2_chk_s_i,2_chk_s_f,2_chk_a,2_long_i,\ 2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_nop,2_nop_b,2_nop_f,\ 2_nop_i,2_nop_m,2_nop_x,2_rse_m,2_scall,2_sem,2_stf,2_st,\ 2_syst_m0,2_syst_m,2_tbit,2_toar_i,2_toar_m,2_tobr,2_tofr,\ @@ -1543,14 +1586,38 @@ (eq_attr "itanium_class" "fcvtfx")) (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F") (define_insn_reservation "2b_fld" 6 - (and (and (eq_attr "cpu" "itanium2") - (eq_attr "itanium_class" "fld")) - (ne (symbol_ref "bundling_p") (const_int 0))) "2b_M") + (and (and (and (and (eq_attr "cpu" "itanium2") + (eq_attr "itanium_class" "fld")) + (eq_attr "data_speculative" "no")) + (eq_attr "check_load" "no")) + (ne (symbol_ref "bundling_p") (const_int 0))) + "2b_M") +(define_insn_reservation "2b_flda" 6 + (and (and (and (eq_attr "cpu" "itanium2") + (eq_attr "itanium_class" "fld")) + (eq_attr "data_speculative" "yes")) + (ne (symbol_ref "bundling_p") (const_int 0))) + "2b_M_only_um01") +(define_insn_reservation "2b_fldc" 0 + (and (and (and (eq_attr "cpu" "itanium2") + (eq_attr "itanium_class" "fld")) + (eq_attr "check_load" "yes")) + (ne (symbol_ref "bundling_p") (const_int 0))) + "2b_M_only_um01") + (define_insn_reservation "2b_fldp" 6 - (and (and (eq_attr "cpu" "itanium2") - (eq_attr "itanium_class" "fldp")) + (and (and (and (eq_attr "cpu" "itanium2") + (eq_attr "itanium_class" "fldp")) + (eq_attr "check_load" "no")) + (ne (symbol_ref "bundling_p") (const_int 0))) + "2b_M_only_um01") +(define_insn_reservation "2b_fldpc" 0 + (and (and (and (eq_attr "cpu" "itanium2") + (eq_attr "itanium_class" "fldp")) + (eq_attr "check_load" "yes")) (ne (symbol_ref "bundling_p") (const_int 0))) "2b_M_only_um01") + (define_insn_reservation "2b_fmac" 4 (and (and (eq_attr "cpu" "itanium2") (eq_attr "itanium_class" "fmac")) @@ -1611,11 +1678,20 @@ (eq_attr "itanium_class" "ishf")) (ne (symbol_ref "bundling_p") (const_int 0))) "2b_I+2b_only_ui0") + (define_insn_reservation "2b_ld" 1 - (and (and (eq_attr "cpu" "itanium2") - (eq_attr "itanium_class" "ld")) + (and (and (and (eq_attr "cpu" "itanium2") + (eq_attr "itanium_class" "ld")) + (eq_attr "check_load" "no")) (ne (symbol_ref "bundling_p") (const_int 0))) "2b_M_only_um01") +(define_insn_reservation "2b_ldc" 0 + (and (and (and (eq_attr "cpu" "itanium2") + (eq_attr "itanium_class" "ld")) + (eq_attr "check_load" "yes")) + (ne (symbol_ref "bundling_p") (const_int 0))) + "2b_M_only_um01") + (define_insn_reservation "2b_long_i" 1 (and (and (eq_attr "cpu" "itanium2") (eq_attr "itanium_class" "long_i")) @@ -1714,11 +1790,23 @@ (and (and (eq_attr "cpu" "itanium2") (eq_attr "itanium_class" "xtd")) (ne (symbol_ref "bundling_p") (const_int 0))) "2b_I") -(define_insn_reservation "2b_chk_s" 0 + +(define_insn_reservation "2b_chk_s_i" 0 (and (and (eq_attr "cpu" "itanium2") - (eq_attr "itanium_class" "chk_s")) + (eq_attr "itanium_class" "chk_s_i")) (ne (symbol_ref "bundling_p") (const_int 0))) "2b_I|2b_M_only_um23") +(define_insn_reservation "2b_chk_s_f" 0 + (and (and (eq_attr "cpu" "itanium2") + (eq_attr "itanium_class" "chk_s_f")) + (ne (symbol_ref "bundling_p") (const_int 0))) + "2b_M_only_um23") +(define_insn_reservation "2b_chk_a" 0 + (and (and (eq_attr "cpu" "itanium2") + (eq_attr "itanium_class" "chk_a")) + (ne (symbol_ref "bundling_p") (const_int 0))) + "2b_M_only_um01") + (define_insn_reservation "2b_lfetch" 0 (and (and (eq_attr "cpu" "itanium2") (eq_attr "itanium_class" "lfetch")) |