diff options
Diffstat (limited to 'gcc/config/ia64/ia64.md')
| -rw-r--r-- | gcc/config/ia64/ia64.md | 208 |
1 files changed, 203 insertions, 5 deletions
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index da7fe6d..f25ad76 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -81,6 +81,12 @@ (UNSPEC_SHRP 29) (UNSPEC_COPYSIGN 30) (UNSPEC_VECT_EXTR 31) + (UNSPEC_LDA 40) + (UNSPEC_LDS 41) + (UNSPEC_LDSA 42) + (UNSPEC_LDCCLR 43) + (UNSPEC_CHKACLR 45) + (UNSPEC_CHKS 47) ]) (define_constants @@ -124,18 +130,19 @@ (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld, fldp,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf, - ld,chk_s,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf, + ld,chk_s_i,chk_s_f,chk_a,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf, st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop, nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle" (const_string "unknown")) -;; chk_s has an I and an M form; use type A for convenience. +;; chk_s_i has an I and an M form; use type A for convenience. (define_attr "type" "unknown,A,I,M,F,B,L,X,S" (cond [(eq_attr "itanium_class" "ld,st,fld,fldp,stf,sem,nop_m") (const_string "M") (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M") (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M") (eq_attr "itanium_class" "lfetch") (const_string "M") - (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog,mmalua") + (eq_attr "itanium_class" "chk_s_f,chk_a") (const_string "M") + (eq_attr "itanium_class" "chk_s_i,ialu,icmp,ilog,mmalua") (const_string "A") (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F") (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F") @@ -170,6 +177,12 @@ ;; when we have full intrinsics support. (define_attr "first_insn" "no,yes" (const_string "no")) + +(define_attr "data_speculative" "no,yes" (const_string "no")) + +(define_attr "control_speculative" "no,yes" (const_string "no")) + +(define_attr "check_load" "no,yes" (const_string "no")) ;; DFA descriptions of ia64 processors used for insn scheduling and ;; bundling. @@ -372,6 +385,191 @@ } [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")]) +(define_mode_macro MODE [BI QI HI SI DI SF DF XF TI]) +(define_mode_macro MODE_FOR_EXTEND [QI HI SI]) + +(define_mode_attr output_a [ + (BI "ld1.a %0 = %1%P1") + (QI "ld1.a %0 = %1%P1") + (HI "ld2.a %0 = %1%P1") + (SI "ld4.a %0 = %1%P1") + (DI + "@ + ld8.a %0 = %1%P1 + ldf8.a %0 = %1%P1") + (SF + "@ + ldfs.a %0 = %1%P1 + ld4.a %0 = %1%P1") + (DF + "@ + ldfd.a %0 = %1%P1 + ld8.a %0 = %1%P1") + (XF "ldfe.a %0 = %1%P1") + (TI "ldfp8.a %X0 = %1%P1")]) + +(define_mode_attr output_s [ + (BI "ld1.s %0 = %1%P1") + (QI "ld1.s %0 = %1%P1") + (HI "ld2.s %0 = %1%P1") + (SI "ld4.s %0 = %1%P1") + (DI + "@ + ld8.s %0 = %1%P1 + ldf8.s %0 = %1%P1") + (SF + "@ + ldfs.s %0 = %1%P1 + ld4.s %0 = %1%P1") + (DF + "@ + ldfd.s %0 = %1%P1 + ld8.s %0 = %1%P1") + (XF "ldfe.s %0 = %1%P1") + (TI "ldfp8.s %X0 = %1%P1")]) + +(define_mode_attr output_sa [ + (BI "ld1.sa %0 = %1%P1") + (QI "ld1.sa %0 = %1%P1") + (HI "ld2.sa %0 = %1%P1") + (SI "ld4.sa %0 = %1%P1") + (DI + "@ + ld8.sa %0 = %1%P1 + ldf8.sa %0 = %1%P1") + (SF + "@ + ldfs.sa %0 = %1%P1 + ld4.sa %0 = %1%P1") + (DF + "@ + ldfd.sa %0 = %1%P1 + ld8.sa %0 = %1%P1") + (XF "ldfe.sa %0 = %1%P1") + (TI "ldfp8.sa %X0 = %1%P1")]) + +(define_mode_attr output_c_clr [ + (BI "ld1.c.clr%O1 %0 = %1%P1") + (QI "ld1.c.clr%O1 %0 = %1%P1") + (HI "ld2.c.clr%O1 %0 = %1%P1") + (SI "ld4.c.clr%O1 %0 = %1%P1") + (DI + "@ + ld8.c.clr%O1 %0 = %1%P1 + ldf8.c.clr %0 = %1%P1") + (SF + "@ + ldfs.c.clr %0 = %1%P1 + ld4.c.clr%O1 %0 = %1%P1") + (DF + "@ + ldfd.c.clr %0 = %1%P1 + ld8.c.clr%O1 %0 = %1%P1") + (XF "ldfe.c.clr %0 = %1%P1") + (TI "ldfp8.c.clr %X0 = %1%P1")]) + +(define_mode_attr ld_reg_constr [(BI "=*r") (QI "=r") (HI "=r") (SI "=r") (DI "=r,*f") (SF "=f,*r") (DF "=f,*r") (XF "=f") (TI "=*x")]) +(define_mode_attr ldc_reg_constr [(BI "+*r") (QI "+r") (HI "+r") (SI "+r") (DI "+r,*f") (SF "+f,*r") (DF "+f,*r") (XF "+f") (TI "+*x")]) +(define_mode_attr chk_reg_constr [(BI "*r") (QI "r") (HI "r") (SI "r") (DI "r,*f") (SF "f,*r") (DF "f,*r") (XF "f") (TI "*x")]) + +(define_mode_attr mem_constr [(BI "*m") (QI "m") (HI "m") (SI "m") (DI "m,Q") (SF "Q,m") (DF "Q,m") (XF "m") (TI "Q")]) + +(define_mode_attr reg_pred_prefix [(BI "gr") (QI "gr") (HI "gr") (SI "gr") (DI "grfr") (SF "grfr") (DF "grfr") (XF "fr") (TI "fr")]) + +(define_mode_attr ld_class [(BI "ld") (QI "ld") (HI "ld") (SI "ld") (DI "ld,fld") (SF "fld,ld") (DF "fld,ld") (XF "fld") (TI "fldp")]) +(define_mode_attr chka_class [(BI "chk_a") (QI "chk_a") (HI "chk_a") (SI "chk_a") (DI "chk_a,chk_a") (SF "chk_a,chk_a") (DF "chk_a,chk_a") (XF "chk_a") (TI "chk_a")]) +(define_mode_attr chks_class [(BI "chk_s_i") (QI "chk_s_i") (HI "chk_s_i") (SI "chk_s_i") (DI "chk_s_i,chk_s_f") (SF "chk_s_f,chk_s_i") (DF "chk_s_f,chk_s_i") (XF "chk_s_f") (TI "chk_s_i")]) + +(define_mode_attr attr_yes [(BI "yes") (QI "yes") (HI "yes") (SI "yes") (DI "yes,yes") (SF "yes,yes") (DF "yes,yes") (XF "yes") (TI "yes")]) + +(define_insn "mov<mode>_advanced" + [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") + (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA))] + "ia64_move_ok (operands[0], operands[1])" + "<output_a>" + [(set_attr "itanium_class" "<ld_class>") + (set_attr "data_speculative" "<attr_yes>")]) + +(define_insn "zero_extend<mode>di2_advanced" + [(set (match_operand:DI 0 "gr_register_operand" "=r") + (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA)))] + "" + "<output_a>" + [(set_attr "itanium_class" "<ld_class>") + (set_attr "data_speculative" "<attr_yes>")]) + +(define_insn "mov<mode>_speculative" + [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") + (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS))] + "ia64_move_ok (operands[0], operands[1])" + "<output_s>" + [(set_attr "itanium_class" "<ld_class>") + (set_attr "control_speculative" "<attr_yes>")]) + +(define_insn "zero_extend<mode>di2_speculative" + [(set (match_operand:DI 0 "gr_register_operand" "=r") + (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS)))] + "" + "<output_s>" + [(set_attr "itanium_class" "<ld_class>") + (set_attr "control_speculative" "<attr_yes>")]) + +(define_insn "mov<mode>_speculative_advanced" + [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") + (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA))] + "ia64_move_ok (operands[0], operands[1])" + "<output_sa>" + [(set_attr "itanium_class" "<ld_class>") + (set_attr "data_speculative" "<attr_yes>") + (set_attr "control_speculative" "<attr_yes>")]) + +(define_insn "zero_extend<mode>di2_speculative_advanced" + [(set (match_operand:DI 0 "gr_register_operand" "=r") + (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA)))] + "" + "<output_sa>" + [(set_attr "itanium_class" "<ld_class>") + (set_attr "data_speculative" "<attr_yes>") + (set_attr "control_speculative" "<attr_yes>")]) + +(define_insn "mov<mode>_clr" + [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>") + (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0)) + (match_operand:MODE 1 "memory_operand" "<mem_constr>") + (match_dup 0)))] + "ia64_move_ok (operands[0], operands[1])" + "<output_c_clr>" + [(set_attr "itanium_class" "<ld_class>") + (set_attr "check_load" "<attr_yes>")]) + +(define_insn "zero_extend<mode>di2_clr" + [(set (match_operand:DI 0 "gr_register_operand" "+r") + (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0)) + (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")) + (match_dup 0)))] + "" + "<output_c_clr>" + [(set_attr "itanium_class" "<ld_class>") + (set_attr "check_load" "<attr_yes>")]) + +(define_insn "advanced_load_check_clr_<mode>" + [(set (pc) + (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKACLR) (const_int 0)) + (pc) + (label_ref (match_operand 1 "" ""))))] + "" + "chk.a.clr %0, %l1" + [(set_attr "itanium_class" "<chka_class>")]) + +(define_insn "speculation_check_<mode>" + [(set (pc) + (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKS) (const_int 0)) + (pc) + (label_ref (match_operand 1 "" ""))))] + "" + "chk.s %0, %l1" + [(set_attr "itanium_class" "<chks_class>")]) + (define_split [(set (match_operand 0 "register_operand" "") (match_operand 1 "symbolic_operand" ""))] @@ -6114,7 +6312,7 @@ [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))] "" "break %0" - [(set_attr "itanium_class" "chk_s")]) + [(set_attr "itanium_class" "chk_s_i")]) (define_expand "conditional_trap" [(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))] @@ -6130,7 +6328,7 @@ (match_operand 2 "const_int_operand" ""))] "" "(%J0) break %2" - [(set_attr "itanium_class" "chk_s") + [(set_attr "itanium_class" "chk_s_i") (set_attr "predicable" "no")]) (define_insn "break_f" |