diff options
Diffstat (limited to 'gcc/config/i386/i386.md')
| -rw-r--r-- | gcc/config/i386/i386.md | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 95a6653c..15c0310 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -11380,6 +11380,8 @@ [(set_attr "type" "alu") (set_attr "mode" "QI")]) +;; *andqi_ext<mode>_3 is defined via *<code>qi_ext<mode>_3 below. + ;; Convert wide AND instructions with immediate operand to shorter QImode ;; equivalents when possible. ;; Don't do the splitting with memory operands, since it introduces risk @@ -12092,6 +12094,26 @@ [(set_attr "type" "alu") (set_attr "mode" "QI")]) +(define_insn "*<code>qi_ext<mode>_3" + [(set (zero_extract:SWI248 + (match_operand 0 "int248_register_operand" "+Q") + (const_int 8) + (const_int 8)) + (zero_extract:SWI248 + (any_logic:SWI248 + (match_operand 1 "int248_register_operand" "%0") + (match_operand 2 "int248_register_operand" "Q")) + (const_int 8) + (const_int 8))) + (clobber (reg:CC FLAGS_REG))] + "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) + /* FIXME: without this LRA can't reload this pattern, see PR82524. */ + && (rtx_equal_p (operands[0], operands[1]) + || rtx_equal_p (operands[0], operands[2]))" + "<logic>{b}\t{%h2, %h0|%h0, %h2}" + [(set_attr "type" "alu") + (set_attr "mode" "QI")]) + ;; Convert wide OR instructions with immediate operand to shorter QImode ;; equivalents when possible. ;; Don't do the splitting with memory operands, since it introduces risk @@ -12206,6 +12228,18 @@ (set_attr "type" "alu") (set_attr "mode" "QI")]) +;; Peephole2 rega = 0; rega op= regb into rega = regb. +(define_peephole2 + [(parallel [(set (match_operand:SWI 0 "general_reg_operand") + (const_int 0)) + (clobber (reg:CC FLAGS_REG))]) + (parallel [(set (match_dup 0) + (any_or_plus:SWI (match_dup 0) + (match_operand:SWI 1 "<general_operand>"))) + (clobber (reg:CC FLAGS_REG))])] + "" + [(set (match_dup 0) (match_dup 1))]) + ;; Split DST = (HI<<32)|LO early to minimize register usage. (define_insn_and_split "*concat<mode><dwi>3_1" [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r") @@ -13365,6 +13399,28 @@ [(const_int 0)] "ix86_split_ashl (operands, operands[3], <DWI>mode); DONE;") +(define_insn_and_split "*ashl<dwi>3_doubleword_highpart" + [(set (match_operand:<DWI> 0 "register_operand" "=r") + (ashift:<DWI> + (any_extend:<DWI> (match_operand:DWIH 1 "nonimmediate_operand" "rm")) + (match_operand:QI 2 "const_int_operand"))) + (clobber (reg:CC FLAGS_REG))] + "INTVAL (operands[2]) >= <MODE_SIZE> * BITS_PER_UNIT + && INTVAL (operands[2]) < <MODE_SIZE> * BITS_PER_UNIT * 2" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_double_mode (<DWI>mode, &operands[0], 1, &operands[0], &operands[3]); + int bits = INTVAL (operands[2]) - (<MODE_SIZE> * BITS_PER_UNIT); + if (!rtx_equal_p (operands[3], operands[1])) + emit_move_insn (operands[3], operands[1]); + if (bits > 0) + emit_insn (gen_ashl<mode>3 (operands[3], operands[3], GEN_INT (bits))); + ix86_expand_clear (operands[0]); + DONE; +}) + (define_insn "x86_64_shld" [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m") (ior:DI (ashift:DI (match_dup 0) |