diff options
Diffstat (limited to 'gcc/config/arm/arm.c')
| -rw-r--r-- | gcc/config/arm/arm.c | 116 |
1 files changed, 116 insertions, 0 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index b3a81b0..c961fb1 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1164,6 +1164,106 @@ const struct cpu_cost_table cortexa7_extra_costs = } }; +const struct cpu_cost_table cortexa12_extra_costs = +{ + /* ALU */ + { + 0, /* Arith. */ + 0, /* Logical. */ + 0, /* Shift. */ + COSTS_N_INSNS (1), /* Shift_reg. */ + COSTS_N_INSNS (1), /* Arith_shift. */ + COSTS_N_INSNS (1), /* Arith_shift_reg. */ + COSTS_N_INSNS (1), /* Log_shift. */ + COSTS_N_INSNS (1), /* Log_shift_reg. */ + 0, /* Extend. */ + COSTS_N_INSNS (1), /* Extend_arith. */ + 0, /* Bfi. */ + COSTS_N_INSNS (1), /* Bfx. */ + COSTS_N_INSNS (1), /* Clz. */ + 0, /* non_exec. */ + true /* non_exec_costs_exec. */ + }, + /* MULT SImode */ + { + { + COSTS_N_INSNS (2), /* Simple. */ + COSTS_N_INSNS (3), /* Flag_setting. */ + COSTS_N_INSNS (2), /* Extend. */ + COSTS_N_INSNS (3), /* Add. */ + COSTS_N_INSNS (2), /* Extend_add. */ + COSTS_N_INSNS (18) /* Idiv. */ + }, + /* MULT DImode */ + { + 0, /* Simple (N/A). */ + 0, /* Flag_setting (N/A). */ + COSTS_N_INSNS (3), /* Extend. */ + 0, /* Add (N/A). */ + COSTS_N_INSNS (3), /* Extend_add. */ + 0 /* Idiv (N/A). */ + } + }, + /* LD/ST */ + { + COSTS_N_INSNS (3), /* Load. */ + COSTS_N_INSNS (3), /* Load_sign_extend. */ + COSTS_N_INSNS (3), /* Ldrd. */ + COSTS_N_INSNS (3), /* Ldm_1st. */ + 1, /* Ldm_regs_per_insn_1st. */ + 2, /* Ldm_regs_per_insn_subsequent. */ + COSTS_N_INSNS (3), /* Loadf. */ + COSTS_N_INSNS (3), /* Loadd. */ + 0, /* Load_unaligned. */ + 0, /* Store. */ + 0, /* Strd. */ + 0, /* Stm_1st. */ + 1, /* Stm_regs_per_insn_1st. */ + 2, /* Stm_regs_per_insn_subsequent. */ + COSTS_N_INSNS (2), /* Storef. */ + COSTS_N_INSNS (2), /* Stored. */ + 0 /* Store_unaligned. */ + }, + { + /* FP SFmode */ + { + COSTS_N_INSNS (17), /* Div. */ + COSTS_N_INSNS (4), /* Mult. */ + COSTS_N_INSNS (8), /* Mult_addsub. */ + COSTS_N_INSNS (8), /* Fma. */ + COSTS_N_INSNS (4), /* Addsub. */ + COSTS_N_INSNS (2), /* Fpconst. */ + COSTS_N_INSNS (2), /* Neg. */ + COSTS_N_INSNS (2), /* Compare. */ + COSTS_N_INSNS (4), /* Widen. */ + COSTS_N_INSNS (4), /* Narrow. */ + COSTS_N_INSNS (4), /* Toint. */ + COSTS_N_INSNS (4), /* Fromint. */ + COSTS_N_INSNS (4) /* Roundint. */ + }, + /* FP DFmode */ + { + COSTS_N_INSNS (31), /* Div. */ + COSTS_N_INSNS (4), /* Mult. */ + COSTS_N_INSNS (8), /* Mult_addsub. */ + COSTS_N_INSNS (8), /* Fma. */ + COSTS_N_INSNS (4), /* Addsub. */ + COSTS_N_INSNS (2), /* Fpconst. */ + COSTS_N_INSNS (2), /* Neg. */ + COSTS_N_INSNS (2), /* Compare. */ + COSTS_N_INSNS (4), /* Widen. */ + COSTS_N_INSNS (4), /* Narrow. */ + COSTS_N_INSNS (4), /* Toint. */ + COSTS_N_INSNS (4), /* Fromint. */ + COSTS_N_INSNS (4) /* Roundint. */ + } + }, + /* Vector */ + { + COSTS_N_INSNS (1) /* Alu. */ + } +}; + const struct cpu_cost_table cortexa15_extra_costs = { /* ALU */ @@ -1563,6 +1663,22 @@ const struct tune_params arm_cortex_a9_tune = false /* Prefer Neon for 64-bits bitops. */ }; +const struct tune_params arm_cortex_a12_tune = +{ + arm_9e_rtx_costs, + &cortexa12_extra_costs, + NULL, + 1, /* Constant limit. */ + 5, /* Max cond insns. */ + ARM_PREFETCH_BENEFICIAL(4,32,32), + false, /* Prefer constant pool. */ + arm_default_branch_cost, + true, /* Prefer LDRD/STRD. */ + {true, true}, /* Prefer non short circuit. */ + &arm_default_vec_cost, /* Vectorizer costs. */ + false /* Prefer Neon for 64-bits bitops. */ +}; + /* armv7m tuning. On Cortex-M4 cores for example, MOVW/MOVT take a single cycle to execute each. An LDR from the constant pool also takes two cycles to execute, but mildly increases pipelining opportunity (consecutive |