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-rw-r--r--gcc/common/config/i386/i386-common.c275
1 files changed, 185 insertions, 90 deletions
diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index 02b19f1..bb14305 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -158,6 +158,8 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
#define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE
#define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
+#define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE
+#define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK
/* Define a set of ISAs which aren't available when a given ISA is
disabled. MMX and SSE ISAs are handled separately. */
@@ -241,7 +243,9 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG
#define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE
#define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD
+#define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE
#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT
+#define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
@@ -677,6 +681,19 @@ ix86_handle_option (struct gcc_options *opts,
}
return true;
+ case OPT_mserialize:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SERIALIZE_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SERIALIZE_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_UNSET;
+ }
+ return true;
+
case OPT_mavx5124fmaps:
if (value)
{
@@ -900,6 +917,19 @@ ix86_handle_option (struct gcc_options *opts,
}
return true;
+ case OPT_mtsxldtrk:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_TSXLDTRK_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_TSXLDTRK_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_UNSET;
+ }
+ return true;
+
case OPT_mfma:
if (value)
{
@@ -1568,6 +1598,8 @@ const char *const processor_names[] =
"cascadelake",
"tigerlake",
"cooperlake",
+ "sapphirerapids",
+ "alderlake",
"intel",
"geode",
"k6",
@@ -1589,164 +1621,206 @@ STATIC_ASSERT (ARRAY_SIZE (processor_names) == PROCESSOR_max);
const pta processor_alias_table[] =
{
- {"i386", PROCESSOR_I386, CPU_NONE, 0},
- {"i486", PROCESSOR_I486, CPU_NONE, 0},
- {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
- {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
- {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
- {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
- {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
- {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
- {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
- {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
+ {"i386", PROCESSOR_I386, CPU_NONE, 0, 0, P_NONE},
+ {"i486", PROCESSOR_I486, CPU_NONE, 0, 0, P_NONE},
+ {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
+ {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
+ {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387,
+ 0, P_NONE},
+ {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX, 0, P_NONE},
+ {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX, 0, P_NONE},
+ {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
+ 0, P_NONE},
+ {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW, 0, P_NONE},
+ {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
+ 0, P_NONE},
{"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
{"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
{"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
{"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
- {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
- {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
- {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
+ {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
+ {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
+ {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR,
+ 0, P_NONE},
{"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
{"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
{"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
{"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
{"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
{"prescott", PROCESSOR_NOCONA, CPU_NONE,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
{"nocona", PROCESSOR_NOCONA, CPU_NONE,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
- {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
- {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
- {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
- {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
+ | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
+ {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2,
+ M_CPU_TYPE (INTEL_CORE2), P_PROC_SSSE3},
+ {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
+ M_CPU_SUBTYPE (INTEL_COREI7_NEHALEM), P_PROC_DYNAMIC},
+ {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
+ M_CPU_TYPE (INTEL_COREI7), P_PROC_DYNAMIC},
+ {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE,
+ M_CPU_SUBTYPE (INTEL_COREI7_WESTMERE), P_PROC_DYNAMIC},
{"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_SANDYBRIDGE},
+ PTA_SANDYBRIDGE,
+ M_CPU_SUBTYPE (INTEL_COREI7_SANDYBRIDGE), P_PROC_DYNAMIC},
{"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_SANDYBRIDGE},
+ PTA_SANDYBRIDGE, 0, P_PROC_DYNAMIC},
{"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_IVYBRIDGE},
+ PTA_IVYBRIDGE,
+ M_CPU_SUBTYPE (INTEL_COREI7_IVYBRIDGE), P_PROC_DYNAMIC},
{"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_IVYBRIDGE},
- {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
- {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
- {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
- {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
+ PTA_IVYBRIDGE, 0, P_PROC_DYNAMIC},
+ {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
+ M_CPU_SUBTYPE (INTEL_COREI7_HASWELL), P_PROC_DYNAMIC},
+ {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
+ 0, P_PROC_DYNAMIC},
+ {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL,
+ M_CPU_SUBTYPE (INTEL_COREI7_BROADWELL), P_PROC_DYNAMIC},
+ {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE,
+ M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE), P_PROC_AVX2},
{"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
- PTA_SKYLAKE_AVX512},
- {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
+ PTA_SKYLAKE_AVX512,
+ M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE_AVX512), P_PROC_AVX512F},
+ {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE,
+ M_CPU_SUBTYPE (INTEL_COREI7_CANNONLAKE), P_PROC_AVX512F},
{"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
- PTA_ICELAKE_CLIENT},
+ PTA_ICELAKE_CLIENT,
+ M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_CLIENT), P_PROC_AVX512F},
{"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
- PTA_ICELAKE_SERVER},
+ PTA_ICELAKE_SERVER,
+ M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_SERVER), P_PROC_AVX512F},
{"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
- PTA_CASCADELAKE},
- {"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE},
- {"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE},
- {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
- {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
- {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
- {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
- {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
- {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
- {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
- {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
- {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
- {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
+ PTA_CASCADELAKE,
+ M_CPU_SUBTYPE (INTEL_COREI7_CASCADELAKE), P_PROC_AVX512F},
+ {"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE,
+ M_CPU_SUBTYPE (INTEL_COREI7_TIGERLAKE), P_PROC_AVX512F},
+ {"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE,
+ M_CPU_SUBTYPE (INTEL_COREI7_COOPERLAKE), P_PROC_AVX512F},
+ {"sapphirerapids", PROCESSOR_SAPPHIRERAPIDS, CPU_HASWELL, PTA_SAPPHIRERAPIDS,
+ M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
+ {"alderlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
+ M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
+ {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
+ M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
+ {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
+ M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
+ {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
+ M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
+ {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
+ M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
+ {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT,
+ M_CPU_TYPE (INTEL_GOLDMONT), P_PROC_SSE4_2},
+ {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS,
+ M_CPU_TYPE (INTEL_GOLDMONT_PLUS), P_PROC_SSE4_2},
+ {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT,
+ M_CPU_TYPE (INTEL_TREMONT), P_PROC_SSE4_2},
+ {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL,
+ M_CPU_TYPE (INTEL_KNL), P_PROC_AVX512F},
+ {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM,
+ M_CPU_TYPE (INTEL_KNM), P_PROC_AVX512F},
+ {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM,
+ M_VENDOR (VENDOR_INTEL), P_NONE},
{"geode", PROCESSOR_GEODE, CPU_GEODE,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
- {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
- {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
- {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
+ {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX, 0, P_NONE},
+ {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
+ {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
{"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
{"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
{"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
{"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
{"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
{"x86-64", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR,
+ 0, P_NONE},
{"eden-x2", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+ PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR,
+ 0, P_NONE},
{"nano", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_FXSR},
+ | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
{"nano-1000", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_FXSR},
+ | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
{"nano-2000", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_FXSR},
+ | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
{"nano-3000", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
{"nano-x2", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
{"eden-x4", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
{"nano-x4", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
{"k8", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
{"k8-sse3", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
{"opteron", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
{"opteron-sse3", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
{"athlon64", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
{"athlon64-sse3", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
{"athlon-fx", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
{"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
- | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
+ | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
+ 0, P_PROC_DYNAMIC},
{"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
- | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
+ | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
+ M_CPU_SUBTYPE (AMDFAM10H_BARCELONA), P_PROC_DYNAMIC},
{"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
- | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
+ | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE,
+ M_CPU_TYPE (AMDFAM15H_BDVER1), P_PROC_XOP},
{"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
- | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
+ | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE,
+ M_CPU_TYPE (AMDFAM15H_BDVER2), P_PROC_FMA},
{"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
- | PTA_XSAVEOPT | PTA_FSGSBASE},
+ | PTA_XSAVEOPT | PTA_FSGSBASE,
+ M_CPU_SUBTYPE (AMDFAM15H_BDVER3), P_PROC_FMA},
{"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
@@ -1754,7 +1828,8 @@ const pta processor_alias_table[] =
| PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
| PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
| PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
- | PTA_MOVBE | PTA_MWAITX},
+ | PTA_MOVBE | PTA_MWAITX,
+ M_CPU_SUBTYPE (AMDFAM15H_BDVER4), P_PROC_AVX2},
{"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
@@ -1763,7 +1838,8 @@ const pta processor_alias_table[] =
| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
| PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
| PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
- | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
+ | PTA_SHA | PTA_LZCNT | PTA_POPCNT,
+ M_CPU_SUBTYPE (AMDFAM17H_ZNVER1), P_PROC_AVX2},
{"znver2", PROCESSOR_ZNVER2, CPU_ZNVER2,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
@@ -1773,24 +1849,43 @@ const pta processor_alias_table[] =
| PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
| PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
| PTA_SHA | PTA_LZCNT | PTA_POPCNT | PTA_CLWB | PTA_RDPID
- | PTA_WBNOINVD},
+ | PTA_WBNOINVD,
+ M_CPU_SUBTYPE (AMDFAM17H_ZNVER2), P_PROC_AVX2},
{"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_PRFCHW
- | PTA_FXSR | PTA_XSAVE},
+ | PTA_FXSR | PTA_XSAVE,
+ M_CPU_SUBTYPE (AMDFAM15H_BDVER1), P_PROC_SSE4_A},
{"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_SSE4_1
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
- | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
+ | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT,
+ M_CPU_TYPE (AMD_BTVER2), P_PROC_BMI},
{"generic", PROCESSOR_GENERIC, CPU_GENERIC,
PTA_64BIT
- | PTA_HLE /* flags are only used for -march switch. */ },
+ | PTA_HLE /* flags are only used for -march switch. */,
+ 0, P_NONE},
+
+ {"amd", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+ M_VENDOR (VENDOR_AMD), P_NONE},
+ {"amdfam10h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+ M_CPU_TYPE (AMDFAM10H), P_NONE},
+ {"amdfam15h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+ M_CPU_TYPE (AMDFAM15H), P_NONE},
+ {"amdfam17h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+ M_CPU_TYPE (AMDFAM17H), P_NONE},
+ {"shanghai", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+ M_CPU_TYPE (AMDFAM10H_SHANGHAI), P_NONE},
+ {"istanbul", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+ M_CPU_TYPE (AMDFAM10H_ISTANBUL), P_NONE},
};
-int const pta_size = ARRAY_SIZE (processor_alias_table);
+/* NB: processor_alias_table stops at the "generic" entry. */
+int const pta_size = ARRAY_SIZE (processor_alias_table) - 6;
+unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table);
/* Provide valid option values for -march and -mtune options. */
generated by cgit v1.1 at 2025-09-27 16:07:58 +0000