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Diffstat (limited to 'gcc/ChangeLog')
| -rw-r--r-- | gcc/ChangeLog | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index db259ce..f4b9b50 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,46 @@ +2024-06-28 Kewen Lin <linkw@linux.ibm.com> + + Backported from master: + 2024-06-21 Kewen Lin <linkw@linux.ibm.com> + Xionghu Luo <xionghuluo@tencent.com> + + PR target/106069 + PR target/115355 + * config/rs6000/altivec.md (altivec_vmrghw_direct_<VSX_W:mode>): Rename + to ... + (altivec_vmrghw_direct_<VSX_W:mode>_be): ... this. Add the condition + BYTES_BIG_ENDIAN. + (altivec_vmrghw_direct_<VSX_W:mode>_le): New define_insn. + (altivec_vmrglw_direct_<VSX_W:mode>): Rename to ... + (altivec_vmrglw_direct_<VSX_W:mode>_be): ... this. Add the condition + BYTES_BIG_ENDIAN. + (altivec_vmrglw_direct_<VSX_W:mode>_le): New define_insn. + (altivec_vmrghw): Adjust by calling gen_altivec_vmrghw_direct_v4si_be + for BE and gen_altivec_vmrglw_direct_v4si_le for LE. + (altivec_vmrglw): Adjust by calling gen_altivec_vmrglw_direct_v4si_be + for BE and gen_altivec_vmrghw_direct_v4si_le for LE. + (vec_widen_umult_hi_v8hi): Adjust the call to + gen_altivec_vmrghw_direct_v4si by gen_altivec_vmrghw for BE + and by gen_altivec_vmrglw for LE. + (vec_widen_smult_hi_v8hi): Likewise. + (vec_widen_umult_lo_v8hi): Adjust the call to + gen_altivec_vmrglw_direct_v4si by gen_altivec_vmrglw for BE + and by gen_altivec_vmrghw for LE + (vec_widen_smult_lo_v8hi): Likewise. + * config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Replace + CODE_FOR_altivec_vmrghw_direct_v4si by + CODE_FOR_altivec_vmrghw_direct_v4si_be for BE and + CODE_FOR_altivec_vmrghw_direct_v4si_le for LE. And replace + CODE_FOR_altivec_vmrglw_direct_v4si by + CODE_FOR_altivec_vmrglw_direct_v4si_be for BE and + CODE_FOR_altivec_vmrglw_direct_v4si_le for LE. + * config/rs6000/vsx.md (vsx_xxmrghw_<VSX_W:mode>): Adjust by calling + gen_altivec_vmrghw_direct_v4si_be for BE and + gen_altivec_vmrglw_direct_v4si_le for LE. + (vsx_xxmrglw_<VSX_W:mode>): Adjust by calling + gen_altivec_vmrglw_direct_v4si_be for BE and + gen_altivec_vmrghw_direct_v4si_le for LE. + 2024-06-27 Wilco Dijkstra <wilco.dijkstra@arm.com> Backported from master: |