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diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a3238a3..2d49dd3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,3729 @@ +2025-09-01 Jonathan Grant <jg@jguk.org> + + * doc/install.texi (Configuration): Fix spelling of "support" + and "floating-point arithmetic". + +2025-09-01 Mark Harmstone <mark@harmstone.com> + + * dwarf2codeview.cc (get_type_num_array_type): Don't try to + encode non-C-style arrays. + +2025-09-01 Jakub Jelinek <jakub@redhat.com> + + * builtins.def: Implement C2Y N3577 - Rename s/uimaxabs/umaxabs/. + (BUILT_IN_UIMAXABS): Rename to ... + (BUILT_IN_UMAXABS): ... this. Change second argument to "umaxabs". + * builtins.cc (fold_builtin_1): Use BUILT_IN_UMAXABS rather than + BUILT_IN_UIMAXABS. + +2025-09-01 Gerald Pfeifer <gerald@pfeifer.com> + + * doc/invoke.texi (Optimize Options): Update the perfwiki web + address. + +2025-09-01 Iain Sandoe <iain@sandoe.co.uk> + + * diagnostics/logging.h (log_param_location_t): Cast + location_t value to fmt_size_t. + +2025-09-01 Iain Sandoe <iain@sandoe.co.uk> + + * configure: Regenerate. + * configure.ac: Do not claim cfi instruction support even + if the assembler has it. + +2025-09-01 Yoshinori Sato <yoshinori.sato@nifty.com> + + PR target/89828 + * config/rx/rx.cc (add_pop_cfi_notes): Release the frame pointer if it is + used. + (rx_expand_prologue): Redesigned stack pointer and frame pointer update + process. + +2025-09-01 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121744 + * tree-vect-patterns.cc (vect_recog_vector_vector_shift_pattern): + Allow constant left operand. + +2025-09-01 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vect_create_epilog_for_reduction): + Use SLP_TREE_REDUC_IDX for following the SLP graph and + for identifying whether we use the 'else' in a COND. + (vectorizable_lane_reducing): Simplify check of whether + we are in a reduction. + (vectorizable_reduction): Add sanity checking around + SLP_TREE_REDUC_IDX and use it where it looks appropriate. + (vect_transform_reduction): Use SLP_TREE_REDUC_IDX. + * tree-vect-stmts.cc (vectorizable_call): Likewise. + (vectorizable_operation): Likewise. + (vectorizable_condition): Likewise. + +2025-09-01 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vectorizable_live_operation): Check + vect_is_reduction on the SLP node rather than + STMT_VINFO_REDUC_DEF on the stmt. + (vectorizable_reduction): Do not set STMT_VINFO_REDUC_DEF + on live stmts. + +2025-09-01 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (vect_reduc_info): New. + (create_info_for_reduction): Likewise. + (VECT_REDUC_INFO_TYPE): Likewise. + (VECT_REDUC_INFO_CODE): Likewise. + (VECT_REDUC_INFO_FN): Likewise. + (VECT_REDUC_INFO_SCALAR_RESULTS): Likewise. + (VECT_REDUC_INFO_INITIAL_VALUES): Likewise. + (VECT_REDUC_INFO_REUSED_ACCUMULATOR): Likewise. + (VECT_REDUC_INFO_INDUC_COND_INITIAL_VAL): Likewise. + (VECT_REDUC_INFO_EPILOGUE_ADJUSTMENT): Likewise. + (VECT_REDUC_INFO_FORCE_SINGLE_CYCLE): Likewise. + (VECT_REDUC_INFO_RESULT_POS): Likewise. + (VECT_REDUC_INFO_VECTYPE): Likewise. + (STMT_VINFO_VEC_INDUC_COND_INITIAL_VAL): Remove. + (STMT_VINFO_REDUC_EPILOGUE_ADJUSTMENT): Likewise. + (STMT_VINFO_FORCE_SINGLE_CYCLE): Likewise. + (STMT_VINFO_REDUC_FN): Likewise. + (STMT_VINFO_REDUC_VECTYPE): Likewise. + (vect_reusable_accumulator::reduc_info): Adjust. + (vect_reduc_type): Adjust. + (_slp_tree::cycle_info): New member. + (SLP_TREE_REDUC_IDX): Likewise. + (vect_reduc_info_s): Move/copy data from ... + (_stmt_vec_info): ... here. + (_loop_vec_info::redcu_infos): New member. + (info_for_reduction): Adjust to take SLP node. + (vect_reduc_type): Adjust. + (vect_is_reduction): Add overload for SLP node. + * tree-vectorizer.cc (vec_info::new_stmt_vec_info): + Do not initialize removed members. + (vec_info::free_stmt_vec_info): Do not release them. + * tree-vect-stmts.cc (vectorizable_condition): Adjust. + * tree-vect-slp.cc (_slp_tree::_slp_tree): Initialize + cycle info. + (vect_build_slp_tree_2): Compute SLP reduc_idx and store + it. Create, populate and propagate reduction info. + (vect_print_slp_tree): Print cycle info. + (vect_analyze_slp_reduc_chain): Set cycle info on the + manual added conversion node. + (vect_optimize_slp_pass::start_choosing_layouts): Adjust. + * tree-vect-loop.cc (_loop_vec_info::~_loop_vec_info): + Release reduction infos. + (info_for_reduction): Get the reduction info from + the vector in the loop_vinfo. + (vect_create_epilog_for_reduction): Adjust. + (vectorizable_reduction): Likewise. + (vect_transform_reduction): Likewise. + (vect_transform_cycle_phi): Likewise, deal with nested + cycles not part of a double reduction have no reduction info. + * config/aarch64/aarch64.cc (aarch64_force_single_cycle): + Use VECT_REDUC_INFO_FORCE_SINGLE_CYCLE, get SLP node and use + that. + (aarch64_vector_costs::count_ops): Adjust. + +2025-09-01 Tobias Burnus <tburnus@baylibre.com> + + PR target/121392 + * doc/install.texi (amdgcn): Mention Newlib commit + that fixes another SIMD issue. + +2025-09-01 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vect_is_simple_iv_evolution): Get + stmt_info and store into STMT_VINFO_LOOP_PHI_EVOLUTION_BASE_UNCHANGED + and STMT_VINFO_LOOP_PHI_EVOLUTION_PART here. Drop unused + output parameters. + (vect_is_nonlinear_iv_evolution): Likewise. + (vect_analyze_scalar_cycles_1): Remove redundant setting + of STMT_VINFO_LOOP_PHI_EVOLUTION_BASE_UNCHANGED and + STMT_VINFO_LOOP_PHI_EVOLUTION_PART. + +2025-09-01 Cui, Lili <lili.cui@intel.com> + + PR rtl-optimization/117838 + * ira-color.cc (improve_allocation): Remove soft conflict related code. + +2025-09-01 liuhongt <hongtao.liu@intel.com> + + PR target/121699 + * config/i386/predicates.md (const_vec_dup_operand): New + predicate. + * config/i386/sse.md (cond_<insn><mode>): Fix predicate of + operands[3], and fix wrong operands passed to + ix86_vgf2p8affine_shift_matrix and + gen_vgf2p8affineqb_<mode>_mask. + +2025-08-31 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/predicates.md (alt_ubranch_operator): + New predicate. + * config/xtensa/xtensa.md (*eqne_in_range): + New insn_and_split pattern. + +2025-08-31 Shreya Munnangi <smunnangi1@ventanamicro.com> + + * config/riscv/riscv-protos.h (synthesize_add_extended): Prototype. + * config/riscv/riscv.cc (synthesize_add_extended): New function. + * config/riscv/riscv.md (addsi3): For RV64, try synthesize_add_extended. + +2025-08-31 Gerald Pfeifer <gerald@pfeifer.com> + + * doc/install.texi (Binaries): Drop MinGW. + +2025-08-30 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/121698 + * tree-ssa-phiopt.cc (spaceship_replacement): Adjust + to handle spaceship unordered value -128 rather than 2 and + stmts from the new std::partial_order::_M_reverse() instead + of (_M_value & ~1) == _M_value etc. + * doc/md.texi (spaceship@var{m}4): Use -128 instead of 2. + * tree-ssa-math-opts.cc (optimize_spaceship): Adjust comments + that libstdc++ unordered value is -128 rather than 2 and use + that as the default unordered value. + * config/i386/i386-expand.cc (ix86_expand_fp_spaceship): Use + GEN_INT (-128) instead of const2_rtx and adjust comment accordingly. + * config/aarch64/aarch64.cc (aarch64_expand_fp_spaceship): Likewise. + * config/s390/s390.cc (s390_expand_fp_spaceship): Likewise. + +2025-08-30 Gerald Pfeifer <gerald@pfeifer.com> + + * doc/extend.texi (Vector Extensions): Improve markup for list + of operators. + +2025-08-30 Gerald Pfeifer <gerald@pfeifer.com> + + * doc/standards.texi (Standards): Update "Object-Oriented + Programming and the Objective-C Language" reference. + +2025-08-30 H.J. Lu <hjl.tools@gmail.com> + + PR target/121725 + * config/i386/i386-features.cc + (pass_x86_cse::candidate_gnu2_tls_p): Use the UNSPEC_DTPOFF + operand to check source operand in TLS64_COMBINE pattern. + +2025-08-30 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/116651 + PR tree-optimization/93265 + PR tree-optimization/103647 + PR tree-optimization/52171 + * tree-ssa-forwprop.cc (simplify_builtin_memcmp): New function. + (simplify_builtin_call): Call simplify_builtin_memcmp for memcmp + memcmp_eq builtins. + +2025-08-29 Gaius Mulley <gaiusmod2@gmail.com> + + PR modula2/121709 + * doc/gm2.texi (Module Search Path): Reflect the new + search order. + +2025-08-29 David Malcolm <dmalcolm@redhat.com> + + * Makefile.in (OBJS-libcommon): Add diagnostics/logging.o. + * diagnostic-global-context.cc: Include "diagnostics/logging.h". + (log_function_params, auto_inc_log_depth): New "using" decls. + (verbatim): Add logging. + (emit_diagnostic): Likewise. + (emit_diagnostic_valist): Likewise. + (emit_diagnostic_valist_meta): Likewise. + (inform): Likewise. + (inform_n): Likewise. + (warning): Likewise. + (warning_at): Likewise. + (warning_meta): Likewise. + (warning_n): Likewise. + (pedwarn): Likewise. + (permerror): Likewise. + (permerror_opt): Likewise. + * diagnostics/context.cc: Include "diagnostics/logging.h". + (context::initialize): Initialize m_logger. Add logging. + (context::finish): Add logging. Clean up m_logger. + (context::dump): Add indent param. + (context::set_sink): Add logging. + (context::add_sink): Add logging. + (diagnostic_kind_debug_text): New. + (get_debug_string_for_kind): New. + (context::report_diagnostic): Add logging. + (context::diagnostic_impl): Likewise. + (context::diagnostic_n_impl): Likewise. + (context::end_group): Likewise. + * diagnostics/context.h: Include "diagnostics/logging.h". + (context::dump): Add indent param. + (context::get_logger): New accessor. + (context::classify_diagnostics): Add logging. + (context::push_diagnostics): Likewise. + (context::pop_diagnostics): Likewise. + (context::m_logger): New field. + * diagnostics/html-sink.cc: Include "diagnostics/logging.h". + (html_builder::flush_to_file): Add logging. + (html_sink::on_report_diagnostic): Likewise. + * diagnostics/kinds.h (get_debug_string_for_kind): New decl. + * diagnostics/logging.cc: New file. + * diagnostics/logging.h: New file. + * diagnostics/output-file.h: Include "label-text.h". + * diagnostics/sarif-sink.cc: Include "diagnostics/logging.h". + (sarif_builder::flush_to_object): Add logging. + (sarif_builder::flush_to_file): Likewise. + (sarif_sink::on_report_diagnostic): Likewise. + * diagnostics/sink.h (sink::get_logger): New. + * diagnostics/text-sink.cc: Include "diagnostics/logging.h". + (text_sink::on_report_diagnostic): Add logging. + * doc/invoke.texi (Environment Variables): Document + GCC_DIAGNOSTICS_LOG. + * opts-diagnostic.cc: Include "diagnostics/logging.h". + (handle_OPT_fdiagnostics_add_output_): Add loggging. + (handle_OPT_fdiagnostics_set_output_): Likewise. + +2025-08-29 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa-protos.h (xtensa_bswapsi2_output): + New function prototype. + * config/xtensa/xtensa.cc + (xtensa_bswapsi2_output_1, xtensa_bswapsi2_output): + New functions. + * config/xtensa/xtensa.md (bswapsi2_internal): + Rewrite in compact syntax and use xtensa_bswapsi2_output() as asm + output. + +2025-08-29 Jeff Law <jlaw@ventanamicro.com> + + PR target/121548 + * config/riscv/riscv-avlprop.cc (get_insn_vtype_mode): Assert + MODE_IDX is smaller than the number of operands. + (simplify_replace_vlmax_avl): Similarly. + (pass_avlprop::get_vlmax_ta_preferred_avl): Similarly. + * config/riscv/vector.md: Override merge_op_idx computation + for simple moves, just like is done for avl_type_idx and mode_idx. + +2025-08-29 Paul-Antoine Arras <parras@baylibre.com> + + * config/riscv/autovec-opt.md + (*vfmin_vf_ieee_<mode>): Add new patterns to combine vec_duplicate + + vfmin.vv (unspec) into vfmin.vf. + (*vfmul_vf_<mode>, *vfrdiv_vf_<mode>, *vfmin_vf_<mode>): Fix attribute + types. + * config/riscv/vector.md (@pred_<ieee_fmaxmin_op><mode>_scalar): Allow + VLS modes. + +2025-08-29 H.J. Lu <hjl.tools@gmail.com> + + PR target/121096 + * config/i386/i386-expand.cc (expand_cpymem_epilogue): Set and + clear by_pieces_in_use when using by_pieces op. + (expand_setmem_epilogue): Likewise. + * config/i386/i386.cc (ix86_use_by_pieces_infrastructure_p): New. + (TARGET_USE_BY_PIECES_INFRASTRUCTURE_P): Likewise. + * config/i386/i386.h (machine_function): Add by_pieces_in_use. + +2025-08-29 H.J. Lu <hjl.tools@gmail.com> + + PR target/121108 + * config/i386/i386-expand.cc (setmem_epilogue_gen_val): Don't + assert op_mode == word_mode and handle any integer modes. + +2025-08-29 H.J. Lu <hjl.tools@gmail.com> + + PR target/121694 + * config/i386/i386-features.cc (redundant_pattern): Add + tlsdesc_val. + (pass_x86_cse): Likewise. + (pass_x86_cse::tls_set_insn_from_symbol): New member function. + (pass_x86_cse::candidate_gnu2_tls_p): Set tlsdesc_val. For + TLS64_COMBINE, match both UNSPEC_TLSDESC and UNSPEC_DTPOFF + symbols. For TLS64_CALL, match the UNSPEC_TLSDESC sumbol. + (pass_x86_cse::x86_cse): Initialize the tlsdesc_val field in + load. Pass the tlsdesc_val field to ix86_place_single_tls_call + for X86_CSE_TLSDESC. + +2025-08-29 Tobias Burnus <tburnus@baylibre.com> + + * doc/invoke.texi (AMD GCN Options: -march): Remove '(experimental)' + from gfx-{9,10-3,11}-generic. + +2025-08-29 Tobias Burnus <tburnus@baylibre.com> + + * doc/install.texi (amdgcn): Clarify which binaries must be the + LLVM version and which must be installed. Update version data for + ROCm for generic architectures. + +2025-08-29 liuhongt <hongtao.liu@intel.com> + + * doc/invoke.texi: Document -param=ix86-vect-unroll-limit. + +2025-08-29 Pan Li <pan2.li@intel.com> + + * config/riscv/autovec-opt.md (*vnmsac_vx_<mode>): Add new + pattern to combine to vx. + * config/riscv/vector.md (@pred_vnmsac_vx_<mode>): Add new + pattern to generate rtl. + (*pred_nmsac_<mode>_scalar_undef): Ditto. + +2025-08-28 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/115201 + * passes.def: Move cleanup_eh before first tail_recursion. + +2025-08-28 Paul-Antoine Arras <parras@baylibre.com> + + * config/riscv/autovec-opt.md (*vfmin_vf_<mode>): Add new pattern to + combine vec_duplicate + vfmin.vv into vfmin.vf. + * config/riscv/vector.md (@pred_<optab><mode>_scalar): Allow VLS modes. + +2025-08-28 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vect_analyze_loop_form): Dump + niter assumption used for versioning. + +2025-08-28 Wilco Dijkstra <wilco.dijkstra@arm.com> + + PR middle-end/66462 + * config/aarch64/aarch64.md (isinf<mode>2): Add new expander. + * config/aarch64/iterators.md (mantissa_bits): Add new mode_attr. + +2025-08-28 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vectorize_fold_left_reduction): Do not get + reduc_var as argument, instead compute it here. + (vect_transform_reduction): Adjust. + +2025-08-28 Gaius Mulley <gaiusmod2@gmail.com> + + PR modula2/121629 + * doc/gm2.texi (Module Search Path): New section. + (Compiler options): New option -fm2-pathname-root=. + New option -fm2-pathname-rootI. + +2025-08-28 Tobias Burnus <tburnus@baylibre.com> + + PR debug/119367 + * acinclude.m4 (gcc_GAS_FLAGS): For gcn, use "--filetype=obj + -triple=amdgcn--amdhsa", if supported. + * configure: Regenerate. + * doc/install.texi (amdgcn-*-*): Also add llvm-objdump to the list of + to-be-copied files. + +2025-08-28 Richard Biener <rguenther@suse.de> + Jakub Jelinek <jakub@redhat.com> + + * tree-vect-patterns.cc (vect_synth_mult_by_constant): Avoid + in cases that introduce multiple uses of reduction operands. + +2025-08-28 Richard Biener <rguenther@suse.de> + + * tree-vect-patterns.cc (vect_recog_divmod_pattern): Avoid + for stmts participating in a reduction. + +2025-08-28 Jakub Jelinek <jakub@redhat.com> + + PR debug/119367 + * configure.ac (gcc_cv_as_leb128): Add fallback using readelf. + Grammar fix in comment. + * configure: Regenerate. + +2025-08-28 Jakub Jelinek <jakub@redhat.com> + + PR debug/119367 + * dwarf2out.cc (output_one_line_info_table) <case LI_adv_address>: If + HAVE_AS_LEB128, use DW_LNS_advance_pc with dw2_asm_output_delta_uleb128 + instead of DW_LNS_fixed_advance_pc with dw2_asm_output_delta. + +2025-08-27 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/121695 + * tree-if-conv.cc (factor_out_operators): Fix typo + in assignment of the phi. + +2025-08-27 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vect_transform_cycle_phi): Remove + unused reduc_stmt_info. + +2025-08-27 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121686 + * tree-vect-slp.cc (vect_analyze_slp): Consider all only-live + non-reduction defs for discovery. + +2025-08-27 H.J. Lu <hjl.tools@gmail.com> + + PR target/121668 + * config/i386/i386-features.cc (ix86_emit_tls_call): Emit the + TLS call after debug marker. + +2025-08-27 Jeff Law <jlaw@ventanamicro.com> + + * config/riscv/riscv-cores.def (xt-c908v): Drop xtheadvdot. + (xt-c910v2): Remove extraenous whitespace. + (xt-c920v2): Drop xtheadvdot and remove extraeonous whitespace. + +2025-08-26 liuhongt <hongtao.liu@intel.com> + + * config/i386/i386.cc (ix86_vector_costs::ix86_vector_costs): + Addd new memeber m_num_reduc, m_prefer_unroll. + (ix86_vector_costs::add_stmt_cost): Set m_prefer_unroll and + m_num_reduc + (ix86_vector_costs::finish_cost): Determine + m_suggested_unroll_vector with consideration of + reduc_lat_mult_thr, m_num_reduction and + ix86_vect_unroll_limit. + * config/i386/i386.h (enum ix86_reduc_unroll_factor): New + enum. + (processor_costs): Add reduc_lat_mult_thr and + vect_unroll_limit. + * config/i386/x86-tune-costs.h: Initialize + reduc_lat_mult_thr and vect_unroll_limit. + * config/i386/i386.opt: Add -param=ix86-vect-unroll-limit. + +2025-08-26 Paul-Antoine Arras <parras@baylibre.com> + + * config/riscv/autovec-opt.md (*vfrdiv_vf_<mode>): Add new pattern to + combine vec_duplicate + vfdiv.vv into vfrdiv.vf. + * config/riscv/vector.md (@pred_<optab><mode>_reverse_scalar): Allow VLS + modes. + +2025-08-26 Tamar Christina <tamar.christina@arm.com> + + PR target/121290 + * config/aarch64/aarch64.cc + (class aarch64_vector_costs ): Add m_loop_fully_scalar_dup. + (aarch64_vector_costs::add_stmt_cost): Detect invariant inner loops. + (adjust_body_cost): Adjust final costing if m_loop_fully_scalar_dup. + +2025-08-26 Paul-Antoine Arras <parras@baylibre.com> + + * config/riscv/autovec-opt.md (*vfmul_vf_<mode>): Add new pattern to + combine vec_duplicate + vfmul.vv into vfmul.vf. + * config/riscv/vector.md (@pred_<optab><mode>_scalar): Allow VLS modes. + +2025-08-26 Jeff Law <jlaw@ventanamicro.com> + + * config/riscv/riscv.cc (riscv_arg_partial_bytes): Remove name + from unused parameter. + +2025-08-26 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (vect_reduc_type): Get SLP node as argument. + * config/aarch64/aarch64.cc (aarch64_sve_in_loop_reduction_latency): + Take SLO node as argument and adjust. + (aarch64_in_loop_reduction_latency): Likewise. + (aarch64_detect_vector_stmt_subtype): Adjust. + (aarch64_vector_costs::count_ops): Likewise. Treat reductions + during scalar costing as single-cycle. + +2025-08-26 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121659 + * tree-vect-slp.cc (vect_build_slp_tree_1): Do not allow + matching up comparison operators by swapping if that would + disturb STMT_VINFO_REDUC_IDX. Make sure to only + actually mark operands for swapping when there was a + mismatch and we're not processing the first stmt. + +2025-08-26 Richard Biener <rguenther@suse.de> + + * tree-vect-stmts.cc (vectorizable_store): Access lanes_ifn + only when VMAT_LOAD_STORE_LANES. + (vectorizable_load): Likewise. + +2025-08-26 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (stmt_vec_info_::reduc_vectype_in): Remove. + (STMT_VINFO_REDUC_VECTYPE_IN): Likewise. + * tree-vect-loop.cc (vect_is_emulated_mixed_dot_prod): Get + at the input vectype via the SLP node child. + (vectorizable_lane_reducing): Likewise. + (vect_transform_reduction): Likewise. + (vectorizable_reduction): Do not set STMT_VINFO_REDUC_VECTYPE_IN. + +2025-08-26 Jakub Jelinek <jakub@redhat.com> + + PR target/121658 + * config/i386/sse.md (<insn><mode>3 any_shift): Use const0_rtx + instead of GEN_INT (0). + (cond_<insn><mode> any_shift): Likewise. Formatting fix. + (<insn><mode>3 any_rotate): Use register_operand predicate instead of + general_operand for match_operand 1. Use const0_rtx instead of + GEN_INT (0). + (<insn>v16qi3 any_rotate): Use force_reg on operands[1]. Formatting + fix. + * config/i386/i386.cc (ix86_shift_rotate_cost): Comment formatting + fixes. + +2025-08-26 Pan Li <pan2.li@intel.com> + + * config/riscv/vector.md (@pred_mul_plus_vx_<mode>): Add new pattern to + generate vmacc rtl. + (*pred_macc_<mode>_scalar_undef): Ditto. + * config/riscv/autovec-opt.md (*vmacc_vx_<mode>): Add new + pattern to match the vmacc vx combine. + +2025-08-25 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/121453 + * omp-expand.cc (expand_omp_for_init_counts): Clear fd->loop.n2 + before first zero count check if zero_iter1_bb is non-NULL upon + entry and fd->loop.n2 has not been written yet. + +2025-08-25 David Faust <david.faust@oracle.com> + + PR debug/121411 + * dwarf2ctf.cc (gen_ctf_subrange_type): Use unsigned HWI for + array_num_elements. Fallback to CTF_K_UNKNOWN if the array + type has too many elements for CTF to represent. + +2025-08-25 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-ssa-forwprop.cc (simplify_permutation): Boolify. + (pass_forwprop::execute): No longer handle 2 as the return + from simplify_permutation. + +2025-08-25 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-ssa-forwprop.cc (forward_propagate_into_comparison): Boolify. + (pass_forwprop::execute): Don't handle return of 2 from + forward_propagate_into_comparison. + +2025-08-25 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-ssa-forwprop.cc (remove_prop_source_from_use): Remove + return type. + (forward_propagate_into_comparison): Update dealing with + no return type of remove_prop_source_from_use. + (forward_propagate_into_gimple_cond): Likewise. + (simplify_permutation): Likewise. + +2025-08-25 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-ssa-forwprop.cc (simplify_gimple_switch): Add simple_dce_worklist + argument. Mark the old index when doing the replacement. + (pass_forwprop::execute): Update call to simplify_gimple_switch. + +2025-08-25 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/121279 + * gimple-fold.cc (gimple_needing_rewrite_undefined): Return + true for non mode precision boolean loads. + (rewrite_to_defined_unconditional): Handle non mode precision loads. + +2025-08-25 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * tree-ssa-loop-im.cc (execute_sm): Call + get_or_create_ssa_default_def for the new uninitialized + decl. + +2025-08-25 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (addsi3, <u>mulhisi3, andsi3, + zero_extend<mode>si2, extendhisi2_internal, movsi_internal, + movhi_internal, movqi_internal, movsf_internal, ashlsi3_internal, + ashrsi3, lshrsi3, rotlsi3, rotrsi3): + Rewrite in compact syntax. + +2025-08-25 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md + (The auxiliary define_split for *masktrue_const_bitcmpl): + Use a more concise function call, i.e., + (1 << GET_MODE_BITSIZE (mode)) - 1 is equivalent to + GET_MODE_MASK (mode). + +2025-08-25 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (mode_bits): + New mode attribute. + (zero_extend<mode>si2): Use the appropriate mode iterator and + attribute to unify "zero_extend[hq]isi2" to this description. + +2025-08-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121638 + * tree-vect-stmts.cc (process_use): Do not make induction + PHI backedge values relevant. + +2025-08-25 Indu Bhagat <indu.bhagat@oracle.com> + Claudiu Zissulescu <claudiu.zissulescu-ianculescu@oracle.com> + + * asan.h (HWASAN_TAG_SIZE): Use targetm.memtag.tag_bitsize. + * config/i386/i386.cc (ix86_memtag_tag_size): Rename to + ix86_memtag_tag_bitsize. + (TARGET_MEMTAG_TAG_SIZE): Renamed to TARGET_MEMTAG_TAG_BITSIZE. + * doc/tm.texi (TARGET_MEMTAG_TAG_SIZE): Likewise. + * doc/tm.texi.in (TARGET_MEMTAG_TAG_SIZE): Likewise. + * target.def (tag_size): Rename to tag_bitsize. + * targhooks.cc (default_memtag_tag_size): Rename to + default_memtag_tag_bitsize. + * targhooks.h (default_memtag_tag_size): Likewise. + +2025-08-25 Kito Cheng <kito.cheng@sifive.com> + + * config/riscv/riscv-protos.h (riscv_init_cumulative_args): Change + fntype parameter from tree to const_tree. + * config/riscv/riscv.cc (riscv_init_cumulative_args): Likewise. + (riscv_function_value): Replace with new implementation that + conforms to TARGET_FUNCTION_VALUE hook signature. + (riscv_libcall_value): New function implementing TARGET_LIBCALL_VALUE. + (TARGET_FUNCTION_VALUE): Define. + (TARGET_LIBCALL_VALUE): Define. + * config/riscv/riscv.h (FUNCTION_VALUE): Remove. + (LIBCALL_VALUE): Remove. + +2025-08-25 Andi Kleen <ak@gcc.gnu.org> + + * config/i386/i386-expand.cc (ix86_vgf2p8affine_shift_matrix): + New function to lookup shift/rotate matrixes for gf2p8affine. + * config/i386/i386-protos.h (ix86_vgf2p8affine_shift_matrix): + Declare new function. + * config/i386/i386.cc (ix86_shift_rotate_cost): Add cost model + for shift/rotate implemented using gf2p8affine. + * config/i386/sse.md (VI1_AVX512_3264): New mode iterator. + (<insn><mode>3): Add GFNI case for shift patterns. + (cond_<insn><mode>3): New pattern. + (<insn><mode>3<mask_name>): Dito. + (<insn>v16qi): New rotate pattern to handle XOP V16QI case + and GFNI. + (rotl<mode>3, rotr<mode>3): Exclude V16QI case. + +2025-08-25 Xi Ruoyao <xry111@xry111.site> + + PR target/121634 + * config/loongarch/simd.md (simd_maddw_evod_<mode>_<su>): Use + WVEC_HALF instead of WVEC for the mode of the sign_extend for + the rhs of multiplication. + +2025-08-25 Jeff Law <jlaw@ventanamicro.com> + + * ifcvt.cc (noce_try_sign_bit_splat): Fix right shift computation. + +2025-08-23 Sam James <sam@gentoo.org> + + PR target/120933 + * config.gcc (supported_defaults): Add tls for i386, x86_64. + * config/i386/i386.h (OPTION_DEFAULT_SPECS): Add tls. + * doc/install.texi: Document --with-tls= for i386, x86_64. + +2025-08-23 John Ericson <git@JohnEricson.me> + + * gcc.cc (for_each_path): templated, to make passing lambdas + possible/easy/safe, and to have a polymorphic return type. + (struct add_to_obstack_info): Deleted, lambda captures replace + it. + (add_to_obstack): Moved to lambda in build_search_list. + (build_search_list): Has above lambda now. + (struct file_at_path_info): Deleted, lambda captures replace + it. + (file_at_path): Moved to lambda in find_a_file. + (find_a_file): Has above lambda now. + (struct spec_path_info): Reamed to just struct spec_path. + (struct spec_path): New name. + (spec_path): Rnamed to spec_path::operator() + (spec_path::operator()): New name + (do_spec_1): Updated for_each_path call sites. + +2025-08-22 Kishan Parmar <kishan@linux.ibm.com> + + PR target/118890 + * config/rs6000/rs6000.cc (can_be_rotated_to_negative_lis): Add bounds + checks for shift counts to prevent undefined behavior. + (rs6000_emit_set_long_const): Likewise. + +2025-08-22 Jeff Law <jlaw@ventanamicro.com> + + PR rtl-optimization/120553 + * ifcvt.cc (noce_try_sign_bit_splat): New function. + (noce_process_if_block): Use it. + +2025-08-22 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vectorizable_live_operation): Pass + the representative of the PHIs node to + vect_create_epilog_for_reduction. + +2025-08-22 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vectorizable_lane_reducing): Get + reduction info properly. Adjust checks according to + comments. + (vectorizable_reduction): Do not set STMT_VINFO_REDUC_VECTYPE_IN + on the reduc info. + (vect_transform_reduction): Query STMT_VINFO_REDUC_VECTYPE_IN + on the actual reduction stmt, not the info. + +2025-08-22 Pan Li <pan2.li@intel.com> + + * match.pd: Add form 3 for unsigned SAT_MUL. + +2025-08-22 H.J. Lu <hjl.tools@gmail.com> + + PR target/121635 + * config/i386/i386-features.cc (ix86_emit_tls_call): Emit the + TLS call after NOTE_INSN_FUNCTION_BEG. + +2025-08-22 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (get_initial_defs_for_reduction): Adjust + comment. + (vect_create_epilog_for_reduction): Get at the reduction + kind via the instance, re-use the slp_reduc flag instead + of checking REDUC_GROUP_FIRST_ELEMENT again. + Remove unreachable code. + (vectorizable_reduction): Compute a reduc_chain flag from + the SLP instance kind, avoid REDUC_GROUP_FIRST_ELEMENT + checks. + (vect_transform_cycle_phi): Likewise. + (vectorizable_live_operation): Check the SLP instance + kind instead of REDUC_GROUP_FIRST_ELEMENT. + +2025-08-22 Richard Biener <rguenther@suse.de> + + * tree-parloops.cc (parloops_is_simple_reduction): Pass + in double reduction inner loop LC phis and query that. + (parloops_force_simple_reduction): Similar, but set it. + Check for valid reduction types here. + (valid_reduction_p): Remove. + (gather_scalar_reductions): Adjust, fixup double + reduction inner loop processing. + +2025-08-22 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * config/riscv/t-rtems: Add -mstrict-align multilibs for + targets without support for misaligned access in hardware. + +2025-08-21 Dimitar Dimitrov <dimitar@dinux.eu> + + * config/pru/pru.cc (pru_init_libfuncs): Set softmpy libgcc + functions for optab multiplication entries if TARGET_OPT_MUL + option is not set. + +2025-08-21 Dimitar Dimitrov <dimitar@dinux.eu> + + * config.gcc: Include pru/t-multilib. + * config/pru/pru.h (MULTILIB_DEFAULTS): Define. + * config/pru/t-multilib: New file. + +2025-08-21 Dimitar Dimitrov <dimitar@dinux.eu> + + * common/config/pru/pru-common.cc (TARGET_DEFAULT_TARGET_FLAGS): + Keep multiplication, FILL and ZERO instructions enabled by + default. + * config/pru/pru.md (prumov<mode>): Gate code generation on + TARGET_OPT_FILLZERO. + (mov<mode>): Ditto. + (zero_extendqidi2): Ditto. + (zero_extendhidi2): Ditto. + (zero_extendsidi2): Ditto. + (@pru_ior_fillbytes<mode>): Ditto. + (@pru_and_zerobytes<mode>): Ditto. + (@<code>di3): Ditto. + (mulsi3): Gate code generation on TARGET_OPT_MUL. + * config/pru/pru.opt: Add mmul and mfillzero options. + * config/pru/pru.opt.urls: Regenerate. + * config/rl78/rl78.opt.urls: Regenerate. + * doc/invoke.texi: Document new options. + +2025-08-21 Richard Sandiford <richard.sandiford@arm.com> + + PR rtl-optimization/121619 + * rtl-ssa/functions.h (function_info::commit_make_use_available): + Declare. + * rtl-ssa/blocks.cc (function_info::commit_make_use_available): + New function. + * rtl-ssa/changes.cc (function_info::apply_changes_to_insn): Use it. + +2025-08-21 Richard Biener <rguenther@suse.de> + + PR tree-optimization/111494 + * gimple-fold.h (arith_code_with_undefined_signed_overflow): Declare. + * gimple-fold.cc (arith_code_with_undefined_signed_overflow): Export. + * tree-vect-stmts.cc (vectorizable_operation): Use unsigned + arithmetic for operations participating in a reduction. + +2025-08-21 H.J. Lu <hjl.tools@gmail.com> + + PR target/121607 + * config/i386/i386-features.cc (ix86_emit_tls_call): Emit the + TLS call after NOTE_INSN_BASIC_BLOCK in a basic block with only + a label. + +2025-08-21 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (*btrue_INT_MIN): + Change the branch insn condition to test for a negative number + rather than testing for the MSB. + +2025-08-21 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (vectorizable_phi): Take bb_vec_info. + (vectorizable_early_exit): Take loop_vec_info. + * tree-vect-loop.cc (vectorizable_phi): Adjust. + * tree-vect-slp.cc (vect_slp_analyze_operations): Likewise. + (vectorize_slp_instance_root_stmt): Likewise. + * tree-vect-stmts.cc (vectorizable_early_exit): Likewise. + (vect_transform_stmt): Likewise. + (vect_analyze_stmt): Merge the sequences of vectorizable_* + where common. + +2025-08-20 Qing Zhao <qing.zhao@oracle.com> + + * common.opt.urls: Regenerate. + +2025-08-20 Qing Zhao <qing.zhao@oracle.com> + + PR tree-optimization/109071 + PR tree-optimization/85788 + PR tree-optimization/88771 + PR tree-optimization/106762 + PR tree-optimization/108770 + PR tree-optimization/115274 + PR tree-optimization/117179 + * Makefile.in (OBJS): Add diagnostic-context-rich-location.o. + * common.opt (fdiagnostics-show-context): New option. + (fdiagnostics-show-context=): New option. + * diagnostic-context-rich-location.cc: New file. + * diagnostic-context-rich-location.h: New file. + * doc/invoke.texi (fdiagnostics-details): Add + documentation for the new options. + * gimple-array-bounds.cc (check_out_of_bounds_and_warn): Add + one new parameter. Use rich location with details for warning_at. + (array_bounds_checker::check_array_ref): Use rich location with + ditails for warning_at. + (array_bounds_checker::check_mem_ref): Add one new parameter. + Use rich location with details for warning_at. + (array_bounds_checker::check_addr_expr): Use rich location with + move_history_diagnostic_path for warning_at. + (array_bounds_checker::check_array_bounds): Call check_mem_ref with + one more parameter. + * gimple-array-bounds.h: Update prototype for check_mem_ref. + * gimple-ssa-warn-access.cc (warn_string_no_nul): Use rich location + with details for warning_at. + (maybe_warn_nonstring_arg): Likewise. + (maybe_warn_for_bound): Likewise. + (warn_for_access): Likewise. + (check_access): Likewise. + (pass_waccess::check_strncat): Likewise. + (pass_waccess::maybe_check_access_sizes): Likewise. + * gimple-ssa-warn-restrict.cc (pass_wrestrict::execute): Calculate + dominance info for diagnostics show context. + (maybe_diag_overlap): Use rich location with details for warning_at. + (maybe_diag_access_bounds): Use rich location with details for + warning_at. + +2025-08-20 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/121568 + * ipa-prop.h (build_ref_for_offset): Remove. + * tree-sra.cc (build_ref_for_offset): Make static. + +2025-08-20 Richard Sandiford <richard.sandiford@arm.com> + + * config.gcc (aarch64*-*-*): Remove aarch64-cc-fusion.o from + extra_objs. + * config/aarch64/aarch64-passes.def (pass_cc_fusion): Delete. + * config/aarch64/aarch64-protos.h (make_pass_cc_fusion): Delete. + * config/aarch64/t-aarch64 (aarch64-cc-fusion.o): Delete. + * config/aarch64/aarch64-cc-fusion.cc: Delete. + * late-combine.cc (late_combine::optimizable_set): Take a set_info * + rather than an insn_info * and move destination tests from... + (late_combine::combine_into_uses): ...here. Take a set_info * rather + an insn_info *. Take the rtx set. + (late_combine::parallelize_insns, late_combine::combine_cc_setter) + (late_combine::combine_insn): New member functions. + (late_combine::m_parallel): New member variable. + * rtlanal.cc (pattern_cost): Handle sets of CC registers in the + same way as comparisons. + +2025-08-20 Richard Sandiford <richard.sandiford@arm.com> + + * rtl-ssa/blocks.cc (function_info::create_degenerate_phi): Fix + inverted test of bitmap_set_bit. Call add_live_out_use even + if the register was previously live-out from the predecessor block. + Instead... + (function_info::add_live_out_use): ...check here whether a live-out + use already exists. + +2025-08-20 Richard Sandiford <richard.sandiford@arm.com> + + * rtl-ssa/accesses.h (use_lookup): New class. + * rtl-ssa/functions.h (function_info::find_def): Expand comment. + (function_info::find_use): Declare. + * rtl-ssa/member-fns.inl (use_lookup::prev_use, use_lookup::next_use) + (use_lookup::matching_use, use_lookup::matching_or_prev_use) + (use_lookup::matching_or_next_use): New member functions. + * rtl-ssa/accesses.cc (function_info::find_use): Likewise. + +2025-08-20 Richard Biener <rguenther@suse.de> + + PR tree-optimization/114480 + * cfganal.cc (compute_idf): Split processing of the initial + workset from the main iteration. Use a vector for the + workset of the main iteration. + +2025-08-20 Georg-Johann Lay <avr@gjlay.de> + + PR target/121608 + * config/avr/specs.h (LINK_RELAX_SPEC): Wrap in %{!r...}. + +2025-08-20 Richard Biener <rguenther@suse.de> + + * tree-vect-slp.cc (vect_analyze_slp_reduc_chain): New, + copied from vect_analyze_slp_instance and only handle + slp_inst_kind_reduc_chain. Inline vect_build_slp_instance. + (vect_analyze_slp_instance): Only handle slp_inst_kind_store. + Inline vect_build_slp_instance. + (vect_build_slp_instance): Remove now unused stmt_info parameter, + remove special code for store groups and reduction chains. + (vect_analyze_slp): Call vect_analyze_slp_reduc_chain + for reduction chain SLP build and adjust. + +2025-08-20 Richard Biener <rguenther@suse.de> + + * tree-vect-data-refs.cc (vect_check_gather_scatter): + Remove restriction on epilogue of epilogue vectorization. + +2025-08-20 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (update_epilogue_loop_vinfo): Remove + fixing up pattern stmt operands and gather/scatter DR_REFs. + (find_in_mapping): Remove. + +2025-08-20 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (vect_load_store_data): New. + (_slp_tree::memory_access_type): Remove. + (SLP_TREE_MEMORY_ACCESS_TYPE): Turn into inline function. + * tree-vect-slp.cc (_slp_tree::_slp_tree): Do not + initialize SLP_TREE_MEMORY_ACCESS_TYPE. + * tree-vect-stmts.cc (check_load_store_for_partial_vectors): + Remove gather_scatter_info pointer argument, instead get + info from the SLP node. + (vect_build_one_gather_load_call): Get SLP node and builtin + decl as argument and remove uses of gather_scatter_info. + (vect_build_one_scatter_store_call): Likewise. + (vect_get_gather_scatter_ops): Remove uses of gather_scatter_info. + (vect_get_strided_load_store_ops): Get SLP node and remove + uses of gather_scatter_info. + (get_load_store_type): Take pointer to vect_load_store_data + instead of individual pointers. + (vectorizable_store): Adjust. Re-use get_load_store_type + result from analysis time. + (vectorizable_load): Likewise. + +2025-08-20 H.J. Lu <hjl.tools@gmail.com> + + PR target/121572 + * config/i386/i386-features.cc (replace_tls_call): Add a bitmap + argument and put the updated TLS instruction in the bitmap. + (ix86_get_dominator_for_reg): New. + (ix86_check_flags_reg): Likewise. + (ix86_emit_tls_call): Likewise. + (ix86_place_single_tls_call): Add 2 bitmap arguments for updated + GNU and GNU2 TLS instructions. Call ix86_emit_tls_call to emit + TLS instruction. Correct debug dump for before instruction. + +2025-08-19 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR middle-end/120024 + * calls.cc (expand_call): Remove start_sequence/end_sequence + for ECF_MALLOC. + Check valreg before deferencing it when it comes to malloc like + functions. Use the return value of emit_move_insn instead of + calling get_last_insn. + +2025-08-19 Richard Biener <rguenther@suse.de> + + * tree-parloops.cc (parloops_is_slp_reduction): Remove. + (parloops_is_simple_reduction): Do not call it. + +2025-08-19 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vectorizable_reduction): Pass the + appropriate SLP node for costing of single-def-use-cycle + operations. + (vectorizable_live_operation): Pass the SLP node to the + costing hook. + * tree-vect-stmts.cc (vectorizable_bswap): Likewise. + (vectorizable_store): Likewise. + +2025-08-19 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121592 + * tree-vect-slp.cc (vect_analyze_slp): When SLP reduction chain + discovery fails, fail overall when the tail of the chain + isn't also the entry for the non-SLP reduction. + +2025-08-19 Richard Biener <rguenther@suse.de> + + * config.gcc (riscv*-*-*): Look for python3, then fall back + to python. Never use python2. + +2025-08-19 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121527 + * tree-sra.cc (build_access_from_expr_1): Do not strip an + outer VIEW_CONVERT_EXPR as it's relevant for the size of + the access. + (get_access_for_expr): Likewise. + +2025-08-19 Tamar Christina <tamar.christina@arm.com> + + PR target/121536 + * config/aarch64/aarch64.cc (aarch64_bool_compound_p): Use + SLP_TREE_VECTYPE instead of STMT_VINFO_VECTYPE. + (aarch64_adjust_stmt_cost, aarch64_vector_costs::count_ops): Pass SLP + node to aarch64_bool_compound_p. + +2025-08-19 Tamar Christina <tamar.christina@arm.com> + + PR target/121536 + * tree-vect-loop.cc (vectorizable_phi, vectorizable_recurr, + vectorizable_nonlinear_induction, vectorizable_induction): Pass slp_node + instead of stmt_info to record_stmt_cost. + +2025-08-19 Tamar Christina <tamar.christina@arm.com> + + PR target/121536 + * config/aarch64/aarch64.cc (aarch64_vector_costs::add_stmt_cost): Set + vectype from type of lhs of gimple stmt. + +2025-08-18 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR middle-end/121581 + * doc/extend.texi (__builtin_object_size): Fix example. + +2025-08-18 Indu Bhagat <indu.bhagat@oracle.com> + + * flag-types.h (sanitize_code_type): Define. + * asan.h (sanitize_flags_p): Use 'sanitize_code_type' instead of + 'unsigned int'. + * common.opt: Likewise. + * dwarf2asm.cc (dw2_output_indirect_constant_1): Likewise. + * opts.cc (find_sanitizer_argument): Likewise. + (report_conflicting_sanitizer_options): Likewise. + (parse_sanitizer_options): Likewise. + (parse_no_sanitize_attribute): Likewise. + * opts.h (parse_sanitizer_options): Likewise. + (parse_no_sanitize_attribute): Likewise. + * tree-cfg.cc (print_no_sanitize_attr_value): Likewise. + * tree.cc (tree_fits_sanitize_code_type_p): Define. + (tree_to_sanitize_code_type): Likewise. + * tree.h (tree_fits_sanitize_code_type_p): Declare. + (tree_to_sanitize_code_type): Likewise. + +2025-08-18 Indu Bhagat <indu.bhagat@oracle.com> + + * config/aarch64/aarch64.md (MEMTAG_TAG_MASK): New define + constant. + (MEMTAG_ADDR_MASK): Likewise. + (irg, subp, ldg): Use new constants. + +2025-08-18 Richard Sandiford <richard.sandiford@arm.com> + + PR rtl-optimization/97497 + * function-abi.h (predefined_function_abi::only_partial_reg_clobbers) + (function_abi::only_partial_reg_clobbers): New member functions. + * gcse-common.cc: Include regs.h and function-abi.h. + (compute_transp): Check for partially call-clobbered registers + and treat them as not being transparent in blocks with calls. + +2025-08-18 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/sync.md (UNSPEC_TI_FETCH_ADD): New unspec. + (UNSPEC_TI_FETCH_SUB): Likewise. + (UNSPEC_TI_FETCH_AND): Likewise. + (UNSPEC_TI_FETCH_XOR): Likewise. + (UNSPEC_TI_FETCH_OR): Likewise. + (UNSPEC_TI_FETCH_NAND_MASK_INVERTED): Likewise. + (ALL_SC): New define_mode_iterator. + (_scq): New define_mode_attr. + (atomic_fetch_nand<mode>): Accept ALL_SC instead of only GPR. + (UNSPEC_TI_FETCH_DIRECT): New define_int_iterator. + (UNSPEC_TI_FETCH): New define_int_iterator. + (amop_ti_fetch): New define_int_attr. + (size_ti_fetch): New define_int_attr. + (atomic_fetch_<amop_ti_fetch>ti_scq): New define_insn. + (atomic_fetch_<amop_ti_fetch>ti): New define_expand. + +2025-08-18 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/sync.md (atomic_exchangeti_scq): New + define_insn. + (atomic_exchangeti): New define_expand. + +2025-08-18 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/sync.md (atomic_compare_and_swapti_scq): New + define_insn. + (atomic_compare_and_swapti): New define_expand. + +2025-08-18 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch.cc (loongarch_print_operand_reloc): + Accept "%t" for printing the number of the 64-bit machine + register holding the upper half of a TImode. + * config/loongarch/sync.md (atomic_storeti_scq): New + define_insn. + (atomic_storeti): expand to atomic_storeti_scq if !ISA_HAS_LSX. + +2025-08-18 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/genopts/isa-evolution.in (scq): New evolution + feature. + * config/loongarch/loongarch-evolution.cc: Regenerate. + * config/loongarch/loongarch-evolution.h: Regenerate. + * config/loongarch/loongarch-str.h: Regenerate. + * config/loongarch/loongarch.opt: Regenerate. + * config/loongarch/loongarch.opt.urls: Regenerate. + * config/loongarch/loongarch-def.cc: Make -mscq the default for + -march=la664 and -march=la64v1.1. + * doc/invoke.texi (LoongArch Options): Document -m[no-]scq. + +2025-08-18 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/sync.md (atomic_storeti_lsx): New + define_insn. + (atomic_storeti): New define_expand. + +2025-08-18 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/sync.md (atomic_loadti_lsx): New define_insn. + (atomic_loadti): New define_expand. + +2025-08-18 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/sync.md + (atomic_fetch_nand_mask_inverted<GPR:mode>): New define_insn. + (atomic_fetch_nand<GPR:mode>): New define_expand. + +2025-08-18 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/sync.md (atomic_fetch_sub<SHORT:mode>): + Disable if ISA_HAS_LAM_BH. + +2025-08-18 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/sync.md (UNSPEC_COMPARE_AND_SWAP_AND): + Remove. + (UNSPEC_COMPARE_AND_SWAP_XOR): Remove. + (UNSPEC_COMPARE_AND_SWAP_OR): Remove. + (atomic_test_and_set): Rename to ... + (atomic_fetch_<any_bitwise:amop><SHORT:mode>): ... this, and + adapt the expansion to use it for any bitwise operations and any + val, instead of just ior 1. + (atomic_test_and_set): New define_expand. + +2025-08-18 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/sync.md (atomic_test_and_set): Remove + unneeded andi instruction from the expansion. + +2025-08-18 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch.cc (loongarch_print_operand_reloc): + Make "%T" output a comment marker if the operand is a memory + order for which the barrier won't be generated; remove "%t". + * config/loongarch/sync.md (atomic_cas_value_strong<mode>): Add + %T before "b 3f". + (atomic_cas_value_cmp_and_7_<mode>): Likewise. + +2025-08-18 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/sync.md (UNSPEC_COMPARE_AND_SWAP_AMCAS): New + UNSPEC code. + (atomic_cas_value_strong<mode>): NFC, update the comment to note + we only need to consider failure memory order. + (atomic_cas_value_strong<mode>_amcas): Use + UNSPEC_COMPARE_AND_SWAP_AMCAS instead of + UNSPEC_COMPARE_AND_SWAP. + (atomic_compare_and_swap<mode:GPR>): Pass failure memorder to + gen_atomic_cas_value_strong<mode>. + (atomic_compare_and_swap<mode:SHORT>): Pass failure memorder to + gen_atomic_cas_value_cmp_and_7_si. + +2025-08-18 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/sync.md (atomic_test_and_set): Use bstrins + for masking the address if possible. + +2025-08-18 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/sync.md (atomic_load<mode>): Remove "+" for + the memory operand. + (atomic_store<mode>): Use "=" instead of "+" for the memory + operand. + +2025-08-18 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/sync.md: Use <size> instead of <amo>. + (amo): Remove. + +2025-08-18 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/sync.md (atomic_optab): Remove. + (atomic_<atomic_optab><mode>): Change atomic_optab to amop. + (atomic_fetch_<atomic_optab><mode>): Likewise. + +2025-08-17 Austin Law <austinklaw@gmail.com> + + PR target/121213 + * config/riscv/sync.md (amo_atomic_exchange<mode>): Allow + (const_int 0) as input operand. Do not tie input to output. + No longer earlyclobber the output. + +2025-08-17 Artemiy Volkov <artemiyv@acm.org> + + * regrename.cc (scan_rtx_reg): Handle fused insn pairs. + +2025-08-17 Jan Dubiec <jdx@o2.pl> + + PR target/109324 + * config/h8300/addsub.md: Explicitly specify mode for plus operation. + * config/h8300/jumpcall.md: Explicitly specify modes for eq and + match_operand operations. + * config/h8300/testcompare.md: Explicitly specify modes for eq, ltu + and compare operations. + +2025-08-17 Artemiy Volkov <artemiyv@acm.org> + + * ira-conflicts.cc (add_insn_allocno_copies): Handle fused insn pairs. + * rtl.h (single_output_fused_pair_p): Declare new function. + * rtlanal.cc (single_output_fused_pair_p): Define it. + +2025-08-17 Dimitar Dimitrov <dimitar@dinux.eu> + + PR target/121538 + * config/riscv/arch-canonicalize (parse_dep_exts): + Match condition block up to closing brace. + (test_parse_long_condition_block): New test. + +2025-08-17 H.J. Lu <hjl.tools@gmail.com> + + PR target/121541 + * config/i386/i386-options.cc + (ix86_valid_target_attribute_inner_p): Add target("80387") + attribute. Set the mask bit in opts_set->x_target_flags if the + mask bit in opts->x_target_flags is updated. + * doc/extend.texi: Document target("80387") function attribute. + +2025-08-17 Pan Li <pan2.li@intel.com> + + * config/riscv/autovec-opt.md: Add supported insn + of vx combine. + +2025-08-17 Pan Li <pan2.li@intel.com> + + * config/riscv/autovec-opt.md: Add missed DONE + for vx combine pattern. + +2025-08-15 Jakub Jelinek <jakub@redhat.com> + + * doc/extend.texi (Type Traits): Document + __builtin_structured_binding_size. + +2025-08-15 Jakub Jelinek <jakub@redhat.com> + + PR c++/121552 + * doc/invoke.texi (-Wno-non-c-typedef-for-linkage): Document. + +2025-08-15 Robert Dubner <rdubner@symas.com> + + * real.cc (real_to_decimal_for_mode): Set str[0] to known value. + +2025-08-15 Vineet Gupta <vineetg@rivosinc.com> + + PR target/121534 + * config/riscv/riscv.md (round_pattern): save/restore fflags. + +2025-08-15 Qing Zhao <qing.zhao@oracle.com> + + * doc/extend.texi: Extend counted_by attribute to pointer fields in + structures. Add one more requirement to pointers with counted_by + attribute. + +2025-08-15 Umesh Kalappa <ukalappa.mips@gmail.com> + + * config/riscv/riscv-ext-mips.def (DEFINE_RISCV_EXT): + Added mips prefetch extension. + * config/riscv/riscv-ext.opt: Generated file. + * config/riscv/riscv.md (prefetch): + Added mips prefetch address operand constraint. + * config/riscv/constraints.md: Added mips specific constraint. + * config/riscv/predicates.md (prefetch_operand): + Updated for mips nine bits offset. + * config/riscv/riscv.cc (riscv_prefetch_offset_address_p): + Legitimate address with offset for prefetch check. + * config/riscv/riscv-protos.h: Likewise. + * config/riscv/riscv.h: + Macros to support for mips cached type. + * doc/riscv-ext.texi: Updated for mips prefetch. + +2025-08-15 Richard Sandiford <richard.sandiford@arm.com> + + * config/riscv/riscv-protos.h + (riscv_process_target_version_attr): Change location_t argument + to location_t *. + * config/riscv/riscv-subset.h + (riscv_subset_list::riscv_subset_list): Change location_t argument + to location_t *. + (riscv_subset_list::parse): Likwise. + (riscv_subset_list::set_loc): Likewise. + (riscv_minimal_hwprobe_feature_bits): Likewise. + (riscv_subset_list::m_loc): Change type to location_t. + * common/config/riscv/riscv-common.cc + (riscv_subset_list::riscv_subset_list): Change location_t argument + to location_t *. + (riscv_subset_list::add): Suppress diagnostics when m_loc is null. + (riscv_subset_list::parsing_subset_version): Likewise. + (riscv_subset_list::parse_profiles): Likewise. + (riscv_subset_list::parse_base_ext): Likewise. + (riscv_subset_list::parse_single_std_ext): Likewise. + (riscv_subset_list::check_conflict_ext): Likewise. + (riscv_subset_list::parse_single_multiletter_ext): Likewise. + (riscv_subset_list::parse): Change location_t argument to location_t *. + (riscv_subset_list::set_loc): Likewise. + (riscv_minimal_hwprobe_feature_bits): Likewise. + (riscv_parse_arch_string): Update call accordingly. + * config/riscv/riscv-target-attr.cc + (riscv_target_attr_parser::m_loc): Change type to location_t *. + (riscv_target_attr_parser::riscv_target_attr_parser): Change + location_t argument to location_t *. + (riscv_process_one_target_attr): Likewise. + (riscv_process_target_attr): Likewise. + (riscv_process_target_version_attr): Likewise. + (riscv_target_attr_parser::parse_arch): Suppress diagnostics when + m_loc is null. + (riscv_target_attr_parser::handle_arch): Likewise. + (riscv_target_attr_parser::handle_cpu): Likewise. + (riscv_target_attr_parser::handle_tune): Likewise. + (riscv_target_attr_parser::handle_priority): Likewise. + (riscv_option_valid_attribute_p): Update call accordingly. + (riscv_option_valid_version_attribute_p): Likewise. + * config/riscv/riscv.cc (parse_features_for_version): Add a + location_t * argument. + (dispatch_function_versions): Update call accordingly. + (riscv_compare_version_priority): Likewise, suppressing diagnostics. + +2025-08-15 Kito Cheng <kito.cheng@sifive.com> + + * tree-nrv.cc (pass_return_slot::execute): Use + gimple_call_fntype instead of gimple_call_fndecl. + +2025-08-15 Lulu Cheng <chenglulu@loongson.cn> + + PR target/121542 + * config/loongarch/loongarch.cc + (loongarch_vector_costs::add_stmt_cost): When using vectype, + first determine whether it is NULL. + +2025-08-14 Jeff Law <jlaw@ventanamicro.com> + + PR target/119275 + * config/riscv/riscv.cc (riscv_legitimize_move): Avoid calling + gen_lowpart for cases where it'll fail. Just use standard expander + paths for those cases. + +2025-08-14 Mikael Pettersson <mikpelinux@gmail.com> + + PR target/121336 + * config/cris/cris.h: Do not abbreviate --emulation. + +2025-08-14 Richard Sandiford <richard.sandiford@arm.com> + + PR target/121501 + * config/rs6000/rs6000.md (cmprb, setb_signed, setb_unsigned) + (cmprb2, cmpeqb): Add missing modes to nested if_then_elses. + +2025-08-14 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/121474 + * passes.def: Update forwprop1/2 to have full_walk to be true. + * tree-ssa-forwprop.cc (optimize_aggr_zeroprop): Add new argument + full_walk. Take into account the full_walk and clobbers at the end + of the limit can be done always. + (simplify_builtin_call): Add new argument, full_walk. + Update call to optimize_aggr_zeroprop. + (pass_forwprop): Add m_full_walk field. + (pass_forwprop::set_pass_param): Update for m_full_walk. + (pass_forwprop::execute): Update call to simplify_builtin_call + and optimize_aggr_zeroprop. + +2025-08-14 Andrew Pinski <quic_apinski@quicinc.com> + + * tree-ssa-forwprop.cc (optimize_agr_copyprop_1): New function split out of ... + (optimize_agr_copyprop): Here. Also try calling optimize_agr_copyprop_arg. + (optimize_agr_copyprop_arg): New function. + +2025-08-14 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> + + * config/s390/s390.md: Merge movdi<mode>_zero_extend_A and + movsi<mode>_zero_extend_A into zero_extendsidi2 and + zero_extendhi<mode>2_z10 and + zero_extend<HQI:mode><GPR:mode>2_extimm. + * config/s390/vector.md (*movdi<mode>_zero_extend_A): Remove. + (*movsi<mode>_zero_extend_A): Remove. + (*movdi<mode>_zero_extend_B): Move to vec_extract patterns and + rename to *vec_extract<mode>_zero_extend. + (*movsi<mode>_zero_extend_B): Ditto. + +2025-08-14 H.J. Lu <hjl.tools@gmail.com> + + PR target/121540 + * config/i386/i386-options.cc (ix86_set_current_function): + Properly check if MMX and 80387 are enabled. + +2025-08-13 Jeff Law <jlaw@ventanamicro.com> + + PR target/121531 + * config/riscv/sifive-p400.md (sifive_p400_unknown): New reservation. + * config/riscv/sifive-p600.md (sifive_p600_unkonwn): Likewise. + +2025-08-13 David Malcolm <dmalcolm@redhat.com> + + * diagnostics/output-spec.cc (sarif_scheme_handler::make_sink): + Populate sarif_generation_options instance directly, rather than + through local variables. + (sarif_scheme_handler::make_sarif_gen_opts): Drop. + (html_scheme_handler::make_sink): Populate html_generation_options + instance directly, rather than through local variables. + +2025-08-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + * config.gcc: Mark epiphany*-*-* and rl78*-*-* as + obsolete targets. + +2025-08-13 H.J. Lu <hjl.tools@gmail.com> + + PR target/81501 + * config/i386/i386-features.cc (x86_cse_kind): Add X86_CSE_TLS_GD, + X86_CSE_TLS_LD_BASE and X86_CSE_TLSDESC. + (redundant_load): Renamed to ... + (redundant_pattern): This. + (ix86_place_single_vector_set): Replace redundant_load with + redundant_pattern. + (replace_tls_call): New. + (ix86_place_single_tls_call): Likewise. + (pass_remove_redundant_vector_load): Renamed to ... + (pass_x86_cse): This. Add val, def_insn, mode, scalar_mode, kind, + x86_cse, candidate_gnu_tls_p, candidate_gnu2_tls_p and + candidate_vector_p. + (pass_x86_cse::candidate_gnu_tls_p): New. + (pass_x86_cse::candidate_gnu2_tls_p): Likewise. + (pass_x86_cse::candidate_vector_p): Likewise. + (remove_redundant_vector_load): Renamed to ... + (pass_x86_cse::x86_cse): This. Extend to remove redundant TLS + calls. + (make_pass_remove_redundant_vector_load): Renamed to ... + (make_pass_x86_cse): This. + * config/i386/i386-passes.def: Replace + pass_remove_redundant_vector_load with pass_x86_cse. + * config/i386/i386-protos.h (ix86_tls_get_addr): New. + (make_pass_remove_redundant_vector_load): Renamed to ... + (make_pass_x86_cse): This. + * config/i386/i386.cc (ix86_tls_get_addr): Remove static. + * config/i386/i386.h (machine_function): Add + tls_descriptor_call_multiple_p. + * config/i386/i386.md (tls64): New attribute. + (@tls_global_dynamic_64_<mode>): Set tls_descriptor_call_multiple_p. + (@tls_local_dynamic_base_64_<mode>): Likewise. + (@tls_dynamic_gnu2_64_<mode>): Likewise. + (*tls_global_dynamic_64_<mode>): Set tls64 attribute to gd. + (*tls_local_dynamic_base_64_<mode>): Set tls64 attribute to ld_base. + (*tls_dynamic_gnu2_lea_64_<mode>): Set tls64 attribute to lea. + (*tls_dynamic_gnu2_call_64_<mode>): Set tls64 attribute to call. + (*tls_dynamic_gnu2_combine_64_<mode>): Set tls64 attribute to + combine. + +2025-08-13 Iain Sandoe <iain@sandoe.co.uk> + + * config.in: Regenerate. + * config/darwin.h (DARWIN_LD_NO_DEDUPLICATE): New. + (LINK_SPEC): Handle -no_deduplicate. + * configure: Regenerate. + * configure.ac: Detect linker support for -no_deduplicate. + +2025-08-13 Iain Sandoe <iain@sandoe.co.uk> + + * config/darwin-sections.def (asan_string_section, + asan_globals_section, asan_liveness_section): New. + * config/darwin.cc (objc_method_decl): Use asan sections + when asan is enabled. + (darwin_encode_section_info): Alter string constant + linker visibility depending on asan. + (machopic_select_section): Use the asan sections when + asan is enabled. + +2025-08-13 Jeff Law <jlaw@ventanamicro.com> + + PR target/121160 + * config/riscv/riscv.cc (canonicalize_comparands); Tighten check for + forcing value into a GPR. + +2025-08-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/121474 + * tree-ssa-forwprop.cc (optimize_aggr_zeroprop): Move the check + for limit before the alias check. + +2025-08-13 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (SLP_TREE_PERMUTE_P): New. + * tree-vect-slp-patterns.cc (linear_loads_p): Adjust. + (vect_detect_pair_op): Likewise. + (addsub_pattern::recognize): Likewise. + * tree-vect-slp.cc (vect_print_slp_tree): Likewise. + (vect_gather_slp_loads): Likewise. + (vect_is_slp_load_node): Likewise. + (optimize_load_redistribution_1): Likewise. + (vect_optimize_slp_pass::is_cfg_latch_edge): Likewise. + (vect_optimize_slp_pass::internal_node_cost): Likewise. + (vect_optimize_slp_pass::start_choosing_layouts): Likewise. + (vect_optimize_slp_pass::backward_cost): Likewise. + (vect_optimize_slp_pass::forward_pass): Likewise. + (vect_optimize_slp_pass::get_result_with_layout): Likewise. + (vect_optimize_slp_pass::materialize): Likewise. + (vect_optimize_slp_pass::dump): Likewise. + (vect_optimize_slp_pass::decide_masked_load_lanes): Likewise. + (vect_update_slp_vf_for_node): Likewise. + (vect_slp_analyze_node_operations_1): Likewise. + (vect_schedule_slp_node): Likewise. + (vect_schedule_scc): Likewise. + * tree-vect-stmts.cc (vect_analyze_stmt): Likewise. + (vect_transform_stmt): Likewise. + (vect_is_simple_use): Likewise. + +2025-08-13 Richard Biener <rguenther@suse.de> + + * tree-vect-stmts.cc (vect_analyze_stmt): Use + SLP_TREE_DEF_TYPE instead of STMT_VINFO_DEF_TYPE. + +2025-08-13 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (vect_memory_access_type): Replace + VMAT_GATHER_SCATTER with three separate access types, + VMAT_GATHER_SCATTER_LEGACY, VMAT_GATHER_SCATTER_IFN and + VMAT_GATHER_SCATTER_EMULATED. + (mat_gather_scatter_p): New predicate. + (GATHER_SCATTER_LEGACY_P): Remove. + (GATHER_SCATTER_IFN_P): Likewise. + (GATHER_SCATTER_EMULATED_P): Likewise. + * tree-vect-stmts.cc (check_load_store_for_partial_vectors): + Adjust. + (get_load_store_type): Likewise. + (vect_get_loop_variant_data_ptr_increment): Likewise. + (vectorizable_store): Likewise. + (vectorizable_load): Likewise. + * config/i386/i386.cc (ix86_vector_costs::add_stmt_cost): + Likewise. + * config/riscv/riscv-vector-costs.cc + (costs::need_additional_vector_vars_p): Likewise. + * config/aarch64/aarch64.cc (aarch64_detect_vector_stmt_subtype): + Likewise. + (aarch64_vector_costs::count_ops): Likewise. + (aarch64_vector_costs::add_stmt_cost): Likewise. + +2025-08-13 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (vect_supportable_dr_alignment): Pass + a bool instead of a pointer to gather_scatter_info. + * tree-vect-data-refs.cc (vect_supportable_dr_alignment): + Likewise. + * tree-vect-stmts.cc (get_load_store_type): Adjust. + +2025-08-13 Lulu Cheng <chenglulu@loongson.cn> + + PR target/120476 + * config/loongarch/loongarch.cc + (loongarch_compute_pressure_classes): New function. + (TARGET_COMPUTE_PRESSURE_CLASSES): Define. + +2025-08-13 Yang Yujie <yangyujie@loongson.cn> + + PR target/117599 + * config/loongarch/loongarch.h: Define a PROMOTE_MODE case for + small _BitInts. + * config/loongarch/loongarch.cc (loongarch_promote_function_mode): + Same. + (loongarch_bitint_type_info): New function. + (TARGET_C_BITINT_TYPE_INFO): Declare. + +2025-08-13 Jeff Law <jlaw@ventanamicro.com> + + PR target/121113 + * config/riscv/sifive-p400.md: Handle HFmode for fdiv/fsqrt. + * config/riscv/sifive-p600.md: Likewise. + * config/riscv/xiangshan.md: Likewise. + +2025-08-13 H.J. Lu <hjl.tools@gmail.com> + Liu, Hongtao <hongtao.liu@intel.com> + + PR target/121497 + * config/i386/i386-features.cc (ix86_broadcast_inner): Convert + integer constant to mode of move + +2025-08-12 Pan Li <pan2.li@intel.com> + + * config/riscv/autovec-opt.md (*merge_vx_<mode>): Add new + pattern to combine the vmerge.vxm. + +2025-08-12 Robin Dapp <rdapp.gcc@gmail.com> + + PR target/121334 + * config/riscv/riscv-v.cc (expand_slide1up): New function. + (expand_vector_init_trailing_same_elem): Use new function. + (expand_const_vector_onestep): New function. + (expand_const_vector): Uew expand_slide1up. + (expand_vector_init_merge_repeating_sequence): Ditto. + (shuffle_off_by_one_patterns): Ditto. + +2025-08-12 mengqinggang <mengqinggang@loongson.cn> + + * config/loongarch/loongarch-def.h (ABI_BASE_LP64D): New macro. + (ABI_BASE_LP64F): New macro. + (ABI_BASE_LP64S): New macro. + (N_ABI_BASE_TYPES): New macro. + +2025-08-12 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vect_analyze_loop_2): Change + slp_done_for_suggested_uf to a boolean + single_lane_slp_done_for_suggested_uf. Change slp + to force_single_lane boolean. + (vect_analyze_loop_1): Adjust similarly. + +2025-08-12 Richard Sandiford <richard.sandiford@arm.com> + + PR rtl-optimization/121253 + * fwprop.cc (forward_propagate_into): Don't propagate asm defs. + +2025-08-12 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121509 + * tree-vect-stmts.cc (vect_mark_stmts_to_be_vectorized): + Fail early when we detect a relevant but not handled PHI. + +2025-08-12 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121514 + * tree-ssa-sccvn.cc (visit_nary_op): Only call + vn_nary_op_insert_stmt for SSA name result. + +2025-08-12 Andrew Pinski <andrew.pinski@oss.qualcomm.com> + + PR tree-optimization/121494 + * tree-ssa-forwprop.cc (optimize_agr_copyprop): Mark the bb of the use + stmt if needed for eh cleanup. + +2025-08-12 Richard Biener <rguenther@suse.de> + + * tree-vect-stmts.cc (vect_analyze_stmt): Only set + STMT_VINFO_VECTYPE for dataref SLP representatives. + Clear it for others and do not restore the original value. + (vect_transform_stmt): Likewise. + +2025-08-12 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (get_initial_defs_for_reduction): + Get vector type as argument. + (vect_find_reusable_accumulator): Likewise. + (vect_transform_cycle_phi): Adjust. + +2025-08-12 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vectorizable_reduction): Replace + STMT_VINFO_VECTYPE use with SLP_TREE_VECTYPE. + +2025-08-12 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121493 + * tree-ssa-sccvn.cc (vn_reference_lookup_3): Opportunistically + strip components with known offset. + +2025-08-12 Richard Biener <rguenther@suse.de> + + * tree-ssa-sccvn.cc (vn_reference_lookup_3): When we fail to + match up the two base MEM_REFs, fail. + +2025-08-12 Shreya Munnangi <smunnangi1@ventanamicro.com> + Jeff Law <jlaw@ventanamicro.com> + Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/riscv-protos.h (synthesize_add): Add prototype. + * config/riscv/riscv.cc (synthesize_add): New function. + * config/riscv/riscv.md (addsi3): Allow any constant as operands[2] + in the expander. Force the constant into a register as needed for + TARGET_64BIT. Use synthesize_add for !TARGET_64BIT. + (*adddi3): Renamed from adddi3. + (adddi3): New expander. Use synthesize_add. + +2025-08-11 Richard Henderson <richard.henderson@linaro.org> + + * config/aarch64/aarch64.md (mov<ALLI>cc): Accept MODE_CC + conditions directly; reject QI/HImode conditions. + +2025-08-11 Richard Henderson <richard.henderson@linaro.org> + + PR target/121388 + * config/aarch64/aarch64.cc (aarch64_cb_rhs): Restrict the + range of LT/GE and GT/LE to their intersections. + * config/aarch64/aarch64.md (*aarch64_cb<INT_CMP><GPI>): Unexport. + Use cmpbr_imm_predicate instead of aarch64_cb_rhs. + * config/aarch64/constraints.md (Uc1): Accept 0..62. + (Uc2): Remove. + * config/aarch64/iterators.md (cmpbr_imm_predicate): New. + (cmpbr_imm_constraint): Update to match aarch64_cb_rhs. + * config/aarch64/predicates.md (aarch64_cb_reg_i63_operand): New. + (aarch64_cb_reg_i62_operand): New. + +2025-08-11 Richard Henderson <richard.henderson@linaro.org> + + * config/aarch64/aarch64.cc (aarch64_if_then_else_costs): + Use aarch64_cb_rhs to match CB insns. + +2025-08-11 Richard Henderson <richard.henderson@linaro.org> + + PR target/121385 + * config/aarch64/aarch64.md (*aarch64_tbz<LTGE><ALLI>1): Remove + cc clobber and expansion via TST+Bcond. + +2025-08-11 Richard Henderson <richard.henderson@linaro.org> + + * config/aarch64/aarch64.h (TARGET_CMPBR): False when + aarch64_track_speculation is true. + +2025-08-11 Richard Henderson <richard.henderson@linaro.org> + + * config/aarch64/aarch64.cc (aarch64_gen_compare_split_imm24): New. + * config/aarch64/aarch64-protos.h: Update. + * config/aarch64/aarch64.md (*aarch64_bcond_wide_imm<GPI>): Use it. + Add match_scratch and cc clobbers. Use match_operator instead of + iterator expansion. + (*compare_cstore<GPI>_insn): Likewise. + +2025-08-11 Richard Henderson <richard.henderson@linaro.org> + + * config/aarch64/predicates.md (aarch64_split_imm24): Rename from + aarch64_imm24; exclude aarch64_move_imm and aarch64_uimm12_shift. + * config/aarch64/aarch64.md (*aarch64_bcond_wide_imm<GPI>): + Update for aarch64_split_imm24. + (*compare_cstore<GPI>_insn): Likewise. + * config/aarch64/aarch64.cc (aarch64_if_then_else_costs): Likewise. + +2025-08-11 Richard Henderson <richard.henderson@linaro.org> + + * config/aarch64/aarch64.md (tbranch_<EQL><SHORT>3): Remove. + (save_stack_nonlocal): Use aarch64_gen_compare_zero_and_branch. + (restore_stack_nonlocal): Likewise. + +2025-08-11 Richard Henderson <richard.henderson@linaro.org> + + * config/aarch64/aarch64.cc + (aarch64_gen_compare_zero_and_branch): Export. + * config/aarch64/aarch64-protos.h + (aarch64_gen_compare_zero_and_branch): Declare it. + * config/aarch64/aarch64-sme.md (aarch64_restore_za): Use it. + * config/aarch64/aarch64.md (*aarch64_cbz<EQL><GPI>): Unexport. + +2025-08-11 Richard Henderson <richard.henderson@linaro.org> + + * config/aarch64/aarch64.cc (aarch64_if_the_else_costs): Reorg to + include the cost of inner within TBZ sign-bit test, only match + CBZ/CBNZ with valid modes, and both for the aarch64_imm24 test. + +2025-08-11 Richard Henderson <richard.henderson@linaro.org> + + * config/aarch64/aarch64.cc (aarch64_if_then_else_costs): Remove + else after return and re-indent. + +2025-08-11 Richard Henderson <richard.henderson@linaro.org> + + * config/aarch64/aarch64.md (BRANCH_LEN_N_1KiB): Rename + from BRANCH_LEN_N_1Kib. + +2025-08-11 Andrew Pinski <quic_apinski@quicinc.com> + + * tree-ssa-forwprop.cc (optimize_aggr_zeroprop): Recognize stores + of integer_zerop as memset of 0. + +2025-08-11 Jeff Law <jlaw@ventanamicro.com> + + * doc/sourcebuild.texi: Add riscv_b_ok and riscv_v_ok target selectors. + +2025-08-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121488 + * tree-ssa-sccvn.cc (visit_nary_op): If the BIT_FIELD_REF + result is of wrong type, try a VIEW_CONVERT_EXPR around it. + +2025-08-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121362 + * tree-ssa-sccvn.cc (vn_reference_lookup_3): Swap index + guards on component stripping loops. + +2025-08-11 Pan Li <pan2.li@intel.com> + + * tree-ssa-math-opts.cc (match_saturation_mul): Add new func + to emit IFN_SAT_MUL if matched. + (math_opts_dom_walker::after_dom_children): Try to match + the phi node for SAT_MUL. + +2025-08-11 Pan Li <pan2.li@intel.com> + + * match.pd: Add form 2 for unsigned SAT_MUL. + +2025-08-11 Pan Li <pan2.li@intel.com> + + * config/riscv/riscv.cc (get_vector_binary_rtx_cost): Remove. + (riscv_rtx_costs): Refactor to serach vec_duplicate on the + sub rtx. + +2025-08-11 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR target/121464 + * config/arm/arm.md (arm_<mrrc>, arm_<mcrr>): Fix operand check. + +2025-08-11 Richard Sandiford <richard.sandiford@arm.com> + + PR rtl-optimization/121306 + * simplify-rtx.cc (simplify_context::simplify_subreg): Distribute + non-narrowing integer-to-integer subregs through logic ops, + in a similar way to the existing word_mode handling. + +2025-08-11 Jakub Jelinek <jakub@redhat.com> + + * tree-cfg.cc (find_case_label_for_value): Fix comment typo, + singe-valued -> single-valued. + * config/arc/arc.md: Fix comment typos, unsinged -> unsigned. + +2025-08-10 Matthew Fortune <matthew.fortune@imgtec.com> + + * config/mips/mips.h (FRAME_GROWS_DOWNWARD) Allow the frame to + grow downwards for mips16 when -mgrow-frame-downwards is set. + * config/mips/mips.opt: Add -mgrow-frame-downwards option. + +2025-08-10 Andrew Pinski <quic_apinski@quicinc.com> + + PR middle-end/121438 + PR middle-end/121444 + * output.h (MAX_ALIGN_MERGABLE): Rename to ... + (MAX_MERGEABLE_BITSIZE): This. + * tree-switch-conversion.cc (switch_conversion::build_one_array): Don't + increase the alignment. + * varasm.cc (mergeable_string_section): Use MAX_MERGEABLE_BITSIZE + instead of MAX_ALIGN_MERGABLE. Also replace `/ 8` with `/ BITS_PER_UNIT`. + (mergeable_constant_section): Select the mergeable section based on + the bitsize rather than the alignment. Make sure the align is less + than the entity size. + +2025-08-10 Andrew Pinski <quic_apinski@quicinc.com> + + PR middle-end/121394 + * varasm.cc (assemble_variable_contents): Pad out + mergeable sections if needed. + (output_constant_pool_1): Change the padding to be explicit + zeroing for mergeable sections. + +2025-08-10 H.J. Lu <hjl.tools@gmail.com> + + * configure: Regenerated. + +2025-08-09 Iain Sandoe <iain@sandoe.co.uk> + + * config/darwin.cc (darwin_encode_section_info): Do not + make anchored symbols linker-visible. + (darwin_use_anchors_for_symbol_p): Disallow anchoring on + symbols that must be linker-visible (or external), even + if the definitions are in this TU. + +2025-08-09 Iain Sandoe <iain@sandoe.co.uk> + + * config/darwin.h (ASM_GENERATE_INTERNAL_LABEL): New + entry for LANCHOR. + +2025-08-09 David Malcolm <dmalcolm@redhat.com> + + * diagnostics/context.cc (context::dump): Bulletproof against + m_reference_printer being null. + * diagnostics/dumping.cc (emit_field<const char *>): Replace + with... + (emit_string_field): ...this. + (emit_field<char *>): Eliminate. + (emit_field<bool>): Replace with... + (emit_bool_field): ...this. + (emit_field<size_t>): Replace with... + (emit_size_t_field): ...this, and use HOST_SIZE_T_PRINT_DEC rather + than %zi in fprintf call. + (emit_field<int>): Replace with... + (emit_int_field): ...this. + (emit_field<unsigned>): Replace with... + (emit_unsigned_field): ...this. + * diagnostics/dumping.h (emit_field): Replace this template decl + with... + (emit_string_field): ...this, + (emit_bool_field): ...this, + (emit_size_t_field): ...this, + (emit_int_field): ...this, + (emit_unsigned_field): ... and this. + (DIAGNOSTICS_DUMPING_EMIT_FIELD): Rename to... + (DIAGNOSTICS_DUMPING_EMIT_BOOL_FIELD): ...this and update for + above change. + * diagnostics/file-cache.cc (file_cache_slot::dump): Replace + emit_field calls with calls that explicitly state the type. Fix + type of dump of m_missing_trailing_newline to use bool. + (file_cache_slot::dump): Use HOST_SIZE_T_PRINT_DEC rather than + %zi in fprintf call. + * diagnostics/html-sink.cc (html_generation_options::dump): Update + for macro renaming. + * diagnostics/sarif-sink.cc + (sarif_serialization_format_json::dump): Likewise. + (sarif_generation_options::dump): Likewise, and for function + renaming. + * diagnostics/text-sink.cc (text_sink::dump): Update for macro + renaming. + * libgdiagnostics.cc (diagnostic_manager_debug_dump_file): Use + HOST_SIZE_T_PRINT_DEC rather than %zi in fprintf call. + * pretty-print.cc: Include "diagnostics/dumping.h". + (pp_formatted_chunks::dump): Use it. + (get_url_format_as_string): New. + (pretty_printer::dump): Use diagnostics::dumping. Bulletproof + against m_buffer being null. + +2025-08-09 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/constraints.md (T): + Change define_memory_constraint to define_special_memory_constraint. + +2025-08-08 Andrew Pinski <quic_apinski@quicinc.com> + + PR tree-optimization/120599 + * tree-ssa-forwprop.cc (optimize_agr_copyprop): Don't try to copy + from statements that throw. + +2025-08-08 Andrew Pinski <quic_apinski@quicinc.com> + + PR tree-optimization/118946 + PR tree-optimization/121422 + * tree-ssa-forwprop.cc (optimize_memcpy_to_memset): Remove. + (optimize_aggr_zeroprop_1): New function. + (optimize_aggr_zeroprop): New function. + (simplify_builtin_call): Don't call optimize_memcpy_to_memset + for memcpy but call optimize_aggr_zeroprop for memset. + (pass_forwprop::execute): Don't call optimize_memcpy_to_memset + for aggregate copies but rather call optimize_aggr_zeroprop + for aggregate stores. + +2025-08-08 Andrew Pinski <quic_apinski@quicinc.com> + + * tree-ssa-forwprop.cc (optimize_agr_copyprop): Change into a + forward looking (looking at vdef's uses) instead of a back + looking (vuse's def). + +2025-08-08 David Malcolm <dmalcolm@redhat.com> + + PR diagnostics/116253 + * common.opt (fdiagnostics-show-nesting): New option. + (fdiagnostics-show-nesting-locations): New option. + (fdiagnostics-show-nesting-levels): New option. + * common.opt.urls: Regenerate. + * diagnostics/context.cc (context::set_show_nesting): New. + (context::set_show_nesting_locations): New. + (context::set_show_nesting_levels): New. + * diagnostics/context.h (context::set_show_nesting): New decl. + (context::set_show_nesting_locations): New decl. + (context::set_show_nesting_levels): New decl. + * diagnostics/html-sink.cc: Tweak comment. + * diagnostics/output-spec.cc (text_scheme_handler::make_sink): + Rename "experimental-nesting" to "show-nesting" and enable by + default. Rename "experimental-nesting-show-locations" to + "show-nesting-locations". Rename + "experimental-nesting-show-levels" to "show-nesting-levels". + * diagnostics/sink.h (sink::dyn_cast_text_sink): New. + * diagnostics/text-sink.h (text_sink::dyn_cast_text_sink): New. + * doc/invoke.texi: Add -fdiagnostics-show-nesting, + -fdiagnostics-show-nesting-locations, and + -fdiagnostics-show-nesting-levels. Update for changes to + output-spec.cc above. + * lto-wrapper.cc (merge_and_complain): Ignore + OPT_fdiagnostics_show_nesting, + OPT_fdiagnostics_show_nesting_locations, and + OPT_fdiagnostics_show_nesting_levels. + (append_compiler_options): Likewise. + (append_diag_options): Likewise. + * opts-common.cc (decode_cmdline_options_to_array): Add + "-fno-diagnostics-show-nesting" to -fdiagnostics-plain-output. + * opts.cc (common_handle_option): Handle the new options. + (gen_command_line_string): Ignore the new options. + * toplev.cc (general_init): Call set_show_nesting, + set_show_nesting_locations, and set_show_nesting_levels on + global_dc. + +2025-08-08 David Malcolm <dmalcolm@redhat.com> + + * Makefile.in (OBJS-libcommon): Add diagnostics/dumping.o. + * diagnostics/buffering.cc: Include "diagnostics/dumping.h". + (buffer::dump): Reimplement using diagnostics::dumping. + * diagnostics/context.cc: Include "diagnostics/dumping.h". + (context::dump): Reimplement using diagnostics::dumping. + Use sink::dump_kind when listing the sinks. + (sink::dump): Reimplement using diagnostics::dumping. + (counters::dump): Likewise. + * diagnostics/dumping.cc: New file. + * diagnostics/dumping.h: New file. + * diagnostics/file-cache.cc: Include "diagnostics/dumping.h". + (file_cache::dump): Reimplement using diagnostics::dumping. + (file_cache_slot::dump): Likewise. + * diagnostics/html-sink.cc: Include "diagnostics/dumping.h". + (html_generation_options::dump): New. + (html_sink_buffer::dump): Reimplement using diagnostics::dumping. + (html_builder::dump): New. + (html_sink::dump): Reimplement using diagnostics::dumping. + Add dump of the html_builder. + (html_file_sink::dump): Replace with... + (html_file_sink::dump_kind): ...this. + (html_buffered_sink::dump_kind): New. + * diagnostics/html-sink.h (html_generation_options::dump): New + decl. + * diagnostics/sarif-sink.cc: Include "diagnostics/dumping.h". + (sarif_serialization_format_json::dump): New. + (sarif_builder::dump): New. + (sarif_sink_buffer::dump): Reimplement using diagnostics::dumping. + (sarif_sink::dump): Likewise. Add dump of the sarif_builder. + (sarif_stream_sink::dump_kind): New. + (sarif_file_sink::dump): Replace with... + (sarif_file_sink::dump_kind): ...this. + (get_dump_string_for_sarif_version): New. + (sarif_generation_options::dump): New. + (class buffered_sink): Rename to... + (class sarif_buffered_sink): ...this. + (sarif_buffered_sink::dump_kind): New. + * diagnostics/sarif-sink.h (sarif_serialization_format::dump): + New. + (sarif_serialization_format_json::dump): New decl. + (sarif_generation_options::dump): New decl. + * diagnostics/sink.h (sink::dump_kind): New. + * diagnostics/text-sink.cc: Include "diagnostics/dumping.h". + (text_sink_buffer::dump): Reimplement using diagnostics::dumping. + (text_sink::dump): Likewise. Emit fields m_show_nesting, + m_show_locations_in_nesting, and m_show_nesting_levels. + * diagnostics/text-sink.h (text_sink::dump_kind): New. + +2025-08-08 David Malcolm <dmalcolm@redhat.com> + + * diagnostic.h (diagnostics::get_cwe_url): Move decl to + diagnostics/metadata.h. + (diagnostics::maybe_line_and_column): Move into + diagnostics::text_sink. + * diagnostics/context.cc: Update for maybe_line_and_column + becoming a static member of text_sink. + * diagnostics/metadata.h (diagnostics::get_cwe_url): Move decl + here from diagnostic.h. + * diagnostics/text-sink.cc (maybe_line_and_column): Convert to... + (text_sink::maybe_line_and_column): ...this. + * diagnostics/text-sink.h (text_sink::maybe_line_and_column): Move + here from diagnostic.h. + +2025-08-08 David Malcolm <dmalcolm@redhat.com> + + * diagnostics/context.cc (context::get_any_inlining_info): Convert + "context" arg of m_set_locations_cb from ptr to const &. + (context::report_diagnostic): Convert "context" arg of + m_adjust_diagnostic_info from ptr to const &. + * diagnostics/context.h (context::set_locations_callback_t): + Likewise. + (context::set_adjust_diagnostic_info_callback): Likewise. + (context::m_adjust_diagnostic_info): Likewise. + * tree-diagnostic.cc (set_inlining_locations): Likewise. + +2025-08-08 David Malcolm <dmalcolm@redhat.com> + + * diagnostics/column-options.h: New file, adding struct + diagnostics::column_options, taken from fields in + diagnostics::context and diagnostics::column_policy. + * diagnostics/context.cc (context::initialize): Update for moving + fields of diagnostics::context into diagnostics::column_options. + (column_policy::column_policy): Likewise. + (column_policy::converted_column): Move implementation to... + (column_options::convert_column): ...this new function. + (context::report_diagnostic): Update for moving fields of + diagnostics::context into diagnostics::column_options. + (assert_location_text): Likewise. + * diagnostics/context.h: Include "diagnostics/column-options.h". + (class column_policy): Replace fields m_column_unit, + m_column_origin, and m_tabstop with m_column_options. + (context::get_column_options): New accessors. + (context::m_column_unit): Move to struct column_options and + replace with m_column_options. + (context::m_column_origin): Likewise. + (context::m_tabstop): Likewise. + * diagnostics/sarif-sink.cc (sarif_builder::sarif_builder): Update + for moving fields of diagnostics::context into + diagnostics::column_options. + * diagnostics/source-printing.cc: Likewise. + * opts.cc (common_handle_option): Likewise. + +2025-08-08 Christophe Lyon <christophe.lyon@linaro.org> + + PR target/120977 + * config/arm/arm.md (call): Move unspec parameter to parallel. + (nonsecure_call_internal): Likewise. + (call_value): Likewise. + (nonsecure_call_value_internal): Likewise. + * config/arm/thumb1.md (nonsecure_call_reg_thumb1_v5): Likewise. + (nonsecure_call_value_reg_thumb1_v5): Likewise. + * config/arm/thumb2.md (nonsecure_call_reg_thumb2_fpcxt): + Likewise. + (nonsecure_call_reg_thumb2): Likewise. + (nonsecure_call_value_reg_thumb2_fpcxt): Likewise. + (nonsecure_call_value_reg_thumb2): Likewise. + * config/arm/arm.cc (cmse_nonsecure_call_inline_register_clear): + Likewise. + +2025-08-08 Pengfei Li <Pengfei.Li2@arm.com> + + PR target/121449 + * config/aarch64/aarch64-sve.md + (mask_gather_load<mode><v_int_container>): Use vg<Vesize> + constraints for alternatives with immediate offset. + (mask_scatter_store<mode><v_int_container>): Likewise. + +2025-08-08 Richard Biener <rguenther@suse.de> + + * doc/tm.texi.in: Add Vectorization and OpenMP and OpenACC + sub-sections to the list of target macros and functions. + * doc/tm.texi: Re-generate. + +2025-08-08 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vect_determine_vectype_for_stmt_1): Remove. + (vect_determine_vectype_for_stmt): Likewise. + (vect_set_stmts_vectype): Likewise. + (vect_analyze_loop_2): Do not call vect_set_stmts_vectype. + * tree-vect-stmts.cc (vect_mark_stmts_to_be_vectorized): Detect + irregular stmts early here. + +2025-08-08 Alex Coplan <alex.coplan@arm.com> + + PR target/120986 + * config/aarch64/aarch64-sve-builtins.cc + (function_expander::expand): Relax fpm_t assert to allow + modeless const_ints. + +2025-08-08 Alex Coplan <alex.coplan@arm.com> + + PR target/120986 + * config/aarch64/aarch64-sve2.md (@aarch64_sve_dot<mode>): + Switch mode iterator from SVE_FULL_HSF to new iterator; + remove insn predicate as this is now taken care of by conditions + in the mode iterator. + (@aarch64_sve_dot_lane<mode>): Likewise. + * config/aarch64/iterators.md (SVE_FULL_HSF_FP8_FDOT): New. + +2025-08-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121454 + * tree-ssa-sccvn.cc (visit_nary_op): Avoid unexpected + BIT_FIELD_REFs. + +2025-08-08 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/121389 + * tree-tailcall.cc (find_tail_calls): For finally_tmp.N + handle not just GIMPLE_CONDs with EQ_EXPR/NE_EXPR and only + values 0 and 1, but arbitrary non-negative values, arbitrary + comparisons in conditions and also GIMPLE_SWITCH next to + GIMPLE_CONDs. + +2025-08-08 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vect_is_emulated_mixed_dot_prod): Get + the SLP node rather than the stmt_info. + (vectorizable_lane_reducing): Adjust, pass SLP node to costing. + (vect_transform_reduction): Adjust. + +2025-08-08 Richard Biener <rguenther@suse.de> + + * tree-vect-stmts.cc (vect_model_promotion_demotion_cost): Pass + in SLP node and drop unused dr argument. Use SLP node for + costing, drop costing of constant/external operands. + (vectorizable_conversion): Adjust. + +2025-08-08 Richard Biener <rguenther@suse.de> + + * tree-vect-stmts.cc (vectorizable_store): Apply SLP_TREE_VECTYPE + to slp_node rather than stmt_info. + +2025-08-07 Richard Sandiford <richard.sandiford@arm.com> + + PR target/121414 + * config/aarch64/aarch64.cc (aarch64_is_variant_pcs): New function, + split out from... + (aarch64_asm_output_variant_pcs): ...here. Handle various types + of SME function type. + +2025-08-07 Richard Sandiford <richard.sandiford@arm.com> + + PR rtl-optimization/120718 + * simplify-rtx.cc (simplify_context::simplify_gen_subreg): + Remove MODE_COMPOSITE_P condition. + +2025-08-07 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121405 + * tree-ssa-sccvn.cc (visit_nary_op): Handle BIT_FIELD_REF + with reference def by looking up a combination of both. + +2025-08-07 Pengfei Li <Pengfei.Li2@arm.com> + + * tree-vect-data-refs.cc (vect_compute_data_ref_alignment): + Allow DR target alignment to be a poly_int. + (vect_enhance_data_refs_alignment): Support peeling and + versioning for VLA modes. + * tree-vect-loop-manip.cc (get_misalign_in_elems): Remove + power-of-two rounding in peeling. + (vect_create_cond_for_align_checks): Update alignment check + logic for poly_int mask. + (vect_create_cond_for_vla_spec_read): New runtime checks. + (vect_loop_versioning): Support new runtime checks. + * tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): Add a new + loop_vinfo field. + (vectorizable_induction): Fix wrong IV offset issue. + * tree-vect-stmts.cc (get_load_store_type): Refactor + vectorizable checks for speculative loads. + * tree-vectorizer.h (LOOP_VINFO_MAX_SPEC_READ_AMOUNT): New + macro for new runtime checks. + (LOOP_REQUIRES_VERSIONING_FOR_SPEC_READ): Likewise + (LOOP_REQUIRES_VERSIONING): Update macro for new runtime checks. + +2025-08-07 Jakub Jelinek <jakub@redhat.com> + + PR preprocessor/120778 + * doc/invoke.texi (Wkeyword-macro): Document. + +2025-08-07 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> + + * config/s390/s390.cc (print_operand): Allow arbitrary wide_int + constants for _BitInt. + (s390_bitint_type_info): Implement target hook + TARGET_C_BITINT_TYPE_INFO. + +2025-08-06 Uros Bizjak <ubizjak@gmail.com> + + PR target/96226 + * config/i386/predicates.md (and_operator): New operator. + * config/i386/i386.md (splitter after *<rotate_insn><mode>3_mask): + Use and_operator to match AND RTX and use its mode + in the split pattern. + +2025-08-06 Gerald Pfeifer <gerald@pfeifer.com> + + PR target/69374 + * doc/install.texi (Prerequisites): Replace bzip2 by xz. + +2025-08-06 Yangyu Chen <cyy@cyyself.name> + + * config/i386/i386.h (PTA_BDVER1): + Add missing PTA_POPCNT and PTA_LZCNT with PTA_ABM. + (PTA_ZNVER1): Ditto. + (PTA_BTVER1): Ditto. + (PTA_LUJIAZUI): Ditto. + (PTA_YONGFENG): Do not include extra PTA_LZCNT. + +2025-08-06 Sam James <sam@gentoo.org> + + PR libstdc++/29286 + * Makefile.in (ALIASING_FLAGS): Drop. + * configure: Regenerate. + * configure.ac: Drop -fno-strict-aliasing workaround for < GCC 4.3. + +2025-08-06 Richard Biener <rguenther@suse.de> + + * tree-vect-data-refs.cc (vect_supportable_dr_alignment): + Prune dead code. + +2025-08-06 Patrick Palka <ppalka@redhat.com> + + PR c++/121231 + PR c++/119688 + PR c++/94511 + * common.opt: Document additional ABI version 21 change. + * doc/invoke.texi: Likewise. + +2025-08-06 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (_slp_tree::gs_scale): New. + (_slp_tree::gs_base): Likewise. + (SLP_TREE_GS_SCALE): Likewise. + (SLP_TREE_GS_BASE): Likewise. + (vect_describe_gather_scatter_call): Declare. + * tree-vect-slp.cc (_slp_tree::_slp_tree): Initialize + new members. + (vect_build_slp_tree_2): Record gather/scatter base and scale. + (vect_get_and_check_slp_defs): For gather/scatter IFNs + describe the call to first_gs_info. + * tree-vect-data-refs.cc (vect_gather_scatter_fn_p): Add + mode of operation with fixed offset vector type. + (vect_describe_gather_scatter_call): Export. + * tree-vect-stmts.cc (get_load_store_type): Do not call + vect_check_gather_scatter to fill gs_info, instead populate + from the SLP tree. Check which of, IFN, decl or fallback + is supported and record that decision. + +2025-08-06 Richard Biener <rguenther@suse.de> + + * tree-vect-stmts.cc (vectorizable_store): Build proper + alias + align pointer value for gather/scatter and SLP + and use it. + (vectorizable_load): Likewise. + +2025-08-06 Richard Biener <rguenther@suse.de> + + * tree-vect-stmts.cc (check_load_store_for_partial_vectors): + Remove redundant gather/scatter target support check, instead + check the recorded ifns. Also allow legacy gather/scatter + with loop masking. + +2025-08-06 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/121413 + * gimple-lower-bitint.cc (gimple_lower_bitint): Fix up last + commit, cast limb_prec to unsigned before comparison. + +2025-08-06 Yang Yujie <yangyujie@loongson.cn> + + * match.pd: Preserve conversion to _BitInt before a VCE + if the _BitInt is extended. + +2025-08-06 Yang Yujie <yangyujie@loongson.cn> + + * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt): + Zero-extend the partial limb of any unsigned _BitInt LHS assigned + with a widening sign-extension. + +2025-08-06 Yang Yujie <yangyujie@loongson.cn> + + * gimple-lower-bitint.cc (bitint_large_huge::limb_access): + Add a parameter abi_load_p. If set, load a limb directly + in its actual precision without casting from m_limb_type. + (struct bitint_large_huge): Same. + (bitint_large_huge::handle_load): Use. + +2025-08-06 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/121413 + * gimple-lower-bitint.cc (abi_limb_prec): New variable + (bitint_precision_kind): Initialize it. + (gimple_lower_bitint): Clear it at the start. For + min_prec > limb_prec descreased precision vars for + INTEGER_CST PHI arguments ensure min_prec is either + prec or multiple of abi_limb_prec. + +2025-08-06 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/121127 + * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr): For + uninitialized SSA_NAME, set *prec_stored to 0 rather than *prec. + Handle that case in narrowing casts. If prec_stored is non-NULL, + set *prec_stored to prec_stored_val. + +2025-08-06 Jakub Jelinek <jakub@redhat.com> + + PR bootstrap/121386 + * Makefile.in (gengtype-lex.cc): Append #define FLEX_SCANNER, + #include "system.h" and #undef FLEX_SCANNER to the prepended lines. + * gengtype-lex.l: Remove inclusion of config.h or bconfig.h, system.h + and definition of malloc/realloc from %{} section. + +2025-08-06 Kito Cheng <kito.cheng@sifive.com> + + * config/riscv/arch-canonicalize: Read extension data from + riscv-ext*.def and adding unittest. + +2025-08-06 Kito Cheng <kito.cheng@sifive.com> + + * common/config/riscv/riscv-common.cc (riscv_expand_arch): + Ignore `unset`. + * config/riscv/riscv.h (OPTION_DEFAULT_SPECS): Handle + `-march=unset`. + (ARCH_UNSET_CLEANUP_SPECS): New. + (DRIVER_SELF_SPECS): Handle -march=unset. + * doc/invoke.texi (RISC-V Options): Update documentation for + `-march=unset`. + +2025-08-06 Kwok Cheung Yeung <kcyeung@baylibre.com> + + * gimplify.cc (remove_unused_omp_iterator_vars): Display unused + variable warning for 'to' and 'from' clauses. + (gimplify_scan_omp_clauses): Add argument for iterator loop sequence. + Gimplify the clause decl and size into the iterator loop if iterators + are used. + (gimplify_omp_workshare): Add argument for iterator loops sequence + in call to gimplify_scan_omp_clauses. + (gimplify_omp_target_update): Call remove_unused_omp_iterator_vars and + build_omp_iterators_loops. Add loop sequence as argument when calling + gimplify_scan_omp_clauses, gimplify_adjust_omp_clauses and building + the Gimple statement. + * tree-pretty-print.cc (dump_omp_clause): Call dump_omp_iterators + for to/from clauses with iterators. + * tree.cc (omp_clause_num_ops): Add extra operand for OMP_CLAUSE_FROM + and OMP_CLAUSE_TO. + * tree.h (OMP_CLAUSE_HAS_ITERATORS): Add check for OMP_CLAUSE_TO and + OMP_CLAUSE_FROM. + (OMP_CLAUSE_ITERATORS): Likewise. + +2025-08-06 Kwok Cheung Yeung <kcyeung@baylibre.com> + Andrew Stubbs <ams@baylibre.com> + + * gimple-pretty-print.cc (dump_gimple_omp_target): Print expanded + iterator loops. + * gimple.cc (gimple_build_omp_target): Add argument for iterator + loops sequence. Initialize iterator loops field. + * gimple.def (GIMPLE_OMP_TARGET): Set GSS symbol to GSS_OMP_TARGET. + * gimple.h (gomp_target): Set GSS symbol to GSS_OMP_TARGET. Add extra + field for iterator loops. + (gimple_build_omp_target): Add argument for iterator loops sequence. + (gimple_omp_target_iterator_loops): New. + (gimple_omp_target_iterator_loops_ptr): New. + (gimple_omp_target_set_iterator_loops): New. + * gimplify.cc (find_var_decl): New. + (copy_omp_iterator): New. + (remap_omp_iterator_var_1): New. + (remap_omp_iterator_var): New. + (remove_unused_omp_iterator_vars): New. + (struct iterator_loop_info_t): New type. + (iterator_loop_info_map_t): New type. + (build_omp_iterators_loops): New. + (enter_omp_iterator_loop_context_1): New. + (enter_omp_iterator_loop_context): New. + (enter_omp_iterator_loop_context): New. + (exit_omp_iterator_loop_context): New. + (gimplify_adjust_omp_clauses): Add argument for iterator loop + sequence. Gimplify the clause decl and size into the iterator + loop if iterators are used. + (gimplify_omp_workshare): Call remove_unused_omp_iterator_vars and + build_omp_iterators_loops for OpenMP target expressions. Add + loop sequence as argument when calling gimplify_adjust_omp_clauses + and building the Gimple statement. + * gimplify.h (enter_omp_iterator_loop_context): New prototype. + (exit_omp_iterator_loop_context): New prototype. + * gsstruct.def (GSS_OMP_TARGET): New. + * omp-low.cc (lower_omp_map_iterator_expr): New. + (lower_omp_map_iterator_size): New. + (finish_omp_map_iterators): New. + (lower_omp_target): Add sorry if iterators used with deep mapping. + Call lower_omp_map_iterator_expr before assigning to sender ref. + Call lower_omp_map_iterator_size before setting the size. Insert + iterator loop sequence before the statements for the target clause. + * tree-nested.cc (convert_nonlocal_reference_stmt): Walk the iterator + loop sequence of OpenMP target statements. + (convert_local_reference_stmt): Likewise. + (convert_tramp_reference_stmt): Likewise. + * tree-pretty-print.cc (dump_omp_iterators): Dump extra iterator + information if present. + (dump_omp_clause): Call dump_omp_iterators for iterators in map + clauses. + * tree.cc (omp_clause_num_ops): Add operand for OMP_CLAUSE_MAP. + (walk_tree_1): Do not walk last operand of OMP_CLAUSE_MAP. + * tree.h (OMP_CLAUSE_HAS_ITERATORS): New. + (OMP_CLAUSE_ITERATORS): New. + +2025-08-05 H.J. Lu <hjl.tools@gmail.com> + + PR target/121410 + * config/i386/i386-expand.cc (ix86_expand_set_or_cpymem): Use + STORE_MAX_PIECES to get the widest vector mode in vector loop + for memset. + +2025-08-05 Georg-Johann Lay <avr@gjlay.de> + + * config/avr/avr.cc (avr_rtx_costs_1) [SIGN_EXTEND]: Adjust cost. + * config/avr/avr.md (*sext.ashift<QIPSI:mode><HISI:mode>2): New + insn and a cc split. + +2025-08-05 Richard Sandiford <richard.sandiford@arm.com> + + PR target/121306 + * config/i386/predicates.md (extract_operator): Replace with... + (extract_high_operator): ...this new predicate. + * config/i386/i386.md (*cmpqi_ext<mode>_1, *cmpqi_ext<mode>_2) + (*cmpqi_ext<mode>_3, *cmpqi_ext<mode>_4, *movstrictqi_ext<mode>_1) + (*extzv<mode>, *insvqi_2, *extendqi<SWI24:mode>_ext_1) + (*addqi_ext<mode>_1_slp, *addqi_ext<mode>_1_slp, *addqi_ext<mode>_0) + (*addqi_ext2<mode>_0, *addqi_ext<mode>_1, *<insn>qi_ext<mode>_2) + (*subqi_ext<mode>_1_slp, *subqi_ext<mode>_2_slp, *subqi_ext<mode>_0) + (*subqi_ext2<mode>_0, *subqi_ext<mode>_1, *testqi_ext<mode>_1) + (*testqi_ext<mode>_2, *<code>qi_ext<mode>_1_slp) + (*<code>qi_ext<mode>_2_slp. *<code>qi_ext<mode>_0) + (*<code>qi_ext2<mode>_0, *<code>qi_ext<mode>_1) + (*<code>qi_ext<mode>_1_cc, *<code>qi_ext<mode>_1_cc) + (*<code>qi_ext<mode>_2, *<code>qi_ext<mode>_3, *negqi_ext<mode>_1) + (*one_cmplqi_ext<mode>_1, *ashlqi_ext<mode>_1, *<insn>qi_ext<mode>_1) + (define_peephole2): Replace uses of extract_operator with + extract_high_operator, matching only the first operand. + Use zero_extract rather than match_op_dup when splitting. + +2025-08-05 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (vect_relevant::hybrid): Remove. + * tree-vect-loop.cc (vect_analyze_loop_2): Do not call + vect_detect_hybrid_slp. + * tree-vect-slp.cc (maybe_push_to_hybrid_worklist): Remove. + (vect_detect_hybrid_slp): Likewise. + +2025-08-05 Georg-Johann Lay <avr@gjlay.de> + + PR target/121359 + * config/avr/avr.h: Remove -mlra and remains of reload. + * config/avr/avr.cc: Same. + * config/avr/avr.md: Same. + * config/avr/avr-log.cc: Same. + * config/avr/avr-protos.h: Same. + * config/avr/avr.opt: Same. + * config/avr/avr.opt.urls: Same. + +2025-08-05 H.J. Lu <hjl.tools@gmail.com> + + PR target/121306 + * config/i386/i386.md (*one_cmplqi_ext<mode>_1): Updated to + support the new pattern. + +2025-08-05 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121395 + * tree-vectorizer.h (_loop_vec_info::alternate_defs): New member. + (LOOP_VINFO_ALTERNATE_DEFS): New. + * tree-vect-stmts.cc (vect_stmt_relevant_p): Populate it. + (vectorizable_simd_clone_call): Do not register a SLP def + when there is none. + * tree-vect-slp.cc (vect_build_slp_tree_1): Allow a NULL + vectype when there's no LHS. Allow all calls w/o LHS. + (vect_analyze_slp): Process LOOP_VINFO_ALTERNATE_DEFS as + SLP graph entries. + (vect_make_slp_decision): Handle a NULL SLP_TREE_VECTYPE. + (vect_slp_analyze_node_operations_1): Likewise. + (vect_schedule_slp_node): Likewise. + +2025-08-05 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (enum slp_vect_type): Rename loop_vect + to not_vect, clarify docs. + (HYBRID_SLP_STMT): Remove. + * tree-vectorizer.cc (vec_info::new_stmt_vec_info): Adjust. + * tree-vect-loop.cc (vect_analyze_loop_2): Likewise. + +2025-08-05 Richard Biener <rguenther@suse.de> + + * tree-vect-data-refs.cc (vect_get_data_access_cost): Use + ncopies == 1. + * tree-vect-slp.cc (vect_remove_slp_scalar_calls): Remove + hybrid/loop SLP skip. + * tree-vect-stmts.cc (vectorizable_store): Remove pure SLP assert. + +2025-08-05 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121382 + * tree-ssa-loop-ivopts.cc (create_new_iv): Rewrite the IV + step to defined form. + +2025-08-05 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121370 + * tree-scalar-evolution.cc (scev_dfs::add_to_evolution_1): + Avoid UB integer overflow in accumulating CHREC_RIGHT. + +2025-08-05 Yang Yujie <yangyujie@loongson.cn> + + * expr.cc (expand_expr_real_1): Do not call + reduce_to_bit_field_precision if the target assumes the _BitInt + results to be already extended. + (EXTEND_BITINT): Same. + * expr.h (bitint_extended): Declare the cache variable. + * function.cc (prepare_function_start): Initialize it. + +2025-08-05 Yang Yujie <yangyujie@loongson.cn> + + * explow.cc (promote_function_mode): Add a case for + small/medium _BitInts. + (promote_mode): Same. + +2025-08-05 Gerald Pfeifer <gerald@pfeifer.com> + + PR target/69374 + * doc/install.texi (Configuration): Mark up atexit as code. + +2025-08-05 Pan Li <pan2.li@intel.com> + + * config/riscv/riscv.cc (riscv_expand_xmode_usmul): Take + umulhu for high bits mul result. + +2025-08-04 Hans-Peter Nilsson <hp@bitrange.com> + + * defaults.h (MAX_FIXED_MODE_SIZE): Default to 2 * BITS_PER_WORD + for larger-than-32-bitters. + * doc/tm.texi.in (MAX_FIXED_MODE_SIZE): Adjust accordingly. Tweak + wording. + * doc/tm.texi: Regenerate. + +2025-08-04 David Malcolm <dmalcolm@redhat.com> + + * dump-context.h: Convert "enum optinfo_item_kind" into + "enum class kind" within class optinfo_item. + * dumpfile.cc: Likewise. Use "auto" in a few places. + Convert "enum optinfo_kind" to "enum class kind" within + class optinfo. + * opt-problem.cc: Likewise. + * optinfo-emit-json.cc: Likewise. + * optinfo.cc: Likewise. + * optinfo.h: Likewise. + +2025-08-04 David Malcolm <dmalcolm@redhat.com> + + PR diagnostics/116253 + * diagnostics/context.cc (context::set_nesting_level): New. + * diagnostics/context.h (context::set_nesting_level): New decl. + * doc/libgdiagnostics/topics/compatibility.rst + (LIBGDIAGNOSTICS_ABI_5): New. + * doc/libgdiagnostics/topics/physical-locations.rst + (diagnostic_manager_set_debug_physical_locations): New. + * libgdiagnostics++.h (manager::set_debug_physical_locations): + New. + * libgdiagnostics-private.h + (private_diagnostic_set_nesting_level): New decl. + * libgdiagnostics.cc (diagnostic_manager::diagnostic_manager): + Initialize m_debug_physical_locations. + (diagnostic_manager::new_location_from_file_and_line): Add debug + printing. + (diagnostic_manager::new_location_from_file_line_column): + Likewise. + (diagnostic_manager::new_location_from_range): Likewise. + (diagnostic_manager::set_debug_physical_locations): New. + (diagnostic_manager::ensure_linemap_for_file_and_line): Avoid + redundant calls to linemap_add. + (diagnostic_manager::new_location): Add debug printing. + (diagnostic_manager::m_debug_physical_locations): New field. + (diagnostic::diagnostic): Initialize m_nesting_level. + (diagnostic::get_nesting_level): New accessor. + (diagnostic::set_nesting_level): New. + (diagnostic::m_nesting_level): New field. + (diagnostic_manager::emit_va): Set and reset the nesting level + of the context from that of the diagnostic. + (diagnostic_manager_set_debug_physical_locations): New. + (private_diagnostic_set_nesting_level): New. + * libgdiagnostics.h + (diagnostic_manager_set_debug_physical_locations): New decl. + * libgdiagnostics.map (LIBGDIAGNOSTICS_ABI_5): New. + * libsarifreplay.cc (sarif_replayer::handle_result_obj): Support + the "nestingLevel" property. + * libsarifreplay.h (replay_options::m_debug_physical_locations): + New field. + * sarif-replay.cc: Add -fdebug-physical-locations. + +2025-08-04 David Malcolm <dmalcolm@redhat.com> + + PR diagnostics/116792 + * diagnostics/html-sink.cc + (html_builder::make_element_for_diagnostic): Don't add the + metadata element if it's empty. + (html_builder::make_element_for_metadata): Return null rather than + an empty element. + +2025-08-04 David Malcolm <dmalcolm@redhat.com> + + * diagnostics/context.h: Move struct counters to its own header + and include it. + * diagnostics/counters.h: New file, from the above. + +2025-08-04 David Malcolm <dmalcolm@redhat.com> + + * diagnostics/context.h: Split struct source_printing_options out + into "diagnostics/source-printing-options.h" and include it. + * diagnostics/source-printing-options.h: New file, from the above. + +2025-08-04 David Malcolm <dmalcolm@redhat.com> + + * diagnostics/context.cc: Update for renaming of option_manager to + option_id_manager and of context::m_option_mgr to + context::m_option_id_mgr. + * diagnostics/context.h: Likewise, moving class declaration to a + new diagnostics/option-id-manager.h. + * diagnostics/lazy-paths.cc: Likewise. + * diagnostics/option-id-manager.h: New file, from material in + diagnostics/context.h. + * lto-wrapper.cc: Update for renaming of option_manager to + option_id_manager. + * opts-common.cc: Likewise. + * opts-diagnostic.h: Likewise. + * opts.cc: Likewise. + * toplev.cc: Likewise. + +2025-08-04 David Malcolm <dmalcolm@redhat.com> + + * diagnostics/buffering.h: Update comment to refer to output sinks + rather than output formats. + +2025-08-04 David Malcolm <dmalcolm@redhat.com> + + * gimple-warn-recursion.cc (pass_warn_recursion::execute): Add + missing auto_diagnostic_group. + +2025-08-04 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu> + + PR rtl-optimization/121303 + * avoid-store-forwarding.cc (is_store_forwarding): Add check + for `off_val` in `is_store_forwarding`. + +2025-08-04 Richard Biener <rguenther@suse.de> + + * tree-vect-slp.cc (vect_analyze_slp): When analyzing a loop + and slp instance discovery fails, immediately fail the whole + process. + +2025-08-04 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-sve-builtins.cc + (function_expander::expand): Assert that the return value + has an appropriate mode. + +2025-08-04 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-protos.h + (aarch64_convert_sve_data_to_pred): Remove the mode argument. + * config/aarch64/aarch64.cc + (aarch64_sve_emit_int_cmp): Allow PRED_MODE to be VNx16BI or + the natural predicate mode for the data mode. + (aarch64_convert_sve_data_to_pred): Remove the mode argument + and instead always create a VNx16BI result. + (aarch64_expand_sve_const_pred): Update call accordingly. + * config/aarch64/aarch64-sve-builtins-base.cc + (svdupq_impl::expand): Likewise, ensuring that the result + has mode VNx16BI. + +2025-08-04 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-protos.h + (aarch64_emit_sve_pred_vec_duplicate): Declare. + * config/aarch64/aarch64.cc + (aarch64_emit_sve_pred_vec_duplicate): New function. + * config/aarch64/aarch64-sve.md (vec_duplicate<PRED_ALL:mode>): Use it. + * config/aarch64/aarch64-sve-builtins-base.cc + (svdup_impl::expand): Handle boolean values specially. Check for + constants and fall back on aarch64_emit_sve_pred_vec_duplicate + for the variable case, ensuring that the result has mode VNx16BI. + +2025-08-04 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/iterators.md (PNEXT_ONLY): New int iterator. + * config/aarch64/aarch64-sve.md + (@aarch64_sve_<sve_pred_op><mode>): Restrict SVE_PITER pattern + to VNx16BI_ONLY. + (@aarch64_sve_<sve_pred_op><mode>): New PNEXT_ONLY pattern for + PRED_HSD. + (*aarch64_sve_<sve_pred_op><mode>): Likewise. + (*aarch64_sve_<sve_pred_op><mode>_cc): Likewise. + +2025-08-04 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-sve2.md (@aarch64_pred_<sve_int_op><mode>): + Split SVE2_MATCH pattern into a VNx16QI_ONLY define_ins and a + VNx8HI_ONLY define_expand. Use a VNx16BI destination for the latter. + (*aarch64_pred_<sve_int_op><mode>): New SVE2_MATCH pattern for + VNx8HI_ONLY. + (*aarch64_pred_<sve_int_op><mode>_cc): Likewise. + +2025-08-04 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-sve.md (@aarch64_pred_fac<cmp_op><mode>): + Replace with... + (@aarch64_pred_fac<cmp_op><mode>_acle): ...this new expander. + (*aarch64_pred_fac<cmp_op><mode>_strict_acle): New pattern. + * config/aarch64/aarch64-sve-builtins-base.cc + (svac_impl::expand): Update accordingly. + +2025-08-04 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-sve.md (@aarch64_pred_fcm<cmp_op><mode>_acle) + (*aarch64_pred_fcm<cmp_op><mode>_acle, @aarch64_pred_fcmuo<mode>_acle) + (*aarch64_pred_fcmuo<mode>_acle): New patterns. + * config/aarch64/aarch64-sve-builtins-base.cc + (svcmp_impl::expand, svcmpuo_impl::expand): Use them. + +2025-08-04 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-sve.md (@aarch64_pred_cmp<cmp_op><mode>_wide): + Split into VNx16QI_ONLY and SVE_FULL_HSI patterns. Use VNx16BI + results for both. + (*aarch64_pred_cmp<cmp_op><mode>_wide): New pattern. + (*aarch64_pred_cmp<cmp_op><mode>_wide_cc): Likewise. + +2025-08-04 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-sve.md + (*aarch64_pred_cmp<cmp_op><mode>_wide_cc): Turn into a + define_insn_and_rewrite and rewrite the governing predicate + of the comparison so that it is identical to the PTEST's. + (*aarch64_pred_cmp<cmp_op><mode>_wide_ptest): Likewise. + +2025-08-04 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-sve.md (@aarch64_pred_cmp<cmp_op><mode>_wide) + (*aarch64_pred_cmp<cmp_op><mode>_wide_cc): Use <VPRED> instead of + VNx16BI for the governing predicate. + (*aarch64_pred_cmp<cmp_op><mode>_wide_ptest): Likewise. + +2025-08-04 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-sve.md (@aarch64_pred_cmp<cmp_op><mode>_acle) + (*aarch64_pred_cmp<cmp_op><mode>_acle, *cmp<cmp_op><mode>_acle_cc) + (*cmp<cmp_op><mode>_acle_and): New patterns that yield VNx16BI + results for all element types. + * config/aarch64/aarch64-sve-builtins-base.cc + (svcmp_impl::expand): Use them. + (svcmp_wide_impl::expand): Likewise when implementing an svcmp_wide + against an in-range constant. + +2025-08-04 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-sve.md (@aarch64_sve_punpk<perm_hilo>_acle) + (*aarch64_sve_punpk<perm_hilo>_acle): New patterns. + * config/aarch64/aarch64-sve-builtins-base.cc + (svunpk_impl::expand): Use them for boolean svunpk*. + +2025-08-04 Richard Sandiford <richard.sandiford@arm.com> + + PR target/121294 + * config/aarch64/aarch64.md (UNSPEC_REV_PRED): New unspec. + * config/aarch64/aarch64-sve.md (@aarch64_sve_rev<mode>_acle) + (*aarch64_sve_rev<mode>_acle): New patterns. + * config/aarch64/aarch64-sve-builtins-base.cc + (svrev_impl::expand): Use the new patterns for boolean svrev. + +2025-08-04 Richard Sandiford <richard.sandiford@arm.com> + + PR target/121294 + * config/aarch64/iterators.md (UNSPEC_TRN1_CONV): Delete. + (UNSPEC_PERMUTE_PRED): New unspec. + * config/aarch64/aarch64-sve.md (@aarch64_sve_trn1_conv<mode>): + Replace with... + (@aarch64_sve_<perm_insn><mode>_acle) + (*aarch64_sve_<perm_insn><mode>_acle): ...these new patterns. + * config/aarch64/aarch64.cc (aarch64_expand_sve_const_pred_trn): + Update accordingly. + * config/aarch64/aarch64-sve-builtins-functions.h + (binary_permute::expand): Use the new _acle patterns for + predicate operations. + +2025-08-04 Richard Sandiford <richard.sandiford@arm.com> + + PR testsuite/121118 + * config/aarch64/iterators.md (VNx16BI_ONLY): New mode iterator. + * config/aarch64/predicates.md (aarch64_ptrue_all_operand): New + predicate. + * config/aarch64/aarch64-sve.md + (@aarch64_sve_while_<while_optab_cmp><GPI:mode><VNx16BI_ONLY:mode>_acle) + (@aarch64_sve_while_<while_optab_cmp><GPI:mode><PRED_HSD:mode>_acle) + (*aarch64_sve_while_<while_optab_cmp><GPI:mode><PRED_HSD:mode>_acle) + (*while_<while_optab_cmp><GPI:mode><PRED_HSD:mode>_acle_cc): New + patterns. + * config/aarch64/aarch64-sve-builtins-functions.h + (while_comparison::expand): Use the new _acle patterns that + always return a VNx16BI. + * config/aarch64/aarch64-sve-builtins-sve2.cc + (svwhilerw_svwhilewr_impl::expand): Likewise. + * config/aarch64/aarch64.cc + (aarch64_sve_move_pred_via_while): Likewise. + +2025-08-04 Richard Sandiford <richard.sandiford@arm.com> + + PR target/121293 + * config/aarch64/aarch64-sve-builtins-base.cc (svdupq_lane::expand): + Use aarch64_sve_reinterpret instead of subregs. Explicitly + reinterpret the result back to the required mode, rather than + leaving the caller to take a subreg. + +2025-08-04 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121362 + * tree-ssa-sccvn.cc (vn_reference_lookup_3): Generalize + aggregate copy handling. + +2025-08-04 Filip Kastl <fkastl@suse.cz> + + * doc/invoke.texi: Add remark about -options being documented + under -fdump-tree. Remove remark about -graph working only for + RTL. + +2025-08-04 H.J. Lu <hjl.tools@gmail.com> + + PR target/120941 + * config/i386/i386-features.cc (x86_cse_kind): Moved before + ix86_place_single_vector_set. + (redundant_load): Likewise. + (ix86_place_single_vector_set): Replace the last argument to the + pointer to redundant_load. For X86_CSE_VEC_DUP, don't place the + vector set outside of the loop to avoid extra spills. + (remove_redundant_vector_load): Pass load to + ix86_place_single_vector_set. + +2025-08-03 Georg-Johann Lay <avr@gjlay.de> + + * config/avr/avr.md (define_insn_and_split) [reload_completed]: + For splits that just append a (clobber (reg:CC REG_CC)) to + the pattern, use avr_add_ccclobber (curr_insn) instead of + repeating the original pattern. + * config/avr/avr-dimode.md: Same. + * config/avr/avr-fixed.md: Same. + +2025-08-03 Georg-Johann Lay <avr@gjlay.de> + + * config/avr/avr.cc (avr_add_ccclobber): New function. + * config/avr/avr-protos.h (avr_add_ccclobber): New proto. + (DONE_ADD_CCC): New define. + +2025-08-03 Richard Biener <rguenther@suse.de> + + PR tree-optimization/90242 + * tree-ssa-sccvn.cc (vn_reference_compute_hash): Use + poly_offset_int for offset accumulation. For hashing + truncate to 64 bits and also hash 64 bits. + (vn_reference_eq): Likewise. + +2025-08-02 Gerald Pfeifer <gerald@pfeifer.com> + + PR target/69374 + * doc/install.texi (Specific) <windows>: Drop note on 16-bit + Windows support. Streamline note on 32-bit support. + +2025-08-01 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121350 + * tree-vect-stmts.cc (vectorizable_store): Pass down SLP + node when costing scalar stores in vect_body. + +2025-08-01 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121349 + * tree-vect-stmts.cc (check_load_store_for_partial_vectors): + Get full SLP mask, reduce to uniform scalar_mask for further + processing if possible. + (vect_check_scalar_mask): Remove scalar mask output, remove + code conditional on slp_mask. + (vectorizable_call): Adjust. + (check_scan_store): Get and check SLP mask. + (vectorizable_store): Eliminate scalar mask variable. + (vectorizable_load): Likewise. + +2025-08-01 Gerald Pfeifer <gerald@pfeifer.com> + + * doc/install.texi (Prerequisites): mdocml.bsd.lv is now + mandoc.bsd.lv. + +2025-08-01 Richard Biener <rguenther@suse.de> + + * tree-vect-stmts.cc (get_group_load_store_type): Remove, + inline into ... + (get_load_store_type): ... this. Remove ncopies parameter. + (vectorizable_load): Adjust. + (vectorizable_store): Likewise. + +2025-08-01 Richard Biener <rguenther@suse.de> + + * tree-vect-stmts.cc (get_group_load_store_type): Remove + checks performed at SLP build time. + (vect_check_store_rhs): Remove scalar RHS output. + (vectorizable_store): Remove uses of scalar RHS. + +2025-08-01 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (VMAT_UNINITIALIZED): New + vect_memory_access_type. + * tree-vect-slp.cc (_slp_tree::_slp_tree): Use it. + +2025-08-01 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121338 + * tree-ssa-loop-ivopts.cc (avg_loop_niter): Return an + unsigned. + (adjust_setup_cost): When niters is so large the division + result is one or zero avoid it. + (create_new_ivs): Adjust. + +2025-08-01 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (vect_simd_clone_data): New. + (_slp_tree::simd_clone_info): Remove. + (SLP_TREE_SIMD_CLONE_INFO): Likewise. + * tree-vect-slp.cc (_slp_tree::_slp_tree): Adjust. + (_slp_tree::~_slp_tree): Likewise. + * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use + tyupe specific data to store SLP_TREE_SIMD_CLONE_INFO. + +2025-08-01 Richard Biener <rguenther@suse.de> + + * tree-vect-slp.cc (_slp_tree::_slp_tree): Adjust. + (_slp_tree::~_slp_tree): Likewise. + * tree-vectorizer.h (vect_data): New base class. + (_slp_tree::u): Remove. + (_slp_tree::data): Add pointer to vect_data. + (_slp_tree::get_data): New helper template. + +2025-08-01 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/121322 + * gimple-ssa-store-merging.cc (find_bswap_or_nop): Return NULL if + count is 0. + +2025-07-31 Georg-Johann Lay <avr@gjlay.de> + + * config/avr/avr.opt.urls (-mfuse-move2): Add url. + +2025-07-31 Georg-Johann Lay <avr@gjlay.de> + + * config/avr/avr.cc (avr_output_addr_vec) <labl>: Asm out its .type. + +2025-07-31 Georg-Johann Lay <avr@gjlay.de> + + PR rtl-optimization/121340 + * config/avr/avr.opt (-mfuse-move2): New option. + * config/avr/avr-passes.def (avr_pass_2moves): Insert after combine. + * config/avr/avr-passes.cc (make_avr_pass_2moves): New function. + (pass_data avr_pass_data_2moves): New static variable. + (avr_pass_2moves): New rtl_opt_pass. + * config/avr/avr-protos.h (make_avr_pass_2moves): New proto. + * common/config/avr/avr-common.cc + (default_options avr_option_optimization_table) <-mfuse-move2>: + Set for -O1 and higher. + * doc/invoke.texi (AVR Options) <-mfuse-move2>: Document. + +2025-07-31 Tamar Christina <tamar.christina@arm.com> + + PR tree-optimization/120805 + * tree-vect-loop-manip.cc (vect_gen_vector_loop_niters): Skip setting + bounds on epilogues. + +2025-07-31 Wilco Dijkstra <wilco.dijkstra@arm.com> + + * common/config/aarch64/cpuinfo.h: Remove unused features, add FEAT_CSSC + and FEAT_MOPS. + * config/aarch64/aarch64-option-extensions.def: Remove FMV support + for RPRES, use PULL rather than AES, add FMV support for CSSC and MOPS. + +2025-07-31 Wilco Dijkstra <wilco.dijkstra@arm.com> + + * config/aarch64/tuning_models/generic_armv9_a.h + (generic_armv9_a_addrcost_table): Use zero cost for himode. + +2025-07-31 Richard Biener <rguenther@suse.de> + + * tree-vect-stmts.cc (get_group_load_store_type): Properly + compare the scalar type of the gather/scatter offset to + the offset vector component type. + +2025-07-31 Richard Biener <rguenther@suse.de> + + * gimple-fold.h (fold_stmt_inplace): Add valueization hook + argument, defaulted to no_follow_ssa_edges. + * gimple-fold.cc (fold_stmt_inplace): Adjust. + +2025-07-31 Artemiy Granat <a.granat@ispras.ru> + + * config/i386/i386-options.cc (ix86_handle_cconv_attribute): + Fix typo. + +2025-07-31 Artemiy Granat <a.granat@ispras.ru> + + * config/i386/i386-options.cc (ix86_handle_cconv_attribute): + Handle simultaneous use of regparm and thiscall attributes in + case when regparm is set before thiscall. + +2025-07-31 Artemiy Granat <a.granat@ispras.ru> + + * config/i386/i386-options.cc (ix86_handle_cconv_attribute): + Fix comments which state that combination of stdcall and fastcall + attributes is valid but redundant. + +2025-07-31 Artemiy Granat <a.granat@ispras.ru> + + * config/i386/i386-options.cc (ix86_handle_cconv_attribute): + Move 64-bit mode check before regparm handling. + +2025-07-31 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121320 + * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Convert + op->off to poly_offset_int before multiplying by + BITS_PER_UNIT. + +2025-07-31 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121323 + * tree-ssa-alias.cc (ao_ref_init_from_ptr_and_range): Check + the pointer offset fits in a HWI when represented in bits. + +2025-07-31 Yury Khrustalev <yury.khrustalev@arm.com> + + * config/aarch64/aarch64.cc (build_ifunc_arg_type): + Add new fields _hwcap3 and _hwcap4. + +2025-07-31 Kishan Parmar <kishan@linux.ibm.com> + + PR target/118890 + * config/rs6000/rs6000.cc (can_be_rotated_to_negative_lis): Avoid left + shift of negative value and guard shift count. + (can_be_built_by_li_and_rldic): Likewise. + (rs6000_emit_set_long_const): Likewise. + * config/rs6000/rs6000.md (splitter for plus into two 16-bit parts): Fix + UB from overflow in addition. + +2025-07-31 Richard Biener <rguenther@suse.de> + + * config/aarch64/aarch64.cc (aarch64_detect_vector_stmt_subtype): + Check for node before dereferencing. + (aarch64_vector_costs::add_stmt_cost): Likewise. + +2025-07-31 Spencer Abson <spencer.abson@arm.com> + + PR target/121028 + * config/aarch64/aarch64-sme.md (aarch64_smstart_sm): Use the .inst + directive if !TARGET_SME. + (aarch64_smstop_sm): Likewise. + +2025-07-31 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (_stmt_vec_info::memory_access_type): Remove. + (STMT_VINFO_MEMORY_ACCESS_TYPE): Likewise. + (vect_mem_access_type): Likewise. + * tree-vect-stmts.cc (vectorizable_store): Do not set + STMT_VINFO_MEMORY_ACCESS_TYPE. Fix SLP_TREE_MEMORY_ACCESS_TYPE + usage. + * tree-vect-loop.cc (update_epilogue_loop_vinfo): Remove + checking of memory access type. + * config/riscv/riscv-vector-costs.cc (costs::compute_local_live_ranges): + Use SLP_TREE_MEMORY_ACCESS_TYPE. + (costs::need_additional_vector_vars_p): Likewise. + (segment_loadstore_group_size): Get SLP node as argument, + use SLP_TREE_MEMORY_ACCESS_TYPE. + (costs::adjust_stmt_cost): Pass down SLP node. + * config/aarch64/aarch64.cc (aarch64_ld234_st234_vectors): Use + SLP_TREE_MEMORY_ACCESS_TYPE instead of vect_mem_access_type. + (aarch64_detect_vector_stmt_subtype): Likewise. + (aarch64_vector_costs::count_ops): Likewise. + (aarch64_vector_costs::add_stmt_cost): Likewise. + +2025-07-31 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vect_transform_loop): Do not verify DRs + have not been modified for epilogue loops. + (update_epilogue_loop_vinfo): Do not copy modified DRs to + the originals. + +2025-07-31 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/121264 + * machmode.h (get_best_mode): Change type of first 2 arguments + from int to HOST_WIDE_INT. + * stor-layout.cc (get_best_mode): Likewise. + +2025-07-31 Jakub Jelinek <jakub@redhat.com> + + * gimple-ssa-store-merging.cc (find_bswap_or_nop): Fix comment typos, + hanlde -> handle. + * config/i386/i386.cc (ix86_gimple_fold_builtin, ix86_rtx_costs): + Likewise. + * config/i386/i386-features.cc (remove_partial_avx_dependency): + Likewise. + +2025-07-31 Richard Biener <rguenther@suse.de> + + * tree-vect-stmts.cc (check_scan_store): Remove redundant + slp_node check. Disallow epilogue vectorization. + +2025-07-31 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (vector_costs::costing_for_scalar): New + accessor. + (add_stmt_cost): For scalar costing force vectype to NULL. + Verify we do not pass in a SLP node. + +2025-07-31 Kito Cheng <kito.cheng@sifive.com> + + PR target/121312 + * config/riscv/arch-canonicalize: Add H extension to the + canonical order. + +2025-07-30 Andrew Pinski <quic_apinski@quicinc.com> + + PR rtl-optimization/121308 + * simplify-rtx.cc (simplify_context::simplify_subreg): Handle + subreg of `not` with word_mode to make it symmetric with the + other bitwise operators. + +2025-07-30 Andrew Pinski <quic_apinski@quicinc.com> + + PR tree-optimization/121236 + PR tree-optimization/121295 + * tree-if-conv.cc (factor_out_operators): Change the phi node + to the new result and args. + +2025-07-30 Andrew Pinski <quic_apinski@quicinc.com> + + Revert: + 2025-07-28 Andrew Pinski <quic_apinski@quicinc.com> + + PR tree-optimization/121236 + * tree-if-conv.cc (is_cond_scalar_reduction): Instead of phi argument, + pass bb and res of the phi. + (factor_out_operators): Add iterator for the phi. Remove the phi + if this is the first time. Return if we had removed the phi. + (predicate_scalar_phi): Add the phi iterator argument. + Update call to is_cond_scalar_reduction. + Update call to factor_out_operators and set the return value to true + when factor_out_operators returns true. + (predicate_all_scalar_phis): Don't remove the phi if predicate_scalar_phi + already removed it. + +2025-07-30 Jan Hubicka <jh@suse.cz> + + * auto-profile.cc (string_table::read): Check gcov_is_error. + (read_profile): Likewise. + * gcov-io.cc (gcov_is_error): Export for gcc linkage. + * gcov-io.h (gcov_is_error): Declare. + +2025-07-30 Richard Biener <rguenther@suse.de> + + * config/i386/i386.cc (ix86_default_vector_cost): Split + out from ... + (ix86_builtin_vectorization_cost): ... this and use + mode instead of vectype as argument. + (ix86_vector_costs::add_stmt_cost): Call + ix86_default_vector_cost instead of ix86_builtin_vectorization_cost. + +2025-07-30 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> + + PR target/117015 + * config/s390/s390-protos.h (s390_expand_int_spaceship): New + function. + (s390_expand_fp_spaceship): New function. + * config/s390/s390.cc (s390_expand_int_spaceship): New function. + (s390_expand_fp_spaceship): New function. + * config/s390/s390.md (spaceship<mode>4): New expander. + +2025-07-30 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> + + * cprop.cc (bypass_block): Extract single set. + (bypass_conditional_jumps): Ditto. + +2025-07-30 H.J. Lu <hjl.tools@gmail.com> + + PR target/120427 + * config/i386/i386.md (peephole2): Transform "movq $-1,reg" to + "pushq $-1; popq reg" for -Oz if reg is a legacy integer register. + +2025-07-30 Jan Hubicka <jh@suse.cz> + + * auto-profile.cc (function_instance::match): Disable warning + about bogus locations since dwarf does not represent enough + info to output them correctly in all cases. + (add_scale): Use nonzero_p instead of orig.force_nonzero () == orig. + (afdo_adjust_guessed_profile): Add missing newline in dump + file. + +2025-07-30 Jan Hubicka <jh@suse.cz> + + * symtab.cc (symbol_table::change_decl_assembler_name): Recompute DECL_RTL + in case it is already computed. + +2025-07-30 Jan Hubicka <jh@suse.cz> + + * predict.cc (unlikely_executed_edge_p): Ignore EDGE_EH if profile + is reliable. + (unlikely_executed_stmt_p): special case builtin_trap/unreachable and + ignore other heuristics for reliable profiles. + (tree_estimate_probability): Disable unlikely bb detection when + doing dry run + +2025-07-30 Andrew Stubbs <ams@baylibre.com> + Julian Brown <julian@codesourcery.com> + + * doc/tm.texi.in (TARGET_VECTORIZE_PREFER_GATHER_SCATTER): Add + documentation hook. + * doc/tm.texi: Regenerate. + * target.def (prefer_gather_scatter): Add target hook under vectorizer. + * hooks.cc (hook_bool_mode_int_unsigned_false): New function. + * hooks.h (hook_bool_mode_int_unsigned_false): New prototype. + * tree-vect-stmts.cc (vect_use_strided_gather_scatters_p): Add + parameters group_size and single_element_p, and rework to use + targetm.vectorize.prefer_gather_scatter. + (get_group_load_store_type): Move some of the condition into + vect_use_strided_gather_scatters_p. + * config/gcn/gcn.cc (gcn_prefer_gather_scatter): New function. + (TARGET_VECTORIZE_PREFER_GATHER_SCATTER): Define hook. + +2025-07-30 Andrew Stubbs <ams@baylibre.com> + + * config/gcn/gcn.cc (gcn_option_override): Add note to set default for + param_vect_partial_vector_usage to "1". + * optc-save-gen.awk: Don't pass through options marked "NoOffload". + * params.opt (-param=vect-epilogues-nomask): Add NoOffload. + (-param=vect-partial-vector-usage): Likewise. + (-param=vect-inner-loop-cost-factor): Likewise. + +2025-07-30 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121130 + * tree-vect-stmts.cc (vectorizable_call): Bail out for + .MASK_CALL. + +2025-07-30 Pengfei Li <Pengfei.Li2@arm.com> + + PR tree-optimization/121020 + * tree-vect-loop-manip.cc (vect_do_peeling): Update the + condition of omitting the skip-vector check. + * tree-vectorizer.h (LOOP_VINFO_USE_VERSIONING_WITHOUT_PEELING): + Add a helper macro. + +2025-07-30 Pengfei Li <Pengfei.Li2@arm.com> + + PR tree-optimization/121190 + * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment): + Increase alignment requirement for speculative loads. + +2025-07-30 Alfie Richards <alfie.richards@arm.com> + + PR target/121300 + * config/aarch64/aarch64-sve-builtins-sme.def (svamin/svamax): Fix + arch gating. + +2025-07-30 Richard Biener <rguenther@suse.de> + + * tree-vect-stmts.cc (get_group_load_store_type): + Process STMT_VINFO_GATHER_SCATTER before reading + memory_access_type. + +2025-07-30 Spencer Abson <spencer.abson@arm.com> + + * config/aarch64/aarch64-sve.md (@cond_<optab><mode>): Extend + to support partial FP modes. + (*cond_<optab><mode>_2_strict): Extend from SVE_FULL_F to SVE_F, + use aarch64_predicate_operand. + (*cond_<optab><mode>_4_strict): Extend from SVE_FULL_F_B16B16 to + SVE_F_B16B16, use aarch64_predicate_operand. + (*cond_<optab><mode>_any_strict): Likewise. + +2025-07-30 Spencer Abson <spencer.abson@arm.com> + + * config/aarch64/aarch64-sve.md (*cond_<optab><mode>_2_relaxed): + Extend from SVE_FULL_F to SVE_F. + (*cond_<optab><mode>_4_relaxed): Extend from SVE_FULL_F_B16B16 + to SVE_F_B16B16. + (*cond_<optab><mode>_any_relaxed): Likewise. + +2025-07-30 Spencer Abson <spencer.abson@arm.com> + + * config/aarch64/aarch64-sve.md (<optab><mode>4): Extend from + SVE_FULL_F_B16B16 to SVE_F_B16B16. Use aarch64_sve_fp_pred instead + of aarch64_ptrue_reg. + (@aarch64_pred_<optab><mode>): Extend from SVE_FULL_F_B16B16 to + SVE_F_B16B16. Use aarch64_predicate_operand. + +2025-07-30 liuhongt <hongtao.liu@intel.com> + + * config/i386/i386-modes.def: Remove VECTOR_MODES(FLOAT, 256) + and VECTOR_MODE (INT, SI, 64). + * config/i386/i386.cc (ix86_hard_regno_nregs): Remove related + code for V64SF/V64SImode. + +2025-07-30 liuhongt <hongtao.liu@intel.com> + + PR target/121274 + * config/i386/sse.md (*vec_concatv2di_0): Add a splitter + before it. + +2025-07-30 Andrew Pinski <quic_apinski@quicinc.com> + + PR rtl-optimization/121302 + * simplify-rtx.cc (simplify_context::simplify_subreg): Use + byte instead of 0 when calling simplify_subreg. + +2025-07-29 Spencer Abson <spencer.abson@arm.com> + + * config/aarch64/aarch64-protos.h (aarch64_sve_emit_masked_fp_pred): + Declare. + * config/aarch64/aarch64-sve.md (and<mode>3): Change this to... + (@and<mode>3): ...this, so that we can use gen_and3. + (@cond_<optab><mode>): Extend from SVE_FULL_F_B16B16 to SVE_F_B16B16, + use aarch64_predicate_operand. + (*cond_<optab><mode>_2_strict): Likewise. + (*cond_<optab><mode>_3_strict): Likewise. + (*cond_<optab><mode>_any_strict): Likwise. + (*cond_<optab><mode>_2_const_strict): Extend from SVE_FULL_F to SVE_F, + use aarch64_predicate_operand. + (*cond_<optab><mode>_any_const_strict): Likewise. + (*cond_sub<mode>_3_const_strict): Likwise. + (*cond_sub<mode>_const_strict): Likewise. + (*vcond_mask_<mode><vpred>): Use aarch64_predicate_operand, and update + the comment here. + * config/aarch64/aarch64.cc (aarch64_sve_emit_masked_fp_pred): New + function. Helper to mask the predicate in conditional expanders. + +2025-07-29 Dongyan Chen <chendongyan@isrc.iscas.ac.cn> + + * Makefile.in: Add riscv-mcpu.texi and riscv-mtune.texi to the list + of files to be processed by the Texinfo generator. + * config/riscv/t-riscv: Add rule for generating riscv-mcpu.texi + and riscv-mtune.texi. + * doc/invoke.texi: Replace hand‑written extension table with + `@include riscv-mcpu.texi` and `@include riscv-mtune.texi` to + pull in auto‑generated entries. + * config/riscv/gen-riscv-mcpu-texi.cc: New file. + * config/riscv/gen-riscv-mtune-texi.cc: New file. + * doc/riscv-mcpu.texi: New file. + * doc/riscv-mtune.texi: New file. + +2025-07-29 Richard Sandiford <richard.sandiford@arm.com> + + * simplify-rtx.cc (simplify_context::simplify_subreg): Distribute + lowpart subregs through AND/IOR/XOR, if doing so eliminates one + of the terms. + (test_scalar_int_ext_ops): Add some tests of the above for integers. + * config/aarch64/aarch64.cc (aarch64_test_sve_folding): Likewise + add tests for predicate modes. + +2025-07-29 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-sve-builtins.cc + (function_expander::get_reg_target): Check whether the target + is a valid register_operand. + +2025-07-29 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu> + + PR rtl-optimization/120660 + * avoid-store-forwarding.cc (process_store_forwarding): + Fix instruction generation when haveing multiple stores with + base offset. + +2025-07-29 Christoph Müllner <christoph.muellner@vrull.eu> + + * common/config/riscv/riscv-common.cc (riscv_ext_is_subset): + Remove use of structured binding to fix compiler warning. + +2025-07-29 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu> + + PR rtl-optimization/119795 + * avoid-store-forwarding.cc + (store_forwarding_analyzer::avoid_store_forwarding): Skip + transformations for stores that operate on the same address + range as deleted ones. + +2025-07-29 Pan Li <pan2.li@intel.com> + + * match.pd: Add mul based unsigned SAT_MUL. + +2025-07-29 Richard Biener <rguenther@suse.de> + + PR tree-optimization/120687 + * tree-ssa-reassoc.cc (reassociate_bb): Do not disturb + the sorted operand order in the early pass. + * tree-vect-slp.cc (vect_analyze_slp): Dump when a detected + reduction chain fails SLP discovery. + +2025-07-29 Alfie Richards <alfie.richards@arm.com> + + PR middle-end/121261 + * vec.h: Add null ptr check. + +2025-07-29 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/121159 + * calls.cc (can_implement_as_sibling_call_p): Don't reject declared + noreturn functions in musttail calls. + +2025-07-29 Andrew Pinski <quic_apinski@quicinc.com> + + * output.h (MAX_ALIGN_MERGABLE): New define. + * tree-switch-conversion.cc (switch_conversion::build_one_array): + Use MAX_ALIGN_MERGABLE instead of 256. + * varasm.cc (mergeable_string_section): Likewise + (mergeable_constant_section): Likewise + +2025-07-29 Andrew Pinski <quic_apinski@quicinc.com> + + PR middle-end/120523 + * output.h (mergeable_constant_section): New declaration taking + unsigned HOST_WIDE_INT for the size. + * tree-switch-conversion.cc (switch_conversion::build_one_array): + Increase the alignment of CSWTCH for sizes less than 32bytes. + * varasm.cc (mergeable_constant_section): Split out twice. + One that takes the size in unsigned HOST_WIDE_INT and the + other size in a tree. + (default_elf_select_section): Pass DECL_SIZE instead of + DECL_MODE to mergeable_constant_section. + +2025-07-29 Richard Biener <rguenther@suse.de> + + * tree-vect-stmts.cc (vectorizable_load): Un-factor VMAT + specific code to their handling blocks. + +2025-07-29 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (gather_scatter_info::offset_dt): Remove. + * tree-vect-data-refs.cc (vect_describe_gather_scatter_call): + Do not set it. + (vect_check_gather_scatter): Likewise. + * tree-vect-stmts.cc (vect_truncate_gather_scatter_offset): + Likewise. + (get_group_load_store_type): Use the vector type of the offset + SLP child. Do not re-check vect_is_simple_use validated by + SLP build. + +2025-07-28 Georg-Johann Lay <avr@gjlay.de> + + PR target/121277 + * config/avr/avr.cc (avr_addr_space_convert): When converting + from generic AS to __flashx, don't set bit 23. + (avr_convert_to_type): Don't -Waddr-space-convert when NULL + is converted to __flashx or to __flash. + +2025-07-28 Andrew Pinski <quic_apinski@quicinc.com> + + PR tree-optimization/121236 + * tree-if-conv.cc (is_cond_scalar_reduction): Instead of phi argument, + pass bb and res of the phi. + (factor_out_operators): Add iterator for the phi. Remove the phi + if this is the first time. Return if we had removed the phi. + (predicate_scalar_phi): Add the phi iterator argument. + Update call to is_cond_scalar_reduction. + Update call to factor_out_operators and set the return value to true + when factor_out_operators returns true. + (predicate_all_scalar_phis): Don't remove the phi if predicate_scalar_phi + already removed it. + +2025-07-28 H.J. Lu <hjl.tools@gmail.com> + + PR target/121208 + * config/i386/i386.cc (ix86_tls_get_addr): Issue an error for + -mtls-dialect=gnu with no_caller_saved_registers attribute and + suggest -mtls-dialect=gnu2. + +2025-07-28 Mikael Pettersson <mikpelinux@gmail.com> + + PR other/121260 + * diagnostics/changes.cc: Correct nesting of namespaces + and #if CHECKING_P blocks. + * diagnostics/context.cc: Likewise. + * diagnostics/html-sink.cc: Likewise. + * diagnostics/output-spec.cc: Likewise. + * diagnostics/sarif-sink.cc: Likewise. + +2025-07-28 Tobias Burnus <tburnus@baylibre.com> + + * config/nvptx/nvptx.opt (march-map=): Add sm_100{,f,a}, + sm_101{,f,a}, sm_103{,a,f}, sm_120{,a,f} and sm_121{,f,a}. + +2025-07-28 Tobias Burnus <tburnus@baylibre.com> + + * config/gcn/gcn.md (atomic_load, atomic_store, atomic_exchange): + Fix CDNA3 L2 cache write-back before atomic instructions. + +2025-07-28 Richard Biener <rguenther@suse.de> + + * tree-vect-stmts.cc (check_load_store_for_partial_vectors): + Make *gs_info const. + (vect_build_one_gather_load_call): Likewise. + (vect_build_one_scatter_store_call): Likewise. + (vect_get_gather_scatter_ops): Likewise. + (vect_get_strided_load_store_ops): Likewise. + +2025-07-28 Tobias Burnus <tburnus@baylibre.com> + + * config/gcn/gcn.md (define_attr "vcmp"): Add with values + vcmp/vcmpx/no. + (*movbi, cstoredi4.., cstore<mode>4): Set it. + * config/gcn/gcn-valu.md (vec_cmp<mode>...): Likewise. + * config/gcn/gcn.cc (gcn_cmpx_insn_p): Remove. + (gcn_md_reorg): Add two new conditions for MI300. + +2025-07-28 Tobias Burnus <tburnus@baylibre.com> + + * config/gcn/gcn-opts.h (enum hsaco_attr_type): Add comment + about 'sc0'. + * config/gcn/gcn.cc (gcn_md_reorg): Use gen_nops instead of gen_nop. + (print_operand_address): Document 'R' and 'V' in the + pre-function comment as well. + * config/gcn/gcn.md (nops): Add. + +2025-07-28 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121256 + * tree-vect-loop.cc (vectorizable_recurr): Build a correct + initialization vector for SLP_TREE_LANES > 1. + +2025-07-28 Richard Biener <rguenther@suse.de> + + * tree-vectorizer.h (_slp_tree::type): Add. + (_slp_tree::u): Likewise. + (_stmt_vec_info::type): Remove. + (STMT_VINFO_TYPE): Likewise. + (SLP_TREE_TYPE): New. + * tree-vectorizer.cc (vec_info::new_stmt_vec_info): Do not + initialize type. + * tree-vect-slp.cc (_slp_tree::_slp_tree): Initialize type. + (vect_slp_analyze_node_operations): Adjust. + (vect_schedule_slp_node): Likewise. + * tree-vect-patterns.cc (vect_init_pattern_stmt): Do not + copy STMT_VINFO_TYPE. + * tree-vect-loop.cc: Set SLP_TREE_TYPE instead of + STMT_VINFO_TYPE everywhere. + (vect_create_loop_vinfo): Do not set STMT_VINFO_TYPE on + loop conditions. + * tree-vect-stmts.cc: Set SLP_TREE_TYPE instead of + STMT_VINFO_TYPE everywhere. + (vect_analyze_stmt): Adjust. + (vect_transform_stmt): Likewise. + * config/aarch64/aarch64.cc (aarch64_vector_costs::count_ops): + Access SLP_TREE_TYPE instead of STMT_VINFO_TYPE. + * config/i386/i386.cc (ix86_vector_costs::add_stmt_cost): + Remove non-SLP element-wise load/store matching. + * config/rs6000/rs6000.cc + (rs6000_cost_data::update_target_cost_per_stmt): Pass in + the SLP node. Use that to get at the memory access + kind and type. + (rs6000_cost_data::add_stmt_cost): Pass down SLP node. + * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): + Use SLP_TREE_TYPE. + (costs::need_additional_vector_vars_p): Likewise. + (costs::update_local_live_ranges): Likewise. + +2025-07-28 Jennifer Schmitz <jschmitz@nvidia.com> + Dhruv Chawla <dhruvc@nvidia.com> + + * config/aarch64/aarch64-cores.def (olympus): Use olympus tuning + model. + * config/aarch64/aarch64.cc: Include olympus.h. + * config/aarch64/tuning_models/olympus.h: New file. + +2025-07-28 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.h + (CASE_VECTOR_SHORTEN_MODE): Delete. + +2025-07-28 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (xtensa_is_insn_L32R_p): + Re-rewrite to more accurately capture insns that could be L32R machine + instructions wherever possible, and add comments that help understand + the intent of the process. + +2025-07-27 Pan Li <pan2.li@intel.com> + + * config/riscv/riscv-v.cc (expand_vx_binary_vxrm_vec_vec_dup): + Add new case UNSPEC_VAADD. + (expand_vx_binary_vxrm_vec_dup_vec): Ditto. + * config/riscv/riscv.cc (riscv_rtx_costs): Ditto. + * config/riscv/vector-iterators.md: Add new case UNSPEC_VAADD to + iterator. + 2025-07-27 Nathaniel Shead <nathanieloshead@gmail.com> PR middle-end/120855 |