diff options
27 files changed, 199 insertions, 579 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 62c0718..496ef95 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,89 @@ -2012-08-15 Segher Boessenkool <segher@kernel.crashing.org> +2012-08-15 Segher Boessenkool <segher@kernel.crashing.org> + + * common/config/rs6000/rs6000-common.c (rs6000_handle_option): + Delete handling for -mno-powerpc and -mpowerpc. + * config/rs6000/aix43.h (ASM_CPU_SPEC): Similar. + (ASM_DEFAULT_SPEC): Use -mppc instead of -mcom. + * config/rs6000/aix51.h (ASM_CPU_SPEC, ASM_DEFAULT_SPEC): Ditto. + * config/rs6000/aix52.h (TARGET_DEFAULT): Delete MASK_POWERPC. + * config/rs6000/aix53.h (TARGET_DEFAULT): Ditto. + * config/rs6000/aix61.h (TARGET_DEFAULT): Ditto. + * config/rs6000/darwin.h (TARGET_DEFAULT): Ditto. + * config/rs6000/darwin64.h (TARGET_DEFAULT): Ditto. + * config/rs6000/default64.h (TARGET_DEFAULT): Ditto. + * config/rs6000/driver-rs6000.c (asm_names): Delete handling + for -mcpu=common and -mpowerpc. + * config/rs6000/eabi.h (TARGET_DEFAULT): Delete MASK_POWERPC. + * config/rs6000/eabialtivec.h (TARGET_DEFAULT): Ditto. + * config/rs6000/eabispe.h (TARGET_DEFAULT): Ditto. + * config/rs6000/linuxaltivec.h (TARGET_DEFAULT): Ditto. + * config/rs6000/linuxspe.h (TARGET_DEFAULT): Ditto. + * config/rs6000/rs6000-builtin.def (RS6000_BUILTIN_CFSTRING): + Use RS6000_BTM_ALWAYS instead of RS6000_BTM_POWERPC. + * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): + Adjust. + (rs6000_cpu_cpp_builtins): Adjust. + * config/rs6000/rs6000.c (POWERPC_BASE_MASK): Delete MASK_POWERPC. + (rs6000_builtin_mask_calculate): Adjust. + (rs6000_emit_move): Delete code for ! TARGET_POWERPC. + (rs6000_init_libfuncs): Ditto. + (rs6000_output_function_prologue): Ditto. + (rs6000_opt_masks): Delete MASK_POWERPC. + (rs6000_builtin_mask_names): Delete RS6000_BTM_POWERPC. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Delete handling for + -mpowerpc. + (RS6000_BTM_POWERPC): Delete. + (RS6000_BTM_COMMON): Delete RS6000_BTM_POWERPC. + * config/rs6000/rs6000.md (extendqisi2 patterns): Adjust for + TARGET_POWERPC always on. + (extendqihi2 patterns): Similar. + (various unnamed subtract patterns): Similar. + (bswaphi2 patterns): Similar. + (divmodsi4): Similar. + (udiv<GPR:mode>3): Similar. + (div<GPR:mode>3 patterns): Similar. + (udivmodsi4): Similar. + (mulhcall): Delete. + (mullcall): Delete. + (divss_call): Delete. + (divus_call): Delete. + (quoss_call): Delete. + (quous_call): Delete. + (insvsi patterns): Adjust. + (addsf3 patterns): Adjust. + (subsf3 patterns): Adjust. + (mulsf3 patterns): Adjust. + (divsf3 patterns): Adjust. + (*fmasf4_fpr): Adjust. + (*fmssf4_fpr): Adjust. + (*nfmasf4_fpr): Adjust. + (*nfmssf4_fpr): Adjust. + (*floatunssidf2_internal): Adjust. + (fix_trunc<SFDF:mode>si2_internal): Adjust. + (fctiwz_<SFDF:mode>): Adjust. + (mulsidi3 patterns): Adjust. + (smulsi3_highpart patterns): Adjust. + (umulsi3_highpart patterns): Adjust. + (fix_trunctfsi2 patterns): Adjust. + (prefetch): Adjust. + * config/rs6000/rs6000.opt (mpowerpc): Replace by stub option. + (mno-powerpc): Delete. + * config/rs6000/sync.md (load_locked<ATOMIC:mode>): Adjust. + (store_conditional<ATOMIC:mode>): Adjust. + (atomic_compare_and_swap<ATOMIC:mode>): Adjust. + (atomic_exchange<ATOMIC:mode>): Adjust. + (atomic_<fetchop_name><ATOMIC:mode>): Adjust. + (atomic_nand<ATOMIC:mode>): Adjust. + (atomic_fetch_<fetchop_name><ATOMIC:mode>): Adjust. + (atomic_fetch_nand<ATOMIC:mode>): Adjust. + (atomic_<fetchop_name>_fetch<ATOMIC:mode>): Adjust. + (atomic_nand_fetch<ATOMIC:mode>): Adjust. + * config/rs6000/sysv4.h (TARGET_DEFAULT): Delete MASK_POWERPC. + * config/rs6000/sysv4le.h (TARGET_DEFAULT): Ditto. + * config/rs6000/vxworks.h (TARGET_DEFAULT): Ditto. + * doc/invoke.texi: Adjust documentation. + +2012-08-15 Segher Boessenkool <segher@kernel.crashing.org> * config/rs6000/rs6000.h (RS6000_BTM_ALWAYS): New. diff --git a/gcc/common/config/rs6000/rs6000-common.c b/gcc/common/config/rs6000/rs6000-common.c index 407e1cc..c903ba3 100644 --- a/gcc/common/config/rs6000/rs6000-common.c +++ b/gcc/common/config/rs6000/rs6000-common.c @@ -81,12 +81,6 @@ rs6000_handle_option (struct gcc_options *opts, struct gcc_options *opts_set, switch (code) { - case OPT_mno_powerpc: - opts->x_target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_POWERPC64); - opts_set->x_target_flags |= (MASK_POWERPC | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_POWERPC64); - break; case OPT_mfull_toc: opts->x_target_flags &= ~MASK_MINIMAL_TOC; opts->x_TARGET_NO_FP_IN_TOC = 0; @@ -113,9 +107,9 @@ rs6000_handle_option (struct gcc_options *opts, struct gcc_options *opts_set, #else case OPT_m64: #endif - opts->x_target_flags |= MASK_POWERPC64 | MASK_POWERPC; + opts->x_target_flags |= MASK_POWERPC64; opts->x_target_flags |= ~opts_set->x_target_flags & MASK_PPC_GFXOPT; - opts_set->x_target_flags |= MASK_POWERPC64 | MASK_POWERPC; + opts_set->x_target_flags |= MASK_POWERPC64; break; #ifdef TARGET_USES_AIX64_OPT @@ -137,11 +131,6 @@ rs6000_handle_option (struct gcc_options *opts, struct gcc_options *opts_set, case OPT_mpowerpc_gpopt: case OPT_mpowerpc_gfxopt: - if (value == 1) - { - opts->x_target_flags |= MASK_POWERPC; - opts_set->x_target_flags |= MASK_POWERPC; - } break; case OPT_mdebug_: diff --git a/gcc/config/rs6000/aix43.h b/gcc/config/rs6000/aix43.h index 9388dd0..e4863ef 100644 --- a/gcc/config/rs6000/aix43.h +++ b/gcc/config/rs6000/aix43.h @@ -49,10 +49,8 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{!mcpu*: %{!maix64: \ - %{mpowerpc*: %{!mpowerpc64: -mppc}} \ - %{mpowerpc64: -mppc64} \ - %{!mpower*: %{!mpowerpc*: %(asm_default)}}}} \ -%{mcpu=common: -mcom} \ + %{!mpowerpc64: -mppc} \ + %{mpowerpc64: -mppc64}}} \ %{mcpu=power3: -m620} \ %{mcpu=power4: -m620} \ %{mcpu=powerpc: -mppc} \ @@ -67,7 +65,7 @@ do { \ %{mcpu=630: -m620}" #undef ASM_DEFAULT_SPEC -#define ASM_DEFAULT_SPEC "-mcom" +#define ASM_DEFAULT_SPEC "-mppc" #undef TARGET_OS_CPP_BUILTINS #define TARGET_OS_CPP_BUILTINS() \ diff --git a/gcc/config/rs6000/aix51.h b/gcc/config/rs6000/aix51.h index 372e781..effd278 100644 --- a/gcc/config/rs6000/aix51.h +++ b/gcc/config/rs6000/aix51.h @@ -43,10 +43,8 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{!mcpu*: %{!maix64: \ - %{mpowerpc*: %{!mpowerpc64: -mppc}} \ - %{mpowerpc64: -mppc64} \ - %{!mpower*: %{!mpowerpc*: %(asm_default)}}}} \ -%{mcpu=common: -mcom} \ + %{!mpowerpc64: -mppc} \ + %{mpowerpc64: -mppc64}}} \ %{mcpu=power3: -m620} \ %{mcpu=power4: -m620} \ %{mcpu=powerpc: -mppc} \ @@ -63,7 +61,7 @@ do { \ %{mcpu=G5: -m620}" #undef ASM_DEFAULT_SPEC -#define ASM_DEFAULT_SPEC "-mcom" +#define ASM_DEFAULT_SPEC "-mppc" #undef TARGET_OS_CPP_BUILTINS #define TARGET_OS_CPP_BUILTINS() \ diff --git a/gcc/config/rs6000/aix52.h b/gcc/config/rs6000/aix52.h index eeeb820..a5f1ca7 100644 --- a/gcc/config/rs6000/aix52.h +++ b/gcc/config/rs6000/aix52.h @@ -99,7 +99,7 @@ do { \ %{pthread: -D_THREAD_SAFE}" #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS) +#define TARGET_DEFAULT MASK_NEW_MNEMONICS #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_POWER4 diff --git a/gcc/config/rs6000/aix53.h b/gcc/config/rs6000/aix53.h index dac0ce0..5c72d57 100644 --- a/gcc/config/rs6000/aix53.h +++ b/gcc/config/rs6000/aix53.h @@ -105,7 +105,7 @@ do { \ %{pthread: -D_THREAD_SAFE}" #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS) +#define TARGET_DEFAULT MASK_NEW_MNEMONICS #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_POWER5 diff --git a/gcc/config/rs6000/aix61.h b/gcc/config/rs6000/aix61.h index 0518d44..c9a89fb 100644 --- a/gcc/config/rs6000/aix61.h +++ b/gcc/config/rs6000/aix61.h @@ -106,7 +106,7 @@ do { \ %{pthread: -D_THREAD_SAFE}" #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS) +#define TARGET_DEFAULT MASK_NEW_MNEMONICS #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_POWER7 diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index 92cd698..13d53f5 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -280,8 +280,7 @@ extern int darwin_emit_branch_islands; default as well. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_POWERPC | MASK_MULTIPLE | MASK_NEW_MNEMONICS \ - | MASK_PPC_GFXOPT) +#define TARGET_DEFAULT (MASK_MULTIPLE | MASK_NEW_MNEMONICS | MASK_PPC_GFXOPT) /* Darwin only runs on PowerPC, so short-circuit POWER patterns. */ #undef TARGET_IEEEQUAD diff --git a/gcc/config/rs6000/darwin64.h b/gcc/config/rs6000/darwin64.h index f97cc29..9b0e257 100644 --- a/gcc/config/rs6000/darwin64.h +++ b/gcc/config/rs6000/darwin64.h @@ -1,5 +1,5 @@ /* Target definitions for PowerPC running Darwin (Mac OS X). - Copyright (C) 2006, 2007, 2010, 2011 Free Software Foundation, Inc. + Copyright (C) 2006-2012 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. @@ -19,7 +19,7 @@ <http://www.gnu.org/licenses/>. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_POWERPC | MASK_POWERPC64 | MASK_64BIT \ +#define TARGET_DEFAULT (MASK_POWERPC64 | MASK_64BIT \ | MASK_MULTIPLE | MASK_NEW_MNEMONICS | MASK_PPC_GFXOPT) #undef DARWIN_ARCH_SPEC diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h index 0ff49aa..8de31b4 100644 --- a/gcc/config/rs6000/default64.h +++ b/gcc/config/rs6000/default64.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for 64 bit powerpc linux defaulting to -m64. - Copyright (C) 2003, 2005, 2007 Free Software Foundation, Inc. + Copyright (C) 2003-2012 Free Software Foundation, Inc. This file is part of GCC. @@ -20,5 +20,4 @@ along with GCC; see the file COPYING3. If not see #undef TARGET_DEFAULT #define TARGET_DEFAULT \ - (MASK_POWERPC | MASK_PPC_GFXOPT | \ - MASK_POWERPC64 | MASK_64BIT | MASK_NEW_MNEMONICS) + (MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_64BIT | MASK_NEW_MNEMONICS) diff --git a/gcc/config/rs6000/driver-rs6000.c b/gcc/config/rs6000/driver-rs6000.c index 36fc27d..5f24ee7 100644 --- a/gcc/config/rs6000/driver-rs6000.c +++ b/gcc/config/rs6000/driver-rs6000.c @@ -371,7 +371,6 @@ static const struct asm_name asm_names[] = { %{!maltivec: %{!mpowerpc64: %(asm_default)}}}" }, #else - { "common", "-mcom" }, { "cell", "-mcell" }, { "power3", "-mppc64" }, { "power4", "-mpower4" }, @@ -419,8 +418,7 @@ static const struct asm_name asm_names[] = { { "e500mc", "-me500mc" }, { NULL, "\ %{mpowerpc64*: -mppc64} \ -%{!mpowerpc64*: %{mpowerpc*: -mppc}} \ -%{!mpowerpc*: %(asm_default)}" }, +%{!mpowerpc64*: %(asm_default)}" }, #endif }; diff --git a/gcc/config/rs6000/eabi.h b/gcc/config/rs6000/eabi.h index 82dec71..d97d12e 100644 --- a/gcc/config/rs6000/eabi.h +++ b/gcc/config/rs6000/eabi.h @@ -1,7 +1,6 @@ /* Core target definitions for GNU compiler for IBM RS/6000 PowerPC targeted to embedded ELF systems. - Copyright (C) 1995, 1996, 2000, 2003, 2004, 2007, 2011 - Free Software Foundation, Inc. + Copyright (C) 1995-2012 Free Software Foundation, Inc. Contributed by Cygnus Support. This file is part of GCC. @@ -22,7 +21,7 @@ /* Add -meabi to target flags. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_EABI) +#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_EABI) /* Invoke an initializer function to set up the GOT. */ #define NAME__MAIN "__eabi" diff --git a/gcc/config/rs6000/eabialtivec.h b/gcc/config/rs6000/eabialtivec.h index 0883f23..af15632 100644 --- a/gcc/config/rs6000/eabialtivec.h +++ b/gcc/config/rs6000/eabialtivec.h @@ -1,6 +1,6 @@ /* Core target definitions for GNU compiler for PowerPC targeted systems with AltiVec support. - Copyright (C) 2001, 2003, 2007, 2011 Free Software Foundation, Inc. + Copyright (C) 2001-2012 Free Software Foundation, Inc. Contributed by Aldy Hernandez (aldyh@redhat.com). This file is part of GCC. @@ -21,7 +21,7 @@ /* Add -meabi and -maltivec to target flags. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_EABI | MASK_ALTIVEC) +#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_EABI | MASK_ALTIVEC) #undef SUBSUBTARGET_OVERRIDE_OPTIONS #define SUBSUBTARGET_OVERRIDE_OPTIONS rs6000_altivec_abi = 1 diff --git a/gcc/config/rs6000/eabispe.h b/gcc/config/rs6000/eabispe.h index e7ffbe3..4fdaf9a 100644 --- a/gcc/config/rs6000/eabispe.h +++ b/gcc/config/rs6000/eabispe.h @@ -1,7 +1,6 @@ /* Core target definitions for GNU compiler for PowerPC embedded targeted systems with SPE support. - Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2011 - Free Software Foundation, Inc. + Copyright (C) 2002-2012 Free Software Foundation, Inc. Contributed by Aldy Hernandez (aldyh@redhat.com). This file is part of GCC. @@ -21,8 +20,7 @@ <http://www.gnu.org/licenses/>. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT \ - (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN | MASK_EABI) +#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN | MASK_EABI) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc -mspe -me500" diff --git a/gcc/config/rs6000/linuxaltivec.h b/gcc/config/rs6000/linuxaltivec.h index 41155c3..c2396fe 100644 --- a/gcc/config/rs6000/linuxaltivec.h +++ b/gcc/config/rs6000/linuxaltivec.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for AltiVec enhanced PowerPC machines running GNU/Linux. - Copyright (C) 2001, 2003, 2007, 2011 Free Software Foundation, Inc. + Copyright (C) 2001-2012 Free Software Foundation, Inc. Contributed by Aldy Hernandez (aldyh@redhat.com). This file is part of GCC. @@ -21,7 +21,7 @@ /* Override rs6000.h and sysv4.h definition. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_ALTIVEC) +#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_ALTIVEC) #undef SUBSUBTARGET_OVERRIDE_OPTIONS #define SUBSUBTARGET_OVERRIDE_OPTIONS rs6000_altivec_abi = 1 diff --git a/gcc/config/rs6000/linuxspe.h b/gcc/config/rs6000/linuxspe.h index 74f7b06..e79ee67 100644 --- a/gcc/config/rs6000/linuxspe.h +++ b/gcc/config/rs6000/linuxspe.h @@ -1,7 +1,6 @@ /* Definitions of target machine for GNU compiler, for PowerPC e500 machines running GNU/Linux. - Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2011 - Free Software Foundation, Inc. + Copyright (C) 2003-2012 Free Software Foundation, Inc. Contributed by Aldy Hernandez (aldy@quesejoda.com). This file is part of GCC. @@ -22,8 +21,7 @@ /* Override rs6000.h and sysv4.h definition. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT \ - (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN) +#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc -mspe -me500" diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 8ef4b05..c8f8f86 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -1,6 +1,5 @@ /* Builtin functions for rs6000/powerpc. - Copyright (C) 2009, 2010, 2011 - Free Software Foundation, Inc. + Copyright (C) 2009-2012 Free Software Foundation, Inc. Contributed by Michael Meissner (meissner@linux.vnet.ibm.com) This file is part of GCC. @@ -1431,5 +1430,5 @@ BU_SPECIAL_X (RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf", RS6000_BTM_FRSQRTES, RS6000_BTC_FP) /* Darwin CfString builtin. */ -BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_POWERPC, +BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS, RS6000_BTC_MISC) diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index c6d344d..a2ef08e 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -293,8 +293,7 @@ rs6000_target_modify_macros (bool define_p, int flags, unsigned bu_mask) (unsigned) flags, bu_mask); /* target_flags based options. */ - if ((flags & MASK_POWERPC) != 0) - rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC"); + rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC"); if ((flags & MASK_PPC_GPOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ"); if ((flags & MASK_PPC_GFXOPT) != 0) @@ -346,10 +345,6 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile) rs6000_target_modify_macros (true, target_flags, rs6000_builtin_mask_calculate ()); - /* _ARCH_COM does not fit in the framework of target_modify_macros, so handle - it specially. */ - if (! TARGET_POWERPC) - builtin_define ("_ARCH_COM"); if (TARGET_FRE) builtin_define ("__RECIP__"); if (TARGET_FRES) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 34948fb..d979b30 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1457,7 +1457,7 @@ static const struct attribute_spec rs6000_attribute_table[] = /* Simplifications for entries below. */ enum { - POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS, + POWERPC_BASE_MASK = MASK_NEW_MNEMONICS, POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC }; @@ -2362,7 +2362,6 @@ rs6000_builtin_mask_calculate (void) | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0) | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0) | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0) - | ((TARGET_POWERPC) ? RS6000_BTM_POWERPC : 0) | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)); } @@ -6953,32 +6952,6 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) && !gpc_reg_operand (operands[1], mode)) operands[1] = force_reg (mode, operands[1]); - if (mode == SFmode && ! TARGET_POWERPC - && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && GET_CODE (operands[0]) == MEM) - { - int regnum; - - if (reload_in_progress || reload_completed) - regnum = true_regnum (operands[1]); - else if (GET_CODE (operands[1]) == REG) - regnum = REGNO (operands[1]); - else - regnum = -1; - - /* If operands[1] is a register, on POWER it may have - double-precision data in it, so truncate it to single - precision. */ - if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) - { - rtx newreg; - newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1]) - : gen_reg_rtx (mode)); - emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); - operands[1] = newreg; - } - } - /* Recognize the case where operand[1] is a reference to thread-local data and load its address to a register. */ if (rs6000_tls_referenced_p (operands[1])) @@ -12685,15 +12658,6 @@ rs6000_common_init_builtins (void) static void rs6000_init_libfuncs (void) { - if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF && !TARGET_POWERPC) - { - /* AIX library routines for float->int conversion. */ - set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc"); - set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc"); - set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc"); - set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc"); - } - if (!TARGET_IEEEQUAD) /* AIX/Darwin/64-bit Linux quad floating point routines. */ if (!TARGET_XL_COMPAT) @@ -20305,18 +20269,6 @@ rs6000_output_function_prologue (FILE *file, } } - /* Write .extern for AIX common mode routines, if needed. */ - if (! TARGET_POWERPC && ! common_mode_defined) - { - fputs ("\t.extern __mulh\n", file); - fputs ("\t.extern __mull\n", file); - fputs ("\t.extern __divss\n", file); - fputs ("\t.extern __divus\n", file); - fputs ("\t.extern __quoss\n", file); - fputs ("\t.extern __quous\n", file); - common_mode_defined = 1; - } - rs6000_pic_labelno++; } @@ -27419,7 +27371,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = #ifdef MASK_STRICT_ALIGN { "strict-align", MASK_STRICT_ALIGN, false, false }, #endif - { "powerpc", MASK_POWERPC, false, false }, { "soft-float", MASK_SOFT_FLOAT, false, false }, { "string", MASK_STRING, false, false }, }; @@ -27436,7 +27387,6 @@ static struct rs6000_opt_mask const rs6000_builtin_mask_names[] = { "frsqrte", RS6000_BTM_FRSQRTE, false, false }, { "frsqrtes", RS6000_BTM_FRSQRTES, false, false }, { "popcntd", RS6000_BTM_POPCNTD, false, false }, - { "powerpc", RS6000_BTM_POWERPC, false, false }, { "cell", RS6000_BTM_CELL, false, false }, }; diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 5c53f85..2edf007 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -102,10 +102,8 @@ #define ASM_CPU_SPEC \ "%{!mcpu*: \ %{mpowerpc64*: -mppc64} \ - %{!mpowerpc64*: %{mpowerpc*: -mppc}} \ - %{!mpowerpc*: %(asm_default)}} \ + %{!mpowerpc64*: %(asm_default)}} \ %{mcpu=native: %(asm_cpu_native)} \ -%{mcpu=common: -mcom} \ %{mcpu=cell: -mcell} \ %{mcpu=power3: -mppc64} \ %{mcpu=power4: -mpower4} \ @@ -2312,7 +2310,6 @@ extern int frame_pointer_needed; #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ -#define RS6000_BTM_POWERPC MASK_POWERPC /* Target is powerpc. */ #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ @@ -2322,7 +2319,6 @@ extern int frame_pointer_needed; | RS6000_BTM_FRSQRTE \ | RS6000_BTM_FRSQRTES \ | RS6000_BTM_POPCNTD \ - | RS6000_BTM_POWERPC \ | RS6000_BTM_CELL) /* Define builtin enum index. */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 6ade53c..19e3a76 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -652,23 +652,10 @@ (const_int 0)))] "") -(define_expand "extendqisi2" - [(use (match_operand:SI 0 "gpc_reg_operand" "")) - (use (match_operand:QI 1 "gpc_reg_operand" ""))] - "" - " -{ - if (TARGET_POWERPC) - emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); - else - emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); - DONE; -}") - -(define_insn "extendqisi2_ppc" +(define_insn "extendqisi2" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] - "TARGET_POWERPC" + "" "extsb %0,%1" [(set_attr "type" "exts")]) @@ -677,7 +664,7 @@ (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) (const_int 0))) (clobber (match_scratch:SI 2 "=r,r"))] - "TARGET_POWERPC" + "" "@ extsb. %2,%1 #" @@ -689,7 +676,7 @@ (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:SI 2 ""))] - "TARGET_POWERPC && reload_completed" + "reload_completed" [(set (match_dup 2) (sign_extend:SI (match_dup 1))) (set (match_dup 0) @@ -703,7 +690,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (sign_extend:SI (match_dup 1)))] - "TARGET_POWERPC" + "" "@ extsb. %0,%1 #" @@ -716,7 +703,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (sign_extend:SI (match_dup 1)))] - "TARGET_POWERPC && reload_completed" + "reload_completed" [(set (match_dup 0) (sign_extend:SI (match_dup 1))) (set (match_dup 2) @@ -724,24 +711,6 @@ (const_int 0)))] "") -(define_expand "extendqisi2_no_power" - [(set (match_dup 2) - (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") - (const_int 24))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (ashiftrt:SI (match_dup 2) - (const_int 24)))] - "! TARGET_POWERPC" - " -{ operands[1] = gen_lowpart (SImode, operands[1]); - operands[2] = gen_reg_rtx (SImode); }") - -(define_expand "zero_extendqihi2" - [(set (match_operand:HI 0 "gpc_reg_operand" "") - (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] - "" - "") - (define_insn "" [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] @@ -803,23 +772,10 @@ (const_int 0)))] "") -(define_expand "extendqihi2" - [(use (match_operand:HI 0 "gpc_reg_operand" "")) - (use (match_operand:QI 1 "gpc_reg_operand" ""))] - "" - " -{ - if (TARGET_POWERPC) - emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); - else - emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); - DONE; -}") - -(define_insn "extendqihi2_ppc" +(define_insn "extendqihi2" [(set (match_operand:HI 0 "gpc_reg_operand" "=r") (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] - "TARGET_POWERPC" + "" "extsb %0,%1" [(set_attr "type" "exts")]) @@ -828,7 +784,7 @@ (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) (const_int 0))) (clobber (match_scratch:HI 2 "=r,r"))] - "TARGET_POWERPC" + "" "@ extsb. %2,%1 #" @@ -840,7 +796,7 @@ (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:HI 2 ""))] - "TARGET_POWERPC && reload_completed" + "reload_completed" [(set (match_dup 2) (sign_extend:HI (match_dup 1))) (set (match_dup 0) @@ -854,7 +810,7 @@ (const_int 0))) (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") (sign_extend:HI (match_dup 1)))] - "TARGET_POWERPC" + "" "@ extsb. %0,%1 #" @@ -867,7 +823,7 @@ (const_int 0))) (set (match_operand:HI 0 "gpc_reg_operand" "") (sign_extend:HI (match_dup 1)))] - "TARGET_POWERPC && reload_completed" + "reload_completed" [(set (match_dup 0) (sign_extend:HI (match_dup 1))) (set (match_dup 2) @@ -875,19 +831,6 @@ (const_int 0)))] "") -(define_expand "extendqihi2_no_power" - [(set (match_dup 2) - (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") - (const_int 24))) - (set (match_operand:HI 0 "gpc_reg_operand" "") - (ashiftrt:SI (match_dup 2) - (const_int 24)))] - "! TARGET_POWERPC" - " -{ operands[0] = gen_lowpart (SImode, operands[0]); - operands[1] = gen_lowpart (SImode, operands[1]); - operands[2] = gen_reg_rtx (SImode); }") - (define_expand "zero_extendhisi2" [(set (match_operand:SI 0 "gpc_reg_operand" "") (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] @@ -1770,41 +1713,21 @@ "") (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") - (match_operand:SI 2 "gpc_reg_operand" "r")))] - "! TARGET_POWERPC" - "{sf%I1|subf%I1c} %0,%2,%1") - -(define_insn "" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I") (match_operand:GPR 2 "gpc_reg_operand" "r,r")))] - "TARGET_POWERPC" + "" "@ subf %0,%2,%1 subfic %0,%2,%1") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] - "! TARGET_POWERPC" - "@ - {sf.|subfc.} %3,%2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r") (match_operand:P 2 "gpc_reg_operand" "r,r")) (const_int 0))) (clobber (match_scratch:P 3 "=r,r"))] - "TARGET_POWERPC" + "" "@ subf. %3,%2,%1 #" @@ -1828,27 +1751,13 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (minus:SI (match_dup 1) (match_dup 2)))] - "! TARGET_POWERPC" - "@ - {sf.|subfc.} %0,%2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r") (match_operand:P 2 "gpc_reg_operand" "r,r")) (const_int 0))) (set (match_operand:P 0 "gpc_reg_operand" "=r,r") (minus:P (match_dup 1) (match_dup 2)))] - "TARGET_POWERPC" + "" "@ subf. %0,%2,%1 #" @@ -2196,7 +2105,7 @@ [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))] - "TARGET_POWERPC" + "" "lhbrx %0,%y1" [(set_attr "length" "4") (set_attr "type" "load")]) @@ -2206,7 +2115,7 @@ (bswap:HI (match_operand:HI 1 "reg_or_mem_operand" ""))) (clobber (match_scratch:SI 2 ""))])] - "TARGET_POWERPC" + "" { if (!REG_P (operands[0]) && !REG_P (operands[1])) operands[1] = force_reg (HImode, operands[1]); @@ -2217,7 +2126,7 @@ (bswap:HI (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r"))) (clobber (match_scratch:SI 2 "=X,X,&r"))] - "TARGET_POWERPC" + "" "@ lhbrx %0,%y1 sthbrx %1,%y0 @@ -2229,7 +2138,7 @@ [(set (match_operand:HI 0 "gpc_reg_operand" "") (bswap:HI (match_operand:HI 1 "gpc_reg_operand" ""))) (clobber (match_operand:SI 2 "gpc_reg_operand" ""))] - "TARGET_POWERPC && reload_completed" + "reload_completed" [(set (match_dup 3) (zero_extract:SI (match_dup 4) (const_int 8) @@ -2704,49 +2613,12 @@ (const_int 0)))] "") -;; Operand 1 is divided by operand 2; quotient goes to operand -;; 0 and remainder to operand 3. -;; ??? At some point, see what, if anything, we can do about if (x % y == 0). -(define_expand "divmodsi4" - [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") - (div:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" ""))) - (set (match_operand:SI 3 "register_operand" "") - (mod:SI (match_dup 1) (match_dup 2)))])] - "! TARGET_POWERPC" - " -{ - emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); - emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); - emit_insn (gen_divss_call ()); - emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); - emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); - DONE; -}") - -(define_expand "udiv<mode>3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "gpc_reg_operand" "")))] - "" - " -{ - if (! TARGET_POWERPC) - { - emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); - emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); - emit_insn (gen_quous_call ()); - emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); - DONE; - } -}") - -(define_insn "*udivsi3" +(define_insn "udiv<mode>3" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") (match_operand:GPR 2 "gpc_reg_operand" "r")))] - "TARGET_POWERPC" + "" "div<wd>u %0,%1,%2" [(set (attr "type") (cond [(match_operand:SI 0 "" "") @@ -2756,37 +2628,24 @@ ;; For powers of two we can do srai/aze for divide and then adjust for ;; modulus. If it isn't a power of two, force operands into register and do -;; a normal divide; for AIX common-mode, use quoss call on register operands. +;; a normal divide. (define_expand "div<mode>3" [(set (match_operand:GPR 0 "gpc_reg_operand" "") (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") (match_operand:GPR 2 "reg_or_cint_operand" "")))] "" - " { - if (GET_CODE (operands[2]) == CONST_INT - && INTVAL (operands[2]) > 0 - && exact_log2 (INTVAL (operands[2])) >= 0) - ; - else if (TARGET_POWERPC) - { - operands[2] = force_reg (<MODE>mode, operands[2]); - } - else - { - emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); - emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); - emit_insn (gen_quoss_call ()); - emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); - DONE; - } -}") + if (GET_CODE (operands[2]) != CONST_INT + || INTVAL (operands[2]) <= 0 + || exact_log2 (INTVAL (operands[2])) < 0) + operands[2] = force_reg (<MODE>mode, operands[2]); +}) -(define_insn "*div<mode>3_no_mq" +(define_insn "*div<mode>3" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") (match_operand:GPR 2 "gpc_reg_operand" "r")))] - "TARGET_POWERPC" + "" "div<wd> %0,%1,%2" [(set (attr "type") (cond [(match_operand:SI 0 "" "") @@ -2886,97 +2745,6 @@ (compare:CC (match_dup 0) (const_int 0)))] "") - -(define_expand "udivmodsi4" - [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") - (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" ""))) - (set (match_operand:SI 3 "gpc_reg_operand" "") - (umod:SI (match_dup 1) (match_dup 2)))])] - "" - " -{ - if (! TARGET_POWERPC) - { - emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); - emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); - emit_insn (gen_divus_call ()); - emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); - emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); - DONE; - } - else - FAIL; -}") - -;; AIX architecture-independent common-mode multiply (DImode), -;; divide/modulus, and quotient subroutine calls. Input operands in R3 and -;; R4; results in R3 and sometimes R4; link register always clobbered by bla -;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but -;; assumed unused if generating common-mode, so ignore. -(define_insn "mulh_call" - [(set (reg:SI 3) - (truncate:SI - (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) - (sign_extend:DI (reg:SI 4))) - (const_int 32)))) - (clobber (reg:SI LR_REGNO))] - "! TARGET_POWERPC" - "bla __mulh" - [(set_attr "type" "imul")]) - -(define_insn "mull_call" - [(set (reg:DI 3) - (mult:DI (sign_extend:DI (reg:SI 3)) - (sign_extend:DI (reg:SI 4)))) - (clobber (reg:SI LR_REGNO)) - (clobber (reg:SI 0))] - "! TARGET_POWERPC" - "bla __mull" - [(set_attr "type" "imul")]) - -(define_insn "divss_call" - [(set (reg:SI 3) - (div:SI (reg:SI 3) (reg:SI 4))) - (set (reg:SI 4) - (mod:SI (reg:SI 3) (reg:SI 4))) - (clobber (reg:SI LR_REGNO)) - (clobber (reg:SI 0))] - "! TARGET_POWERPC" - "bla __divss" - [(set_attr "type" "idiv")]) - -(define_insn "divus_call" - [(set (reg:SI 3) - (udiv:SI (reg:SI 3) (reg:SI 4))) - (set (reg:SI 4) - (umod:SI (reg:SI 3) (reg:SI 4))) - (clobber (reg:SI LR_REGNO)) - (clobber (reg:SI 0)) - (clobber (match_scratch:CC 0 "=x")) - (clobber (reg:CC CR1_REGNO))] - "! TARGET_POWERPC" - "bla __divus" - [(set_attr "type" "idiv")]) - -(define_insn "quoss_call" - [(set (reg:SI 3) - (div:SI (reg:SI 3) (reg:SI 4))) - (clobber (reg:SI LR_REGNO))] - "! TARGET_POWERPC" - "bla __quoss" - [(set_attr "type" "idiv")]) - -(define_insn "quous_call" - [(set (reg:SI 3) - (udiv:SI (reg:SI 3) (reg:SI 4))) - (clobber (reg:SI LR_REGNO)) - (clobber (reg:SI 0)) - (clobber (match_scratch:CC 0 "=x")) - (clobber (reg:CC CR1_REGNO))] - "! TARGET_POWERPC" - "bla __quous" - [(set_attr "type" "idiv")]) ;; Logical instructions ;; The logical instructions are mostly combined by using match_operator, @@ -3615,7 +3383,7 @@ (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) (match_operand:SI 5 "mask_operand" "i"))))] - "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])" + "INTVAL(operands[1]) == ~INTVAL(operands[5])" "* { int me = extract_ME(operands[5]); @@ -3634,7 +3402,7 @@ (match_operand:SI 5 "mask_operand" "i")) (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") (match_operand:SI 1 "mask_operand" "i"))))] - "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])" + "INTVAL(operands[1]) == ~INTVAL(operands[5])" "* { int me = extract_ME(operands[5]); @@ -4885,13 +4653,6 @@ "frsp %0,%1" [(set_attr "type" "fp")]) -(define_insn "aux_truncdfsf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))] - "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" - "frsp %0,%1" - [(set_attr "type" "fp")]) - (define_expand "negsf2" [(set (match_operand:SF 0 "gpc_reg_operand" "") (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] @@ -4936,19 +4697,11 @@ [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (match_operand:SF 2 "gpc_reg_operand" "f")))] - "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "fadds %0,%1,%2" [(set_attr "type" "fp") (set_attr "fp_type" "fp_addsub_s")]) -(define_insn "" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") - (match_operand:SF 2 "gpc_reg_operand" "f")))] - "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" - "{fa|fadd} %0,%1,%2" - [(set_attr "type" "fp")]) - (define_expand "subsf3" [(set (match_operand:SF 0 "gpc_reg_operand" "") (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") @@ -4960,19 +4713,11 @@ [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") (match_operand:SF 2 "gpc_reg_operand" "f")))] - "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "fsubs %0,%1,%2" [(set_attr "type" "fp") (set_attr "fp_type" "fp_addsub_s")]) -(define_insn "" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") - (match_operand:SF 2 "gpc_reg_operand" "f")))] - "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" - "{fs|fsub} %0,%1,%2" - [(set_attr "type" "fp")]) - (define_expand "mulsf3" [(set (match_operand:SF 0 "gpc_reg_operand" "") (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") @@ -4984,19 +4729,11 @@ [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (match_operand:SF 2 "gpc_reg_operand" "f")))] - "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "fmuls %0,%1,%2" [(set_attr "type" "fp") (set_attr "fp_type" "fp_mul_s")]) -(define_insn "" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") - (match_operand:SF 2 "gpc_reg_operand" "f")))] - "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" - "{fm|fmul} %0,%1,%2" - [(set_attr "type" "dmul")]) - (define_expand "divsf3" [(set (match_operand:SF 0 "gpc_reg_operand" "") (div:SF (match_operand:SF 1 "gpc_reg_operand" "") @@ -5008,20 +4745,11 @@ [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") (match_operand:SF 2 "gpc_reg_operand" "f")))] - "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU" "fdivs %0,%1,%2" [(set_attr "type" "sdiv")]) -(define_insn "" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") - (match_operand:SF 2 "gpc_reg_operand" "f")))] - "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS - && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU" - "{fd|fdiv} %0,%1,%2" - [(set_attr "type" "ddiv")]) - (define_insn "fres" [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))] @@ -5036,11 +4764,7 @@ (match_operand:SF 2 "gpc_reg_operand" "f") (match_operand:SF 3 "gpc_reg_operand" "f")))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" -{ - return (TARGET_POWERPC - ? "fmadds %0,%1,%2,%3" - : "{fma|fmadd} %0,%1,%2,%3"); -} + "fmadds %0,%1,%2,%3" [(set_attr "type" "fp") (set_attr "fp_type" "fp_maddsub_s")]) @@ -5050,11 +4774,7 @@ (match_operand:SF 2 "gpc_reg_operand" "f") (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" -{ - return (TARGET_POWERPC - ? "fmsubs %0,%1,%2,%3" - : "{fms|fmsub} %0,%1,%2,%3"); -} + "fmsubs %0,%1,%2,%3" [(set_attr "type" "fp") (set_attr "fp_type" "fp_maddsub_s")]) @@ -5064,11 +4784,7 @@ (match_operand:SF 2 "gpc_reg_operand" "f") (match_operand:SF 3 "gpc_reg_operand" "f"))))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" -{ - return (TARGET_POWERPC - ? "fnmadds %0,%1,%2,%3" - : "{fnma|fnmadd} %0,%1,%2,%3"); -} + "fnmadds %0,%1,%2,%3" [(set_attr "type" "fp") (set_attr "fp_type" "fp_maddsub_s")]) @@ -5078,11 +4794,7 @@ (match_operand:SF 2 "gpc_reg_operand" "f") (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" -{ - return (TARGET_POWERPC - ? "fnmsubs %0,%1,%2,%3" - : "{fnms|fnmsub} %0,%1,%2,%3"); -} + "fnmsubs %0,%1,%2,%3" [(set_attr "type" "fp") (set_attr "fp_type" "fp_maddsub_s")]) @@ -5900,8 +5612,7 @@ (define_expand "fix_trunc<mode>si2" [(set (match_operand:SI 0 "gpc_reg_operand" "") (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))] - "TARGET_POWERPC && TARGET_HARD_FLOAT - && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)" + "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)" " { if (!<E500_CONVERT>) @@ -5971,7 +5682,7 @@ (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>"))) (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d")) (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))] - "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "#" "" [(pc)] @@ -6082,7 +5793,7 @@ [(set (match_operand:DI 0 "gpc_reg_operand" "=d") (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))] UNSPEC_FCTIWZ))] - "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "{fcirz|fctiwz} %0,%1" [(set_attr "type" "fp")]) @@ -6542,42 +6253,16 @@ [(set_attr "type" "two") (set_attr "length" "8")]) -(define_expand "mulsidi3" - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) - (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] - "! TARGET_POWERPC64" - " -{ - if (! TARGET_POWERPC) - { - emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); - emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); - emit_insn (gen_mull_call ()); - if (WORDS_BIG_ENDIAN) - emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); - else - { - emit_move_insn (operand_subword (operands[0], 0, 0, DImode), - gen_rtx_REG (SImode, 3)); - emit_move_insn (operand_subword (operands[0], 1, 0, DImode), - gen_rtx_REG (SImode, 4)); - } - DONE; - } -}") - -(define_insn "*mulsidi3_no_mq" +(define_insn "mulsidi3" [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] - "TARGET_POWERPC && ! TARGET_POWERPC64" - "* + "! TARGET_POWERPC64" { return (WORDS_BIG_ENDIAN) ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; -}" +} [(set_attr "type" "imul") (set_attr "length" "8")]) @@ -6585,7 +6270,7 @@ [(set (match_operand:DI 0 "gpc_reg_operand" "") (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] - "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" + "! TARGET_POWERPC64 && reload_completed" [(set (match_dup 3) (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) @@ -6605,7 +6290,7 @@ [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] - "TARGET_POWERPC && ! TARGET_POWERPC64" + "! TARGET_POWERPC64" "* { return (WORDS_BIG_ENDIAN) @@ -6619,7 +6304,7 @@ [(set (match_operand:DI 0 "gpc_reg_operand" "") (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] - "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" + "! TARGET_POWERPC64 && reload_completed" [(set (match_dup 3) (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) @@ -6635,28 +6320,7 @@ operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); }") -(define_expand "smulsi3_highpart" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (truncate:SI - (lshiftrt:DI (mult:DI (sign_extend:DI - (match_operand:SI 1 "gpc_reg_operand" "")) - (sign_extend:DI - (match_operand:SI 2 "gpc_reg_operand" ""))) - (const_int 32))))] - "" - " -{ - if (! TARGET_POWERPC) - { - emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); - emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); - emit_insn (gen_mulh_call ()); - emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); - DONE; - } -}") - -(define_insn "*smulsi3_highpart_no_mq" +(define_insn "smulsi3_highpart" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI @@ -6664,22 +6328,11 @@ (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 32))))] - "TARGET_POWERPC" + "" "mulhw %0,%1,%2" [(set_attr "type" "imul")]) -(define_expand "umulsi3_highpart" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (truncate:SI - (lshiftrt:DI (mult:DI (zero_extend:DI - (match_operand:SI 1 "gpc_reg_operand" "")) - (zero_extend:DI - (match_operand:SI 2 "gpc_reg_operand" ""))) - (const_int 32))))] - "TARGET_POWERPC" - "") - -(define_insn "*umulsi3_highpart_no_mq" +(define_insn "umulsi3_highpart" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI @@ -6687,7 +6340,7 @@ (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 32))))] - "TARGET_POWERPC" + "" "mulhwu %0,%1,%2" [(set_attr "type" "imul")]) @@ -8943,7 +8596,7 @@ (define_expand "fix_trunctfsi2" [(set (match_operand:SI 0 "gpc_reg_operand" "") (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))] - "!TARGET_IEEEQUAD && TARGET_POWERPC && TARGET_HARD_FLOAT + "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128" { if (TARGET_E500_DOUBLE) @@ -8960,7 +8613,7 @@ (clobber (match_dup 3)) (clobber (match_dup 4)) (clobber (match_dup 5))])] - "!TARGET_IEEEQUAD && TARGET_POWERPC + "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" { operands[2] = gen_reg_rtx (DFmode); @@ -14364,7 +14017,7 @@ [(prefetch (match_operand 0 "indexed_or_indirect_address" "a") (match_operand:SI 1 "const_int_operand" "n") (match_operand:SI 2 "const_int_operand" "n"))] - "TARGET_POWERPC" + "" "* { if (GET_CODE (operands[0]) == REG) diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 5091796..9f3567a 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -90,13 +90,9 @@ unsigned int rs6000_debug TargetSave int rs6000_target_flags_explicit +;; This option existed in the past, but now is always on. mpowerpc -Target Report RejectNegative Mask(POWERPC) -Use PowerPC instruction set - -mno-powerpc -Target Report RejectNegative -Do not use PowerPC instruction set +Target RejectNegative Undocumented Ignore mpowerpc64 Target Report Mask(POWERPC64) diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md index 5b79428..59ad0c6 100644 --- a/gcc/config/rs6000/sync.md +++ b/gcc/config/rs6000/sync.md @@ -1,6 +1,5 @@ ;; Machine description for PowerPC synchronization instructions. -;; Copyright (C) 2005, 2007, 2008, 2009, 2011 -;; Free Software Foundation, Inc. +;; Copyright (C) 2005-2012 Free Software Foundation, Inc. ;; Contributed by Geoffrey Keating. ;; This file is part of GCC. @@ -172,7 +171,7 @@ [(set (match_operand:ATOMIC 0 "gpc_reg_operand" "=r") (unspec_volatile:ATOMIC [(match_operand:ATOMIC 1 "memory_operand" "Z")] UNSPECV_LL))] - "TARGET_POWERPC" + "" "<larx> %0,%y1" [(set_attr "type" "load_l")]) @@ -181,7 +180,7 @@ (unspec_volatile:CC [(const_int 0)] UNSPECV_SC)) (set (match_operand:ATOMIC 1 "memory_operand" "=Z") (match_operand:ATOMIC 2 "gpc_reg_operand" "r"))] - "TARGET_POWERPC" + "" "<stcx> %2,%y1" [(set_attr "type" "store_c")]) @@ -194,7 +193,7 @@ (match_operand:SI 5 "const_int_operand" "") ;; is_weak (match_operand:SI 6 "const_int_operand" "") ;; model succ (match_operand:SI 7 "const_int_operand" "")] ;; model fail - "TARGET_POWERPC" + "" { rs6000_expand_atomic_compare_and_swap (operands); DONE; @@ -205,7 +204,7 @@ (match_operand:INT1 1 "memory_operand" "") ;; memory (match_operand:INT1 2 "gpc_reg_operand" "") ;; input (match_operand:SI 3 "const_int_operand" "")] ;; model - "TARGET_POWERPC" + "" { rs6000_expand_atomic_exchange (operands); DONE; @@ -216,7 +215,7 @@ (FETCHOP:INT1 (match_dup 0) (match_operand:INT1 1 "<fetchop_pred>" "")) ;; operand (match_operand:SI 2 "const_int_operand" "")] ;; model - "TARGET_POWERPC" + "" { rs6000_expand_atomic_op (<CODE>, operands[0], operands[1], NULL_RTX, NULL_RTX, operands[2]); @@ -227,7 +226,7 @@ [(match_operand:INT1 0 "memory_operand" "") ;; memory (match_operand:INT1 1 "gpc_reg_operand" "") ;; operand (match_operand:SI 2 "const_int_operand" "")] ;; model - "TARGET_POWERPC" + "" { rs6000_expand_atomic_op (NOT, operands[0], operands[1], NULL_RTX, NULL_RTX, operands[2]); @@ -240,7 +239,7 @@ (FETCHOP:INT1 (match_dup 1) (match_operand:INT1 2 "<fetchop_pred>" "")) ;; operand (match_operand:SI 3 "const_int_operand" "")] ;; model - "TARGET_POWERPC" + "" { rs6000_expand_atomic_op (<CODE>, operands[1], operands[2], operands[0], NULL_RTX, operands[3]); @@ -252,7 +251,7 @@ (match_operand:INT1 1 "memory_operand" "") ;; memory (match_operand:INT1 2 "gpc_reg_operand" "") ;; operand (match_operand:SI 3 "const_int_operand" "")] ;; model - "TARGET_POWERPC" + "" { rs6000_expand_atomic_op (NOT, operands[1], operands[2], operands[0], NULL_RTX, operands[3]); @@ -265,7 +264,7 @@ (FETCHOP:INT1 (match_dup 1) (match_operand:INT1 2 "<fetchop_pred>" "")) ;; operand (match_operand:SI 3 "const_int_operand" "")] ;; model - "TARGET_POWERPC" + "" { rs6000_expand_atomic_op (<CODE>, operands[1], operands[2], NULL_RTX, operands[0], operands[3]); @@ -277,7 +276,7 @@ (match_operand:INT1 1 "memory_operand" "") ;; memory (match_operand:INT1 2 "gpc_reg_operand" "") ;; operand (match_operand:SI 3 "const_int_operand" "")] ;; model - "TARGET_POWERPC" + "" { rs6000_expand_atomic_op (NOT, operands[1], operands[2], NULL_RTX, operands[0], operands[3]); diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h index b9fe92b..d43a699 100644 --- a/gcc/config/rs6000/sysv4.h +++ b/gcc/config/rs6000/sysv4.h @@ -220,7 +220,7 @@ do { \ /* Override rs6000.h definition. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS) +#define TARGET_DEFAULT MASK_NEW_MNEMONICS /* Override rs6000.h definition. */ #undef PROCESSOR_DEFAULT diff --git a/gcc/config/rs6000/sysv4le.h b/gcc/config/rs6000/sysv4le.h index 1559777..128dbac 100644 --- a/gcc/config/rs6000/sysv4le.h +++ b/gcc/config/rs6000/sysv4le.h @@ -1,6 +1,6 @@ /* Target definitions for GCC for a little endian PowerPC running System V.4 - Copyright (C) 1995, 2000, 2003, 2007 Free Software Foundation, Inc. + Copyright (C) 1995-2012 Free Software Foundation, Inc. Contributed by Cygnus Support. This file is part of GCC. @@ -20,7 +20,7 @@ <http://www.gnu.org/licenses/>. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_LITTLE_ENDIAN) +#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_LITTLE_ENDIAN) #undef CC1_ENDIAN_DEFAULT_SPEC #define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_little)" diff --git a/gcc/config/rs6000/vxworks.h b/gcc/config/rs6000/vxworks.h index 6169f16..2f5f6ef 100644 --- a/gcc/config/rs6000/vxworks.h +++ b/gcc/config/rs6000/vxworks.h @@ -1,6 +1,5 @@ /* Definitions of target machine for GNU compiler. Vxworks PowerPC version. - Copyright (C) 1996, 2000, 2002, 2003, 2004, 2005, 2007, 2009, 2010, 2011 - Free Software Foundation, Inc. + Copyright (C) 1996-2012 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. This file is part of GCC. @@ -99,8 +98,7 @@ VXWORKS_ADDITIONAL_CPP_SPEC #undef MULTILIB_DEFAULTS #undef TARGET_DEFAULT -#define TARGET_DEFAULT \ - (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_EABI | MASK_STRICT_ALIGN) +#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_EABI | MASK_STRICT_ALIGN) #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_PPC604 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index f0d8a4a..78bcde7 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -797,7 +797,7 @@ See RS/6000 and PowerPC Options. @gccoptlist{-mcpu=@var{cpu-type} @gol -mtune=@var{cpu-type} @gol -mcmodel=@var{code-model} @gol --mpowerpc -mpowerpc64 -mno-powerpc @gol +-mpowerpc64 @gol -maltivec -mno-altivec @gol -mpowerpc-gpopt -mno-powerpc-gpopt @gol -mpowerpc-gfxopt -mno-powerpc-gfxopt @gol @@ -16555,9 +16555,7 @@ standard hardware multiplication defined in the RL78 software manual. These @samp{-m} options are defined for the IBM RS/6000 and PowerPC: @table @gcctabopt -@item -mpowerpc -@itemx -mno-powerpc -@itemx -mpowerpc-gpopt +@item -mpowerpc-gpopt @itemx -mno-powerpc-gpopt @itemx -mpowerpc-gfxopt @itemx -mno-powerpc-gfxopt @@ -16579,8 +16577,6 @@ These @samp{-m} options are defined for the IBM RS/6000 and PowerPC: @itemx -mno-mfpgpr @itemx -mhard-dfp @itemx -mno-hard-dfp -@opindex mpowerpc -@opindex mno-powerpc @opindex mpowerpc-gpopt @opindex mno-powerpc-gpopt @opindex mpowerpc-gfxopt @@ -16601,17 +16597,6 @@ These @samp{-m} options are defined for the IBM RS/6000 and PowerPC: @opindex mno-mfpgpr @opindex mhard-dfp @opindex mno-hard-dfp -GCC supports two related instruction set architectures for the -RS/6000 and PowerPC@. The @dfn{POWER} instruction set are those -instructions supported by the @samp{rios} chip set used in the original -RS/6000 systems and the @dfn{PowerPC} instruction set is the -architecture of the Freescale MPC5xx, MPC6xx, MPC8xx microprocessors, and -the IBM 4xx, 6xx, and follow-on microprocessors. - -Neither architecture is a subset of the other. However there is a -large common subset of instructions supported by both. An MQ -register is included in processors supporting the POWER architecture. - You use these options to specify which instructions are available on the processor you are using. The default value of these options is determined when configuring GCC@. Specifying the @@ -16619,12 +16604,10 @@ determined when configuring GCC@. Specifying the options. We recommend you use the @option{-mcpu=@var{cpu_type}} option rather than the options listed above. -The @option{-mpowerpc} option allows GCC to generate instructions that -are found only in the 32-bit subset of the PowerPC architecture. -Specifying @option{-mpowerpc-gpopt} implies @option{-mpowerpc} and also allows +Specifying @option{-mpowerpc-gpopt} allows GCC to use the optional PowerPC architecture instructions in the General Purpose group, including floating-point square root. Specifying -@option{-mpowerpc-gfxopt} implies @option{-mpowerpc} and also allows GCC to +@option{-mpowerpc-gfxopt} allows GCC to use the optional PowerPC architecture instructions in the Graphics group, including floating-point select. @@ -16657,10 +16640,6 @@ The @option{-mpowerpc64} option allows GCC to generate the additional and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to @option{-mno-powerpc64}. -If you specify @option{-mno-powerpc}, GCC uses only the instructions -in the common subset of both the POWER and PowerPC -architectures plus some special AIX common-mode calls. - @item -mnew-mnemonics @itemx -mold-mnemonics @opindex mnew-mnemonics @@ -16691,17 +16670,11 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{e5500}, @samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+}, -@samp{power6}, @samp{power6x}, @samp{power7}, @samp{common}, @samp{powerpc}, +@samp{power6}, @samp{power6x}, @samp{power7}, @samp{powerpc}, @samp{powerpc64}, and @samp{rs64}. -@option{-mcpu=common} selects a completely generic processor. Code -generated under this option runs on any POWER or PowerPC processor. -GCC uses only the instructions in the common subset of both -architectures, and does not use the MQ register. GCC assumes a generic -processor model for scheduling purposes. - @option{-mcpu=powerpc}, and @option{-mcpu=powerpc64} specify pure 32-bit -PowerPC (i.e., not MPC601) and 64-bit PowerPC architecture machine +PowerPC and 64-bit PowerPC architecture machine types, with an appropriate, generic processor model assumed for scheduling purposes. @@ -16900,8 +16873,8 @@ only on files that contain less frequently-executed code. @opindex maix32 Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit @code{long} type, and the infrastructure needed to support them. -Specifying @option{-maix64} implies @option{-mpowerpc64} and -@option{-mpowerpc}, while @option{-maix32} disables the 64-bit ABI and +Specifying @option{-maix64} implies @option{-mpowerpc64}, +while @option{-maix32} disables the 64-bit ABI and implies @option{-mno-powerpc64}. GCC defaults to @option{-maix32}. @item -mxl-compat |