diff options
27 files changed, 126 insertions, 72 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b0a478a..84d9817 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,42 @@ 2014-05-23 Segher Boessenkool <segher@kernel.crashing.org> + * config/rs6000/rs6000.md (type): Delete "idiv", "ldiv". Add + "div". + (bits): New mode_attr. + (idiv_ldiv): Delete mode_attr. + (udiv<mode>3, *div<mode>3, div<div_extend>_<mode>): Adjust. + * config/rs6000/rs6000.c (rs6000_adjust_cost, is_cracked_insn, + rs6000_adjust_priority, is_nonpipeline_insn, + insn_must_be_first_in_group, insn_must_be_last_in_group): Adjust. + + * config/rs6000/40x.md (ppc403-idiv): Adjust. + * config/rs6000/440.md (ppc440-idiv): Adjust. + * config/rs6000/476.md (ppc476-idiv): Adjust. + * config/rs6000/601.md (ppc601-idiv): Adjust. + * config/rs6000/603.md (ppc603-idiv): Adjust. + * config/rs6000/6xx.md (ppc604-idiv, ppc620-idiv, ppc630-idiv, + ppc620-ldiv): Adjust. + * config/rs6000/7450.md (ppc7450-idiv): Adjust. + * config/rs6000/7xx.md (ppc750-idiv): Adjust. + * config/rs6000/8540.md (ppc8540_divide): Adjust. + * config/rs6000/a2.md (ppca2-idiv, ppca2-ldiv): Adjust. + * config/rs6000/cell.md (cell-idiv, cell-ldiv): Adjust. + * config/rs6000/e300c2c3.md (ppce300c3_divide): Adjust. + * config/rs6000/e500mc.md (e500mc_divide): Adjust. + * config/rs6000/e500mc64.md (e500mc64_divide): Adjust. + * config/rs6000/e5500.md (e5500_divide, e5500_divide_d): Adjust. + * config/rs6000/e6500.md (e6500_divide, e6500_divide_d): Adjust. + * config/rs6000/mpc.md (mpccore-idiv): Adjust. + * config/rs6000/power4.md (power4-idiv, power4-ldiv): Adjust. + * config/rs6000/power5.md (power5-idiv, power5-ldiv): Adjust. + * config/rs6000/power6.md (power6-idiv, power6-ldiv): Adjust. + * config/rs6000/power7.md (power7-idiv, power7-ldiv): Adjust. + * config/rs6000/power8.md (power8-idiv, power8-ldiv): Adjust. + * config/rs6000/rs64.md (rs64a-idiv, rs64a-ldiv): Adjust. + * config/rs6000/titan.md (titan_fxu_div): Adjust. + +2014-05-23 Segher Boessenkool <segher@kernel.crashing.org> + * config/rs6000/rs6000.md (type): Delete "insert_word", "insert_dword". Add "insert". (size): Update comment. diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md index 02971cb..8ddccba 100644 --- a/gcc/config/rs6000/40x.md +++ b/gcc/config/rs6000/40x.md @@ -82,7 +82,7 @@ "iu_40x") (define_insn_reservation "ppc403-idiv" 33 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") (eq_attr "cpu" "ppc403,ppc405")) "iu_40x*33") diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md index 292177d..e6c28a7 100644 --- a/gcc/config/rs6000/440.md +++ b/gcc/config/rs6000/440.md @@ -84,7 +84,7 @@ "ppc440_issue,ppc440_i_pipe") (define_insn_reservation "ppc440-idiv" 34 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") (eq_attr "cpu" "ppc440")) "ppc440_issue,ppc440_i_pipe*33") diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md index 403752a..5acd668 100644 --- a/gcc/config/rs6000/476.md +++ b/gcc/config/rs6000/476.md @@ -88,7 +88,7 @@ ppc476_i_pipe") (define_insn_reservation "ppc476-idiv" 11 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") (eq_attr "cpu" "ppc476")) "ppc476_issue,\ ppc476_i_pipe*11") diff --git a/gcc/config/rs6000/601.md b/gcc/config/rs6000/601.md index d0afcf7..85892c8 100644 --- a/gcc/config/rs6000/601.md +++ b/gcc/config/rs6000/601.md @@ -66,7 +66,7 @@ "iu_ppc601*5") (define_insn_reservation "ppc601-idiv" 36 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") (eq_attr "cpu" "ppc601")) "iu_ppc601*36") diff --git a/gcc/config/rs6000/603.md b/gcc/config/rs6000/603.md index e6cc444..5f38741 100644 --- a/gcc/config/rs6000/603.md +++ b/gcc/config/rs6000/603.md @@ -87,7 +87,7 @@ "iu_603*2") (define_insn_reservation "ppc603-idiv" 37 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") (eq_attr "cpu" "ppc603")) "iu_603*37") diff --git a/gcc/config/rs6000/6xx.md b/gcc/config/rs6000/6xx.md index 3a3271e..3ff4caf 100644 --- a/gcc/config/rs6000/6xx.md +++ b/gcc/config/rs6000/6xx.md @@ -123,22 +123,25 @@ "mciu_6xx*5") (define_insn_reservation "ppc604-idiv" 20 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") (eq_attr "cpu" "ppc604,ppc604e")) "mciu_6xx*19") (define_insn_reservation "ppc620-idiv" 37 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") + (eq_attr "size" "32") (eq_attr "cpu" "ppc620")) "mciu_6xx*36") (define_insn_reservation "ppc630-idiv" 21 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") + (eq_attr "size" "32") (eq_attr "cpu" "ppc630")) "mciu_6xx*20") (define_insn_reservation "ppc620-ldiv" 37 - (and (eq_attr "type" "ldiv") + (and (eq_attr "type" "div") + (eq_attr "size" "64") (eq_attr "cpu" "ppc620,ppc630")) "mciu_6xx*36") diff --git a/gcc/config/rs6000/7450.md b/gcc/config/rs6000/7450.md index a6a4a1b..3333fd9 100644 --- a/gcc/config/rs6000/7450.md +++ b/gcc/config/rs6000/7450.md @@ -102,7 +102,7 @@ "ppc7450_du,mciu_7450") (define_insn_reservation "ppc7450-idiv" 23 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") (eq_attr "cpu" "ppc7450")) "ppc7450_du,mciu_7450*23") diff --git a/gcc/config/rs6000/7xx.md b/gcc/config/rs6000/7xx.md index 332a663..67f3d11 100644 --- a/gcc/config/rs6000/7xx.md +++ b/gcc/config/rs6000/7xx.md @@ -95,7 +95,7 @@ "ppc750_du,iu1_7xx") (define_insn_reservation "ppc750-idiv" 19 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") (eq_attr "cpu" "ppc750,ppc7400")) "ppc750_du,iu1_7xx*19") diff --git a/gcc/config/rs6000/8540.md b/gcc/config/rs6000/8540.md index 53545ee..578cf8e 100644 --- a/gcc/config/rs6000/8540.md +++ b/gcc/config/rs6000/8540.md @@ -121,7 +121,7 @@ ;; reservation of miu_stage3 here because we use the average latency ;; time. (define_insn_reservation "ppc8540_divide" 14 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") (eq_attr "cpu" "ppc8540,ppc8548")) "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\ ppc8540_mu_div*13") diff --git a/gcc/config/rs6000/a2.md b/gcc/config/rs6000/a2.md index 7cab4d3..52dbbd4 100644 --- a/gcc/config/rs6000/a2.md +++ b/gcc/config/rs6000/a2.md @@ -62,12 +62,14 @@ ;; D.4.9 (define_insn_reservation "ppca2-idiv" 32 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") + (eq_attr "size" "32") (eq_attr "cpu" "ppca2")) "mult*32") (define_insn_reservation "ppca2-ldiv" 65 - (and (eq_attr "type" "ldiv") + (and (eq_attr "type" "div") + (eq_attr "size" "64") (eq_attr "cpu" "ppca2")) "mult*65") diff --git a/gcc/config/rs6000/cell.md b/gcc/config/rs6000/cell.md index 3a2668f..1bf308e 100644 --- a/gcc/config/rs6000/cell.md +++ b/gcc/config/rs6000/cell.md @@ -246,12 +246,14 @@ ;; divide (define_insn_reservation "cell-idiv" 32 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") + (eq_attr "size" "32") (eq_attr "cpu" "cell")) "slot1,nonpipeline,nonpipeline*30") (define_insn_reservation "cell-ldiv" 64 - (and (eq_attr "type" "ldiv") + (and (eq_attr "type" "div") + (eq_attr "size" "64") (eq_attr "cpu" "cell")) "slot1,nonpipeline,nonpipeline*62") diff --git a/gcc/config/rs6000/e300c2c3.md b/gcc/config/rs6000/e300c2c3.md index e9c8f18..2abdfdb 100644 --- a/gcc/config/rs6000/e300c2c3.md +++ b/gcc/config/rs6000/e300c2c3.md @@ -110,7 +110,7 @@ ;; Divide. We use the average latency time here. We omit reserving a ;; retire unit because of the result automata will be huge. (define_insn_reservation "ppce300c3_divide" 20 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\ ppce300c3_mu_div*19") diff --git a/gcc/config/rs6000/e500mc.md b/gcc/config/rs6000/e500mc.md index 426903d..580c30d 100644 --- a/gcc/config/rs6000/e500mc.md +++ b/gcc/config/rs6000/e500mc.md @@ -98,7 +98,7 @@ ;; Divide. We use the average latency time here. (define_insn_reservation "e500mc_divide" 14 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") (eq_attr "cpu" "ppce500mc")) "e500mc_decode,e500mc_issue+e500mc_mu_stage0+e500mc_mu_div,\ e500mc_mu_div*13") diff --git a/gcc/config/rs6000/e500mc64.md b/gcc/config/rs6000/e500mc64.md index 584aef3..8844113 100644 --- a/gcc/config/rs6000/e500mc64.md +++ b/gcc/config/rs6000/e500mc64.md @@ -106,7 +106,7 @@ ;; Divide. We use the average latency time here. (define_insn_reservation "e500mc64_divide" 14 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") (eq_attr "cpu" "ppce500mc64")) "e500mc64_decode,e500mc64_issue+e500mc64_mu_stage0+e500mc64_mu_div,\ e500mc64_mu_div*13") diff --git a/gcc/config/rs6000/e5500.md b/gcc/config/rs6000/e5500.md index fd79ca5..6b257d6 100644 --- a/gcc/config/rs6000/e5500.md +++ b/gcc/config/rs6000/e5500.md @@ -117,13 +117,15 @@ ;; CFX - Divide. (define_insn_reservation "e5500_divide" 16 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") + (eq_attr "size" "32") (eq_attr "cpu" "ppce5500")) "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\ e5500_cfx_div*15") (define_insn_reservation "e5500_divide_d" 26 - (and (eq_attr "type" "ldiv") + (and (eq_attr "type" "div") + (eq_attr "size" "64") (eq_attr "cpu" "ppce5500")) "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\ e5500_cfx_div*25") diff --git a/gcc/config/rs6000/e6500.md b/gcc/config/rs6000/e6500.md index b84f703..52565d9 100644 --- a/gcc/config/rs6000/e6500.md +++ b/gcc/config/rs6000/e6500.md @@ -120,13 +120,15 @@ ;; CFX - Divide. (define_insn_reservation "e6500_divide" 16 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") + (eq_attr "size" "32") (eq_attr "cpu" "ppce6500")) "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\ e6500_cfx_div*15") (define_insn_reservation "e6500_divide_d" 26 - (and (eq_attr "type" "ldiv") + (and (eq_attr "type" "div") + (eq_attr "size" "64") (eq_attr "cpu" "ppce6500")) "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\ e6500_cfx_div*25") diff --git a/gcc/config/rs6000/mpc.md b/gcc/config/rs6000/mpc.md index c4dff56..7fe889c 100644 --- a/gcc/config/rs6000/mpc.md +++ b/gcc/config/rs6000/mpc.md @@ -63,7 +63,7 @@ ; Divide latency varies greatly from 2-11, use 6 as average (define_insn_reservation "mpccore-idiv" 6 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") (eq_attr "cpu" "mpccore")) "mciu_mpc*6") diff --git a/gcc/config/rs6000/power4.md b/gcc/config/rs6000/power4.md index f905a0d..73eac1f 100644 --- a/gcc/config/rs6000/power4.md +++ b/gcc/config/rs6000/power4.md @@ -314,12 +314,14 @@ ; SPR move only executes in first IU. ; Integer division only executes in second IU. (define_insn_reservation "power4-idiv" 36 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") + (eq_attr "size" "32") (eq_attr "cpu" "power4")) "du1_power4+du2_power4,iu2_power4*35") (define_insn_reservation "power4-ldiv" 68 - (and (eq_attr "type" "ldiv") + (and (eq_attr "type" "div") + (eq_attr "size" "64") (eq_attr "cpu" "power4")) "du1_power4+du2_power4,iu2_power4*67") diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md index 407ec71..8aa477a 100644 --- a/gcc/config/rs6000/power5.md +++ b/gcc/config/rs6000/power5.md @@ -255,12 +255,14 @@ ; SPR move only executes in first IU. ; Integer division only executes in second IU. (define_insn_reservation "power5-idiv" 36 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") + (eq_attr "size" "32") (eq_attr "cpu" "power5")) "du1_power5+du2_power5,iu2_power5*35") (define_insn_reservation "power5-ldiv" 68 - (and (eq_attr "type" "ldiv") + (and (eq_attr "type" "div") + (eq_attr "size" "64") (eq_attr "cpu" "power5")) "du1_power5+du2_power5,iu2_power5*67") diff --git a/gcc/config/rs6000/power6.md b/gcc/config/rs6000/power6.md index 3a77fc5..26e17f9 100644 --- a/gcc/config/rs6000/power6.md +++ b/gcc/config/rs6000/power6.md @@ -410,7 +410,8 @@ "store_data_bypass_p") (define_insn_reservation "power6-idiv" 44 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") + (eq_attr "size" "32") (eq_attr "cpu" "power6")) "(iu1_power6*44+iu2_power6*44+fpu1_power6*44)\ |(iu1_power6*44+iu2_power6*44+fpu2_power6*44)"); @@ -425,7 +426,8 @@ ; "store_data_bypass_p") (define_insn_reservation "power6-ldiv" 56 - (and (eq_attr "type" "ldiv") + (and (eq_attr "type" "div") + (eq_attr "size" "64") (eq_attr "cpu" "power6")) "(iu1_power6*56+iu2_power6*56+fpu1_power6*56)\ |(iu1_power6*56+iu2_power6*56+fpu2_power6*56)"); diff --git a/gcc/config/rs6000/power7.md b/gcc/config/rs6000/power7.md index d6ddc24..5527829 100644 --- a/gcc/config/rs6000/power7.md +++ b/gcc/config/rs6000/power7.md @@ -219,12 +219,14 @@ "DU2F_power7,FXU_power7,nothing*3,FXU_power7") (define_insn_reservation "power7-idiv" 36 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") + (eq_attr "size" "32") (eq_attr "cpu" "power7")) "DU2F_power7,iu1_power7*36|iu2_power7*36") (define_insn_reservation "power7-ldiv" 68 - (and (eq_attr "type" "ldiv") + (and (eq_attr "type" "div") + (eq_attr "size" "64") (eq_attr "cpu" "power7")) "DU2F_power7,iu1_power7*68|iu2_power7*68") diff --git a/gcc/config/rs6000/power8.md b/gcc/config/rs6000/power8.md index f7bd9f8..99c9ec7 100644 --- a/gcc/config/rs6000/power8.md +++ b/gcc/config/rs6000/power8.md @@ -250,12 +250,14 @@ ; FXU divides are not pipelined (define_insn_reservation "power8-idiv" 37 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") + (eq_attr "size" "32") (eq_attr "cpu" "power8")) "DU_any_power8,fxu0_power8*37|fxu1_power8*37") (define_insn_reservation "power8-ldiv" 68 - (and (eq_attr "type" "ldiv") + (and (eq_attr "type" "div") + (eq_attr "size" "64") (eq_attr "cpu" "power8")) "DU_any_power8,fxu0_power8*68|fxu1_power8*68") diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index c8aba1f..46cf08e 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -26261,16 +26261,10 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) return 17; break; } - case TYPE_IDIV: + case TYPE_DIV: { if (! store_data_bypass_p (dep_insn, insn)) - return 45; - break; - } - case TYPE_LDIV: - { - if (! store_data_bypass_p (dep_insn, insn)) - return 57; + return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57; break; } default: @@ -26331,16 +26325,10 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) return 17; break; } - case TYPE_IDIV: - { - if (set_to_load_agen (dep_insn, insn)) - return 45; - break; - } - case TYPE_LDIV: + case TYPE_DIV: { if (set_to_load_agen (dep_insn, insn)) - return 57; + return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57; break; } default: @@ -26492,7 +26480,7 @@ is_cracked_insn (rtx insn) || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE || (type == TYPE_MUL && get_attr_dot (insn) == DOT_YES) - || type == TYPE_IDIV || type == TYPE_LDIV + || type == TYPE_DIV || (type == TYPE_INSERT && get_attr_size (insn) == SIZE_32)) return true; @@ -26649,7 +26637,7 @@ rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) break; case TYPE_MUL: - case TYPE_IDIV: + case TYPE_DIV: fprintf (stderr, "priority was %#x (%d) before adjustment\n", priority, priority); if (priority >= 0 && priority < 0x01000000) @@ -26703,8 +26691,7 @@ is_nonpipeline_insn (rtx insn) type = get_attr_type (insn); if (type == TYPE_MUL - || type == TYPE_IDIV - || type == TYPE_LDIV + || type == TYPE_DIV || type == TYPE_SDIV || type == TYPE_DDIV || type == TYPE_SSQRT @@ -27303,8 +27290,7 @@ insn_must_be_first_in_group (rtx insn) case TYPE_CR_LOGICAL: case TYPE_MTJMPR: case TYPE_MFJMPR: - case TYPE_IDIV: - case TYPE_LDIV: + case TYPE_DIV: case TYPE_LOAD_L: case TYPE_STORE_C: case TYPE_ISYNC: @@ -27325,7 +27311,6 @@ insn_must_be_first_in_group (rtx insn) case TYPE_VAR_SHIFT_ROTATE: case TYPE_TRAP: case TYPE_MUL: - case TYPE_IDIV: case TYPE_INSERT: case TYPE_DELAYED_COMPARE: case TYPE_FPCOMPARE: @@ -27338,6 +27323,11 @@ insn_must_be_first_in_group (rtx insn) case TYPE_LOAD_L: case TYPE_STORE_C: return true; + case TYPE_DIV: + if (get_attr_size (insn) == SIZE_32) + return true; + else + break; case TYPE_LOAD: case TYPE_STORE: case TYPE_FPLOAD: @@ -27359,8 +27349,7 @@ insn_must_be_first_in_group (rtx insn) case TYPE_MFCR: case TYPE_MFCRF: case TYPE_MTCR: - case TYPE_IDIV: - case TYPE_LDIV: + case TYPE_DIV: case TYPE_COMPARE: case TYPE_DELAYED_COMPARE: case TYPE_VAR_DELAYED_COMPARE: @@ -27469,7 +27458,6 @@ insn_must_be_last_in_group (rtx insn) case TYPE_VAR_SHIFT_ROTATE: case TYPE_TRAP: case TYPE_MUL: - case TYPE_IDIV: case TYPE_DELAYED_COMPARE: case TYPE_FPCOMPARE: case TYPE_MFCR: @@ -27481,6 +27469,11 @@ insn_must_be_last_in_group (rtx insn) case TYPE_LOAD_L: case TYPE_STORE_C: return true; + case TYPE_DIV: + if (get_attr_size (insn) == SIZE_32) + return true; + else + break; default: break; } diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 0150e43..0de26c9 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -160,7 +160,7 @@ (define_attr "type" "integer,two,three, shift,var_shift_rotate,insert, - mul,halfmul,idiv,ldiv, + mul,halfmul,div, exts,cntlz,popcnt,isel, load,store,fpload,fpstore,vecload,vecstore, cmp, @@ -423,6 +423,9 @@ (V4SI "w") (V2DI "d")]) +;; How many bits in this mode? +(define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")]) + ; DImode bits (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")]) @@ -539,11 +542,6 @@ (V2DI "X,X,X,X,X") (V2DF "X,X,X,X,X") (V1TI "X,X,X,X,X")]) - -;; Mode attribute to give the correct type for integer divides -(define_mode_attr idiv_ldiv [(SI "idiv") - (DI "ldiv")]) - ;; Start with fixed-point load and store insns. Here we put only the more ;; complex forms. Basic data transfer is done later. @@ -2747,7 +2745,8 @@ (match_operand:GPR 2 "gpc_reg_operand" "r")))] "" "div<wd>u %0,%1,%2" - [(set_attr "type" "<idiv_ldiv>")]) + [(set_attr "type" "div") + (set_attr "size" "<bits>")]) ;; For powers of two we can do srai/aze for divide and then adjust for @@ -2771,7 +2770,8 @@ (match_operand:GPR 2 "gpc_reg_operand" "r")))] "" "div<wd> %0,%1,%2" - [(set_attr "type" "<idiv_ldiv>")]) + [(set_attr "type" "div") + (set_attr "size" "<bits>")]) (define_expand "mod<mode>3" [(use (match_operand:GPR 0 "gpc_reg_operand" "")) @@ -15507,7 +15507,8 @@ UNSPEC_DIV_EXTEND))] "TARGET_POPCNTD" "div<wd><div_extend> %0,%1,%2" - [(set_attr "type" "<idiv_ldiv>")]) + [(set_attr "type" "div") + (set_attr "size" "<bits>")]) ;; Pack/unpack 128-bit floating point types that take 2 scalar registers diff --git a/gcc/config/rs6000/rs64.md b/gcc/config/rs6000/rs64.md index aaddb59..0260a1c 100644 --- a/gcc/config/rs6000/rs64.md +++ b/gcc/config/rs6000/rs64.md @@ -86,12 +86,14 @@ "mciu_rs64*34") (define_insn_reservation "rs64a-idiv" 66 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") + (eq_attr "size" "32") (eq_attr "cpu" "rs64a")) "mciu_rs64*66") (define_insn_reservation "rs64a-ldiv" 66 - (and (eq_attr "type" "ldiv") + (and (eq_attr "type" "div") + (eq_attr "size" "64") (eq_attr "cpu" "rs64a")) "mciu_rs64*66") diff --git a/gcc/config/rs6000/titan.md b/gcc/config/rs6000/titan.md index 6c7516d..1d33c0f 100644 --- a/gcc/config/rs6000/titan.md +++ b/gcc/config/rs6000/titan.md @@ -67,7 +67,7 @@ ;; through its latency and initial disptach bottlenecks (i.e. issue ;; slots and fxu scheduler availability) (define_insn_reservation "titan_fxu_div" 34 - (and (eq_attr "type" "idiv") + (and (eq_attr "type" "div") (eq_attr "cpu" "titan")) "titan_issue,titan_fxu_sh") |