diff options
-rw-r--r-- | gcc/ChangeLog | 16 | ||||
-rw-r--r-- | gcc/config.gcc | 2 | ||||
-rw-r--r-- | gcc/config/i386/driver-i386.c | 5 | ||||
-rw-r--r-- | gcc/config/i386/i386-c.c | 7 | ||||
-rw-r--r-- | gcc/config/i386/i386.c | 49 | ||||
-rw-r--r-- | gcc/config/i386/i386.h | 2 | ||||
-rw-r--r-- | gcc/doc/invoke.texi | 8 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
-rw-r--r-- | gcc/testsuite/g++.dg/ext/mv16.C | 6 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/funcspec-56.inc | 1 | ||||
-rw-r--r-- | libgcc/ChangeLog | 4 | ||||
-rw-r--r-- | libgcc/config/i386/cpuinfo.h | 1 |
12 files changed, 100 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5ef0f8d..85ab7f6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,21 @@ 2018-02-02 Julia Koval <julia.koval@intel.com> + * config.gcc: Add -march=icelake. + * config/i386/driver-i386.c (host_detect_local_cpu): Detect icelake. + * config/i386/i386-c.c (ix86_target_macros_internal): Handle icelake. + * config/i386/i386.c (processor_costs): Add m_ICELAKE. + (PTA_ICELAKE, PTA_AVX512VNNI, PTA_GFNI, PTA_VAES, PTA_AVX512VBMI2, + PTA_VPCLMULQDQ, PTA_RDPID, PTA_AVX512BITALG): New. + (processor_target_table): Add icelake. + (ix86_option_override_internal): Handle new PTAs. + (get_builtin_code_for_version): Handle icelake. + (M_INTEL_COREI7_ICELAKE): New. + (fold_builtin_cpu): Handle icelake. + * config/i386/i386.h (TARGET_ICELAKE, PROCESSOR_ICELAKE): New. + * doc/invoke.texi: Add -march=icelake. + +2018-02-02 Julia Koval <julia.koval@intel.com> + * config/i386/i386.c (ix86_option_override_internal): Change flags type to wide_int_bitmask. * wide-int-bitmask.h: New. diff --git a/gcc/config.gcc b/gcc/config.gcc index ec6822b..c52fecf 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -635,7 +635,7 @@ x86_64_archs="amdfam10 athlon64 athlon64-sse3 barcelona bdver1 bdver2 \ bdver3 bdver4 znver1 btver1 btver2 k8 k8-sse3 opteron opteron-sse3 nocona \ core2 corei7 corei7-avx core-avx-i core-avx2 atom slm nehalem westmere \ sandybridge ivybridge haswell broadwell bonnell silvermont knl knm \ -skylake-avx512 cannonlake x86-64 native" +skylake-avx512 cannonlake icelake x86-64 native" # Additional x86 processors supported by --with-cpu=. Each processor # MUST be separated by exactly one space. diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index 5b20575..ca1a2e0 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -822,8 +822,11 @@ const char *host_detect_local_cpu (int argc, const char **argv) if (arch) { /* This is unknown family 0x6 CPU. */ + /* Assume Ice Lake. */ + if (has_gfni) + cpu = "icelake"; /* Assume Cannon Lake. */ - if (has_avx512vbmi) + else if (has_avx512vbmi) cpu = "cannonlake"; /* Assume Knights Mill. */ else if (has_avx5124vnniw) diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 78dd657..c0b4ffe 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -190,6 +190,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__cannonlake"); def_or_undef (parse_in, "__cannonlake__"); break; + case PROCESSOR_ICELAKE: + def_or_undef (parse_in, "__icelake"); + def_or_undef (parse_in, "__icelake__"); + break; /* use PROCESSOR_max to not set/unset the arch macro. */ case PROCESSOR_max: break; @@ -311,6 +315,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, case PROCESSOR_CANNONLAKE: def_or_undef (parse_in, "__tune_cannonlake__"); break; + case PROCESSOR_ICELAKE: + def_or_undef (parse_in, "__tune_icelake__"); + break; case PROCESSOR_LAKEMONT: def_or_undef (parse_in, "__tune_lakemont__"); break; diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 801f8e1..5fa5d9e 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -146,6 +146,7 @@ const struct processor_costs *ix86_cost = NULL; #define m_KNM (1U<<PROCESSOR_KNM) #define m_SKYLAKE_AVX512 (1U<<PROCESSOR_SKYLAKE_AVX512) #define m_CANNONLAKE (1U<<PROCESSOR_CANNONLAKE) +#define m_ICELAKE (1U<<PROCESSOR_ICELAKE) #define m_INTEL (1U<<PROCESSOR_INTEL) #define m_GEODE (1U<<PROCESSOR_GEODE) @@ -858,7 +859,8 @@ static const struct ptt processor_target_table[PROCESSOR_max] = {"knl", &slm_cost, 16, 15, 16, 7, 16}, {"knm", &slm_cost, 16, 15, 16, 7, 16}, {"skylake-avx512", &skylake_cost, 16, 10, 16, 10, 16}, - {"cannonlake", &core_cost, 16, 10, 16, 10, 16}, + {"cannonlake", &skylake_cost, 16, 10, 16, 10, 16}, + {"icelake", &skylake_cost, 16, 10, 16, 10, 16}, {"intel", &intel_cost, 16, 15, 16, 7, 16}, {"geode", &geode_cost, 0, 0, 0, 0, 0}, {"k6", &k6_cost, 32, 7, 32, 7, 32}, @@ -3446,6 +3448,13 @@ ix86_option_override_internal (bool main_args_p, const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61); const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62); const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63); + const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U); + const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1); + const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2); + const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3); + const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4); + const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5); + const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6); const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR; @@ -3467,6 +3476,9 @@ ix86_option_override_internal (bool main_args_p, | PTA_CLWB; const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE_AVX512 | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA; + const wide_int_bitmask PTA_ICELAKE = PTA_CANNONLAKE | PTA_AVX512VNNI + | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG + | PTA_RDPID; const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD; const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE; @@ -3537,7 +3549,8 @@ ix86_option_override_internal (bool main_args_p, {"skylake", PROCESSOR_HASWELL, CPU_HASWELL, PTA_SKYLAKE}, {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_SKYLAKE_AVX512}, - {"cannonlake", PROCESSOR_HASWELL, CPU_HASWELL, PTA_CANNONLAKE}, + {"cannonlake", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_CANNONLAKE}, + {"icelake", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_ICELAKE}, {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL}, {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL}, {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT}, @@ -4107,6 +4120,23 @@ ix86_option_override_internal (bool main_args_p, if (((processor_alias_table[i].flags & PTA_AVX512IFMA) != 0) && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512IFMA)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA; + if (((processor_alias_table[i].flags & PTA_AVX512VNNI) != 0) + && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VNNI)) + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI; + if (((processor_alias_table[i].flags & PTA_GFNI) != 0) + && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_GFNI)) + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI; + if (((processor_alias_table[i].flags & PTA_AVX512VBMI2) != 0) + && !(opts->x_ix86_isa_flags_explicit + & OPTION_MASK_ISA_AVX512VBMI2)) + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2; + if (((processor_alias_table[i].flags & PTA_VPCLMULQDQ) != 0) + && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_VPCLMULQDQ)) + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ; + if (((processor_alias_table[i].flags & PTA_AVX512BITALG) != 0) + && !(opts->x_ix86_isa_flags_explicit + & OPTION_MASK_ISA_AVX512BITALG)) + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG; if (((processor_alias_table[i].flags & PTA_AVX5124VNNIW) != 0) && !(opts->x_ix86_isa_flags2_explicit @@ -4123,6 +4153,12 @@ ix86_option_override_internal (bool main_args_p, if (((processor_alias_table[i].flags & PTA_SGX) != 0) && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX)) opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX; + if (((processor_alias_table[i].flags & PTA_VAES) != 0) + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_VAES)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_VAES; + if (((processor_alias_table[i].flags & PTA_RDPID) != 0) + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_RDPID)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID; if ((processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)) != 0) @@ -32124,7 +32160,10 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) break; case PROCESSOR_HASWELL: case PROCESSOR_SKYLAKE_AVX512: - if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VBMI) + if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_GFNI) + arg_str = "icelake"; + else if (new_target->x_ix86_isa_flags + & OPTION_MASK_ISA_AVX512VBMI) arg_str = "cannonlake"; else if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VL) arg_str = "skylake-avx512"; @@ -32849,7 +32888,8 @@ fold_builtin_cpu (tree fndecl, tree *args) M_INTEL_COREI7_BROADWELL, M_INTEL_COREI7_SKYLAKE, M_INTEL_COREI7_SKYLAKE_AVX512, - M_INTEL_COREI7_CANNONLAKE + M_INTEL_COREI7_CANNONLAKE, + M_INTEL_COREI7_ICELAKE }; static struct _arch_names_table @@ -32874,6 +32914,7 @@ fold_builtin_cpu (tree fndecl, tree *args) {"skylake", M_INTEL_COREI7_SKYLAKE}, {"skylake-avx512", M_INTEL_COREI7_SKYLAKE_AVX512}, {"cannonlake", M_INTEL_COREI7_CANNONLAKE}, + {"icelake", M_INTEL_COREI7_ICELAKE}, {"bonnell", M_INTEL_BONNELL}, {"silvermont", M_INTEL_SILVERMONT}, {"knl", M_INTEL_KNL}, diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 59522cc..9d86450 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -383,6 +383,7 @@ extern const struct processor_costs ix86_size_cost; #define TARGET_KNM (ix86_tune == PROCESSOR_KNM) #define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512) #define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE) +#define TARGET_ICELAKE (ix86_tune == PROCESSOR_ICELAKE) #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL) #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC) #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) @@ -2263,6 +2264,7 @@ enum processor_type PROCESSOR_KNM, PROCESSOR_SKYLAKE_AVX512, PROCESSOR_CANNONLAKE, + PROCESSOR_ICELAKE, PROCESSOR_INTEL, PROCESSOR_GEODE, PROCESSOR_K6, diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index dbc5c47..f3d9336 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -25606,6 +25606,14 @@ RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB and UMIP instruction set support. +@item Icelake +Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, +SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, +XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, +AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, +AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support. + @item k6 AMD K6 CPU with MMX instruction set support. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 21c8134..a9e5d03 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-02-02 Julia Koval <julia.koval@intel.com> + + * gcc.target/i386/funcspec-56.inc: Handle new march. + * g++.dg/ext/mv16.C: Ditto. + 2018-02-02 Georg-Johann Lay <avr@gjlay.de> * lib/target-supports.exp diff --git a/gcc/testsuite/g++.dg/ext/mv16.C b/gcc/testsuite/g++.dg/ext/mv16.C index 1e1ae3d..8fbdb47 100644 --- a/gcc/testsuite/g++.dg/ext/mv16.C +++ b/gcc/testsuite/g++.dg/ext/mv16.C @@ -60,6 +60,10 @@ int __attribute__ ((target("arch=cannonlake"))) foo () { return 16; } +int __attribute__ ((target("arch=icelake"))) foo () { + return 17; +} + int main () { int val = foo (); @@ -82,6 +86,8 @@ int main () assert (val == 15); else if (__builtin_cpu_is ("cannonlake")) assert (val == 16); + else if (__builtin_cpu_is ("icelake")) + assert (val == 17); else assert (val == 0); diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc index ed0748b..837cdc3 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc @@ -145,6 +145,7 @@ extern void test_arch_knl (void) __attribute__((__target__("arch=knl"))); extern void test_arch_knm (void) __attribute__((__target__("arch=knm"))); extern void test_arch_skylake_avx512 (void) __attribute__((__target__("arch=skylake-avx512"))); extern void test_arch_cannonlake (void) __attribute__((__target__("arch=cannonlake"))); +extern void test_arch_icelake (void) __attribute__((__target__("arch=icelake"))); extern void test_arch_k8 (void) __attribute__((__target__("arch=k8"))); extern void test_arch_k8_sse3 (void) __attribute__((__target__("arch=k8-sse3"))); extern void test_arch_opteron (void) __attribute__((__target__("arch=opteron"))); diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index 79c79e8..1eb1663 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,7 @@ +2018-02-02 Julia Koval <julia.koval@intel.com> + + * config/i386/cpuinfo.h (processor_subtypes): Add INTEL_COREI7_ICELAKE. + 2018-01-26 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/lib1funcs.S (__udivmodsi4): Use safe version for RF16 diff --git a/libgcc/config/i386/cpuinfo.h b/libgcc/config/i386/cpuinfo.h index c43d941..a247072 100644 --- a/libgcc/config/i386/cpuinfo.h +++ b/libgcc/config/i386/cpuinfo.h @@ -70,6 +70,7 @@ enum processor_subtypes INTEL_COREI7_SKYLAKE, INTEL_COREI7_SKYLAKE_AVX512, INTEL_COREI7_CANNONLAKE, + INTEL_COREI7_ICELAKE, CPU_SUBTYPE_MAX }; |