diff options
| -rw-r--r-- | gcc/config/aarch64/aarch64.cc | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/pr115969.c | 8 |
2 files changed, 11 insertions, 2 deletions
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 89eb6634..9e51236 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -23377,8 +23377,9 @@ aarch64_endian_lane_rtx (machine_mode mode, unsigned int n) bool aarch64_simd_mem_operand_p (rtx op) { - return MEM_P (op) && (GET_CODE (XEXP (op, 0)) == POST_INC - || REG_P (XEXP (op, 0))); + return (MEM_P (op) + && (GET_CODE (XEXP (op, 0)) == POST_INC || REG_P (XEXP (op, 0))) + && memory_operand (op, VOIDmode)); } /* Return true if OP is a valid MEM operand for an SVE LD1R instruction. */ diff --git a/gcc/testsuite/gcc.target/aarch64/pr115969.c b/gcc/testsuite/gcc.target/aarch64/pr115969.c new file mode 100644 index 0000000..ea46626 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr115969.c @@ -0,0 +1,8 @@ +/* { dg-options "-O2" } */ + +#define vec8 __attribute__((vector_size(8))) +vec8 int f(int *a) +{ + asm("":"+w"(a)); + return (vec8 int){a[0], a[0]}; +} |