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-rw-r--r--gcc/ChangeLog6
-rw-r--r--gcc/testsuite/gcc.target/i386/pr17692.c21
2 files changed, 27 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 36ae71b..46d1a4d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2005-07-28 Richard Henderson <rth@redhat.com>
+
+ PR target/17692
+ * config/i386/i386.c (ix86_split_sse_movcc): Emit DELETED note
+ when expanding to nothing.
+
2005-07-28 Josh Conner <jconner@apple.com>
* ipa-inline.c (update_caller_keys): Fix estimated_growth caching.
diff --git a/gcc/testsuite/gcc.target/i386/pr17692.c b/gcc/testsuite/gcc.target/i386/pr17692.c
new file mode 100644
index 0000000..a837386
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr17692.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mfpmath=sse -msse2" } */
+/* The fact that t1 and t2 are uninitialized is critical. With them
+ uninitialized, the register allocator is free to put them in the same
+ hard register, which results in
+
+ xmm0 = xmm0 >= xmm0 ? xmm0 : xmm0
+
+ Which is of course a nop, but one for which we would ICE splitting the
+ pattern. */
+
+double out;
+
+static void foo(void)
+{
+ double t1, t2, t3, t4;
+
+ t4 = t1 >= t2 ? t1 : t2;
+ t4 = t4 >= t3 ? t4 : t3;
+ out = t4;
+}