diff options
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c | 31 |
1 files changed, 16 insertions, 15 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c index 6deca32..b020a04 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c @@ -1,31 +1,32 @@ /* { dg-do compile } */ -/* { dg-options "-O -g" } */ +/* { dg-options "-O -mtune=generic -g" } */ /* { dg-final { check-function-bodies "**" "" "" { target lp64 } } } */ #include <arm_sve.h> /* ** callee_pred: -** addvl sp, sp, #-1 -** str p[0-9]+, \[sp\] -** str p[0-9]+, \[sp, #1, mul vl\] -** ldr (p[0-9]+), \[x0\] -** ldr (p[0-9]+), \[x1\] -** brkpa (p[0-7])\.b, p0/z, p1\.b, p2\.b -** brkpb (p[0-7])\.b, \3/z, p3\.b, \1\.b -** brka p0\.b, \4/z, \2\.b -** ldr p[0-9]+, \[sp\] -** ldr p[0-9]+, \[sp, #1, mul vl\] -** addvl sp, sp, #1 +** brkpa (p[0-3])\.b, p0/z, p1\.b, p2\.b +** ( +** ldr (p[0-3]), \[x0\] +** ldr (p[0-3]), \[x1\] +** brkpb (p[0-3])\.b, \1/z, \2\.b, \3\.b +** brka p0\.b, \4/z, p3\.b +** | +** ldr (p[0-3]), \[x1\] +** ldr (p[0-3]), \[x0\] +** brkpb (p[0-3])\.b, \1/z, \6\.b, \5\.b +** brka p0\.b, \7/z, p3\.b +** ) ** ret */ -__SVBool_t __attribute__((noipa)) +__SVBool_t __attribute__((noipa, optimize("schedule-insns"))) callee_pred (__SVBool_t p0, __SVBool_t p1, __SVBool_t p2, __SVBool_t p3, __SVBool_t mem0, __SVBool_t mem1) { p0 = svbrkpa_z (p0, p1, p2); - p0 = svbrkpb_z (p0, p3, mem0); - return svbrka_z (p0, mem1); + p0 = svbrkpb_z (p0, mem0, mem1); + return svbrka_z (p0, p3); } /* |